From: Al Stone ahs3@redhat.com
Signed-off-by: Al Stone al.stone@linaro.org --- platforms/exynos5250-arndale.acpi/ssdt0.asl | 338 ++++++++++++++++++++++++++++ 1 file changed, 338 insertions(+)
diff --git a/platforms/exynos5250-arndale.acpi/ssdt0.asl b/platforms/exynos5250-arndale.acpi/ssdt0.asl index 48fa409..c85fa1f 100644 --- a/platforms/exynos5250-arndale.acpi/ssdt0.asl +++ b/platforms/exynos5250-arndale.acpi/ssdt0.asl @@ -16,6 +16,344 @@ DefinitionBlock ( { Scope (_SB) { + // Base Address: 0x13400000 + Device (SPC1) // Samsung pin controller + { + Name (_HID, "LINA0002") + Name (_UID, 0x1) + + Name (BNKS, 0x9) // number of pin banks + Name (NGRP, 0x9) // number of pin groups + + Method (_CRS, 0x0, Serialized) + { + // Base address for the pin controller + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x13400000, + 0x20) + }) + Return (RBUF) + } + + Device (GPE0) // GPIO chip GPE0 -- first bank + { + Name (TAG, "gpe0") // human-readable name + Name (BASE, 0x0) // base pin number + Name (NPIN, 0x8) // number of pins + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x13400000, + 0x20) + }) + Return (RBUF) + } + } + + Device (GPE1) // GPIO chip GPE1 -- 2nd bank + { + Name (TAG, "gpe1") // human-readable name + Name (BASE, 0x0) // base pin number + Name (NPIN, 0x8) // number of pins + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x13400020, + 0x20) + }) + Return (RBUF) + } + } + + Device (GPF0) // GPIO chip GPF0 -- 3rd bank + { + Name (TAG, "gpf0") // human-readable name + Name (BASE, 0x0) // base pin number + Name (NPIN, 0x8) // number of pins + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x13400040, + 0x20) + }) + Return (RBUF) + } + } + + Device (GPF1) // GPIO chip GPF1 -- 4th bank + { + Name (TAG, "gpf1") // human-readable name + Name (BASE, 0x0) // base pin number + Name (NPIN, 0x8) // number of pins + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x13400060, + 0x20) + }) + Return (RBUF) + } + } + + Device (GPG0) // GPIO chip GPG0 -- 5th bank + { + Name (TAG, "gpg0") // human-readable name + Name (BASE, 0x0) // base pin number + Name (NPIN, 0x8) // number of pins + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x13400080, + 0x20) + }) + Return (RBUF) + } + } + + Device (GPG1) // GPIO chip GPG1 -- 6th bank + { + Name (TAG, "gpg1") // human-readable name + Name (BASE, 0x0) // base pin number + Name (NPIN, 0x8) // number of pins + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x134000a0, + 0x20) + }) + Return (RBUF) + } + } + + Device (GPG2) // GPIO chip GPG2 -- 7th bank + { + Name (TAG, "gpg2") // human-readable name + Name (BASE, 0x0) // base pin number + Name (NPIN, 0x8) // number of pins + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x134000c0, + 0x20) + }) + Return (RBUF) + } + } + + Device (GPH0) // GPIO chip GPH0 -- 8th bank + { + Name (TAG, "gph0") // human-readable name + Name (BASE, 0x0) // base pin number + Name (NPIN, 0x8) // number of pins + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x134000e0, + 0x20) + }) + Return (RBUF) + } + } + + Device (GPH1) // GPIO chip GPH1 -- 9th bank + { + Name (TAG, "gph1") // human-readable name + Name (BASE, 0x0) // base pin number + Name (NPIN, 0x8) // number of pins + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x13400100, + 0x20) + }) + Return (RBUF) + } + } + + Device (CGA) // First pin group + { + Name (NPIN, 0xa) // number of pins + Name (FUNC, 0x2) // function number + Name (PUD, 0x0) // direction + Name (DRV, 0x0) // drive + + Method (PINS, 0x0, NotSerialized) + { + Return (Package () { + "gpe0-0", "gpe0-1", "gpe0-2", + "gpe0-3", "gpe0-4", "gpe0-5", + "gpe0-6", "gpe0-7", + "gpe1-0", "gpe1-1" + }) + } + } + + Device (CGB) // 2nd pin group + { + Name (NPIN, 0x8) // number of pins + Name (FUNC, 0x3) // function number + Name (PUD, 0x0) // direction + Name (DRV, 0x0) // drive + + Method (PINS, 0x0, NotSerialized) + { + Return (Package () { + "gpf0-0", "gpf0-1", "gpf0-2", + "gpf0-3", + "gpf1-0", "gpf1-1", "gpf1-2", + "gpf1-3" + }) + } + } + + Device (CI2B) // 3rd pin group + { + Name (NPIN, 0x2) // number of pins + Name (FUNC, 0x4) // function number + Name (PUD, 0x3) // direction + Name (DRV, 0x0) // drive + + Method (PINS, 0x0, NotSerialized) + { + Return (Package () { + "gpe0-6", "gpe1-0" + }) + } + } + + Device (CS1B) // 4th pin group + { + Name (NPIN, 0x4) // number of pins + Name (FUNC, 0x4) // function number + Name (PUD, 0x0) // direction + Name (DRV, 0x0) // drive + + Method (PINS, 0x0, NotSerialized) + { + Return (Package () { + "gpe0-4", "gpe0-5", + "gpf0-2", "gpf0-3" + }) + } + } + + Device (CI1B) // 5th pin group + { + Name (NPIN, 0x2) // number of pins + Name (FUNC, 0x2) // function number + Name (PUD, 0x3) // direction + Name (DRV, 0x0) // drive + + Method (PINS, 0x0, NotSerialized) + { + Return (Package () { + "gpf0-2", "gpf0-3" + }) + } + } + + Device (CI0B) // 6th pin group + { + Name (NPIN, 0x2) // number of pins + Name (FUNC, 0x2) // function number + Name (PUD, 0x3) // direction + Name (DRV, 0x0) // drive + + Method (PINS, 0x0, NotSerialized) + { + Return (Package () { + "gpf0-0", "gpf0-1" + }) + } + } + + Device (CS0B) // 7th pin group + { + Name (NPIN, 0x4) // number of pins + Name (FUNC, 0x2) // function number + Name (PUD, 0x0) // direction + Name (DRV, 0x0) // drive + + Method (PINS, 0x0, NotSerialized) + { + Return (Package () { + "gpf1-0", "gpf1-1", + "gpf1-2", "gpf1-3" + }) + } + } + + Device (CBRB) // 8th pin group + { + Name (NPIN, 0x12) // number of pins + Name (FUNC, 0x2) // function number + Name (PUD, 0x0) // direction + Name (DRV, 0x0) // drive + + Method (PINS, 0x0, NotSerialized) + { + Return (Package () { + "gpg0-0", "gpg0-1", "gpg0-2", + "gpg0-3", "gpg0-4", "gpg0-5", + "gpg0-6", "gpg0-7", + "gpg1-0", "gpg1-1", "gpg1-2", + "gpg1-3", "gpg1-4", "gpg1-5", + "gpg1-6", "gpg1-7", + "gpg2-0", "gpg2-1" + }) + } + } + + Device (CPA) // 9th pin group + { + Name (NPIN, 0xc) // number of pins + Name (FUNC, 0x2) // function number + Name (PUD, 0x0) // direction + Name (DRV, 0x0) // drive + + Method (PINS, 0x0, NotSerialized) + { + Return (Package () { + "gph0-0", "gph0-1", "gph0-2", + "gph0-3", + "gph1-0", "gph1-1", "gph1-2", + "gph1-3", "gph1-4", "gph1-5", + "gph1-6", "gph1-7" + }) + } + } + + } + // Base Address: 0x10d10000 Device (SPC2) // Samsung pin controller {