From: Mark Rutland mark.rutland@arm.com
Currently the bootwrapper still lumps together logically distinct pieces of hardware initialisation, making porting to new platforms or adding new features difficult. It would be nicer if we could separate some of the functional units to make the code clearer and easier to extend.
To this end, this patch factors the secure GIC initialisation into its own file. Additionally, the code is modified to route all interrupts to the non-secure side, not just the first 64.
Signed-off-by: Mark Rutland mark.rutland@arm.com --- Makefile | 4 ++-- boot.S | 27 +-------------------------- gic.S | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ model.lds.S | 2 ++ 4 files changed, 54 insertions(+), 28 deletions(-) create mode 100644 gic.S
diff --git a/Makefile b/Makefile index 21fd8b8..ad969ed 100644 --- a/Makefile +++ b/Makefile @@ -65,9 +65,9 @@ DTC := $(if $(wildcard ./dtc), ./dtc, $(shell which dtc)) all: $(IMAGE)
clean: - rm -f $(IMAGE) boot.o ns.o model.lds fdt.dtb + rm -f $(IMAGE) boot.o gic.o ns.o model.lds fdt.dtb
-$(IMAGE): boot.o ns.o model.lds fdt.dtb $(KERNEL) $(FILESYSTEM) +$(IMAGE): boot.o gic.o ns.o model.lds fdt.dtb $(KERNEL) $(FILESYSTEM) $(LD) -o $@ --script=model.lds
%.o: %.S Makefile diff --git a/boot.S b/boot.S index 391e74b..e4577fb 100644 --- a/boot.S +++ b/boot.S @@ -31,32 +31,7 @@ _start: ldr x0, =CNTFRQ msr cntfrq_el0, x0
- /* - * Check for the primary CPU to avoid a race on the distributor - * registers. - */ - mrs x0, mpidr_el1 - ldr x1, =MPIDR_ID_BITS - tst x0, x1 - b.ne 1f // secondary CPU - - ldr x1, =GIC_DIST_BASE // GICD_CTLR - mov w0, #3 // EnableGrp0 | EnableGrp1 - str w0, [x1] - -1: ldr x1, =GIC_DIST_BASE + 0x80 // GICD_IGROUPR - mov w0, #~0 // Grp1 interrupts - str w0, [x1] - b.ne 2f // Only local interrupts for secondary CPUs - str w0, [x1, #4] - str w0, [x1, #8] - -2: ldr x1, =GIC_CPU_BASE // GICC_CTLR - mov w0, #3 // EnableGrp0 | EnableGrp1 - str w0, [x1] - - mov w0, #1 << 7 // allow NS access to GICC_PMR - str w0, [x1, #4] // GICC_PMR + bl gic_secure_init
msr sctlr_el2, xzr
diff --git a/gic.S b/gic.S new file mode 100644 index 0000000..e16b64a --- /dev/null +++ b/gic.S @@ -0,0 +1,49 @@ +/* + * gic.S - Secure gic initialisation for stand-alone Linux booting + * + * Copyright (C) 2013 ARM Limited. All rights reserved. + * + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE.txt file. + */ + +#include "common.S" + + .text + + .global gic_secure_init + +gic_secure_init: + /* + * Check for the primary CPU to avoid a race on the distributor + * registers. + */ + mrs x0, mpidr_el1 + ldr x1, =MPIDR_ID_BITS + tst x0, x1 + b.ne 1f // secondary CPU + + ldr x1, =GIC_DIST_BASE // GICD_CTLR + mov w0, #3 // EnableGrp0 | EnableGrp1 + str w0, [x1] + +1: ldr x1, =GIC_DIST_BASE + 0x80 // GICD_IGROUPR + mov w0, #~0 // Grp1 interrupts + str w0, [x1] + b.ne 2f // Only local interrupts for secondary CPUs + ldr x2, =GIC_DIST_BASE + 0x04 // GICD_TYPER + ldr w3, [x2] + ands w3, w3, #0x1f // ITLinesNumber + b.eq 2f +1: str w0, [x1, #4]! + subs w3, w3, #1 + b.ne 1b + +2: ldr x1, =GIC_CPU_BASE // GICC_CTLR + mov w0, #3 // EnableGrp0 | EnableGrp1 + str w0, [x1] + + mov w0, #1 << 7 // allow NS access to GICC_PMR + str w0, [x1, #4] // GICC_PMR + + ret diff --git a/model.lds.S b/model.lds.S index 23aa1bf..92a3b8a 100644 --- a/model.lds.S +++ b/model.lds.S @@ -12,6 +12,7 @@ OUTPUT_ARCH(aarch64) TARGET(binary)
INPUT(./boot.o) +INPUT(./gic.o) INPUT(./ns.o) INPUT(KERNEL) INPUT(./fdt.dtb) @@ -24,6 +25,7 @@ SECTIONS { . = PHYS_OFFSET; .text : { boot.o } + .text : { gic.o } .text : { ns.o } . = PHYS_OFFSET + MBOX_OFFSET; mbox = .;