On Tue, Sep 16 2014 at 03:46:01 PM, Wei Huang wei@redhat.com wrote:
On 9/16/14 4:04 AM, Alexander Spyridakis wrote:
On 15 September 2014 23:26, Wei Huang wei@redhat.com wrote:
diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 35b0c12..af652f2 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -35,6 +35,8 @@ #define VGIC_V2_MAX_LRS (1 << 6) #define VGIC_V3_MAX_LRS 16
+#define VGIC_CPU_INTERFACE_SIZE 0x2000
Given that GIC_CPU interface is well known, instead of defining VGIC_CPU_INTERFACE_SIZE, SZ_8K can be used directly below.
Yes, I thought to be more explicit but skipping that define would be better I guess.
vgic->maint_irq = acpi_register_gsi(NULL,vgic_acpi->vgic_interrupt, trigger, ACPI_ACTIVE_HIGH);Unless I missed something, according to GIC-400 all PPIs are active-LOW, including maintenance interrupt.
Hmm I am confused. You are indeed right that GIC-400 at 2.3.2 states that all PPIs are active-LOW, on the other hand though, the device tree files for the gic node describe the virtual maintenance interrupt as active high (0xf04 description from Documentation/devicetree/bindings/arm/gic.txt). Am I missing something?
Not sure about what the GIC-400 describes (I don't have the documentation at hand), but the GICv2 architecture document only talks of level and edge, not high/low and rising/falling.
It sounds to me that GIC-400 is wrong. It is better for Marc to answer it.
Marc: Because ACPI 5.1 only specifies trigger type for maintenance IRQ, instead of parsing ACPI entry we have to use hard-code value for polarity when calling acpi_register_gsi(). Could you take a look?
I'd tend to agree with the ACPI spec. What the GIC-400 documentation probably describe is the actual wire signaling. What the GICv2 architecture (and thus ACPI) describe is the logical view of that.
So whatever you put there (high or low) doesn't matter at all (the GIC only knows about level).
Thanks,
M.