[RFC PATCH 0/9] Add self-probe infrastructure and stacked irqdomain support for ACPI based GICv2/3 init
This patch set introduce self-probe infrastructure to init IRQ controllers and stacked irqdomain support for ACPI based GICv2/3 init.
The self-probe infrastructure for ACPI GIC init is similar as IRQCHIP_DECLARE() and based on the GIC version support in ACPI MADT table.
We introduce acpi_irq_domain for GICv2/3 core domain to support stacked irqdomain, and pass the gsi (global system interrupt) as the agument (void *arg) for gic_irq_domain_alloc(), then we can alloc virqs via acpi_register_gsi() with stacked irqdomain.
I already compiled this patch set ok with both ACPI=on/off on ARM64 and also compiled ok on x86, tested with GICv2 init on FVP model and it boot successfully.
Next step I would consolidate all the ACPI GIC init into one file -- drivers/irqchip/irq-gic-acpi.c, and introduce ITS and IORT support.
please comment on this patchset to see if we are on the right direction.
Hanjun Guo (6): irqchip / gic: Add GIC version support in ACPI MADT irqchip: gic: ACPI: Use IRQCHIP_ACPI_DECLARE to simplify GICv2 init code irqchip / gic: Add stacked irqdomain support for ACPI based GICv2 init ACPI / gsi: Add gsi_mutex to synchronize acpi_register_gsi()/acpi_unregister_gsi() irqchip / GICv3: Add ACPI support for GICv3+ initialization irqchip / GICv3: Add stacked irqdomain support for ACPI based init
Tomasz Nowicki (3): ACPICA: Introduce GIC version for arm based system ACPI / irqchip: Add self-probe infrastructure to initialize IRQ controller irqchip / GICv3: Refactor gic_of_init() for GICv3 driver
arch/arm64/Kconfig | 1 + arch/arm64/include/asm/irq.h | 13 -- arch/arm64/kernel/acpi.c | 25 ---- drivers/acpi/Makefile | 1 + drivers/acpi/gsi.c | 39 ++--- drivers/acpi/irq.c | 40 ++++++ drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-gic-acpi.c | 116 +++++++++++++++ drivers/irqchip/irq-gic-v3.c | 267 ++++++++++++++++++++++++++++------- drivers/irqchip/irq-gic.c | 38 ++--- drivers/irqchip/irqchip.h | 12 ++ include/acpi/actbl1.h | 17 ++- include/asm-generic/vmlinux.lds.h | 13 ++ include/linux/acpi.h | 14 ++ include/linux/acpi_irq.h | 4 +- include/linux/irqchip/arm-gic-acpi.h | 12 +- include/linux/mod_devicetable.h | 7 + 18 files changed, 489 insertions(+), 134 deletions(-) create mode 100644 drivers/acpi/irq.c create mode 100644 drivers/irqchip/irq-gic-acpi.c
From: Tomasz Nowicki tomasz.nowicki@linaro.org
A new field is added in GIC distributor to indication the GIC version, support it in ACPICA for later use
Signed-off-by: Tomasz Nowicki tomasz.nowicki@linaro.org Signed-off-by: Hanjun Guo hanjun.guo@linaro.org --- include/acpi/actbl1.h | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index b80b0e6..b4f0f74 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -819,7 +819,7 @@ struct acpi_madt_generic_interrupt { #define ACPI_MADT_PERFORMANCE_IRQ_MODE (1<<1) /* 01: Performance Interrupt Mode */ #define ACPI_MADT_VGIC_IRQ_MODE (1<<2) /* 02: VGIC Maintenance Interrupt mode */
-/* 12: Generic Distributor (ACPI 5.0) */ +/* 12: Generic Distributor (ACPI 6.0) */
struct acpi_madt_generic_distributor { struct acpi_subtable_header header; @@ -827,7 +827,20 @@ struct acpi_madt_generic_distributor { u32 gic_id; u64 base_address; u32 global_irq_base; - u32 reserved2; /* reserved - must be zero */ + u8 gic_version; + u8 reserved2[3]; /* reserved - must be zero */ +}; + +/* Values for gic_version in Generic Distributor (ACPI 6.0) */ + +enum acpi_madt_gic_ver_type +{ + ACPI_MADT_GIC_VER_UNKNOWN = 0, + ACPI_MADT_GIC_VER_V1 = 1, + ACPI_MADT_GIC_VER_V2 = 2, + ACPI_MADT_GIC_VER_V3 = 3, + ACPI_MADT_GIC_VER_V4 = 4, + ACPI_MADT_GIC_VER_RESERVED = 5 /* 5 and greater are reserved */ };
/* 13: Generic MSI Frame (ACPI 5.1) */
From: Tomasz Nowicki tomasz.nowicki@linaro.org
This self-probe infrastructure works in the similar way as OF, but there is some different in the mechanism:
For OF, the init fn will be called once it finds comptiable strings in DT, but for ACPI, we init irqchips by static tables, and in static ACPI tables, there are no comptiable strings to indicate irqchips, so every init function with IRQCHIP_ACPI_DECLARE in the same table will be called, but thanks to the GIC version presented in ACPI table, we can init different GIC irqchips with this framework.
This mechanism can also be used for clock declare and may also works on x86 for some table parsing too.
Signed-off-by: Tomasz Nowicki tomasz.nowicki@linaro.org [hj: introduce struct acpi_table_id instead of acpi_device_id] [hj: rework it more generic to all ACPI tables and fix some issues] Signed-off-by: Hanjun Guo hanjun.guo@linaro.org --- drivers/acpi/Makefile | 1 + drivers/acpi/irq.c | 37 +++++++++++++++++++++++++++++++++++++ drivers/irqchip/irqchip.h | 12 ++++++++++++ include/asm-generic/vmlinux.lds.h | 13 +++++++++++++ include/linux/acpi.h | 14 ++++++++++++++ include/linux/mod_devicetable.h | 7 +++++++ 6 files changed, 84 insertions(+) create mode 100644 drivers/acpi/irq.c
diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile index 431e587..0b34d99 100644 --- a/drivers/acpi/Makefile +++ b/drivers/acpi/Makefile @@ -80,6 +80,7 @@ obj-$(CONFIG_ACPI_HED) += hed.o obj-$(CONFIG_ACPI_EC_DEBUGFS) += ec_sys.o obj-$(CONFIG_ACPI_CUSTOM_METHOD)+= custom_method.o obj-$(CONFIG_ACPI_BGRT) += bgrt.o +obj-$(CONFIG_IRQCHIP) += irq.o obj-$(CONFIG_ACPI_SPCR) += acpi_spcr.o
# processor has its own "processor." module_param namespace diff --git a/drivers/acpi/irq.c b/drivers/acpi/irq.c new file mode 100644 index 0000000..65d6b93 --- /dev/null +++ b/drivers/acpi/irq.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015, Linaro Ltd. + * Author: Tomasz Nowicki tomasz.nowicki@linaro.org + * Hanjun Guo hanjun.guo@linaro.org + * + * Inspired by drivers/irqchip/irqchip.c + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + */ + +#include <linux/init.h> +#include <linux/acpi.h> + +/* + * This special acpi_table_id is the sentinel at the end of the + * acpi_table_id[] array of all irqchips. It is automatically placed at + * the end of the array by the linker, thanks to being part of a + * special section. + */ +static const struct acpi_table_id +irqchip_acpi_match_end __used __section(__irqchip_acpi_table_end); + +extern struct acpi_table_id __irqchip_acpi_table[]; + +void __init acpi_irqchip_init(void) +{ + struct acpi_table_id *id; + + if (acpi_disabled) + return; + + for (id = __irqchip_acpi_table; id->id[0]; id++) + acpi_table_parse(id->id, (acpi_tbl_table_handler)id->data); +} diff --git a/drivers/irqchip/irqchip.h b/drivers/irqchip/irqchip.h index 0f6486d..1949546 100644 --- a/drivers/irqchip/irqchip.h +++ b/drivers/irqchip/irqchip.h @@ -11,6 +11,7 @@ #ifndef _IRQCHIP_H #define _IRQCHIP_H
+#include <linux/acpi.h> #include <linux/of.h>
/* @@ -25,4 +26,15 @@ */ #define IRQCHIP_DECLARE(name, compat, fn) OF_DECLARE_2(irqchip, name, compat, fn)
+/* + * This macro must be used by the different irqchip drivers to declare + * the association between their ACPI table and their initialization function. + * + * @name: name that must be unique accross all IRQCHIP_ACPI_DECLARE of the + * same file. + * @table_id: name of the ACPI table signature + * @fn: initialization function + */ +#define IRQCHIP_ACPI_DECLARE(name, table_id, fn) \ + ACPI_DECLARE(irqchip, name, table_id, fn) #endif diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h index 8bd374d..625776c 100644 --- a/include/asm-generic/vmlinux.lds.h +++ b/include/asm-generic/vmlinux.lds.h @@ -181,6 +181,18 @@ #define CPUIDLE_METHOD_OF_TABLES() OF_TABLE(CONFIG_CPU_IDLE, cpuidle_method) #define EARLYCON_OF_TABLES() OF_TABLE(CONFIG_SERIAL_EARLYCON, earlycon)
+#ifdef CONFIG_ACPI +#define ACPI_TABLE(name) \ + . = ALIGN(8); \ + VMLINUX_SYMBOL(__##name##_acpi_table) = .; \ + *(__##name##_acpi_table) \ + *(__##name##_acpi_table_end) + +#define IRQCHIP_ACPI_MATCH_TABLE() ACPI_TABLE(irqchip) +#else +#define IRQCHIP_ACPI_MATCH_TABLE() +#endif + #define KERNEL_DTB() \ STRUCT_ALIGN(); \ VMLINUX_SYMBOL(__dtb_start) = .; \ @@ -516,6 +528,7 @@ CPUIDLE_METHOD_OF_TABLES() \ KERNEL_DTB() \ IRQCHIP_OF_MATCH_TABLE() \ + IRQCHIP_ACPI_MATCH_TABLE() \ EARLYCON_TABLE() \ EARLYCON_OF_TABLES()
diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 4f2dfe6..c6cdbaf 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -820,6 +820,20 @@ static inline struct acpi_device *acpi_get_next_child(struct device *dev,
#endif
+#ifdef CONFIG_ACPI +#define ACPI_DECLARE(table, name, table_id, fn) \ + static const struct acpi_table_id __acpi_table_##name \ + __used __section(__##table##_acpi_table) \ + = { .id = table_id, \ + .data = (void *)fn } +#else +#define ACPI_DECLARE(table, name, table_id, fn) \ + static const struct acpi_table_id __acpi_table_##name \ + __attribute__((unused)) \ + = { .id = table_id, \ + .data = (void*)fn } +#endif + /* Provide support for using the SPCR table to define the console */ #ifdef CONFIG_ACPI_SPCR extern u64 spcr_serial_addr; diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h index 3bfd567..47c1ea1 100644 --- a/include/linux/mod_devicetable.h +++ b/include/linux/mod_devicetable.h @@ -199,6 +199,13 @@ struct pnp_device_id { kernel_ulong_t driver_data; };
+#define ACPI_TABLE_ID_LEN 5 + +struct acpi_table_id { + __u8 id[ACPI_TABLE_ID_LEN]; + const void *data; +}; + struct pnp_card_device_id { __u8 id[PNP_ID_LEN]; kernel_ulong_t driver_data;
There is a field added in ACPI MADT table to indicate the GIC version, so parse the table to get its value for later use.
If GIC version presented in MADT is 0, we need to fallback to hardware discovery to get the GIC version.
Signed-off-by: Hanjun Guo hanjun.guo@linaro.org --- arch/arm64/Kconfig | 1 + drivers/acpi/irq.c | 3 + drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-gic-acpi.c | 111 +++++++++++++++++++++++++++++++++++ include/linux/irqchip/arm-gic-acpi.h | 2 + 6 files changed, 121 insertions(+) create mode 100644 drivers/irqchip/irq-gic-acpi.c
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index ac50e83..6bf27d0 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -16,6 +16,7 @@ config ARM64 select ARM_AMBA select ARM_ARCH_TIMER select ARM_GIC + select ARM_GIC_ACPI if ACPI select AUDIT_ARCH_COMPAT_GENERIC select ARM_GIC_V2M if PCI_MSI select ARM_GIC_V3 diff --git a/drivers/acpi/irq.c b/drivers/acpi/irq.c index 65d6b93..855ead9 100644 --- a/drivers/acpi/irq.c +++ b/drivers/acpi/irq.c @@ -32,6 +32,9 @@ void __init acpi_irqchip_init(void) if (acpi_disabled) return;
+ if (acpi_gic_version_init()) + return; + for (id = __irqchip_acpi_table; id->id[0]; id++) acpi_table_parse(id->id, (acpi_tbl_table_handler)id->data); } diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 6de62a9..0dd64c5 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -46,6 +46,9 @@ config ARM_VIC_NR The maximum number of VICs available in the system, for power management.
+config ARM_GIC_ACPI + bool + config ATMEL_AIC_IRQ bool select GENERIC_IRQ_CHIP diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index dda4927..0bd8e49 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-common.o obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o +obj-$(CONFIG_ARM_GIC_ACPI) += irq-gic-acpi.o obj-$(CONFIG_ARM_NVIC) += irq-nvic.o obj-$(CONFIG_ARM_VIC) += irq-vic.o obj-$(CONFIG_ATMEL_AIC_IRQ) += irq-atmel-aic-common.o irq-atmel-aic.o diff --git a/drivers/irqchip/irq-gic-acpi.c b/drivers/irqchip/irq-gic-acpi.c new file mode 100644 index 0000000..4796f07 --- /dev/null +++ b/drivers/irqchip/irq-gic-acpi.c @@ -0,0 +1,111 @@ +/* + * ACPI based support for ARM GIC init + * + * Copyright (C) 2013-2015, Linaro Ltd. + * Author: Hanjun Guo hanjun.guo@linaro.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define pr_fmt(fmt) "ACPI: GIC: " fmt + +#include <linux/acpi.h> +#include <linux/init.h> +#include <linux/irqchip/arm-gic-v3.h> +#include <linux/irqchip/arm-gic-acpi.h> + +/* GIC version presented in MADT GIC distributor structure */ +static u8 gic_version __initdata = ACPI_MADT_GIC_VER_UNKNOWN; + +static phys_addr_t dist_phy_base __initdata; + +static int __init +acpi_gic_parse_distributor(struct acpi_subtable_header *header, + const unsigned long end) +{ + struct acpi_madt_generic_distributor *dist; + + dist = (struct acpi_madt_generic_distributor *)header; + + if (BAD_MADT_ENTRY(dist, end)) + return -EINVAL; + + gic_version = dist->gic_version; + dist_phy_base = dist->base_address; + return 0; +} + +static int __init +match_gic_redist(struct acpi_subtable_header *header, const unsigned long end) +{ + return 0; +} + +static bool __init acpi_gic_redist_is_present(void) +{ + int count; + + /* scan MADT table to find if we have redistributor entries */ + count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, + match_gic_redist, 0); + + /* has at least one GIC redistributor entry */ + if (count > 0) + return true; + else + return false; +} + +int __init acpi_gic_version_init(void) +{ + int count; + void __iomem *dist_base; + u32 reg; + + count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, + acpi_gic_parse_distributor, 0); + + if (count <= 0) { + pr_err("No valid GIC distributor entry exists\n"); + return -ENODEV; + } + + if (gic_version >= ACPI_MADT_GIC_VER_RESERVED) { + pr_err("Invalid GIC version %d in MADT\n", gic_version); + return -EINVAL; + } + + /* + * when the GIC version is 0, we fallback to hardware discovery. + * this is also needed to keep compatiable with ACPI 5.1, + * which has no gic_version field in distributor structure and + * reserved as 0. + * + * For hardware discovery, the offset for GICv1/2 and GICv3/4 to + * get the GIC version is different (0xFE8 for GICv1/2 and 0xFFE8 + * for GICv3/4), so we need to handle it separately. + */ + if (gic_version == ACPI_MADT_GIC_VER_UNKNOWN) { + /* it's GICv3/v4 if redistributor is present */ + if (acpi_gic_redist_is_present()) { + dist_base = ioremap(dist_phy_base, + ACPI_GICV3_DIST_MEM_SIZE); + if (!dist_base) + return -ENOMEM; + + reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; + if (reg == GIC_PIDR2_ARCH_GICv3) + gic_version = ACPI_MADT_GIC_VER_V3; + else + gic_version = ACPI_MADT_GIC_VER_V4; + + iounmap(dist_base); + } else { + gic_version = ACPI_MADT_GIC_VER_V2; + } + } + + return 0; +} diff --git a/include/linux/irqchip/arm-gic-acpi.h b/include/linux/irqchip/arm-gic-acpi.h index de3419e..0d5f204 100644 --- a/include/linux/irqchip/arm-gic-acpi.h +++ b/include/linux/irqchip/arm-gic-acpi.h @@ -19,11 +19,13 @@ */ #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K) #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K) +#define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
struct acpi_table_header;
int gic_v2_acpi_init(struct acpi_table_header *table); void acpi_gic_init(void); +int acpi_gic_version_init(void); #else static inline void acpi_gic_init(void) { } #endif
As the ACPI self-probe infrastructure for irqchip is ready, we use the infrastructure and the GIC version to simplify GICv2 init code.
From now on, GIC init calls reside in theirs drivers only.
This means the code becomes cleaner and it is not spread outside irqchip driver.
Signed-off-by: Hanjun Guo hanjun.guo@linaro.org --- arch/arm64/include/asm/irq.h | 13 ------------- arch/arm64/kernel/acpi.c | 25 ------------------------- drivers/acpi/irq.c | 2 +- drivers/irqchip/irq-gic-acpi.c | 5 +++++ drivers/irqchip/irq-gic.c | 6 +++++- include/linux/acpi_irq.h | 4 +++- include/linux/irqchip/arm-gic-acpi.h | 10 ++-------- 7 files changed, 16 insertions(+), 49 deletions(-)
diff --git a/arch/arm64/include/asm/irq.h b/arch/arm64/include/asm/irq.h index bbb251b..94c5367 100644 --- a/arch/arm64/include/asm/irq.h +++ b/arch/arm64/include/asm/irq.h @@ -1,8 +1,6 @@ #ifndef __ASM_IRQ_H #define __ASM_IRQ_H
-#include <linux/irqchip/arm-gic-acpi.h> - #include <asm-generic/irq.h>
struct pt_regs; @@ -10,15 +8,4 @@ struct pt_regs; extern void migrate_irqs(void); extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
-static inline void acpi_irq_init(void) -{ - /* - * Hardcode ACPI IRQ chip initialization to GICv2 for now. - * Proper irqchip infrastructure will be implemented along with - * incoming GICv2m|GICv3|ITS bits. - */ - acpi_gic_init(); -} -#define acpi_irq_init acpi_irq_init - #endif diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c index 8b83955..69809e7 100644 --- a/arch/arm64/kernel/acpi.c +++ b/arch/arm64/kernel/acpi.c @@ -318,28 +318,3 @@ void __init acpi_boot_table_init(void) disable_acpi(); } } - -void __init acpi_gic_init(void) -{ - struct acpi_table_header *table; - acpi_status status; - acpi_size tbl_size; - int err; - - if (acpi_disabled) - return; - - status = acpi_get_table_with_size(ACPI_SIG_MADT, 0, &table, &tbl_size); - if (ACPI_FAILURE(status)) { - const char *msg = acpi_format_exception(status); - - pr_err("Failed to get MADT table, %s\n", msg); - return; - } - - err = gic_v2_acpi_init(table); - if (err) - pr_err("Failed to initialize GIC IRQ controller"); - - early_acpi_os_unmap_memory((char *)table, tbl_size); -} diff --git a/drivers/acpi/irq.c b/drivers/acpi/irq.c index 855ead9..7bd1ef6 100644 --- a/drivers/acpi/irq.c +++ b/drivers/acpi/irq.c @@ -25,7 +25,7 @@ irqchip_acpi_match_end __used __section(__irqchip_acpi_table_end);
extern struct acpi_table_id __irqchip_acpi_table[];
-void __init acpi_irqchip_init(void) +void __init acpi_irq_init(void) { struct acpi_table_id *id;
diff --git a/drivers/irqchip/irq-gic-acpi.c b/drivers/irqchip/irq-gic-acpi.c index 4796f07..7172ff1 100644 --- a/drivers/irqchip/irq-gic-acpi.c +++ b/drivers/irqchip/irq-gic-acpi.c @@ -21,6 +21,11 @@ static u8 gic_version __initdata = ACPI_MADT_GIC_VER_UNKNOWN;
static phys_addr_t dist_phy_base __initdata;
+u8 __init acpi_gic_version(void) +{ + return gic_version; +} + static int __init acpi_gic_parse_distributor(struct acpi_subtable_header *header, const unsigned long end) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 7b315e3..476dc7b 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -1154,12 +1154,15 @@ gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header, return 0; }
-int __init +static int __init gic_v2_acpi_init(struct acpi_table_header *table) { void __iomem *cpu_base, *dist_base; int count;
+ if (acpi_gic_version() >= ACPI_MADT_GIC_VER_V3) + return -ENODEV; + /* Collect CPU base addresses */ count = acpi_parse_entries(ACPI_SIG_MADT, sizeof(struct acpi_table_madt), @@ -1210,4 +1213,5 @@ gic_v2_acpi_init(struct acpi_table_header *table) acpi_irq_model = ACPI_IRQ_MODEL_GIC; return 0; } +IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_SIG_MADT, gic_v2_acpi_init); #endif diff --git a/include/linux/acpi_irq.h b/include/linux/acpi_irq.h index f10c872..4c0e108 100644 --- a/include/linux/acpi_irq.h +++ b/include/linux/acpi_irq.h @@ -3,7 +3,9 @@
#include <linux/irq.h>
-#ifndef acpi_irq_init +#ifdef CONFIG_ACPI +void acpi_irq_init(void); +#else static inline void acpi_irq_init(void) { } #endif
diff --git a/include/linux/irqchip/arm-gic-acpi.h b/include/linux/irqchip/arm-gic-acpi.h index 0d5f204..021e8e8 100644 --- a/include/linux/irqchip/arm-gic-acpi.h +++ b/include/linux/irqchip/arm-gic-acpi.h @@ -21,13 +21,7 @@ #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K) #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
-struct acpi_table_header; - -int gic_v2_acpi_init(struct acpi_table_header *table); -void acpi_gic_init(void); int acpi_gic_version_init(void); -#else -static inline void acpi_gic_init(void) { } -#endif - +u8 acpi_gic_version(void); +#endif /* CONFIG_ACPI */ #endif /* ARM_GIC_ACPI_H_ */
Introduce acpi_irq_domain for GICv2 core domain instead of referring to the irq_default_domain, based on that, pass gsi as the argument and get the gsi in gic_irq_domain_alloc() to add stacked irqdomain support for ACPI based GICv2 init.
Signed-off-by: Hanjun Guo hanjun.guo@linaro.org --- drivers/acpi/gsi.c | 26 +++++++++++--------------- drivers/irqchip/irq-gic.c | 32 +++++++++++++++++--------------- include/linux/irqchip/arm-gic-acpi.h | 2 ++ 3 files changed, 30 insertions(+), 30 deletions(-)
diff --git a/drivers/acpi/gsi.c b/drivers/acpi/gsi.c index 38208f2..f4110d8 100644 --- a/drivers/acpi/gsi.c +++ b/drivers/acpi/gsi.c @@ -13,6 +13,7 @@ #include <linux/irqdomain.h>
enum acpi_irq_model_id acpi_irq_model; +struct irq_domain *acpi_irq_domain;
static unsigned int acpi_gsi_get_irq_type(int trigger, int polarity) { @@ -45,12 +46,7 @@ static unsigned int acpi_gsi_get_irq_type(int trigger, int polarity) */ int acpi_gsi_to_irq(u32 gsi, unsigned int *irq) { - /* - * Only default domain is supported at present, always find - * the mapping corresponding to default domain by passing NULL - * as irq_domain parameter - */ - *irq = irq_find_mapping(NULL, gsi); + *irq = irq_find_mapping(acpi_irq_domain, gsi); /* * *irq == 0 means no mapping, that should * be reported as a failure @@ -72,16 +68,16 @@ EXPORT_SYMBOL_GPL(acpi_gsi_to_irq); int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity) { - unsigned int irq; + int irq; unsigned int irq_type = acpi_gsi_get_irq_type(trigger, polarity);
- /* - * There is no way at present to look-up the IRQ domain on ACPI, - * hence always create mapping referring to the default domain - * by passing NULL as irq_domain parameter - */ - irq = irq_create_mapping(NULL, gsi); - if (!irq) + irq = irq_find_mapping(acpi_irq_domain, gsi); + if (irq > 0) + return irq; + + irq = irq_domain_alloc_irqs(acpi_irq_domain, 1, dev_to_node(dev), + &gsi); + if (irq <= 0) return -EINVAL;
/* Set irq type if specified and different than the current one */ @@ -98,7 +94,7 @@ EXPORT_SYMBOL_GPL(acpi_register_gsi); */ void acpi_unregister_gsi(u32 gsi) { - int irq = irq_find_mapping(NULL, gsi); + int irq = irq_find_mapping(acpi_irq_domain, gsi);
irq_dispose_mapping(irq); } diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 476dc7b..0b712f8 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -919,15 +919,22 @@ static struct notifier_block gic_cpu_notifier = { static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs, void *arg) { - int i, ret; + int i; irq_hw_number_t hwirq; - unsigned int type = IRQ_TYPE_NONE; - struct of_phandle_args *irq_data = arg;
- ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args, - irq_data->args_count, &hwirq, &type); - if (ret) - return ret; + if (domain->of_node) { /* DT case */ + int ret; + unsigned int type = IRQ_TYPE_NONE; + struct of_phandle_args *irq_data = arg; + + ret = gic_irq_domain_xlate(domain, irq_data->np, + irq_data->args, + irq_data->args_count, &hwirq, &type); + if (ret) + return ret; + } else { /* ACPI case */ + hwirq = (irq_hw_number_t)*(u32 *)arg; + }
for (i = 0; i < nr_irqs; i++) gic_irq_domain_map(domain, virq + i, hwirq + i); @@ -1013,11 +1020,11 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start, gic_irqs = 1020; gic->gic_irqs = gic_irqs;
- if (node) { /* DT case */ + if (node || !acpi_disabled) { /* DT or ACPI case */ gic->domain = irq_domain_add_linear(node, gic_irqs, &gic_irq_domain_hierarchy_ops, gic); - } else { /* Non-DT case */ + } else { /* Non-DT and ACPI case */ /* * For primary GICs, skip over SGIs. * For secondary GICs, skip over PPIs, too. @@ -1202,13 +1209,8 @@ gic_v2_acpi_init(struct acpi_table_header *table) return -ENOMEM; }
- /* - * Initialize zero GIC instance (no multi-GIC support). Also, set GIC - * as default IRQ domain to allow for GSI registration and GSI to IRQ - * number translation (see acpi_register_gsi() and acpi_gsi_to_irq()). - */ gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL); - irq_set_default_host(gic_data[0].domain); + acpi_irq_domain = gic_data[0].domain;
acpi_irq_model = ACPI_IRQ_MODEL_GIC; return 0; diff --git a/include/linux/irqchip/arm-gic-acpi.h b/include/linux/irqchip/arm-gic-acpi.h index 021e8e8..245386d 100644 --- a/include/linux/irqchip/arm-gic-acpi.h +++ b/include/linux/irqchip/arm-gic-acpi.h @@ -21,6 +21,8 @@ #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K) #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
+extern struct irq_domain *acpi_irq_domain; + int acpi_gic_version_init(void); u8 acpi_gic_version(void); #endif /* CONFIG_ACPI */
Add a mutex for acpi_register_gsi()/acpi_unregister_gsi() to avoid concurrency issues.
Signed-off-by: Hanjun Guo hanjun.guo@linaro.org --- drivers/acpi/gsi.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/acpi/gsi.c b/drivers/acpi/gsi.c index f4110d8..f0f219c 100644 --- a/drivers/acpi/gsi.c +++ b/drivers/acpi/gsi.c @@ -14,6 +14,7 @@
enum acpi_irq_model_id acpi_irq_model; struct irq_domain *acpi_irq_domain; +static DEFINE_MUTEX(gsi_mutex);
static unsigned int acpi_gsi_get_irq_type(int trigger, int polarity) { @@ -71,20 +72,24 @@ int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int irq; unsigned int irq_type = acpi_gsi_get_irq_type(trigger, polarity);
+ mutex_lock(&gsi_mutex); irq = irq_find_mapping(acpi_irq_domain, gsi); if (irq > 0) - return irq; + goto out;
irq = irq_domain_alloc_irqs(acpi_irq_domain, 1, dev_to_node(dev), &gsi); if (irq <= 0) - return -EINVAL; + goto out;
/* Set irq type if specified and different than the current one */ if (irq_type != IRQ_TYPE_NONE && irq_type != irq_get_trigger_type(irq)) irq_set_irq_type(irq, irq_type); - return irq; + +out: + mutex_unlock(&gsi_mutex); + return irq > 0 ? irq : -EINVAL; } EXPORT_SYMBOL_GPL(acpi_register_gsi);
@@ -94,8 +99,12 @@ EXPORT_SYMBOL_GPL(acpi_register_gsi); */ void acpi_unregister_gsi(u32 gsi) { - int irq = irq_find_mapping(acpi_irq_domain, gsi); + int irq; + + mutex_lock(&gsi_mutex); + irq = irq_find_mapping(acpi_irq_domain, gsi);
irq_dispose_mapping(irq); + mutex_unlock(&gsi_mutex); } EXPORT_SYMBOL_GPL(acpi_unregister_gsi);
From: Tomasz Nowicki tomasz.nowicki@linaro.org
Isolate hardware abstraction (FDT) code to gic_of_init(). Rest of the logic goes to gic_init_bases() and expects well defined data to initialize GIC properly. The same solution is used for GICv2 driver.
This is needed for ACPI initialization later.
Signed-off-by: Tomasz Nowicki tomasz.nowicki@linaro.org Signed-off-by: Hanjun Guo hanjun.guo@linaro.org --- drivers/irqchip/irq-gic-v3.c | 105 +++++++++++++++++++++++++------------------ 1 file changed, 61 insertions(+), 44 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 49875ad..87cf81b 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -765,17 +765,69 @@ static const struct irq_domain_ops gic_irq_domain_ops = { .free = gic_irq_domain_free, };
+static int __init gic_init_bases(void __iomem *dist_base, + struct redist_region *rdist_regs, + u32 nr_redist_regions, + u64 redist_stride, + struct device_node *node) +{ + u32 typer; + int gic_irqs; + int err; + + gic_data.dist_base = dist_base; + gic_data.redist_regions = rdist_regs; + gic_data.nr_redist_regions = nr_redist_regions; + gic_data.redist_stride = redist_stride; + + /* + * Find out how many interrupts are supported. + * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) + */ + typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); + gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); + gic_irqs = GICD_TYPER_IRQS(typer); + if (gic_irqs > 1020) + gic_irqs = 1020; + gic_data.irq_nr = gic_irqs; + + gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops, + &gic_data); + gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); + + if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { + err = -ENOMEM; + goto out_free; + } + + set_handle_irq(gic_handle_irq); + + if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) + its_init(node, &gic_data.rdists, gic_data.domain); + + gic_smp_init(); + gic_dist_init(); + gic_cpu_init(); + gic_cpu_pm_init(); + + return 0; + +out_free: + if (gic_data.domain) + irq_domain_remove(gic_data.domain); + free_percpu(gic_data.rdists.rdist); + return err; +} + +#ifdef CONFIG_OF static int __init gic_of_init(struct device_node *node, struct device_node *parent) { void __iomem *dist_base; struct redist_region *rdist_regs; u64 redist_stride; u32 nr_redist_regions; - u32 typer; u32 reg; - int gic_irqs; - int err; - int i; + int err, i;
dist_base = of_iomap(node, 0); if (!dist_base) { @@ -819,47 +871,11 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) redist_stride = 0;
- gic_data.dist_base = dist_base; - gic_data.redist_regions = rdist_regs; - gic_data.nr_redist_regions = nr_redist_regions; - gic_data.redist_stride = redist_stride; - - /* - * Find out how many interrupts are supported. - * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) - */ - typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); - gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); - gic_irqs = GICD_TYPER_IRQS(typer); - if (gic_irqs > 1020) - gic_irqs = 1020; - gic_data.irq_nr = gic_irqs; + err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, + redist_stride, node); + if (!err) + return 0;
- gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops, - &gic_data); - gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); - - if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { - err = -ENOMEM; - goto out_free; - } - - set_handle_irq(gic_handle_irq); - - if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) - its_init(node, &gic_data.rdists, gic_data.domain); - - gic_smp_init(); - gic_dist_init(); - gic_cpu_init(); - gic_cpu_pm_init(); - - return 0; - -out_free: - if (gic_data.domain) - irq_domain_remove(gic_data.domain); - free_percpu(gic_data.rdists.rdist); out_unmap_rdist: for (i = 0; i < nr_redist_regions; i++) if (rdist_regs[i].redist_base) @@ -871,3 +887,4 @@ out_unmap_dist: }
IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); +#endif
With the refator of gic_of_init(), GICv3/4 can be initialized by gic_init_bases() with gic distributor base address and gic redistributor region(s).
So get the redistributor region base addresses from MADT GIC redistributor subtable, and the distributor base address from GICD subtable to init GICv3 irqchip in ACPI way.
Signed-off-by: Tomasz Nowicki tomasz.nowicki@linaro.org [hj: Rework this patch and fix multi issues] Signed-off-by: Hanjun Guo hanjun.guo@linaro.org --- drivers/irqchip/irq-gic-v3.c | 146 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 142 insertions(+), 4 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 87cf81b..11946a6 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -15,6 +15,7 @@ * along with this program. If not, see http://www.gnu.org/licenses/. */
+#include <linux/acpi.h> #include <linux/cpu.h> #include <linux/cpu_pm.h> #include <linux/delay.h> @@ -25,6 +26,7 @@ #include <linux/percpu.h> #include <linux/slab.h>
+#include <linux/irqchip/arm-gic-acpi.h> #include <linux/irqchip/arm-gic-v3.h>
#include <asm/cputype.h> @@ -819,6 +821,16 @@ out_free: return err; }
+static int __init detect_distributor(void __iomem *dist_base) +{ + u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; + + if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) + return -ENODEV; + + return 0; +} + #ifdef CONFIG_OF static int __init gic_of_init(struct device_node *node, struct device_node *parent) { @@ -826,7 +838,6 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare struct redist_region *rdist_regs; u64 redist_stride; u32 nr_redist_regions; - u32 reg; int err, i;
dist_base = of_iomap(node, 0); @@ -836,11 +847,10 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare return -ENXIO; }
- reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; - if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) { + err = detect_distributor(dist_base); + if (err) { pr_err("%s: no distributor detected, giving up\n", node->full_name); - err = -ENODEV; goto out_unmap_dist; }
@@ -888,3 +898,131 @@ out_unmap_dist:
IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); #endif + +#ifdef CONFIG_ACPI +static struct redist_region *redist_regs __initdata; +static u32 nr_redist_regions __initdata; +static phys_addr_t dist_phy_base __initdata; + +static int __init +gic_acpi_register_redist(u64 phys_base, u64 size) +{ + struct redist_region *redist_regs_new; + void __iomem *redist_base; + + redist_regs_new = krealloc(redist_regs, + sizeof(*redist_regs) * (nr_redist_regions + 1), + GFP_KERNEL); + if (!redist_regs_new) { + pr_err("Couldn't allocate resource for GICR region\n"); + return -ENOMEM; + } + + redist_regs = redist_regs_new; + + redist_base = ioremap(phys_base, size); + if (!redist_base) { + pr_err("Couldn't map GICR region @%llx\n", phys_base); + return -ENOMEM; + } + + redist_regs[nr_redist_regions].phys_base = phys_base; + redist_regs[nr_redist_regions].redist_base = redist_base; + nr_redist_regions++; + return 0; +} + +static int __init +gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, + const unsigned long end) +{ + struct acpi_madt_generic_redistributor *redist; + + if (BAD_MADT_ENTRY(header, end)) + return -EINVAL; + + redist = (struct acpi_madt_generic_redistributor *)header; + if (!redist->base_address) + return -EINVAL; + + return gic_acpi_register_redist(redist->base_address, redist->length); +} + +static int __init +gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header, + const unsigned long end) +{ + struct acpi_madt_generic_distributor *dist; + + dist = (struct acpi_madt_generic_distributor *)header; + + if (BAD_MADT_ENTRY(dist, end)) + return -EINVAL; + + dist_phy_base = dist->base_address; + return 0; +} + +static int __init +gic_v3_acpi_init(struct acpi_table_header *table) +{ + int count, i, err = 0; + void __iomem *dist_base; + + if (acpi_gic_version() < ACPI_MADT_GIC_VER_V3) + return -ENODEV; + + /* Get distributor base address */ + count = acpi_parse_entries(ACPI_SIG_MADT, + sizeof(struct acpi_table_madt), + gic_acpi_parse_madt_distributor, table, + ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0); + if (count <= 0) { + pr_err("No valid GICD entry exist\n"); + return -EINVAL; + } else if (count > 1) { + pr_err("More than one GICD entry detected\n"); + return -EINVAL; + } + + dist_base = ioremap(dist_phy_base, ACPI_GICV3_DIST_MEM_SIZE); + if (!dist_base) { + pr_err("Unable to map GICD registers\n"); + return -ENOMEM; + } + + err = detect_distributor(dist_base); + if (err) { + pr_err("No distributor detected at @%p, giving up", dist_base); + goto out_dist_unmap; + } + + /* Collect redistributor base addresses */ + count = acpi_parse_entries(ACPI_SIG_MADT, + sizeof(struct acpi_table_madt), + gic_acpi_parse_madt_redist, table, + ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 0); + if (count <= 0) { + pr_info("No valid GICR entries exist\n"); + err = -EINVAL; + goto out_redist_unmap; + } + + err = gic_init_bases(dist_base, redist_regs, nr_redist_regions, 0, NULL); + if (err) + goto out_redist_unmap; + + irq_set_default_host(gic_data.domain); + return 0; + +out_redist_unmap: + for (i = 0; i < nr_redist_regions; i++) + if (redist_regs[i].redist_base) + iounmap(redist_regs[i].redist_base); + kfree(redist_regs); +out_dist_unmap: + iounmap(dist_base); + return err; +} +IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_SIG_MADT, gic_v3_acpi_init); +#endif
Similar as stacked domain support for ACPI based GICv2 init, let acpi_irq_domain point to the core domain of GICv3 and pass the gsi as the arg to support stacked irqdomain.
Signed-off-by: Hanjun Guo hanjun.guo@linaro.org --- drivers/irqchip/irq-gic-v3.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 11946a6..e7f134e 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -733,15 +733,21 @@ static int gic_irq_domain_xlate(struct irq_domain *d, static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs, void *arg) { - int i, ret; + int i; irq_hw_number_t hwirq; - unsigned int type = IRQ_TYPE_NONE; - struct of_phandle_args *irq_data = arg;
- ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args, - irq_data->args_count, &hwirq, &type); - if (ret) - return ret; + if (domain->of_node) { /* DT case */ + int ret; + unsigned int type = IRQ_TYPE_NONE; + struct of_phandle_args *irq_data = arg; + + ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args, + irq_data->args_count, &hwirq, &type); + if (ret) + return ret; + } else { /* ACPI case */ + hwirq = (irq_hw_number_t)*(u32 *)arg; + }
for (i = 0; i < nr_irqs; i++) gic_irq_domain_map(domain, virq + i, hwirq + i); @@ -1012,7 +1018,7 @@ gic_v3_acpi_init(struct acpi_table_header *table) if (err) goto out_redist_unmap;
- irq_set_default_host(gic_data.domain); + acpi_irq_domain = gic_data.domain; return 0;
out_redist_unmap:
On Tuesday, May 05, 2015 09:50:48 PM Hanjun Guo wrote:
This patch set introduce self-probe infrastructure to init IRQ controllers and stacked irqdomain support for ACPI based GICv2/3 init.
The self-probe infrastructure for ACPI GIC init is similar as IRQCHIP_DECLARE() and based on the GIC version support in ACPI MADT table.
We introduce acpi_irq_domain for GICv2/3 core domain to support stacked irqdomain, and pass the gsi (global system interrupt) as the agument (void *arg) for gic_irq_domain_alloc(), then we can alloc virqs via acpi_register_gsi() with stacked irqdomain.
I already compiled this patch set ok with both ACPI=on/off on ARM64 and also compiled ok on x86, tested with GICv2 init on FVP model and it boot successfully.
Next step I would consolidate all the ACPI GIC init into one file -- drivers/irqchip/irq-gic-acpi.c, and introduce ITS and IORT support.
please comment on this patchset to see if we are on the right direction.
Hanjun Guo (6): irqchip / gic: Add GIC version support in ACPI MADT irqchip: gic: ACPI: Use IRQCHIP_ACPI_DECLARE to simplify GICv2 init code irqchip / gic: Add stacked irqdomain support for ACPI based GICv2 init ACPI / gsi: Add gsi_mutex to synchronize acpi_register_gsi()/acpi_unregister_gsi() irqchip / GICv3: Add ACPI support for GICv3+ initialization irqchip / GICv3: Add stacked irqdomain support for ACPI based init
Tomasz Nowicki (3): ACPICA: Introduce GIC version for arm based system ACPI / irqchip: Add self-probe infrastructure to initialize IRQ controller irqchip / GICv3: Refactor gic_of_init() for GICv3 driver
arch/arm64/Kconfig | 1 + arch/arm64/include/asm/irq.h | 13 -- arch/arm64/kernel/acpi.c | 25 ---- drivers/acpi/Makefile | 1 + drivers/acpi/gsi.c | 39 ++--- drivers/acpi/irq.c | 40 ++++++ drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-gic-acpi.c | 116 +++++++++++++++ drivers/irqchip/irq-gic-v3.c | 267 ++++++++++++++++++++++++++++------- drivers/irqchip/irq-gic.c | 38 ++--- drivers/irqchip/irqchip.h | 12 ++ include/acpi/actbl1.h | 17 ++- include/asm-generic/vmlinux.lds.h | 13 ++ include/linux/acpi.h | 14 ++ include/linux/acpi_irq.h | 4 +- include/linux/irqchip/arm-gic-acpi.h | 12 +- include/linux/mod_devicetable.h | 7 + 18 files changed, 489 insertions(+), 134 deletions(-) create mode 100644 drivers/acpi/irq.c create mode 100644 drivers/irqchip/irq-gic-acpi.c
What's the connection between this and the Jiang Liu's patchset?
On 2015年05月06日 04:28, Rafael J. Wysocki wrote:
On Tuesday, May 05, 2015 09:50:48 PM Hanjun Guo wrote:
This patch set introduce self-probe infrastructure to init IRQ controllers and stacked irqdomain support for ACPI based GICv2/3 init.
The self-probe infrastructure for ACPI GIC init is similar as IRQCHIP_DECLARE() and based on the GIC version support in ACPI MADT table.
We introduce acpi_irq_domain for GICv2/3 core domain to support stacked irqdomain, and pass the gsi (global system interrupt) as the agument (void *arg) for gic_irq_domain_alloc(), then we can alloc virqs via acpi_register_gsi() with stacked irqdomain.
I already compiled this patch set ok with both ACPI=on/off on ARM64 and also compiled ok on x86, tested with GICv2 init on FVP model and it boot successfully.
Next step I would consolidate all the ACPI GIC init into one file -- drivers/irqchip/irq-gic-acpi.c, and introduce ITS and IORT support.
please comment on this patchset to see if we are on the right direction.
Hanjun Guo (6): irqchip / gic: Add GIC version support in ACPI MADT irqchip: gic: ACPI: Use IRQCHIP_ACPI_DECLARE to simplify GICv2 init code irqchip / gic: Add stacked irqdomain support for ACPI based GICv2 init ACPI / gsi: Add gsi_mutex to synchronize acpi_register_gsi()/acpi_unregister_gsi() irqchip / GICv3: Add ACPI support for GICv3+ initialization irqchip / GICv3: Add stacked irqdomain support for ACPI based init
Tomasz Nowicki (3): ACPICA: Introduce GIC version for arm based system ACPI / irqchip: Add self-probe infrastructure to initialize IRQ controller irqchip / GICv3: Refactor gic_of_init() for GICv3 driver
arch/arm64/Kconfig | 1 + arch/arm64/include/asm/irq.h | 13 -- arch/arm64/kernel/acpi.c | 25 ---- drivers/acpi/Makefile | 1 + drivers/acpi/gsi.c | 39 ++--- drivers/acpi/irq.c | 40 ++++++ drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-gic-acpi.c | 116 +++++++++++++++ drivers/irqchip/irq-gic-v3.c | 267 ++++++++++++++++++++++++++++------- drivers/irqchip/irq-gic.c | 38 ++--- drivers/irqchip/irqchip.h | 12 ++ include/acpi/actbl1.h | 17 ++- include/asm-generic/vmlinux.lds.h | 13 ++ include/linux/acpi.h | 14 ++ include/linux/acpi_irq.h | 4 +- include/linux/irqchip/arm-gic-acpi.h | 12 +- include/linux/mod_devicetable.h | 7 + 18 files changed, 489 insertions(+), 134 deletions(-) create mode 100644 drivers/acpi/irq.c create mode 100644 drivers/irqchip/irq-gic-acpi.c
What's the connection between this and the Jiang Liu's patchset?
If you are mentioning Jiang Liu's patchset (Consolidate ACPI PCI root common code into ACPI core), there is no direct connection with my patchset, but this patch set is based on stacked irqdomain which was introduced by Jiang Liu, and this is needed to support PCI MSI on ARM64 in ACPI way.
Thanks Hanjun
On Wed, May 06, 2015 at 04:00:32AM +0100, Hanjun Guo wrote:
On 2015???05???06??? 04:28, Rafael J. Wysocki wrote:
On Tuesday, May 05, 2015 09:50:48 PM Hanjun Guo wrote:
This patch set introduce self-probe infrastructure to init IRQ controllers and stacked irqdomain support for ACPI based GICv2/3 init.
The self-probe infrastructure for ACPI GIC init is similar as IRQCHIP_DECLARE() and based on the GIC version support in ACPI MADT table.
We introduce acpi_irq_domain for GICv2/3 core domain to support stacked irqdomain, and pass the gsi (global system interrupt) as the agument (void *arg) for gic_irq_domain_alloc(), then we can alloc virqs via acpi_register_gsi() with stacked irqdomain.
I already compiled this patch set ok with both ACPI=on/off on ARM64 and also compiled ok on x86, tested with GICv2 init on FVP model and it boot successfully.
Next step I would consolidate all the ACPI GIC init into one file -- drivers/irqchip/irq-gic-acpi.c, and introduce ITS and IORT support.
please comment on this patchset to see if we are on the right direction.
Hanjun Guo (6): irqchip / gic: Add GIC version support in ACPI MADT irqchip: gic: ACPI: Use IRQCHIP_ACPI_DECLARE to simplify GICv2 init code irqchip / gic: Add stacked irqdomain support for ACPI based GICv2 init ACPI / gsi: Add gsi_mutex to synchronize acpi_register_gsi()/acpi_unregister_gsi() irqchip / GICv3: Add ACPI support for GICv3+ initialization irqchip / GICv3: Add stacked irqdomain support for ACPI based init
Tomasz Nowicki (3): ACPICA: Introduce GIC version for arm based system ACPI / irqchip: Add self-probe infrastructure to initialize IRQ controller irqchip / GICv3: Refactor gic_of_init() for GICv3 driver
arch/arm64/Kconfig | 1 + arch/arm64/include/asm/irq.h | 13 -- arch/arm64/kernel/acpi.c | 25 ---- drivers/acpi/Makefile | 1 + drivers/acpi/gsi.c | 39 ++--- drivers/acpi/irq.c | 40 ++++++ drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-gic-acpi.c | 116 +++++++++++++++ drivers/irqchip/irq-gic-v3.c | 267 ++++++++++++++++++++++++++++------- drivers/irqchip/irq-gic.c | 38 ++--- drivers/irqchip/irqchip.h | 12 ++ include/acpi/actbl1.h | 17 ++- include/asm-generic/vmlinux.lds.h | 13 ++ include/linux/acpi.h | 14 ++ include/linux/acpi_irq.h | 4 +- include/linux/irqchip/arm-gic-acpi.h | 12 +- include/linux/mod_devicetable.h | 7 + 18 files changed, 489 insertions(+), 134 deletions(-) create mode 100644 drivers/acpi/irq.c create mode 100644 drivers/irqchip/irq-gic-acpi.c
What's the connection between this and the Jiang Liu's patchset?
If you are mentioning Jiang Liu's patchset (Consolidate ACPI PCI root common code into ACPI core), there is no direct connection with my patchset, but this patch set is based on stacked irqdomain which was introduced by Jiang Liu, and this is needed to support PCI MSI on ARM64 in ACPI way.
Well, there is no direct connection but the two sets are fundamental to get PCIe ACPI support on arm64, as you mentioned this patchset is a requirement (stacked domains) for introducing ACPI PCI MSI support on arm64, that should be done with a separate patch on top of this series (I have one but first I have to find a decent solution for ACPI MSI frame <-> device matching).
Lorenzo
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Hanjun Guo -
Lorenzo Pieralisi -
Rafael J. Wysocki