Create GTDT table to convert arch timer for early boot.
Signed-off-by: Hanjun Guo hanjun.guo@linaro.org --- platforms/rtsm_ve-aemv8a.acpi/gtdt.asl | 37 +++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 13 deletions(-)
diff --git a/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl b/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl index 068ad4a..26eac38 100644 --- a/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl +++ b/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl @@ -1,6 +1,7 @@ /* * Copyright (c) 2013, Al Stone al.stone@linaro.org - * + * Hanjun Guo hanjun.guo@linaro.org + * * [GTDT] Generic Timer Description Table * Format: [ByteLength] FieldName : HexFieldValue * @@ -21,22 +22,32 @@ [0004] Flags (decoded below) : 00000001 Memory Present : 1
-[0004] Secure PL1 Interrupt : 00000000 -[0004] SPL1 Flags (decoded below) : 00000000 - Trigger Mode : 0 +/* In Foundation model's dts file, the last cell of interrupts + * is 0xff01, it means its cpu mask is FF, and trigger type + * and flag is 1 = low-to-high edge triggered. + * + * so in ACPI the Trigger Mode is 1 - Edge triggered, and + * Polarity is 0 - Active high as ACPI spec describled. + * + * using direct mapping for hwirqs, it means that we using + * ID [16, 31] for PPI, not [0, 15] used in FDT. + */ +[0004] Secure PL1 Interrupt : 0000001d +[0004] SPL1 Flags (decoded below) : 00000001 + Trigger Mode : 1 Polarity : 0
-[0004] Non-Secure PL1 Interrupt : 00000000 -[0004] NSPL1 Flags (decoded below) : 00000000 - Trigger Mode : 0 +[0004] Non-Secure PL1 Interrupt : 0000001e +[0004] NSPL1 Flags (decoded below) : 00000001 + Trigger Mode : 1 Polarity : 0
-[0004] Virtual Timer Interrupt : 00000000 -[0004] VT Flags (decoded below) : 00000000 - Trigger Mode : 0 +[0004] Virtual Timer Interrupt : 0000001b +[0004] VT Flags (decoded below) : 00000001 + Trigger Mode : 1 Polarity : 0
-[0004] Non-Secure PL2 Interrupt : 00000000 -[0004] NSPL2 Flags (decoded below) : 00000000 - Trigger Mode : 0 +[0004] Non-Secure PL2 Interrupt : 0000001a +[0004] NSPL2 Flags (decoded below) : 00000001 + Trigger Mode : 1 Polarity : 0
On 11/15/2013 03:24 AM, Hanjun Guo wrote:
Create GTDT table to convert arch timer for early boot.
Signed-off-by: Hanjun Guo hanjun.guo@linaro.org
platforms/rtsm_ve-aemv8a.acpi/gtdt.asl | 37 +++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 13 deletions(-)
diff --git a/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl b/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl index 068ad4a..26eac38 100644 --- a/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl +++ b/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl @@ -1,6 +1,7 @@ /*
- Copyright (c) 2013, Al Stone al.stone@linaro.org
Hanjun Guo <hanjun.guo@linaro.org>
- [GTDT] Generic Timer Description Table
- Format: [ByteLength] FieldName : HexFieldValue
@@ -21,22 +22,32 @@ [0004] Flags (decoded below) : 00000001 Memory Present : 1
-[0004] Secure PL1 Interrupt : 00000000 -[0004] SPL1 Flags (decoded below) : 00000000
Trigger Mode : 0+/* In Foundation model's dts file, the last cell of interrupts
- is 0xff01, it means its cpu mask is FF, and trigger type
- and flag is 1 = low-to-high edge triggered.
- so in ACPI the Trigger Mode is 1 - Edge triggered, and
- Polarity is 0 - Active high as ACPI spec describled.
- using direct mapping for hwirqs, it means that we using
- ID [16, 31] for PPI, not [0, 15] used in FDT.
- */
+[0004] Secure PL1 Interrupt : 0000001d +[0004] SPL1 Flags (decoded below) : 00000001
Trigger Mode : 1 Polarity : 0-[0004] Non-Secure PL1 Interrupt : 00000000 -[0004] NSPL1 Flags (decoded below) : 00000000
Trigger Mode : 0+[0004] Non-Secure PL1 Interrupt : 0000001e +[0004] NSPL1 Flags (decoded below) : 00000001
Trigger Mode : 1 Polarity : 0-[0004] Virtual Timer Interrupt : 00000000 -[0004] VT Flags (decoded below) : 00000000
Trigger Mode : 0+[0004] Virtual Timer Interrupt : 0000001b +[0004] VT Flags (decoded below) : 00000001
Trigger Mode : 1 Polarity : 0-[0004] Non-Secure PL2 Interrupt : 00000000 -[0004] NSPL2 Flags (decoded below) : 00000000
Trigger Mode : 0+[0004] Non-Secure PL2 Interrupt : 0000001a +[0004] NSPL2 Flags (decoded below) : 00000001
Trigger Mode : 1 Polarity : 0
Thanks for the clarification in the comments on the hwirq mapping.
Acked-by: Al Stone al.stone@linaro.org
On 15 November 2013 18:24, Hanjun Guo hanjun.guo@linaro.org wrote:
Create GTDT table to convert arch timer for early boot.
Signed-off-by: Hanjun Guo hanjun.guo@linaro.org
platforms/rtsm_ve-aemv8a.acpi/gtdt.asl | 37 +++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 13 deletions(-)
diff --git a/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl b/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl index 068ad4a..26eac38 100644 --- a/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl +++ b/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl @@ -1,6 +1,7 @@ /*
- Copyright (c) 2013, Al Stone al.stone@linaro.org
Hanjun Guo <hanjun.guo@linaro.org>
- [GTDT] Generic Timer Description Table
- Format: [ByteLength] FieldName : HexFieldValue
@@ -21,22 +22,32 @@ [0004] Flags (decoded below) : 00000001 Memory Present : 1
-[0004] Secure PL1 Interrupt : 00000000 -[0004] SPL1 Flags (decoded below) : 00000000
Trigger Mode : 0+/* In Foundation model's dts file, the last cell of interrupts
Oh, sorry, typo, should be RTSM model. will in update next version.
- is 0xff01, it means its cpu mask is FF, and trigger type
- and flag is 1 = low-to-high edge triggered.
- so in ACPI the Trigger Mode is 1 - Edge triggered, and
- Polarity is 0 - Active high as ACPI spec describled.
- using direct mapping for hwirqs, it means that we using
- ID [16, 31] for PPI, not [0, 15] used in FDT.
- */
+[0004] Secure PL1 Interrupt : 0000001d +[0004] SPL1 Flags (decoded below) : 00000001
Trigger Mode : 1 Polarity : 0-[0004] Non-Secure PL1 Interrupt : 00000000 -[0004] NSPL1 Flags (decoded below) : 00000000
Trigger Mode : 0+[0004] Non-Secure PL1 Interrupt : 0000001e +[0004] NSPL1 Flags (decoded below) : 00000001
Trigger Mode : 1 Polarity : 0-[0004] Virtual Timer Interrupt : 00000000 -[0004] VT Flags (decoded below) : 00000000
Trigger Mode : 0+[0004] Virtual Timer Interrupt : 0000001b +[0004] VT Flags (decoded below) : 00000001
Trigger Mode : 1 Polarity : 0-[0004] Non-Secure PL2 Interrupt : 00000000 -[0004] NSPL2 Flags (decoded below) : 00000000
Trigger Mode : 0+[0004] Non-Secure PL2 Interrupt : 0000001a +[0004] NSPL2 Flags (decoded below) : 00000001
Trigger Mode : 1 Polarity : 0-- 1.7.9.5
On Mon, Nov 18, 2013 at 09:01:24PM +0800, Hanjun Guo wrote:
On 15 November 2013 18:24, Hanjun Guo <[1]hanjun.guo@linaro.org> wrote:
Create GTDT table to convert arch timer for early boot. Signed-off-by: Hanjun Guo <[2]hanjun.guo@linaro.org> --- platforms/rtsm_ve-aemv8a.acpi/gtdt.asl | 37 +++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 13 deletions(-) diff --git a/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl b/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl index 068ad4a..26eac38 100644 --- a/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl +++ b/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl @@ -1,6 +1,7 @@ /* * Copyright (c) 2013, Al Stone <[3]al.stone@linaro.org> - * + * Hanjun Guo <[4]hanjun.guo@linaro.org> + * * [GTDT] Generic Timer Description Table * Format: [ByteLength] FieldName : HexFieldValue * @@ -21,22 +22,32 @@ [0004] Flags (decoded below) : 00000001 Memory Present : 1 -[0004] Secure PL1 Interrupt : 00000000 -[0004] SPL1 Flags (decoded below) : 00000000 - Trigger Mode : 0 +/* In Foundation model's dts file, the last cell of interruptsOh, sorry, typo, should be RTSM model. will in update next version.
I did it while adding it to the tree.
Graeme
+ * is 0xff01, it means its cpu mask is FF, and trigger type + * and flag is 1 = low-to-high edge triggered. + * + * so in ACPI the Trigger Mode is 1 - Edge triggered, and + * Polarity is 0 - Active high as ACPI spec describled. + * + * using direct mapping for hwirqs, it means that we using + * ID [16, 31] for PPI, not [0, 15] used in FDT. + */ +[0004] Secure PL1 Interrupt : 0000001d +[0004] SPL1 Flags (decoded below) : 00000001 + Trigger Mode : 1 Polarity : 0 -[0004] Non-Secure PL1 Interrupt : 00000000 -[0004] NSPL1 Flags (decoded below) : 00000000 - Trigger Mode : 0 +[0004] Non-Secure PL1 Interrupt : 0000001e +[0004] NSPL1 Flags (decoded below) : 00000001 + Trigger Mode : 1 Polarity : 0 -[0004] Virtual Timer Interrupt : 00000000 -[0004] VT Flags (decoded below) : 00000000 - Trigger Mode : 0 +[0004] Virtual Timer Interrupt : 0000001b +[0004] VT Flags (decoded below) : 00000001 + Trigger Mode : 1 Polarity : 0 -[0004] Non-Secure PL2 Interrupt : 00000000 -[0004] NSPL2 Flags (decoded below) : 00000000 - Trigger Mode : 0 +[0004] Non-Secure PL2 Interrupt : 0000001a +[0004] NSPL2 Flags (decoded below) : 00000001 + Trigger Mode : 1 Polarity : 0 -- 1.7.9.5References
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Linaro-acpi mailing list Linaro-acpi@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-acpi
On 2013-11-18 22:06, Graeme Gregory wrote:
On Mon, Nov 18, 2013 at 09:01:24PM +0800, Hanjun Guo wrote:
On 15 November 2013 18:24, Hanjun Guo <[1]hanjun.guo@linaro.org> wrote:
Create GTDT table to convert arch timer for early boot. Signed-off-by: Hanjun Guo <[2]hanjun.guo@linaro.org> --- platforms/rtsm_ve-aemv8a.acpi/gtdt.asl | 37 +++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 13 deletions(-) diff --git a/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl b/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl index 068ad4a..26eac38 100644 --- a/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl +++ b/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl @@ -1,6 +1,7 @@ /* * Copyright (c) 2013, Al Stone <[3]al.stone@linaro.org> - * + * Hanjun Guo <[4]hanjun.guo@linaro.org> + * * [GTDT] Generic Timer Description Table * Format: [ByteLength] FieldName : HexFieldValue * @@ -21,22 +22,32 @@ [0004] Flags (decoded below) : 00000001 Memory Present : 1 -[0004] Secure PL1 Interrupt : 00000000 -[0004] SPL1 Flags (decoded below) : 00000000 - Trigger Mode : 0 +/* In Foundation model's dts file, the last cell of interruptsOh, sorry, typo, should be RTSM model. will in update next version.
I did it while adding it to the tree.
Thank you :)
-
Al Stone -
Graeme Gregory -
Hanjun Guo