From: Mark Rutland mark.rutland@arm.com
We currently do an ldr from GICC_CTLR to w0, then immediately overwrite w0 with a mov. Reading the GICC_CTLR has no effect on the state of the GIC, so there's no reason to do the ldr. It's also inconsistent with the way we set the GICD_CTLR.
Fix this.
Signed-off-by: Mark Rutland mark.rutland@arm.com --- boot.S | 1 - 1 file changed, 1 deletion(-)
diff --git a/boot.S b/boot.S index a1f25e2..7c28e84 100644 --- a/boot.S +++ b/boot.S @@ -49,7 +49,6 @@ _start: str w0, [x1], #4
2: ldr x1, =GIC_CPU_BASE // GICC_CTLR - ldr w0, [x1] mov w0, #3 // EnableGrp0 | EnableGrp1 str w0, [x1]
From: Mark Rutland mark.rutland@arm.com
When we set the GICD_IGROUPRn registers, we have a dangling post-increment at the end which is never useful, being overwritten in every path. As we're only writing to 3 registers, the offsets of which can be represented in immediates, use movs with immediate offsets to perform the writes.
Reported-by: Nigel Stephens nigel.stephens@arm.com Signed-off-by: Mark Rutland mark.rutland@arm.com --- boot.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/boot.S b/boot.S index 7c28e84..95dc41e 100644 --- a/boot.S +++ b/boot.S @@ -43,10 +43,10 @@ _start:
1: ldr x1, =GIC_DIST_BASE + 0x80 // GICD_IGROUPR mov w0, #~0 // Grp1 interrupts - str w0, [x1], #4 + str w0, [x1] b.ne 2f // Only local interrupts for secondary CPUs - str w0, [x1], #4 - str w0, [x1], #4 + str w0, [x1, #4] + str w0, [x1, #8]
2: ldr x1, =GIC_CPU_BASE // GICC_CTLR mov w0, #3 // EnableGrp0 | EnableGrp1
From: Mark Rutland mark.rutland@arm.com
Currently. we don't ignore several files produced during the build in the .gitignore, which can make the output of git status very noisy.
Let's ignore all of the external dependencies we might add to the source directory (dtc, *.dts{i,}, *.cpio.gz), and all of the files we'll produce during the build (*.o, *.axf). Ignoring the general case of all of these files should produce less churn in .gitignore in future, and we can always add special exemptions if required.
Signed-off-by: Mark Rutland mark.rutland@arm.com --- .gitignore | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/.gitignore b/.gitignore index 20026d8..f63ca94 100644 --- a/.gitignore +++ b/.gitignore @@ -1,4 +1,8 @@ -linux-system.axf +*.axf +*.cpio.gz +*.dts +*.dtsi +*.o Image +dtc model.lds -boot.o
From: Mark Rutland mark.rutland@arm.com
PSCI needs to be able to drop cores to EL2 repeatedly, and it doesn't make sense to always throw CPUs through the original boot path.
This patch changes the EL drop into a macro, and moves it to a common file that can be used by different boot protocol / service implementations. While doing so, the SPSR value used is split out to be more legible.
Signed-off-by: Mark Rutland mark.rutland@arm.com --- boot.S | 8 ++++---- common.S | 26 ++++++++++++++++++++++++++ 2 files changed, 30 insertions(+), 4 deletions(-) create mode 100644 common.S
diff --git a/boot.S b/boot.S index 95dc41e..9cc382b 100644 --- a/boot.S +++ b/boot.S @@ -7,6 +7,8 @@ * found in the LICENSE.txt file. */
+#include "common.S" + .text
.globl _start @@ -61,10 +63,8 @@ _start: * Prepare the switch to the EL2_SP1 mode from EL3 */ ldr x0, =start_ns // Return after mode switch - mov x1, #0x3c9 // EL2_SP1 | D | A | I | F - msr elr_el3, x0 - msr spsr_el3, x1 - eret + mov x1, #SPSR_KERNEL + drop_el x1, x0
start_ns: /* diff --git a/common.S b/common.S new file mode 100644 index 0000000..d82d11b --- /dev/null +++ b/common.S @@ -0,0 +1,26 @@ +/* + * common.S - common definitions useful for boot code + * + * Copyright (C) 2013 ARM Limited. All rights reserved. + * + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE.txt file. + */ + +#define SPSR_A (1 << 8) /* System Error masked */ +#define SPSR_D (1 << 9) /* Debug masked */ +#define SPSR_I (1 << 7) /* IRQ masked */ +#define SPSR_F (1 << 6) /* FIQ masked */ +#define SPSR_EL2H (9 << 0) /* EL2 Handler mode */ + +#define SPSR_KERNEL (SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL2H) + + /* + * Drop EL to that specified by the spsr value in register mode, at + * the address specified in register addr. + */ + .macro drop_el mode addr + msr elr_el3, \addr + msr spsr_el3, \mode + eret + .endm
From: Mark Rutland mark.rutland@arm.com
Add a CURRENTEL_EL3 #define to make tests against the value of CurrentEL clearer.
Signed-off-by: Mark Rutland mark.rutland@arm.com --- boot.S | 2 +- common.S | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/boot.S b/boot.S index 9cc382b..69d1714 100644 --- a/boot.S +++ b/boot.S @@ -17,7 +17,7 @@ _start: * EL3 initialisation */ mrs x0, CurrentEL - cmp x0, #0xc // EL3? + cmp x0, #CURRENTEL_EL3 b.ne start_ns // skip EL3 initialisation
mov x0, #0x30 // RES1 diff --git a/common.S b/common.S index d82d11b..bbe005b 100644 --- a/common.S +++ b/common.S @@ -7,6 +7,8 @@ * found in the LICENSE.txt file. */
+#define CURRENTEL_EL3 (3 << 2) + #define SPSR_A (1 << 8) /* System Error masked */ #define SPSR_D (1 << 9) /* Debug masked */ #define SPSR_I (1 << 7) /* IRQ masked */
From: Mark Rutland mark.rutland@arm.com
To support more complex functionality, it would be nice if we could separate bits of the boot code into separate files.
This patch refactors the Makefile, allowing us to add more source files later without having to add a new rule for each file. The defines we pass to each object are also factored into separate lines for easier modification in future.
Signed-off-by: Mark Rutland mark.rutland@arm.com --- Makefile | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/Makefile b/Makefile index 38595a3..4d5a850 100644 --- a/Makefile +++ b/Makefile @@ -14,6 +14,12 @@ GIC_DIST_BASE := 0x2c001000 GIC_CPU_BASE := 0x2c002000 CNTFRQ := 0x01800000 # 24Mhz
+DEFINES += -DCNTFRQ=$(CNTFRQ) +DEFINES += -DGIC_CPU_BASE=$(GIC_CPU_BASE) +DEFINES += -DGIC_DIST_BASE=$(GIC_DIST_BASE) +DEFINES += -DSYSREGS_BASE=$(SYSREGS_BASE) +DEFINES += -DUART_BASE=$(UART_BASE) + #INITRD_FLAGS := -DUSE_INITRD CPPFLAGS += $(INITRD_FLAGS)
@@ -64,8 +70,8 @@ clean: $(IMAGE): boot.o model.lds fdt.dtb $(KERNEL) $(FILESYSTEM) $(LD) -o $@ --script=model.lds
-boot.o: $(BOOTLOADER) Makefile - $(CC) $(CPPFLAGS) -DCNTFRQ=$(CNTFRQ) -DUART_BASE=$(UART_BASE) -DSYSREGS_BASE=$(SYSREGS_BASE) -DGIC_DIST_BASE=$(GIC_DIST_BASE) -DGIC_CPU_BASE=$(GIC_CPU_BASE) -c -o $@ $(BOOTLOADER) +%.o: %.S Makefile + $(CC) $(CPPFLAGS) $(DEFINES) -c -o $@ $<
model.lds: $(LD_SCRIPT) Makefile $(CC) $(CPPFLAGS) -DPHYS_OFFSET=$(PHYS_OFFSET) -DMBOX_OFFSET=$(MBOX_OFFSET) -DKERNEL_OFFSET=$(KERNEL_OFFSET) -DFDT_OFFSET=$(FDT_OFFSET) -DFS_OFFSET=$(FS_OFFSET) -DKERNEL=$(KERNEL) -DFILESYSTEM=$(FILESYSTEM) -E -P -C -o $@ $<
From: Mark Rutland mark.rutland@arm.com
Currently we only test the Aff0 bits of the MPIDR to determine the 'primary' CPU. In multi-cluster systems, MPIDR.Aff{3,2,1} may not be zero, and there may by multiple CPUs where MPIDR.Aff0 is zero. In these systems we might determine that two cpus are the primary CPU.
This patch adds a MPIDR_ID_BITS mask, and uses it in all cases we test the MPIDR, making this safe for multi-cluster systems. This doesn't bring full support for multi-cluster systems, however, as they may require additional hardware to be set up (e.g. CCI).
Signed-off-by: Mark Rutland mark.rutland@arm.com --- boot.S | 6 ++++-- common.S | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/boot.S b/boot.S index 69d1714..eda42f9 100644 --- a/boot.S +++ b/boot.S @@ -36,7 +36,8 @@ _start: * registers. */ mrs x0, mpidr_el1 - tst x0, #15 + ldr x1, =MPIDR_ID_BITS + tst x0, x1 b.ne 1f // secondary CPU
ldr x1, =GIC_DIST_BASE // GICD_CTLR @@ -76,7 +77,8 @@ start_ns: mov x3, xzr
mrs x4, mpidr_el1 - tst x4, #15 + ldr x5, =MPIDR_ID_BITS + tst x4, x5 b.eq 2f
/* diff --git a/common.S b/common.S index bbe005b..70ed17e 100644 --- a/common.S +++ b/common.S @@ -7,6 +7,8 @@ * found in the LICENSE.txt file. */
+#define MPIDR_ID_BITS (0xff00ffffff) + #define CURRENTEL_EL3 (3 << 2)
#define SPSR_A (1 << 8) /* System Error masked */
From: Mark Rutland mark.rutland@arm.com
When we add PSCI, we'll want to share the same non-secure sysetem initialisation code. As we're going to want to put spin-table and PSCI implementations in separate files, it would be nice to have the initialisation code in its own file, to make clear the separation between early boot, platform interface code, and non-secure system initialisation.
Signed-off-by: Mark Rutland mark.rutland@arm.com --- Makefile | 4 ++-- boot.S | 18 +----------------- model.lds.S | 2 ++ ns.S | 41 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 46 insertions(+), 19 deletions(-) create mode 100644 ns.S
diff --git a/Makefile b/Makefile index 4d5a850..21fd8b8 100644 --- a/Makefile +++ b/Makefile @@ -65,9 +65,9 @@ DTC := $(if $(wildcard ./dtc), ./dtc, $(shell which dtc)) all: $(IMAGE)
clean: - rm -f $(IMAGE) boot.o model.lds fdt.dtb + rm -f $(IMAGE) boot.o ns.o model.lds fdt.dtb
-$(IMAGE): boot.o model.lds fdt.dtb $(KERNEL) $(FILESYSTEM) +$(IMAGE): boot.o ns.o model.lds fdt.dtb $(KERNEL) $(FILESYSTEM) $(LD) -o $@ --script=model.lds
%.o: %.S Makefile diff --git a/boot.S b/boot.S index eda42f9..391e74b 100644 --- a/boot.S +++ b/boot.S @@ -90,27 +90,11 @@ start_ns: br x4 // branch to the given address
2: - /* - * UART initialisation (38400 8N1) - */ - ldr x4, =UART_BASE // UART base - mov w5, #0x10 // ibrd - str w5, [x4, #0x24] - mov w5, #0xc300 - orr w5, w5, #0x0001 // cr - str w5, [x4, #0x30] - - /* - * CLCD output site MB - */ - ldr x4, =SYSREGS_BASE - ldr w5, =(1 << 31) | (1 << 30) | (7 << 20) | (0 << 16) // START|WRITE|MUXFPGA|SITE_MB - str wzr, [x4, #0xa0] // V2M_SYS_CFGDATA - str w5, [x4, #0xa4] // V2M_SYS_CFGCTRL
/* * Primary CPU */ + bl ns_init_system ldr x0, =dtb // device tree blob b kernel
diff --git a/model.lds.S b/model.lds.S index ec27433..23aa1bf 100644 --- a/model.lds.S +++ b/model.lds.S @@ -12,6 +12,7 @@ OUTPUT_ARCH(aarch64) TARGET(binary)
INPUT(./boot.o) +INPUT(./ns.o) INPUT(KERNEL) INPUT(./fdt.dtb)
@@ -23,6 +24,7 @@ SECTIONS { . = PHYS_OFFSET; .text : { boot.o } + .text : { ns.o } . = PHYS_OFFSET + MBOX_OFFSET; mbox = .; .mbox : { QUAD(0x0) } diff --git a/ns.S b/ns.S new file mode 100644 index 0000000..f432bcf --- /dev/null +++ b/ns.S @@ -0,0 +1,41 @@ +/* + * ns.S - code to initialise everything required when first booting non-secure. + * + * Copyright (C) 2013 ARM Limited. All rights reserved. + * + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE.txt file. + */ + +#define PL011_UARTIBRD 0x24 +#define PL011_UARTCR 0x30 + +#define V2M_SYS_CFGDATA 0xa0 +#define V2M_SYS_CFGCTRL 0xa4 + + .text + .globl ns_init_system + +ns_init_system: + /* + * UART initialisation (38400 8N1) + */ + ldr x4, =UART_BASE + mov w5, #0x10 + str w5, [x4, #PL011_UARTIBRD] + mov w5, #0xc300 + orr w5, w5, #0x0001 + str w5, [x4, #PL011_UARTCR] + + /* + * CLCD output site MB + */ + ldr x4, =SYSREGS_BASE + ldr w5, =(1 << 31) | (1 << 30) | (7 << 20) | (0 << 16) // START|WRITE|MUXFPGA|SITE_MB + str wzr, [x4, #V2M_SYS_CFGDATA] + str w5, [x4, #V2M_SYS_CFGCTRL] + + ret + + .ltorg + .org 0x40
From: Mark Rutland mark.rutland@arm.com
Currently the bootwrapper still lumps together logically distinct pieces of hardware initialisation, making porting to new platforms or adding new features difficult. It would be nicer if we could separate some of the functional units to make the code clearer and easier to extend.
To this end, this patch factors the secure GIC initialisation into its own file. Additionally, the code is modified to route all interrupts to the non-secure side, not just the first 64.
Signed-off-by: Mark Rutland mark.rutland@arm.com --- Makefile | 4 ++-- boot.S | 27 +-------------------------- gic.S | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ model.lds.S | 2 ++ 4 files changed, 54 insertions(+), 28 deletions(-) create mode 100644 gic.S
diff --git a/Makefile b/Makefile index 21fd8b8..ad969ed 100644 --- a/Makefile +++ b/Makefile @@ -65,9 +65,9 @@ DTC := $(if $(wildcard ./dtc), ./dtc, $(shell which dtc)) all: $(IMAGE)
clean: - rm -f $(IMAGE) boot.o ns.o model.lds fdt.dtb + rm -f $(IMAGE) boot.o gic.o ns.o model.lds fdt.dtb
-$(IMAGE): boot.o ns.o model.lds fdt.dtb $(KERNEL) $(FILESYSTEM) +$(IMAGE): boot.o gic.o ns.o model.lds fdt.dtb $(KERNEL) $(FILESYSTEM) $(LD) -o $@ --script=model.lds
%.o: %.S Makefile diff --git a/boot.S b/boot.S index 391e74b..e4577fb 100644 --- a/boot.S +++ b/boot.S @@ -31,32 +31,7 @@ _start: ldr x0, =CNTFRQ msr cntfrq_el0, x0
- /* - * Check for the primary CPU to avoid a race on the distributor - * registers. - */ - mrs x0, mpidr_el1 - ldr x1, =MPIDR_ID_BITS - tst x0, x1 - b.ne 1f // secondary CPU - - ldr x1, =GIC_DIST_BASE // GICD_CTLR - mov w0, #3 // EnableGrp0 | EnableGrp1 - str w0, [x1] - -1: ldr x1, =GIC_DIST_BASE + 0x80 // GICD_IGROUPR - mov w0, #~0 // Grp1 interrupts - str w0, [x1] - b.ne 2f // Only local interrupts for secondary CPUs - str w0, [x1, #4] - str w0, [x1, #8] - -2: ldr x1, =GIC_CPU_BASE // GICC_CTLR - mov w0, #3 // EnableGrp0 | EnableGrp1 - str w0, [x1] - - mov w0, #1 << 7 // allow NS access to GICC_PMR - str w0, [x1, #4] // GICC_PMR + bl gic_secure_init
msr sctlr_el2, xzr
diff --git a/gic.S b/gic.S new file mode 100644 index 0000000..e16b64a --- /dev/null +++ b/gic.S @@ -0,0 +1,49 @@ +/* + * gic.S - Secure gic initialisation for stand-alone Linux booting + * + * Copyright (C) 2013 ARM Limited. All rights reserved. + * + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE.txt file. + */ + +#include "common.S" + + .text + + .global gic_secure_init + +gic_secure_init: + /* + * Check for the primary CPU to avoid a race on the distributor + * registers. + */ + mrs x0, mpidr_el1 + ldr x1, =MPIDR_ID_BITS + tst x0, x1 + b.ne 1f // secondary CPU + + ldr x1, =GIC_DIST_BASE // GICD_CTLR + mov w0, #3 // EnableGrp0 | EnableGrp1 + str w0, [x1] + +1: ldr x1, =GIC_DIST_BASE + 0x80 // GICD_IGROUPR + mov w0, #~0 // Grp1 interrupts + str w0, [x1] + b.ne 2f // Only local interrupts for secondary CPUs + ldr x2, =GIC_DIST_BASE + 0x04 // GICD_TYPER + ldr w3, [x2] + ands w3, w3, #0x1f // ITLinesNumber + b.eq 2f +1: str w0, [x1, #4]! + subs w3, w3, #1 + b.ne 1b + +2: ldr x1, =GIC_CPU_BASE // GICC_CTLR + mov w0, #3 // EnableGrp0 | EnableGrp1 + str w0, [x1] + + mov w0, #1 << 7 // allow NS access to GICC_PMR + str w0, [x1, #4] // GICC_PMR + + ret diff --git a/model.lds.S b/model.lds.S index 23aa1bf..92a3b8a 100644 --- a/model.lds.S +++ b/model.lds.S @@ -12,6 +12,7 @@ OUTPUT_ARCH(aarch64) TARGET(binary)
INPUT(./boot.o) +INPUT(./gic.o) INPUT(./ns.o) INPUT(KERNEL) INPUT(./fdt.dtb) @@ -24,6 +25,7 @@ SECTIONS { . = PHYS_OFFSET; .text : { boot.o } + .text : { gic.o } .text : { ns.o } . = PHYS_OFFSET + MBOX_OFFSET; mbox = .;
From: Mark Rutland mark.rutland@arm.com
This patch factors out the spin-table boot protocol into its own file, leaving boot.S to do all of the required EL3 initialisation, and calling upon ns_init to perform EL2 initialisation.
Signed-off-by: Mark Rutland mark.rutland@arm.com --- Makefile | 7 ++++--- boot.S | 42 +++--------------------------------------- model.lds.S | 2 ++ spin.S | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 66 insertions(+), 42 deletions(-) create mode 100644 spin.S
diff --git a/Makefile b/Makefile index ad969ed..827dc7c 100644 --- a/Makefile +++ b/Makefile @@ -24,6 +24,7 @@ DEFINES += -DUART_BASE=$(UART_BASE) CPPFLAGS += $(INITRD_FLAGS)
BOOTLOADER := boot.S +BOOTMETHOD := spin.o MBOX_OFFSET := 0xfff8 KERNEL := Image KERNEL_OFFSET := 0x80000 @@ -65,16 +66,16 @@ DTC := $(if $(wildcard ./dtc), ./dtc, $(shell which dtc)) all: $(IMAGE)
clean: - rm -f $(IMAGE) boot.o gic.o ns.o model.lds fdt.dtb + rm -f $(IMAGE) boot.o gic.o ns.o $(BOOTMETHOD) model.lds fdt.dtb
-$(IMAGE): boot.o gic.o ns.o model.lds fdt.dtb $(KERNEL) $(FILESYSTEM) +$(IMAGE): boot.o gic.o ns.o $(BOOTMETHOD) model.lds fdt.dtb $(KERNEL) $(FILESYSTEM) $(LD) -o $@ --script=model.lds
%.o: %.S Makefile $(CC) $(CPPFLAGS) $(DEFINES) -c -o $@ $<
model.lds: $(LD_SCRIPT) Makefile - $(CC) $(CPPFLAGS) -DPHYS_OFFSET=$(PHYS_OFFSET) -DMBOX_OFFSET=$(MBOX_OFFSET) -DKERNEL_OFFSET=$(KERNEL_OFFSET) -DFDT_OFFSET=$(FDT_OFFSET) -DFS_OFFSET=$(FS_OFFSET) -DKERNEL=$(KERNEL) -DFILESYSTEM=$(FILESYSTEM) -E -P -C -o $@ $< + $(CC) $(CPPFLAGS) -DPHYS_OFFSET=$(PHYS_OFFSET) -DMBOX_OFFSET=$(MBOX_OFFSET) -DKERNEL_OFFSET=$(KERNEL_OFFSET) -DFDT_OFFSET=$(FDT_OFFSET) -DFS_OFFSET=$(FS_OFFSET) -DKERNEL=$(KERNEL) -DFILESYSTEM=$(FILESYSTEM) -DBOOTMETHOD=$(BOOTMETHOD) -E -P -C -o $@ $<
ifeq ($(DTC),) $(error No dtc found! You can git clone from git://git.jdl.com/software/dtc.git) diff --git a/boot.S b/boot.S index e4577fb..29ffb6f 100644 --- a/boot.S +++ b/boot.S @@ -18,7 +18,7 @@ _start: */ mrs x0, CurrentEL cmp x0, #CURRENTEL_EL3 - b.ne start_ns // skip EL3 initialisation + b.ne start_no_el3 // skip EL3 initialisation
mov x0, #0x30 // RES1 orr x0, x0, #(1 << 0) // Non-secure EL1 @@ -35,44 +35,8 @@ _start:
msr sctlr_el2, xzr
- /* - * Prepare the switch to the EL2_SP1 mode from EL3 - */ - ldr x0, =start_ns // Return after mode switch - mov x1, #SPSR_KERNEL - drop_el x1, x0 - -start_ns: - /* - * Kernel parameters - */ - mov x0, xzr - mov x1, xzr - mov x2, xzr - mov x3, xzr - - mrs x4, mpidr_el1 - ldr x5, =MPIDR_ID_BITS - tst x4, x5 - b.eq 2f - - /* - * Secondary CPUs - */ -1: wfe - ldr x4, mbox - cbz x4, 1b - br x4 // branch to the given address - -2: - - /* - * Primary CPU - */ - bl ns_init_system - ldr x0, =dtb // device tree blob - b kernel + b start_el3
.ltorg
- .org 0x200 + .org 0x100 diff --git a/model.lds.S b/model.lds.S index 92a3b8a..3931857 100644 --- a/model.lds.S +++ b/model.lds.S @@ -14,6 +14,7 @@ TARGET(binary) INPUT(./boot.o) INPUT(./gic.o) INPUT(./ns.o) +INPUT(./BOOTMETHOD) INPUT(KERNEL) INPUT(./fdt.dtb)
@@ -27,6 +28,7 @@ SECTIONS .text : { boot.o } .text : { gic.o } .text : { ns.o } + .text : { BOOTMETHOD } . = PHYS_OFFSET + MBOX_OFFSET; mbox = .; .mbox : { QUAD(0x0) } diff --git a/spin.S b/spin.S new file mode 100644 index 0000000..4ad3cf2 --- /dev/null +++ b/spin.S @@ -0,0 +1,57 @@ +/* + * spin.S - spin-table boot protocol implementation + * + * Copyright (C) 2013 ARM Limited. All rights reserved. + * + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE.txt file. + */ + +#include "common.S" + + .text + + .globl start_no_el3 + .globl start_el3 + +start_el3: + /* + * Prepare the switch to the EL2_SP1 mode from EL3 + */ + ldr x0, =start_no_el3 // Return after mode switch + mov x1, #SPSR_KERNEL + drop_el x1, x0 + +start_no_el3: + /* + * Kernel parameters + */ + mov x0, xzr + mov x1, xzr + mov x2, xzr + mov x3, xzr + + mrs x4, mpidr_el1 + ldr x5, =MPIDR_ID_BITS + tst x4, x5 + b.eq 2f + + /* + * Secondary CPUs + */ +1: wfe + ldr x4, mbox + cbz x4, 1b + br x4 // branch to the given address + +2: + /* + * Primary CPU + */ + bl ns_init_system + ldr x0, =dtb // device tree blob + b kernel + + .ltorg + + .org 0x80
From: Mark Rutland mark.rutland@arm.com
Linux expects to be handed a system with caches disabled and invalidated. While the model currently brings CPUs up with caches invalidated, we'll need to invalidate caches when leaving the bootwrapper if we enable them within the bootwrapper (e.g. for the use of exclusive operations), as lines may be allocated.
This patch adds code to invalidate the dcaches and icaches. It is not yet called.
Signed-off-by: Mark Rutland mark.rutland@arm.com --- Makefile | 4 +-- cache.S | 81 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ model.lds.S | 2 ++ 3 files changed, 85 insertions(+), 2 deletions(-) create mode 100644 cache.S
diff --git a/Makefile b/Makefile index 827dc7c..50dca3b 100644 --- a/Makefile +++ b/Makefile @@ -66,9 +66,9 @@ DTC := $(if $(wildcard ./dtc), ./dtc, $(shell which dtc)) all: $(IMAGE)
clean: - rm -f $(IMAGE) boot.o gic.o ns.o $(BOOTMETHOD) model.lds fdt.dtb + rm -f $(IMAGE) boot.o cache.o gic.o ns.o $(BOOTMETHOD) model.lds fdt.dtb
-$(IMAGE): boot.o gic.o ns.o $(BOOTMETHOD) model.lds fdt.dtb $(KERNEL) $(FILESYSTEM) +$(IMAGE): boot.o cache.o gic.o ns.o $(BOOTMETHOD) model.lds fdt.dtb $(KERNEL) $(FILESYSTEM) $(LD) -o $@ --script=model.lds
%.o: %.S Makefile diff --git a/cache.S b/cache.S new file mode 100644 index 0000000..ce928eb --- /dev/null +++ b/cache.S @@ -0,0 +1,81 @@ +/* + * cache.S - simple cache clean+invalidate code for stand-alone Linux booting + * + * Copyright (C) 2013 ARM Limited. All rights reserved. + * + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE.txt file. + */ + .text + + .globl flush_caches + +flush_caches: + mrs x0, clidr_el1 + + /* find what out the max cache level to flush */ + lsr x1, x0, #24 + and x1, x0, #(0x7) + cbz x1, dcaches_done + + mov x2, #0 /* level 1 (represented 1-off) */ + +1: cmp x2, x1 /* gone over all levels */ + b.eq dcaches_done + + /* find out if we have a cache at this level */ + add x3, x2, x2, lsl 1 /* amount to shift for CtypeN */ + lsr x4, x0, x3 + and x4, x4, #0x7 + + cmp x4, #1 + b.eq 5f /* no dcache at this level */ + + lsl x3, x2, #1 + msr csselr_el1, x3 + isb + mrs x3, ccsidr_el1 + and x4, x3, #0x7 + add x4, x4, #4 /* log2 line size, corrected for offset */ + ubfx x6, x3, #3, #10 /* ways */ + clz w5, w6 /* log2 ways, rounded down */ + ubfx x7, x3, #13, #15 /* sets */ + + /* loop over ways */ +2: mov x8, x7 /* temporary (sets) */ + + /* loop over sets */ + /* build the set/way command */ +3: lsl x9, x2, #1 /* cache level (-1) */ + lsl x10, x8, x5 /* way << shift */ + orr x9, x9, x10 + lsl x10, x6, x4 /* set << line size */ + orr x9, x9, x10 + + dc cisw, x9 + dsb sy + + cbz x8, 4f + sub x8, x8, #1 + b 3b + +4: /* completed all sets for this way */ + cbz x6, 5f + sub x6, x6, #1 + b 2b + +5: /* finished this level, try the next */ + dsb sy + add x2, x2, #1 + b 1b + +dcaches_done: + + dsb sy + ic iallu + dsb sy + isb + ret + + .ltorg + .org 0x100 diff --git a/model.lds.S b/model.lds.S index 3931857..53d0f7f 100644 --- a/model.lds.S +++ b/model.lds.S @@ -12,6 +12,7 @@ OUTPUT_ARCH(aarch64) TARGET(binary)
INPUT(./boot.o) +INPUT(./cache.o) INPUT(./gic.o) INPUT(./ns.o) INPUT(./BOOTMETHOD) @@ -26,6 +27,7 @@ SECTIONS { . = PHYS_OFFSET; .text : { boot.o } + .text : { cache.o } .text : { gic.o } .text : { ns.o } .text : { BOOTMETHOD }
From: Mark Rutland mark.rutland@arm.com
This patch adds a simple PSCI implementation, only supporting CPU_ON and CPU_OFF. As this does not communicate with any hardware power controller (yet), CPUs spin in an internal pen, with a wfe to limit their polling speed.
While the model brings up CPUs with caches invalidated, we enable caches and the MMU to allow the use of exclusive operations in the bootwrapper, and thus the cache may allocate entries while in EL3. As PSCI requires that caches are invalid when executing from a CPU_ON entry point, the caches must be cleaned and invalided when we drop to EL2. This cleaning is performed in a shim in EL2 as this is simpler than enabling/disabling caches and the MMU on each SMC.
The list of all CPU IDs (MPIDRS with non-aff bits masked out) in the system must be provided in the Makefile as the comma-separated list CPU_IDs, to enable the bootwrapper to differentiate CPUs and provide the correct error messages if for example the OS attempts to power on a CPU multiple times. If this list does not match the CPUs present, it may not be possible to bring some CPUs online, and the PSCI implementation may erroneously acknowledge power on requests for non-existent CPUs.
Signed-off-by: Mark Rutland mark.rutland@arm.com --- Makefile | 8 +- mmu.S | 146 +++++++++++++++++++++++++++++++++ model.lds.S | 2 + psci.S | 262 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 415 insertions(+), 3 deletions(-) create mode 100644 mmu.S create mode 100644 psci.S
diff --git a/Makefile b/Makefile index 50dca3b..18bc910 100644 --- a/Makefile +++ b/Makefile @@ -13,8 +13,10 @@ SYSREGS_BASE := 0x1c010000 GIC_DIST_BASE := 0x2c001000 GIC_CPU_BASE := 0x2c002000 CNTFRQ := 0x01800000 # 24Mhz +CPU_IDS ?= 0x0,0x1,0x2,0x3
DEFINES += -DCNTFRQ=$(CNTFRQ) +DEFINES += -DCPU_IDS=$(CPU_IDS) DEFINES += -DGIC_CPU_BASE=$(GIC_CPU_BASE) DEFINES += -DGIC_DIST_BASE=$(GIC_DIST_BASE) DEFINES += -DSYSREGS_BASE=$(SYSREGS_BASE) @@ -24,7 +26,7 @@ DEFINES += -DUART_BASE=$(UART_BASE) CPPFLAGS += $(INITRD_FLAGS)
BOOTLOADER := boot.S -BOOTMETHOD := spin.o +BOOTMETHOD := psci.o MBOX_OFFSET := 0xfff8 KERNEL := Image KERNEL_OFFSET := 0x80000 @@ -66,9 +68,9 @@ DTC := $(if $(wildcard ./dtc), ./dtc, $(shell which dtc)) all: $(IMAGE)
clean: - rm -f $(IMAGE) boot.o cache.o gic.o ns.o $(BOOTMETHOD) model.lds fdt.dtb + rm -f $(IMAGE) boot.o cache.o gic.o mmu.o ns.o $(BOOTMETHOD) model.lds fdt.dtb
-$(IMAGE): boot.o cache.o gic.o ns.o $(BOOTMETHOD) model.lds fdt.dtb $(KERNEL) $(FILESYSTEM) +$(IMAGE): boot.o cache.o gic.o mmu.o ns.o $(BOOTMETHOD) model.lds fdt.dtb $(KERNEL) $(FILESYSTEM) $(LD) -o $@ --script=model.lds
%.o: %.S Makefile diff --git a/mmu.S b/mmu.S new file mode 100644 index 0000000..5468b5e --- /dev/null +++ b/mmu.S @@ -0,0 +1,146 @@ +/* + * mmu.S - EL3 MMU identity map code to enable the use of exclusives. + * + * Copyright (C) 2013 ARM Limited. All rights reserved. + * + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE.txt file. + */ + +#define ATTR_UPPER_XN (1 << 54) /* Non-Executable */ +#define ATTR_UPPER_PXN (1 << 53) /* Non-Executable */ + +#define MEM_ATTR_UPPER 0 +#define DEV_ATTR_UPPER (ATTR_UPPER_XN | ATTR_UPPER_PXN) + +#define ATTR_LOWER_AF (1 << 10) /* Don't trap accesses */ +#define ATTR_LOWER_SH_IS (3 << 8) /* Inner shareable */ +#define ATTR_LOWER_SH_NS (0 << 8) /* Inner shareable */ + +#define ATTR_LOWER_AP_RW_ANY (1 << 6) /* Writeable at any privilege level */ + +#define ATTR_LOWER_NS (1 << 5) /* non-secure PA */ +#define ATTR_LOWER_ATTRINDEX(n) ((n) << 2) /* MAIR_EL3 attrN */ + +#define MEM_ATTR_LOWER (ATTR_LOWER_AF | ATTR_LOWER_SH_IS | \ + ATTR_LOWER_NS | ATTR_LOWER_ATTRINDEX(0)) + +#define DEV_ATTR_LOWER (ATTR_LOWER_AF | ATTR_LOWER_SH_NS | \ + ATTR_LOWER_NS | ATTR_LOWER_ATTRINDEX(1)) + +#define BLOCK_VALID (1 << 0) /* Valid block entry */ + +/* + * the top 10 bits of PA [39:30] + */ +#define BLOCK_1GB_PA(_pa) ((_pa) & (0x3ff << 30)) + +#define BLOCK_MEM_1GB(_pa) (MEM_ATTR_UPPER | BLOCK_1GB_PA(_pa) | \ + MEM_ATTR_LOWER | BLOCK_VALID) + +#define BLOCK_DEV_1GB(_pa) (DEV_ATTR_UPPER | BLOCK_1GB_PA(_pa) | \ + DEV_ATTR_LOWER | BLOCK_VALID) + + .data + +#define BLOCK_INVALID (0 << 0) + + /* + * 1st level page table. + * 512 entries, each covering 1GB. + */ + .align 12 +pgtable_l1: + .quad BLOCK_DEV_1GB(0x00000000) + .quad BLOCK_INVALID + .quad BLOCK_MEM_1GB(0x80000000) + .quad BLOCK_MEM_1GB(0xC0000000) + .rept 30 + .quad BLOCK_INVALID + .endr + .quad BLOCK_MEM_1GB(0x880000000) + .quad BLOCK_MEM_1GB(0x8C0000000) + .rept (512-36) + .quad BLOCK_INVALID + .endr + +/* + * attr0: Normal memory, outer non-cacheable, inner write-through non-transient + * attrN: device-nGnRnE + */ +#define MAIR_ATTR 0x48 + +#define TCR_RES1 ((1 << 31) | (1 << 23)) +#define TCR_PS (2 << 16) /* 40 bits */ +#define TCR_TG0 (0 << 14) /* 4KB */ +#define TCR_SH0 (3 << 12) /* inner shareable */ +#define TCR_ORGN0 (0 << 10) /* normal outer non-cacheable */ +#define TCR_IRGN0 (2 << 8) /* normal inner write-through */ +#define TCR_T0SZ (25 << 0) /* 2^39 bits (2^(64-25)) */ + +#define TCR_VAL (TCR_RES1 | TCR_PS | TCR_TG0 | TCR_SH0 | TCR_ORGN0 | TCR_IRGN0 | TCR_T0SZ) + +#define SCTLR_RES1 ((3 << 28) | (3 << 22) | (1 << 18) | (1 << 16) | (1 << 11) | (3 << 4)) +#define SCTLR_EE (0 << 25) /* little endian */ +#define SCTLR_WXN (0 << 19) /* regions with write permission not forced to XN */ +#define SCTLR_I (0 << 12) /* Disable I cache */ +#define SCTLR_SA (0 << 3) /* No stack alignment checking */ +#define SCTLR_C (0 << 2) /* Disable caches */ +#define SCTLR_A (0 << 1) /* No alignment checking */ +#define SCTLR_M (1 << 0) /* enable MMU */ + +#define SCTLR_VAL (SCTLR_RES1 | SCTLR_EE | SCTLR_WXN | SCTLR_I | \ + SCTLR_SA | SCTLR_C | SCTLR_A | SCTLR_M) + + .text + + .globl switch_to_idmap + .globl switch_to_physmap + +switch_to_idmap: + + mov x28, x30 + + /* + * We assume that the d-caches are invalid at power-on, and hence do + * not need to be invalidated. However the icache(s) and TLBs may still + * be filled with garbage. + */ + ic iallu + tlbi alle3 + dsb sy + isb + + adr x0, pgtable_l1 + msr ttbr0_el3, x0 + + ldr x0, =MAIR_ATTR + msr mair_el3, x0 + + ldr x0, =TCR_VAL + msr tcr_el3, x0 + + isb + + ldr x0, =SCTLR_VAL + msr sctlr_el3, x0 + + isb + + /* Identity map now active, branch back to phys/virt address */ + ret x28 + +switch_to_physmap: + mov x28, x30 + + mrs x0, sctlr_el3 + mov x1, #(SCTLR_M | SCTLR_C) + bic x0, x0, x1 + msr sctlr_el3, x0 + + isb + + bl flush_caches + + ret x28 + diff --git a/model.lds.S b/model.lds.S index 53d0f7f..401ea5f 100644 --- a/model.lds.S +++ b/model.lds.S @@ -14,6 +14,7 @@ TARGET(binary) INPUT(./boot.o) INPUT(./cache.o) INPUT(./gic.o) +INPUT(./mmu.o) INPUT(./ns.o) INPUT(./BOOTMETHOD) INPUT(KERNEL) @@ -29,6 +30,7 @@ SECTIONS .text : { boot.o } .text : { cache.o } .text : { gic.o } + .text : { mmu.o } .text : { ns.o } .text : { BOOTMETHOD } . = PHYS_OFFSET + MBOX_OFFSET; diff --git a/psci.S b/psci.S new file mode 100644 index 0000000..5f59e2a --- /dev/null +++ b/psci.S @@ -0,0 +1,262 @@ +/* + * psci.S - basic PSCI implementation + * + * Copyright (C) 2013 ARM Limited. All rights reserved. + * + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE.txt file. + */ +#include "common.S" + +#define PSCI_CPU_OFF 0x84000001 +#define PSCI_CPU_ON 0x84000002 + +#define PSCI_RET_SUCCESS 0 +#define PSCI_RET_NOT_IMPL (-1) +#define PSCI_RET_INVALID (-2) +#define PSCI_RET_DENIED (-3) + +#ifndef CPU_IDS +#error No CPU MPIDRs provided. +#endif + +#define MPIDR_INVALID (-1) +#define ADDR_INVALID (-1) + + .macro ventry label + .align 7 + b \label + .endm + + .data + + .align 11 +vector: + // current EL, SP_EL0 + ventry err_exception // synchronous + ventry err_exception // IRQ + ventry err_exception // FIQ + ventry err_exception // SError + + // current EL, SP_ELx + ventry err_exception + ventry err_exception + ventry err_exception + ventry err_exception + + // lower EL, AArch64 + ventry psci_call64 + ventry err_exception + ventry err_exception + ventry err_exception + + // lower EL, AArch32 + ventry psci_call32 + ventry err_exception + ventry err_exception + ventry err_exception + + /* + * Array of the CPU ID (MPIDR & MPIDR_ID_BITS) of each CPU in the system. + * The index into the array is used as a logical id, and an index into + * the branch table. The branch table is automatically padded to the + * same size as the id table. + * + * The first CPU in the table is considered to be the primary CPU, and + * is the only CPU to immediately branch off to the kernel. + */ + .align 3 +id_table: + .quad CPU_IDS +__id_end: + .quad MPIDR_INVALID + +.equ nr_cpus, ((__id_end - id_table) / 8) + +branch_table: + .rept (nr_cpus) + .quad ADDR_INVALID + .endr + + .text + + .globl start_no_el3 + .globl start_el3 + +err_exception: + b err_exception + +psci_call32: + mov w0, PSCI_RET_NOT_IMPL + eret + +psci_call64: + ldr x7, =PSCI_CPU_OFF + cmp x0, x7 + b.eq psci_cpu_off + + ldr x7, =PSCI_CPU_ON + cmp x0, x7 + b.eq psci_cpu_on + + mov x0, PSCI_RET_NOT_IMPL + eret + +/* + * x1 - optional power state parameter, ignored here + */ +psci_cpu_off: + mrs x0, mpidr_el1 + ldr x1, =MPIDR_ID_BITS + and x0, x0, x1 + bl find_logical_id + adr x1, branch_table + mov x2, #ADDR_INVALID + str x2, [x1, x0, lsl #3] + + b spin + +/* + * x1 - target cpu + * x2 - address + */ +psci_cpu_on: + mov x15, x30 + mov x14, x2 + mov x0, x1 + + bl find_logical_id + cmp x0, #-1 + b.eq 1f + + adr x3, branch_table + add x3, x3, x0, lsl #3 + + ldr x4, =ADDR_INVALID + + ldxr x5, [x3] + cmp x4, x5 + b.ne 1f + + stxr w4, x14, [x3] + cbnz w4, 1f + + dsb ishst + sev + + mov x0, #PSCI_RET_SUCCESS + mov x30, x15 + eret + +1: mov x0, #PSCI_RET_DENIED + mov x30, x15 + eret + + +/* + * Takes masked MPIDR in x0, returns logical id in x0 + * Returns -1 for unknown MPIDRs + * Clobbers x1, x2, x3 + */ +find_logical_id: +__find_logical_index: + adr x2, id_table + mov x1, xzr +1: mov x3, #nr_cpus // check we haven't walked off the end of the array + cmp x1, x3 + b.gt 3f + ldr x3, [x2, x1, lsl #3] + cmp x3, x0 + b.eq 2f + add x1, x1, #1 + b 1b +2: mov x0, x1 + ret +3: mov x0, #-1 + ret + +setup_vector: + adr x0, vector + msr VBAR_EL3, x0 + isb + ret + +start_el3: + bl setup_vector + bl switch_to_idmap + + /* only boot the primary cpu (entry 0 in the table) */ + mrs x0, mpidr_el1 + ldr x1, =MPIDR_ID_BITS + and x0, x0, x1 + bl find_logical_id + cbnz x0, spin + + adr x2, branch_table + adr x1, start_cpu0 + str x1, [x2] + sevl + b spin + +/* + * Poll the release table, waiting for a valid address to appear. + * When a valid address appears, branch to it. + */ +spin: + mrs x0, mpidr_el1 + ldr x1, =MPIDR_ID_BITS + and x0, x0, x1 + bl find_logical_id + cmp x0, #-1 + b.eq spin_dead + + adr x1, branch_table + mov x3, #ADDR_INVALID + + add x1, x1, x0, lsl #3 + +1: wfe + ldr x2, [x1] + cmp x2, x3 + b.eq 1b + + mov x3, #SPSR_KERNEL + adr x4, el2_trampoline + mov x0, x2 + drop_el x3, x4 + +/* + * This PSCI implementation requires EL3. Without EL3 we'll only boot the + * primary cpu, all others will be trapped in an infinite loop. + */ +start_no_el3: + mrs x0, mpidr_el1 + ldr x1, =MPIDR_ID_BITS + and x0, x0, x1 + bl find_logical_id + cbz x0, start_cpu0 +spin_dead: + wfe + b spin_dead + + +/* + * Clean and invalidate the caches at EL2 to simplify EL3's cache usage. + */ +el2_trampoline: + mov x15, x0 + bl flush_caches + br x15 + +start_cpu0: + /* + * Kernel parameters + */ + mov x0, xzr + mov x1, xzr + mov x2, xzr + mov x3, xzr + + bl ns_init_system + ldr x0, =dtb + b kernel
From: Graeme Gregory graeme.gregory@linaro.org
For armv8 ACPI on model before there is bootloader support pass an ACPI blob via the chosen node of the FDT. This is the same method used on armv7 prototype.
Signed-off-by: Graeme Gregory graeme.gregory@linaro.org Signed-off-by: Hanjun Guo hanjun.guo@linaro.org --- Makefile | 36 +++++++++++++++++++++++++++--------- model.lds.S | 9 +++++++++ 2 files changed, 36 insertions(+), 9 deletions(-)
diff --git a/Makefile b/Makefile index 18bc910..24eb06b 100644 --- a/Makefile +++ b/Makefile @@ -23,7 +23,8 @@ DEFINES += -DSYSREGS_BASE=$(SYSREGS_BASE) DEFINES += -DUART_BASE=$(UART_BASE)
#INITRD_FLAGS := -DUSE_INITRD -CPPFLAGS += $(INITRD_FLAGS) +ACPI_FLAGS := -DUSE_ACPI +CPPFLAGS += $(INITRD_FLAGS) $(ACPI_FLAGS)
BOOTLOADER := boot.S BOOTMETHOD := psci.o @@ -39,6 +40,12 @@ FILESYSTEM_START:= $(shell echo $$(($(PHYS_OFFSET) + $(FS_OFFSET)))) FILESYSTEM_SIZE := $(shell stat -Lc %s $(FILESYSTEM) 2>/dev/null || echo 0) FILESYSTEM_END := $(shell echo $$(($(FILESYSTEM_START) + $(FILESYSTEM_SIZE))))
+ACPI := tables.acpi +ACPI_OFFSET := 0x08100000 +ACPI_START := $(shell echo $$(($(PHYS_OFFSET) + $(ACPI_OFFSET)))) +ACPI_SIZE := $(shell stat -Lc %s $(ACPI) 2>/dev/null || echo 0) +ACPI_END := $(shell echo $$(($(ACPI_START) + $(ACPI_SIZE)))) + FDT_SRC := rtsm_ve-aemv8a.dts FDT_INCL_REGEX := (/include/[[:space:]]*")([^"]+)(".*) FDT_DEPS := $(FDT_SRC) $(addprefix $(dir $(FDT_SRC)), $(shell sed -ne 'sq$(strip $(FDT_INCL_REGEX)q\2q p' < $(FDT_SRC)))) @@ -46,19 +53,30 @@ FDT_OFFSET := 0x08000000
BOOTARGS_COMMON := "console=ttyAMA0 earlyprintk=pl011,0x1c090000 $(BOOTARGS_EXTRA)"
+CHOSEN_NODE := chosen { ifneq (,$(findstring USE_INITRD,$(CPPFLAGS))) BOOTARGS := "$(BOOTARGS_COMMON)" -CHOSEN_NODE := chosen { \ - bootargs = "$(BOOTARGS)"; \ +CHOSEN_NODE += bootargs = "$(BOOTARGS)"; \ linux,initrd-start = <$(FILESYSTEM_START)>; \ - linux,initrd-end = <$(FILESYSTEM_END)>; \ - }; + linux,initrd-end = <$(FILESYSTEM_END)>; + +ifneq (,$(findstring USE_ACPI,$(CPPFLAGS))) +CHOSEN_NODE += linux,acpi-start = <$(ACPI_START)>; \ + linux,acpi-len = <$(ACPI_SIZE)>; +endif + else BOOTARGS := "root=/dev/nfs nfsroot=<serverip>:<rootfs>,tcp rw ip=dhcp $(BOOTARGS_COMMON)" CHOSEN_NODE := chosen { \ - bootargs = "$(BOOTARGS)"; \ - }; + bootargs = "$(BOOTARGS)"; + +ifneq (,$(findstring USE_ACPI,$(CPPFLAGS))) +CHOSEN_NODE += linux,acpi-start = <$(ACPI_START)>; \ + linux,acpi-len = <$(ACPI_SIZE)>; +endif + endif +CHOSEN_NODE += };
CROSS_COMPILE ?= aarch64-none-linux-gnu- CC := $(CROSS_COMPILE)gcc @@ -77,14 +95,14 @@ $(IMAGE): boot.o cache.o gic.o mmu.o ns.o $(BOOTMETHOD) model.lds fdt.dtb $(KERN $(CC) $(CPPFLAGS) $(DEFINES) -c -o $@ $<
model.lds: $(LD_SCRIPT) Makefile - $(CC) $(CPPFLAGS) -DPHYS_OFFSET=$(PHYS_OFFSET) -DMBOX_OFFSET=$(MBOX_OFFSET) -DKERNEL_OFFSET=$(KERNEL_OFFSET) -DFDT_OFFSET=$(FDT_OFFSET) -DFS_OFFSET=$(FS_OFFSET) -DKERNEL=$(KERNEL) -DFILESYSTEM=$(FILESYSTEM) -DBOOTMETHOD=$(BOOTMETHOD) -E -P -C -o $@ $< + $(CC) $(CPPFLAGS) -DPHYS_OFFSET=$(PHYS_OFFSET) -DMBOX_OFFSET=$(MBOX_OFFSET) -DKERNEL_OFFSET=$(KERNEL_OFFSET) -DFDT_OFFSET=$(FDT_OFFSET) -DFS_OFFSET=$(FS_OFFSET) -DKERNEL=$(KERNEL) -DFILESYSTEM=$(FILESYSTEM) -DBOOTMETHOD=$(BOOTMETHOD) -DACPI=$(ACPI) -DACPI_OFFSET=$(ACPI_OFFSET) -E -P -C -o $@ $<
ifeq ($(DTC),) $(error No dtc found! You can git clone from git://git.jdl.com/software/dtc.git) endif
fdt.dtb: $(FDT_DEPS) Makefile - ( echo "/include/ "$(FDT_SRC)"" ; echo "/ { $(CHOSEN_NODE) };" ) | $(DTC) -O dtb -o $@ - + ( echo "/include/ "$(FDT_SRC)"" ; echo "/ { $(CHOSEN_NODE) };" ) | tee chosen.dts | $(DTC) -O dtb -o $@ -
# The filesystem archive might not exist if INITRD is not being used .PHONY: all clean $(FILESYSTEM) diff --git a/model.lds.S b/model.lds.S index 401ea5f..7dd34b5 100644 --- a/model.lds.S +++ b/model.lds.S @@ -20,6 +20,10 @@ INPUT(./BOOTMETHOD) INPUT(KERNEL) INPUT(./fdt.dtb)
+#ifdef USE_ACPI +INPUT(ACPI) +#endif + #ifdef USE_INITRD INPUT(FILESYSTEM) #endif @@ -43,6 +47,11 @@ SECTIONS . = PHYS_OFFSET + FDT_OFFSET; dtb = .; .dtb : { ./fdt.dtb } + . = PHYS_OFFSET + ACPI_OFFSET; + acpi = .; +#ifdef USE_ACPI + .acpi : { ACPI } +#endif . = PHYS_OFFSET + FS_OFFSET; filesystem = .; #ifdef USE_INITRD
W dniu 02.09.2013 14:03, Hanjun Guo pisze:
From: Mark Rutland mark.rutland@arm.com
We currently do an ldr from GICC_CTLR to w0, then immediately overwrite w0 with a mov. Reading the GICC_CTLR has no effect on the state of the GIC, so there's no reason to do the ldr. It's also inconsistent with the way we set the GICD_CTLR.
Fix this.
Signed-off-by: Mark Rutland mark.rutland@arm.com
boot.S | 1 - 1 file changed, 1 deletion(-)
diff --git a/boot.S b/boot.S index a1f25e2..7c28e84 100644 --- a/boot.S +++ b/boot.S @@ -49,7 +49,6 @@ _start: str w0, [x1], #4
2: ldr x1, =GIC_CPU_BASE // GICC_CTLR
- ldr w0, [x1] mov w0, #3 // EnableGrp0 | EnableGrp1 str w0, [x1]
Hi Hanjun,
Should it be reviewed? I see one Graeme's commit (already reviewed) and the others around assembler code. Is it enabler that has locked order?
Tomasz
On 2013-9-5 16:51, Tomasz Nowicki wrote:
W dniu 02.09.2013 14:03, Hanjun Guo pisze:
From: Mark Rutland mark.rutland@arm.com
We currently do an ldr from GICC_CTLR to w0, then immediately overwrite w0 with a mov. Reading the GICC_CTLR has no effect on the state of the GIC, so there's no reason to do the ldr. It's also inconsistent with the way we set the GICD_CTLR.
Fix this.
Signed-off-by: Mark Rutland mark.rutland@arm.com
boot.S | 1 - 1 file changed, 1 deletion(-)
diff --git a/boot.S b/boot.S index a1f25e2..7c28e84 100644 --- a/boot.S +++ b/boot.S @@ -49,7 +49,6 @@ _start: str w0, [x1], #4
2: ldr x1, =GIC_CPU_BASE // GICC_CTLR
- ldr w0, [x1] mov w0, #3 // EnableGrp0 | EnableGrp1 str w0, [x1]
Hi Hanjun,
Should it be reviewed? I see one Graeme's commit (already reviewed) and the others around assembler code. Is it enabler that has locked order?
I don't think we should review this patch set, because this patch set for boot wrapper is already in ARM's boot wrapper git tree:
http://linux-arm.org/git?p=boot-wrapper-aarch64.git%3Ba=shortlog%3Bh=refs/he...
This patch set is based on this commit (73ecb28f, Allow CROSS_COMPILE override on the make command line), and I rebased Graeme's ACPI blob patch on top of it to test my CPU hotplug code.
Tomasz
On Thu, Sep 05, 2013 at 05:16:05PM +0800, Hanjun Guo wrote:
On 2013-9-5 16:51, Tomasz Nowicki wrote:
W dniu 02.09.2013 14:03, Hanjun Guo pisze:
From: Mark Rutland mark.rutland@arm.com
We currently do an ldr from GICC_CTLR to w0, then immediately overwrite w0 with a mov. Reading the GICC_CTLR has no effect on the state of the GIC, so there's no reason to do the ldr. It's also inconsistent with the way we set the GICD_CTLR.
Fix this.
Signed-off-by: Mark Rutland mark.rutland@arm.com
boot.S | 1 - 1 file changed, 1 deletion(-)
diff --git a/boot.S b/boot.S index a1f25e2..7c28e84 100644 --- a/boot.S +++ b/boot.S @@ -49,7 +49,6 @@ _start: str w0, [x1], #4
2: ldr x1, =GIC_CPU_BASE // GICC_CTLR
- ldr w0, [x1] mov w0, #3 // EnableGrp0 | EnableGrp1 str w0, [x1]
Hi Hanjun,
Should it be reviewed? I see one Graeme's commit (already reviewed) and the others around assembler code. Is it enabler that has locked order?
I don't think we should review this patch set, because this patch set for boot wrapper is already in ARM's boot wrapper git tree:
http://linux-arm.org/git?p=boot-wrapper-aarch64.git%3Ba=shortlog%3Bh=refs/he...
This patch set is based on this commit (73ecb28f, Allow CROSS_COMPILE override on the make command line), and I rebased Graeme's ACPI blob patch on top of it to test my CPU hotplug code.
Hi Hanjun,
Have you pushed the results of that to a repository? It sounds like we should update to use your bootwrapper?
Graeme
On 2013-9-5 17:22, Graeme Gregory wrote:
On Thu, Sep 05, 2013 at 05:16:05PM +0800, Hanjun Guo wrote:
On 2013-9-5 16:51, Tomasz Nowicki wrote:
W dniu 02.09.2013 14:03, Hanjun Guo pisze:
From: Mark Rutland mark.rutland@arm.com
We currently do an ldr from GICC_CTLR to w0, then immediately overwrite w0 with a mov. Reading the GICC_CTLR has no effect on the state of the GIC, so there's no reason to do the ldr. It's also inconsistent with the way we set the GICD_CTLR.
Fix this.
Signed-off-by: Mark Rutland mark.rutland@arm.com
boot.S | 1 - 1 file changed, 1 deletion(-)
diff --git a/boot.S b/boot.S index a1f25e2..7c28e84 100644 --- a/boot.S +++ b/boot.S @@ -49,7 +49,6 @@ _start: str w0, [x1], #4
2: ldr x1, =GIC_CPU_BASE // GICC_CTLR
- ldr w0, [x1] mov w0, #3 // EnableGrp0 | EnableGrp1 str w0, [x1]
Hi Hanjun,
Should it be reviewed? I see one Graeme's commit (already reviewed) and the others around assembler code. Is it enabler that has locked order?
I don't think we should review this patch set, because this patch set for boot wrapper is already in ARM's boot wrapper git tree:
http://linux-arm.org/git?p=boot-wrapper-aarch64.git%3Ba=shortlog%3Bh=refs/he...
This patch set is based on this commit (73ecb28f, Allow CROSS_COMPILE override on the make command line), and I rebased Graeme's ACPI blob patch on top of it to test my CPU hotplug code.
Hi Hanjun,
Have you pushed the results of that to a repository? It sounds like we should
Not yet. Can I create a branch for it in your bootwrapper git repo?
update to use your bootwrapper?
I have no objections, but this version of bootwrapper contains PSCI support, if this is no impact to our test (I have tested it with our foundation-v8-acpi.dts and ACPI kernel, it is OK, still need your conformation), we can update it.
Graeme
On Thu, Sep 05, 2013 at 06:30:01PM +0800, Hanjun Guo wrote:
On 2013-9-5 17:22, Graeme Gregory wrote:
On Thu, Sep 05, 2013 at 05:16:05PM +0800, Hanjun Guo wrote:
On 2013-9-5 16:51, Tomasz Nowicki wrote:
W dniu 02.09.2013 14:03, Hanjun Guo pisze:
From: Mark Rutland mark.rutland@arm.com
We currently do an ldr from GICC_CTLR to w0, then immediately overwrite w0 with a mov. Reading the GICC_CTLR has no effect on the state of the GIC, so there's no reason to do the ldr. It's also inconsistent with the way we set the GICD_CTLR.
Fix this.
Signed-off-by: Mark Rutland mark.rutland@arm.com
boot.S | 1 - 1 file changed, 1 deletion(-)
diff --git a/boot.S b/boot.S index a1f25e2..7c28e84 100644 --- a/boot.S +++ b/boot.S @@ -49,7 +49,6 @@ _start: str w0, [x1], #4
2: ldr x1, =GIC_CPU_BASE // GICC_CTLR
- ldr w0, [x1] mov w0, #3 // EnableGrp0 | EnableGrp1 str w0, [x1]
Hi Hanjun,
Should it be reviewed? I see one Graeme's commit (already reviewed) and the others around assembler code. Is it enabler that has locked order?
I don't think we should review this patch set, because this patch set for boot wrapper is already in ARM's boot wrapper git tree:
http://linux-arm.org/git?p=boot-wrapper-aarch64.git%3Ba=shortlog%3Bh=refs/he...
This patch set is based on this commit (73ecb28f, Allow CROSS_COMPILE override on the make command line), and I rebased Graeme's ACPI blob patch on top of it to test my CPU hotplug code.
Hi Hanjun,
Have you pushed the results of that to a repository? It sounds like we should
Not yet. Can I create a branch for it in your bootwrapper git repo?
I have just converted it to a shared repo so yes this is OK, please do.
update to use your bootwrapper?
I have no objections, but this version of bootwrapper contains PSCI support, if this is no impact to our test (I have tested it with our foundation-v8-acpi.dts and ACPI kernel, it is OK, still need your conformation), we can update it.
Yes I think if it does not break anything we should use it as default.
Graeme
On 5 September 2013 19:00, Graeme Gregory graeme.gregory@linaro.org wrote:
On Thu, Sep 05, 2013 at 06:30:01PM +0800, Hanjun Guo wrote:
On 2013-9-5 17:22, Graeme Gregory wrote:
On Thu, Sep 05, 2013 at 05:16:05PM +0800, Hanjun Guo wrote:
On 2013-9-5 16:51, Tomasz Nowicki wrote:
W dniu 02.09.2013 14:03, Hanjun Guo pisze:
[...]
I have just converted it to a shared repo so yes this is OK, please do.
Ok, I will finish it tomorrow. After I finish this, I will let you know.
update to use your bootwrapper?
I have no objections, but this version of bootwrapper contains PSCI
support, if
this is no impact to our test (I have tested it with our
foundation-v8-acpi.dts
and ACPI kernel, it is OK, still need your conformation), we can update
it.
Yes I think if it does not break anything we should use it as default.
Graeme
On 2013-9-5 19:00, Graeme Gregory wrote:
On Thu, Sep 05, 2013 at 06:30:01PM +0800, Hanjun Guo wrote:
On 2013-9-5 17:22, Graeme Gregory wrote:
On Thu, Sep 05, 2013 at 05:16:05PM +0800, Hanjun Guo wrote:
On 2013-9-5 16:51, Tomasz Nowicki wrote:
W dniu 02.09.2013 14:03, Hanjun Guo pisze:
[]...
Hi Hanjun,
Have you pushed the results of that to a repository? It sounds like we should
Not yet. Can I create a branch for it in your bootwrapper git repo?
I have just converted it to a shared repo so yes this is OK, please do.
I have create a branch "cpu-hotplug" for this: https://git.linaro.org/gitweb?p=people/graemegregory/bootwrapper.git%3Ba=sho...
sorry for the late response, I'm busy with the preparation for visa last week.
update to use your bootwrapper?
I have no objections, but this version of bootwrapper contains PSCI support, if this is no impact to our test (I have tested it with our foundation-v8-acpi.dts and ACPI kernel, it is OK, still need your conformation), we can update it.
Yes I think if it does not break anything we should use it as default.
if we use the default kernel branch "acpi" and the default boot-wrapper branch "master", it will break anything.
But if we want to use acpi cpu hot plug, we should use: a) boot-wrapper branch "cpu-hotplug" b) kernel branch "cpu-hotplug": https://git.linaro.org/gitweb?p=arm/acpi/acpi.git%3Ba=shortlog%3Bh=refs/head...
Thanks Hanjun
Graeme
On Mon, Sep 16, 2013 at 08:08:28PM +0800, Hanjun Guo wrote:
On 2013-9-5 19:00, Graeme Gregory wrote:
On Thu, Sep 05, 2013 at 06:30:01PM +0800, Hanjun Guo wrote:
On 2013-9-5 17:22, Graeme Gregory wrote:
On Thu, Sep 05, 2013 at 05:16:05PM +0800, Hanjun Guo wrote:
On 2013-9-5 16:51, Tomasz Nowicki wrote:
W dniu 02.09.2013 14:03, Hanjun Guo pisze:
[]...
Hi Hanjun,
Have you pushed the results of that to a repository? It sounds like we should
Not yet. Can I create a branch for it in your bootwrapper git repo?
I have just converted it to a shared repo so yes this is OK, please do.
I have create a branch "cpu-hotplug" for this: https://git.linaro.org/gitweb?p=people/graemegregory/bootwrapper.git%3Ba=sho...
sorry for the late response, I'm busy with the preparation for visa last week.
update to use your bootwrapper?
I have no objections, but this version of bootwrapper contains PSCI support, if this is no impact to our test (I have tested it with our foundation-v8-acpi.dts and ACPI kernel, it is OK, still need your conformation), we can update it.
Yes I think if it does not break anything we should use it as default.
if we use the default kernel branch "acpi" and the default boot-wrapper branch "master", it will break anything.
But if we want to use acpi cpu hot plug, we should use: a) boot-wrapper branch "cpu-hotplug" b) kernel branch "cpu-hotplug": https://git.linaro.org/gitweb?p=arm/acpi/acpi.git%3Ba=shortlog%3Bh=refs/head...
Can you create a wiki page with this info?
emails tend to get lost!
Thanks
Graeme
On 2013-9-16 20:27, Graeme Gregory wrote:
On Mon, Sep 16, 2013 at 08:08:28PM +0800, Hanjun Guo wrote:
On 2013-9-5 19:00, Graeme Gregory wrote:
On Thu, Sep 05, 2013 at 06:30:01PM +0800, Hanjun Guo wrote:
On 2013-9-5 17:22, Graeme Gregory wrote:
On Thu, Sep 05, 2013 at 05:16:05PM +0800, Hanjun Guo wrote:
On 2013-9-5 16:51, Tomasz Nowicki wrote: > W dniu 02.09.2013 14:03, Hanjun Guo pisze:
[]...
Hi Hanjun,
Have you pushed the results of that to a repository? It sounds like we should
Not yet. Can I create a branch for it in your bootwrapper git repo?
I have just converted it to a shared repo so yes this is OK, please do.
I have create a branch "cpu-hotplug" for this: https://git.linaro.org/gitweb?p=people/graemegregory/bootwrapper.git%3Ba=sho...
sorry for the late response, I'm busy with the preparation for visa last week.
update to use your bootwrapper?
I have no objections, but this version of bootwrapper contains PSCI support, if this is no impact to our test (I have tested it with our foundation-v8-acpi.dts and ACPI kernel, it is OK, still need your conformation), we can update it.
Yes I think if it does not break anything we should use it as default.
if we use the default kernel branch "acpi" and the default boot-wrapper branch "master", it will break anything.
But if we want to use acpi cpu hot plug, we should use: a) boot-wrapper branch "cpu-hotplug" b) kernel branch "cpu-hotplug": https://git.linaro.org/gitweb?p=arm/acpi/acpi.git%3Ba=shortlog%3Bh=refs/head...
Can you create a wiki page with this info?
emails tend to get lost!
Agreed, actually, I'm working on it now :)
Thanks
Graeme
-
Graeme Gregory -
Hanjun Guo -
Tomasz Nowicki