This reverts commit b527efad22647cce76bf555252ae1574ea364529.

Since Mark Rutland implmented cpu online/offline on ARM64, this commit should be reverted and apply Mark's patch set instead. --- arch/arm64/Kconfig | 7 ------- arch/arm64/include/asm/smp.h | 3 --- arch/arm64/kernel/smp.c | 21 --------------------- 3 files changed, 31 deletions(-)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index b0fd1aa..db8ad10 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -183,13 +183,6 @@ config NR_CPUS default "8" if ARCH_XGENE default "4"

-config HOTPLUG_CPU - bool "Support for hot-pluggable CPUs" - depends on SMP && HOTPLUG - help - Say Y here to experiment with turning CPUs off and on. CPUs - can be controlled through /sys/devices/system/cpu. - source kernel/Kconfig.preempt

config HZ diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h index 95c9f58..4b8023c 100644 --- a/arch/arm64/include/asm/smp.h +++ b/arch/arm64/include/asm/smp.h @@ -63,9 +63,6 @@ extern struct secondary_data secondary_data; extern void secondary_holding_pen(void); extern volatile unsigned long secondary_holding_pen_release;

-extern int __cpu_disable(void); -extern void __cpu_die(unsigned int cpu); - extern void arch_send_call_function_single_ipi(int cpu); extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);

diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index b923cfc..d2cd58c 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -261,27 +261,6 @@ static const struct smp_enable_ops * __init smp_get_enable_ops(const char *name) return NULL; }

-#ifdef CONFIG_HOTPLUG_CPU -/* - * __cpu_disable runs on the processor to be shutdown. - */ -int __cpuinit __cpu_disable(void) -{ - pr_info("entered __cpu_disable(), assume always success\n"); - return 0; -} - -/* - * called on the thread which is asking for a CPU to be shutdown - - * waits until shutdown has completed, or it is timed out. - */ -void __cpuinit __cpu_die(unsigned int cpu) -{ - pr_info("entered __cpu_disable(), cpu %d will go away\n", cpu); - return; -} -#endif /* CONFIG_HOTPLUG_CPU */ - /* * Enumerate the possible CPU set from the device tree and build the * cpu logical map array containing MPIDR values related to logical

From: Mark Rutland mark.rutland@arm.com

The arm64 kernel has an internal holding pen, which is necessary for some systems where we can't bring CPUs online individually and must hold multiple CPUs in a safe area until the kernel is able to handle them. The current SMP infrastructure for arm64 is closely coupled to this holding pen, and alternative boot methods must launch CPUs into the pen, where they sit before they are launched into the kernel proper.

With PSCI (and possibly other future boot methods), we can bring CPUs online individually, and need not perform the secondary_holding_pen dance. Instead, this patch factors the holding pen management code out to the spin-table boot method code, as it is the only boot method requiring the pen.

A new entry point for secondaries, secondary_entry is added for other boot methods to use, which bypasses the holding pen and its associated overhead when bringing CPUs online. The smp.pen.text section is also removed, as the pen can live in head.text without problem.

The smp_operations structure is extended with two new functions, cpu_boot and cpu_postboot, for bringing a cpu into the kernel and performing any post-boot cleanup required by a bootmethod (e.g. resetting the secondary_holding_pen_release to INVALID_HWID). Documentation is added for smp_operations.

Signed-off-by: Mark Rutland mark.rutland@arm.com Cc: Santosh Shilimkar santosh.shilimkar@ti.com --- arch/arm64/include/asm/smp.h | 19 ++++++++- arch/arm64/kernel/head.S | 12 +++++- arch/arm64/kernel/smp.c | 67 +++----------------------------- arch/arm64/kernel/smp_psci.c | 16 ++++---- arch/arm64/kernel/smp_spin_table.c | 75 ++++++++++++++++++++++++++++++++++++ arch/arm64/kernel/vmlinux.lds.S | 1 - 6 files changed, 117 insertions(+), 73 deletions(-)

diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h index 90626b6..831090a 100644 --- a/arch/arm64/include/asm/smp.h +++ b/arch/arm64/include/asm/smp.h @@ -60,18 +60,33 @@ struct secondary_data { void *stack; }; extern struct secondary_data secondary_data; -extern void secondary_holding_pen(void); -extern volatile unsigned long secondary_holding_pen_release; +extern void secondary_entry(void);

extern void arch_send_call_function_single_ipi(int cpu); extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);

struct device_node;

+/** + * struct smp_operations - Callback operations for hotplugging CPUs. + * + * @name: Name of the property as appears in a devicetree cpu node's + * enable-method property. + * @cpu_init: Reads any data necessary for a specific enable-method form the + * devicetree, for a given cpu node and proposed logical id. + * @cpu_prepare: Early one-time preparation step for a cpu. If there is a + * mechanism for doing so, tests whether it is possible to boot + * the given CPU. + * @cpu_boot: Boots a cpu into the kernel. + * @cpu_postboot: Optionally, perform any post-boot cleanup or necesary + * synchronisation. Called from the cpu being booted. + */ struct smp_operations { const char *name; int (*cpu_init)(struct device_node *, unsigned int); int (*cpu_prepare)(unsigned int); + int (*cpu_boot)(unsigned int); + void (*cpu_postboot)(void); };

extern const struct smp_operations smp_spin_table_ops; diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 53dcae4..3532ca6 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -217,7 +217,6 @@ ENTRY(__boot_cpu_mode) .quad PAGE_OFFSET

#ifdef CONFIG_SMP - .pushsection .smp.pen.text, "ax" .align 3 1: .quad . .quad secondary_holding_pen_release @@ -242,7 +241,16 @@ pen: ldr x4, [x3] wfe b pen ENDPROC(secondary_holding_pen) - .popsection + + /* + * Secondary entry point that jumps straight into the kernel. Only to + * be used where CPUs are brought online dynamically by the kernel. + */ +ENTRY(secondary_entry) + bl __calc_phys_offset // x2=phys offset + bl el2_setup // Drop to EL1 + b secondary_startup +ENDPROC(secondary_entry)

ENTRY(secondary_startup) /* diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 3cedd3f..f633252 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -55,7 +55,6 @@ * where to place its SVC stack */ struct secondary_data secondary_data; -volatile unsigned long secondary_holding_pen_release = INVALID_HWID;

enum ipi_msg_type { IPI_RESCHEDULE, @@ -64,22 +63,7 @@ enum ipi_msg_type { IPI_CPU_STOP, };

-static DEFINE_RAW_SPINLOCK(boot_lock); - -/* - * Write secondary_holding_pen_release in a way that is guaranteed to be - * visible to all observers, irrespective of whether they're taking part - * in coherency or not. This is necessary for the hotplug code to work - * reliably. - */ -static void write_pen_release(u64 val) -{ - void *start = (void *)&secondary_holding_pen_release; - unsigned long size = sizeof(secondary_holding_pen_release); - - secondary_holding_pen_release = val; - __flush_dcache_area(start, size); -} +static const struct smp_operations *smp_ops[NR_CPUS];

/* * Boot a secondary CPU, and assign it the specified idle task. @@ -87,38 +71,10 @@ static void write_pen_release(u64 val) */ static int boot_secondary(unsigned int cpu, struct task_struct *idle) { - unsigned long timeout; - - /* - * Set synchronisation state between this boot processor - * and the secondary one - */ - raw_spin_lock(&boot_lock); - - /* - * Update the pen release flag. - */ - write_pen_release(cpu_logical_map(cpu)); - - /* - * Send an event, causing the secondaries to read pen_release. - */ - sev(); - - timeout = jiffies + (1 * HZ); - while (time_before(jiffies, timeout)) { - if (secondary_holding_pen_release == INVALID_HWID) - break; - udelay(10); - } - - /* - * Now the secondary core is starting up let it run its - * calibrations, then wait for it to finish - */ - raw_spin_unlock(&boot_lock); + if (smp_ops[cpu]->cpu_boot) + return smp_ops[cpu]->cpu_boot(cpu);

- return secondary_holding_pen_release != INVALID_HWID ? -ENOSYS : 0; + return -EOPNOTSUPP; }

static DECLARE_COMPLETION(cpu_running); @@ -188,17 +144,8 @@ asmlinkage void secondary_start_kernel(void) preempt_disable(); trace_hardirqs_off();

- /* - * Let the primary processor know we're out of the - * pen, then head off into the C entry point - */ - write_pen_release(INVALID_HWID); - - /* - * Synchronise with the boot thread. - */ - raw_spin_lock(&boot_lock); - raw_spin_unlock(&boot_lock); + if (smp_ops[cpu]->cpu_postboot) + smp_ops[cpu]->cpu_postboot();

store_cpu_topology(cpu);

@@ -245,8 +192,6 @@ static const struct smp_operations *supported_smp_ops[] __initconst = { NULL, };

-static const struct smp_operations *smp_ops[NR_CPUS]; - static const struct smp_operations * __init smp_get_ops(const char *name) { const struct smp_operations **ops = supported_smp_ops; diff --git a/arch/arm64/kernel/smp_psci.c b/arch/arm64/kernel/smp_psci.c index 2f0d3dd..20499bc 100644 --- a/arch/arm64/kernel/smp_psci.c +++ b/arch/arm64/kernel/smp_psci.c @@ -30,24 +30,26 @@ static int smp_psci_cpu_init(struct device_node *dn, unsigned int cpu)

static int smp_psci_cpu_prepare(unsigned int cpu) { - int err; - if (!psci_ops.cpu_on) { pr_err("psci: no cpu_on method, not booting CPU%d\n", cpu); return -ENODEV; }

- err = psci_ops.cpu_on(cpu_logical_map(cpu), __pa(secondary_holding_pen)); - if (err) { + return 0; +} + +static int smp_psci_cpu_boot(unsigned int cpu) +{ + int err = psci_ops.cpu_on(cpu_logical_map(cpu), __pa(secondary_entry)); + if (err) pr_err("psci: failed to boot CPU%d (%d)\n", cpu, err); - return err; - }

- return 0; + return err; }

const struct smp_operations smp_psci_ops = { .name = "psci", .cpu_init = smp_psci_cpu_init, .cpu_prepare = smp_psci_cpu_prepare, + .cpu_boot = smp_psci_cpu_boot, }; diff --git a/arch/arm64/kernel/smp_spin_table.c b/arch/arm64/kernel/smp_spin_table.c index 5fecffc..87af6bb 100644 --- a/arch/arm64/kernel/smp_spin_table.c +++ b/arch/arm64/kernel/smp_spin_table.c @@ -16,13 +16,36 @@ * along with this program. If not, see http://www.gnu.org/licenses/. */

+#include <linux/delay.h> #include <linux/init.h> #include <linux/of.h> #include <linux/smp.h>

#include <asm/cacheflush.h> +#include <asm/cputype.h> +#include <asm/smp_plat.h> + +extern void secondary_holding_pen(void); +volatile unsigned long secondary_holding_pen_release = INVALID_HWID;

static phys_addr_t cpu_release_addr[NR_CPUS]; +static DEFINE_RAW_SPINLOCK(boot_lock); + +/* + * Write secondary_holding_pen_release in a way that is guaranteed to be + * visible to all observers, irrespective of whether they're taking part + * in coherency or not. This is necessary for the hotplug code to work + * reliably. + */ +static void write_pen_release(u64 val) +{ + void *start = (void *)&secondary_holding_pen_release; + unsigned long size = sizeof(secondary_holding_pen_release); + + secondary_holding_pen_release = val; + __flush_dcache_area(start, size); +} +

static int smp_spin_table_cpu_init(struct device_node *dn, unsigned int cpu) { @@ -59,8 +82,60 @@ static int smp_spin_table_cpu_prepare(unsigned int cpu) return 0; }

+static int smp_spin_table_cpu_boot(unsigned int cpu) +{ + unsigned long timeout; + + /* + * Set synchronisation state between this boot processor + * and the secondary one + */ + raw_spin_lock(&boot_lock); + + /* + * Update the pen release flag. + */ + write_pen_release(cpu_logical_map(cpu)); + + /* + * Send an event, causing the secondaries to read pen_release. + */ + sev(); + + timeout = jiffies + (1 * HZ); + while (time_before(jiffies, timeout)) { + if (secondary_holding_pen_release == INVALID_HWID) + break; + udelay(10); + } + + /* + * Now the secondary core is starting up let it run its + * calibrations, then wait for it to finish + */ + raw_spin_unlock(&boot_lock); + + return secondary_holding_pen_release != INVALID_HWID ? -ENOSYS : 0; +} + +void smp_spin_table_cpu_postboot(void) +{ + /* + * Let the primary processor know we're out of the pen. + */ + write_pen_release(INVALID_HWID); + + /* + * Synchronise with the boot thread. + */ + raw_spin_lock(&boot_lock); + raw_spin_unlock(&boot_lock); +} + const struct smp_operations smp_spin_table_ops = { .name = "spin-table", .cpu_init = smp_spin_table_cpu_init, .cpu_prepare = smp_spin_table_cpu_prepare, + .cpu_boot = smp_spin_table_cpu_boot, + .cpu_postboot = smp_spin_table_cpu_postboot, }; diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S index f5e5574..d8ca8d9 100644 --- a/arch/arm64/kernel/vmlinux.lds.S +++ b/arch/arm64/kernel/vmlinux.lds.S @@ -54,7 +54,6 @@ SECTIONS } .text : { /* Real text segment */ _stext = .; /* Text and read-only data */ - *(.smp.pen.text) __exception_text_start = .; *(.exception.text) __exception_text_end = .;

From: Mark Rutland mark.rutland@arm.com

This patch adds the basic infrastructure necessary to support CPU_HOTPLUG on arm64, based on the arm implementation. Actual hotplug support will depend on an implementation's smp_operations (e.g. PSCI).

Signed-off-by: Mark Rutland mark.rutland@arm.com --- arch/arm64/Kconfig | 7 +++ arch/arm64/include/asm/irq.h | 1 + arch/arm64/include/asm/smp.h | 14 ++++++ arch/arm64/kernel/cputable.c | 2 +- arch/arm64/kernel/irq.c | 61 ++++++++++++++++++++++++++ arch/arm64/kernel/process.c | 7 +++ arch/arm64/kernel/smp.c | 97 ++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 188 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index db8ad10..e285ba1 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -183,6 +183,13 @@ config NR_CPUS default "8" if ARCH_XGENE default "4"

+config HOTPLUG_CPU + bool "Support for hot-pluggable CPUs" + depends on SMP + help + Say Y here to experiment with turning CPUs off and on. CPUs + can be controlled through /sys/devices/system/cpu. + source kernel/Kconfig.preempt

config HZ diff --git a/arch/arm64/include/asm/irq.h b/arch/arm64/include/asm/irq.h index 0332fc0..e1f7ecd 100644 --- a/arch/arm64/include/asm/irq.h +++ b/arch/arm64/include/asm/irq.h @@ -4,6 +4,7 @@ #include <asm-generic/irq.h>

extern void (*handle_arch_irq)(struct pt_regs *); +extern void migrate_irqs(void); extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));

#endif diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h index 831090a..d2ef02e 100644 --- a/arch/arm64/include/asm/smp.h +++ b/arch/arm64/include/asm/smp.h @@ -67,6 +67,11 @@ extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);

struct device_node;

+extern int __cpu_disable(void); + +extern void __cpu_die(unsigned int cpu); +extern void cpu_die(void); + /** * struct smp_operations - Callback operations for hotplugging CPUs. * @@ -80,6 +85,11 @@ struct device_node; * @cpu_boot: Boots a cpu into the kernel. * @cpu_postboot: Optionally, perform any post-boot cleanup or necesary * synchronisation. Called from the cpu being booted. + * @cpu_disable: Prepares a cpu to die. May fail for some mechanism-specific + * reason, which will cause the hot unplug to be aborted. Called + * from the cpu to be killed. + * @cpu_die: Makes the a leave the kernel. Must not fail. Called from the + * cpu being killed. */ struct smp_operations { const char *name; @@ -87,6 +97,10 @@ struct smp_operations { int (*cpu_prepare)(unsigned int); int (*cpu_boot)(unsigned int); void (*cpu_postboot)(void); +#ifdef CONFIG_HOTPLUG_CPU + int (*cpu_disable)(unsigned int cpu); + void (*cpu_die)(unsigned int cpu); +#endif };

extern const struct smp_operations smp_spin_table_ops; diff --git a/arch/arm64/kernel/cputable.c b/arch/arm64/kernel/cputable.c index 63cfc4a..fd3993c 100644 --- a/arch/arm64/kernel/cputable.c +++ b/arch/arm64/kernel/cputable.c @@ -22,7 +22,7 @@

extern unsigned long __cpu_setup(void);

-struct cpu_info __initdata cpu_table[] = { +struct cpu_info cpu_table[] = { { .cpu_id_val = 0x000f0000, .cpu_id_mask = 0x000f0000, diff --git a/arch/arm64/kernel/irq.c b/arch/arm64/kernel/irq.c index ecb3354..473e5db 100644 --- a/arch/arm64/kernel/irq.c +++ b/arch/arm64/kernel/irq.c @@ -81,3 +81,64 @@ void __init init_IRQ(void) if (!handle_arch_irq) panic("No interrupt controller found."); } + +#ifdef CONFIG_HOTPLUG_CPU +static bool migrate_one_irq(struct irq_desc *desc) +{ + struct irq_data *d = irq_desc_get_irq_data(desc); + const struct cpumask *affinity = d->affinity; + struct irq_chip *c; + bool ret = false; + + /* + * If this is a per-CPU interrupt, or the affinity does not + * include this CPU, then we have nothing to do. + */ + if (irqd_is_per_cpu(d) || !cpumask_test_cpu(smp_processor_id(), affinity)) + return false; + + if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) { + affinity = cpu_online_mask; + ret = true; + } + + c = irq_data_get_irq_chip(d); + if (!c->irq_set_affinity) + pr_debug("IRQ%u: unable to set affinity\n", d->irq); + else if (c->irq_set_affinity(d, affinity, true) == IRQ_SET_MASK_OK && ret) + cpumask_copy(d->affinity, affinity); + + return ret; +} + +/* + * The current CPU has been marked offline. Migrate IRQs off this CPU. + * If the affinity settings do not allow other CPUs, force them onto any + * available CPU. + * + * Note: we must iterate over all IRQs, whether they have an attached + * action structure or not, as we need to get chained interrupts too. + */ +void migrate_irqs(void) +{ + unsigned int i; + struct irq_desc *desc; + unsigned long flags; + + local_irq_save(flags); + + for_each_irq_desc(i, desc) { + bool affinity_broken; + + raw_spin_lock(&desc->lock); + affinity_broken = migrate_one_irq(desc); + raw_spin_unlock(&desc->lock); + + if (affinity_broken) + pr_warn_ratelimited("IRQ%u no longer affine to CPU%u\n", + i, smp_processor_id()); + } + + local_irq_restore(flags); +} +#endif /* CONFIG_HOTPLUG_CPU */ diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 2a7a649..b05026c 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -102,6 +102,13 @@ void arch_cpu_idle(void) local_irq_enable(); }

+#ifdef CONFIG_HOTPLUG_CPU +void arch_cpu_idle_dead(void) +{ + cpu_die(); +} +#endif + void machine_shutdown(void) { #ifdef CONFIG_SMP diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index a30ac03..f074292 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -171,6 +171,103 @@ asmlinkage void secondary_start_kernel(void) cpu_startup_entry(CPUHP_ONLINE); }

+#ifdef CONFIG_HOTPLUG_CPU +static int op_cpu_disable(unsigned int cpu) +{ + /* + * If we don't have a cpu_die method, abort before we reach the point + * of no return. CPU0 may not have an smp_ops, so test for it. + */ + if (!smp_ops[cpu] || !smp_ops[cpu]->cpu_die) + return -EOPNOTSUPP; + + /* + * We may need to abort a hot unplug for some other mechanism-specific + * reason. + */ + if (smp_ops[cpu]->cpu_disable) + return smp_ops[cpu]->cpu_disable(cpu); + + return 0; +} + +/* + * __cpu_disable runs on the processor to be shutdown. + */ +int __cpu_disable(void) +{ + unsigned int cpu = smp_processor_id(); + int ret; + + ret = op_cpu_disable(cpu); + if (ret) + return ret; + + /* + * Take this CPU offline. Once we clear this, we can't return, + * and we must not schedule until we're ready to give up the cpu. + */ + set_cpu_online(cpu, false); + + /* + * OK - migrate IRQs away from this CPU + */ + migrate_irqs(); + + /* + * Remove this CPU from the vm mask set of all processes. + */ + clear_tasks_mm_cpumask(cpu); + + return 0; +} + +static DECLARE_COMPLETION(cpu_died); + +/* + * called on the thread which is asking for a CPU to be shutdown - + * waits until shutdown has completed, or it is timed out. + */ +void __cpu_die(unsigned int cpu) +{ + if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) { + pr_crit("CPU%u: cpu didn't die\n", cpu); + return; + } + pr_notice("CPU%u: shutdown\n", cpu); +} + +/* + * Called from the idle thread for the CPU which has been shutdown. + * + * Note that we disable IRQs here, but do not re-enable them + * before returning to the caller. This is also the behaviour + * of the other hotplug-cpu capable cores, so presumably coming + * out of idle fixes this. + */ +void __ref cpu_die(void) +{ + unsigned int cpu = smp_processor_id(); + + idle_task_exit(); + + local_irq_disable(); + mb(); + + /* Tell __cpu_die() that this CPU is now safe to dispose of */ + complete(&cpu_died); + + /* + * Actually shutdown the CPU. This must never fail. The specific hotplug + * mechanism must perform all required cache maintenance to ensure that + * no dirty lines are lost in the process of shutting down the CPU. + */ + smp_ops[cpu]->cpu_die(cpu); + + BUG(); +} +#endif + void __init smp_cpus_done(unsigned int max_cpus) { unsigned long bogosum = loops_per_jiffy * num_online_cpus();

From: Mark Rutland mark.rutland@arm.com

On Thu, Jul 11, 2013 at 04:10:51PM +0100, Hanjun Guo wrote:

Hi Mark,

Hi Hanjun,

I tested this patch set on the armv8 foundation model, it's panic.

I seems that we need to do something more, I'll also checkout what's going on here.

Thanks Hanjun

dump formation: root@genericarmv8:/sys/devices/system/cpu/cpu3# echo 0 > online CPU3: Booted secondary processor CPU3: shutdown BUG: failure at kernel/time/clockevents.c:284/clockevents_register_device()! Kernel panic - not syncing: BUG! CPU: 3 PID: 0 Comm: swapper/3 Not tainted 3.10.0+ #2 Call trace: [<ffffffc0000873e0>] dump_backtrace+0x0/0x12c [<ffffffc000087520>] show_stack+0x14/0x1c [<ffffffc0003f2e7c>] dump_stack+0x20/0x28 [<ffffffc0003efd24>] panic+0xe8/0x214 [<ffffffc0000d049c>] clockevents_set_mode+0x0/0x6c [<ffffffc0000d074c>] clockevents_config_and_register+0x24/0x30 [<ffffffc0003ef840>] arch_timer_setup+0xd8/0x140 [<ffffffc0003ef8f0>] arch_timer_cpu_notify+0x48/0xc8 [<ffffffc0000b83e4>] notifier_call_chain+0x48/0x88 [<ffffffc0000b8500>] __raw_notifier_call_chain+0xc/0x14 [<ffffffc0000973f0>] __cpu_notify+0x30/0x58 [<ffffffc00009742c>] cpu_notify+0x14/0x1c [<ffffffc0003ed46c>] notify_cpu_starting+0x14/0x1c [<ffffffc0003ece74>] secondary_start_kernel+0xc0/0xf4

That looks suspicious. It looks like the CPU didn't actually die and jumped immediately to secondary_start_kernel. At a guess, did you update your dts with a psci node and cpu enable-methods?

I can see the code's broken if you try hotplug with spin-table, because cpu_disable and cpu_die are both NULL, and the sanity checking doesn't attempt to deal with this case, so the cpu will end up getting into cpu_die, won't call anything, and jump straight back into the kernel. I'll fix up the op_cpu_disable checks to cover this.

The other possibility is that you're using PSCI but your function id for cpu_off is wrong, and thus the psci cpu_off call fails. Did you update your dts for PSCI? Below is a patch to do so.

Thanks, Mark. --- arch/arm64/boot/dts/foundation-v8.dts | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/foundation-v8.dts b/arch/arm64/boot/dts/foundation-v8.dts index 84fcc50..335a88f 100644 --- a/arch/arm64/boot/dts/foundation-v8.dts +++ b/arch/arm64/boot/dts/foundation-v8.dts @@ -22,6 +22,13 @@ serial3 = &v2m_serial3; };

+ psci { + compatible = "arm,psci"; + method = "smc"; + cpu_off = <0x84000001>; + cpu_on = <0x84000002>; + }; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -30,29 +37,25 @@ device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; + enable-method = "psci"; }; cpu@1 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; + enable-method = "psci"; }; cpu@2 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x2>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; + enable-method = "psci"; }; cpu@3 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x3>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; + enable-method = "psci"; }; };

__cpuinit is gone in kernel now, remove them.

__init belongs after the return type on functions, not before, correct them too.

Signed-off-by: Hanjun Guo hanjun.guo@linaro.org --- drivers/acpi/plat/arm/boot.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/acpi/plat/arm/boot.c b/drivers/acpi/plat/arm/boot.c index 8600cd0..928f6c9 100644 --- a/drivers/acpi/plat/arm/boot.c +++ b/drivers/acpi/plat/arm/boot.c @@ -147,7 +147,7 @@ static int __init acpi_parse_madt(struct acpi_table_header *table) }

/* Local APIC = GIC cpu interface on ARM */ -static void __cpuinit acpi_register_lapic(int id, u8 enabled) +static void acpi_register_lapic(int id, u8 enabled) { int cpu;

@@ -365,7 +365,7 @@ early_param("possible_cpus", _setup_possible_cpus); * We do this because additional CPUs waste a lot of memory. * -AK */ -__init void prefill_possible_map(void) +void __init prefill_possible_map(void) { int i; int possible, disabled_cpus; @@ -405,7 +405,7 @@ __init void prefill_possible_map(void) #ifdef CONFIG_ACPI_HOTPLUG_CPU #include <acpi/processor.h>

-static void __cpuinit acpi_map_cpu2node(acpi_handle handle, int cpu, int physid) +static void acpi_map_cpu2node(acpi_handle handle, int cpu, int physid) { #ifdef CONFIG_ACPI_NUMA int nid; @@ -418,7 +418,7 @@ static void __cpuinit acpi_map_cpu2node(acpi_handle handle, int cpu, int physid) #endif }

-static int __cpuinit _acpi_map_lsapic(acpi_handle handle, int *pcpu) +static int _acpi_map_lsapic(acpi_handle handle, int *pcpu) { struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; union acpi_object *obj; @@ -582,7 +582,7 @@ static int __init acpi_parse_hpet(struct acpi_table_header *table) * hpet_insert_resource inserts the HPET resources used into the resource * tree. */ -static __init int hpet_insert_resource(void) +static int __init hpet_insert_resource(void) { if (!hpet_res) return 1;