From: Al Stone al.stone@linaro.org
These patches are my best guess at initial ACPI tables for XGene, in accordance with the new ACPI 5.1 specification.
These have not been fully tested yet but that process has been started.
Al Stone (3): APM / XGene: Minor cleanup of some of the basics APM / XGene: Update core tables to replace ACPI 5.1 changes APM / XGene: Add in empty SSDT for future use in developing complete tables
platforms/APMXGene.acpi/APMXGene.manifest | 1 + platforms/APMXGene.acpi/Apic.asl | 262 ++-- platforms/APMXGene.acpi/Dsdt.asl | 2215 ++++++++++++++++------------- platforms/APMXGene.acpi/Facp.asl | 57 +- platforms/APMXGene.acpi/Gtdt.asl | 87 +- platforms/APMXGene.acpi/Rsdp.asl | 2 +- platforms/APMXGene.acpi/Ssdt.asl | 21 + platforms/APMXGene.acpi/Xsdt.asl | 10 +- 8 files changed, 1508 insertions(+), 1147 deletions(-) create mode 100644 platforms/APMXGene.acpi/Ssdt.asl
From: Al Stone al.stone@linaro.org
Signed-off-by: Al Stone al.stone@linaro.org --- platforms/APMXGene.acpi/Rsdp.asl | 2 +- platforms/APMXGene.acpi/Xsdt.asl | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/platforms/APMXGene.acpi/Rsdp.asl b/platforms/APMXGene.acpi/Rsdp.asl index e76a4ce..af7a226 100644 --- a/platforms/APMXGene.acpi/Rsdp.asl +++ b/platforms/APMXGene.acpi/Rsdp.asl @@ -19,6 +19,6 @@ [0001] Revision : 02 [0004] RSDT Address : 00000000 [0004] Length : 00000024 -[0008] XSDT Address : 0000000085000024 +[0008] XSDT Address : 0000004003800024 [0001] Extended Checksum : DC [0003] Reserved : 000000 diff --git a/platforms/APMXGene.acpi/Xsdt.asl b/platforms/APMXGene.acpi/Xsdt.asl index 2be7fa8..0556872 100644 --- a/platforms/APMXGene.acpi/Xsdt.asl +++ b/platforms/APMXGene.acpi/Xsdt.asl @@ -19,11 +19,11 @@ [0001] Revision : 01 [0001] Checksum : 8B [0006] Oem ID : "APM " -[0008] Oem Table ID : "APMACPI " -[0004] Oem Revision : 00000001 +[0008] Oem Table ID : "XGENE " +[0004] Oem Revision : 00000002 [0004] Asl Compiler ID : "INTL" [0004] Asl Compiler Revision : 20100528
-[0008] ACPI Table Address 0 : 0000000085000060 -[0008] ACPI Table Address 1 : 000000008500016C -[0008] ACPI Table Address 2 : 00000000850001BC +[0008] ACPI Table Address 0 : 00000004003800060 +[0008] ACPI Table Address 1 : 0000000400380016C +[0008] ACPI Table Address 2 : 000000040038001BC
From: Al Stone al.stone@linaro.org
Signed-off-by: Al Stone al.stone@linaro.org --- platforms/APMXGene.acpi/Apic.asl | 262 +++-- platforms/APMXGene.acpi/Dsdt.asl | 2215 +++++++++++++++++++++----------------- platforms/APMXGene.acpi/Facp.asl | 57 +- platforms/APMXGene.acpi/Gtdt.asl | 87 +- 4 files changed, 1480 insertions(+), 1141 deletions(-)
diff --git a/platforms/APMXGene.acpi/Apic.asl b/platforms/APMXGene.acpi/Apic.asl index 2196eb6..9104a1f 100644 --- a/platforms/APMXGene.acpi/Apic.asl +++ b/platforms/APMXGene.acpi/Apic.asl @@ -1,10 +1,10 @@ /** * Copyright (c) 2013, AppliedMicro Corp. All rights reserved. * - * This program and the accompanying materials - * are licensed and made available under the terms and conditions of the BSD License - * which accompanies this distribution. The full text of the license may be found at - * http://opensource.org/licenses/bsd-license.php + * This program and the accompanying materials are licensed and made + * available under the terms and conditions of the BSD License which + * accompanies this distribution. The full text of the license may be + * found at * http://opensource.org/licenses/bsd-license.php * * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. @@ -15,120 +15,160 @@ * **/
-[0004] Signature : "APIC" [Multiple APIC Description Table (MADT)] -[0004] Table Length : 00000184 -[0001] Revision : 01 -[0001] Checksum : 00 -[0006] Oem ID : "APM " -[0008] Oem Table ID : "APMACPI " -[0004] Oem Revision : 00000001 -[0004] Asl Compiler ID : "INTL" -[0004] Asl Compiler Revision : 20110623 +[0004] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[0004] Table Length : 0000028C +[0001] Revision : 03 +[0001] Checksum : 00 +[0006] Oem ID : "APM " +[0008] Oem Table ID : "XGENE " +[0004] Oem Revision : 00000003 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20140424
-[0004] Local Apic Address : 00000000 -[0004] Flags (decoded below) : 00000001 - PC-AT Compatibility : 1 +[0004] Local Apic Address : 00000000 +[0004] Flags (decoded below) : 00000000 + PC-AT Compatibility : 0
-[0001] Subtable Type : 0B [Generic Interrupt Controller] -[0001] Length : 28 -[0002] Reserved : 0000 -[0004] Local GIC Hardware ID : 00000000 -[0004] Processor UID : 00000000 -[0004] Flags (decoded below) : 00000001 - Processor Enabled : 1 -[0004] Parking Protocol Version : 00000001 -[0004] Performance Interrupt : 00000000 -[0008] Parked Address : 0000004000008000 -[0008] Base Address : 0000000078020000 +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 4C +[0002] Reserved : 0000 +[0004] CPU Interface Number : 00000000 +[0004] Processor UID : 00000000 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[0004] Parking Protocol Version : 00000001 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 000000400000F000 +[0008] Base Address : 0000000078020000 +[0008] Virtual GIC Base Address : 0000000078060000 +[0008] Hyp GIC Base Address : 0000000078040000 +[0004] Virtual GIC Maintenance Interrupt : 00000009 +[0008] RedistBaseAddress : 0000000078010000 +[0008] MPIDR : 0000000000000000
-[0001] Subtable Type : 0B [Generic Interrupt Controller] -[0001] Length : 28 -[0002] Reserved : 0000 -[0004] Local GIC Hardware ID : 00000001 -[0004] Processor UID : 00000001 -[0004] Flags (decoded below) : 00000001 - Processor Enabled : 1 -[0004] Parking Protocol Version : 00000001 -[0004] Performance Interrupt : 00000000 -[0008] Parked Address : 0000004000009000 -[0008] Base Address : 0000000078020000 +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 4C +[0002] Reserved : 0000 +[0004] CPU Interface Number : 00000000 +[0004] Processor UID : 00000001 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[0004] Parking Protocol Version : 00000001 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 000000400000F000 +[0008] Base Address : 0000000078020000 +[0008] Virtual GIC Base Address : 0000000078060000 +[0008] Hyp GIC Base Address : 0000000078040000 +[0004] Virtual GIC Maintenance Interrupt : 00000009 +[0008] RedistBaseAddress : 0000000078010000 +[0008] MPIDR : 0000000000000001
-[0001] Subtable Type : 0B [Generic Interrupt Controller] -[0001] Length : 28 -[0002] Reserved : 0000 -[0004] Local GIC Hardware ID : 00000002 -[0004] Processor UID : 00000002 -[0004] Flags (decoded below) : 00000001 - Processor Enabled : 1 -[0004] Parking Protocol Version : 00000001 -[0004] Performance Interrupt : 00000000 -[0008] Parked Address : 000000400000a000 -[0008] Base Address : 0000000078020000 +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 4C +[0002] Reserved : 0000 +[0004] CPU Interface Number : 00000000 +[0004] Processor UID : 00000100 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[0004] Parking Protocol Version : 00000001 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 000000400000F000 +[0008] Base Address : 0000000078020000 +[0008] Virtual GIC Base Address : 0000000078060000 +[0008] Hyp GIC Base Address : 0000000078040000 +[0004] Virtual GIC Maintenance Interrupt : 00000009 +[0008] RedistBaseAddress : 0000000078010000 +[0008] MPIDR : 0000000000000100
-[0001] Subtable Type : 0B [Generic Interrupt Controller] -[0001] Length : 28 -[0002] Reserved : 0000 -[0004] Local GIC Hardware ID : 00000003 -[0004] Processor UID : 00000003 -[0004] Flags (decoded below) : 00000001 - Processor Enabled : 1 -[0004] Parking Protocol Version : 00000001 -[0004] Performance Interrupt : 00000000 -[0008] Parked Address : 000000400000b000 -[0008] Base Address : 0000000078020000 +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 4C +[0002] Reserved : 0000 +[0004] CPU Interface Number : 00000000 +[0004] Processor UID : 00000101 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[0004] Parking Protocol Version : 00000001 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 000000400000F000 +[0008] Base Address : 0000000078020000 +[0008] Virtual GIC Base Address : 0000000078060000 +[0008] Hyp GIC Base Address : 0000000078040000 +[0004] Virtual GIC Maintenance Interrupt : 00000009 +[0008] RedistBaseAddress : 0000000078010000 +[0008] MPIDR : 0000000000000101
-[0001] Subtable Type : 0B [Generic Interrupt Controller] -[0001] Length : 28 -[0002] Reserved : 0000 -[0004] Local GIC Hardware ID : 00000004 -[0004] Processor UID : 00000004 -[0004] Flags (decoded below) : 00000001 - Processor Enabled : 1 -[0004] Parking Protocol Version : 00000001 -[0004] Performance Interrupt : 00000000 -[0008] Parked Address : 000000400000c000 -[0008] Base Address : 0000000078020000 +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 4C +[0002] Reserved : 0000 +[0004] CPU Interface Number : 00000000 +[0004] Processor UID : 00000200 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[0004] Parking Protocol Version : 00000001 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 000000400000F000 +[0008] Base Address : 0000000078020000 +[0008] Virtual GIC Base Address : 0000000078060000 +[0008] Hyp GIC Base Address : 0000000078040000 +[0004] Virtual GIC Maintenance Interrupt : 00000009 +[0008] RedistBaseAddress : 0000000078010000 +[0008] MPIDR : 0000000000000200
-[0001] Subtable Type : 0B [Generic Interrupt Controller] -[0001] Length : 28 -[0002] Reserved : 0000 -[0004] Local GIC Hardware ID : 00000005 -[0004] Processor UID : 00000005 -[0004] Flags (decoded below) : 00000001 - Processor Enabled : 1 -[0004] Parking Protocol Version : 00000001 -[0004] Performance Interrupt : 00000000 -[0008] Parked Address : 000000400000d000 -[0008] Base Address : 0000000078020000 +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 4C +[0002] Reserved : 0000 +[0004] CPU Interface Number : 00000000 +[0004] Processor UID : 00000201 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[0004] Parking Protocol Version : 00000001 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 000000400000F000 +[0008] Base Address : 0000000078020000 +[0008] Virtual GIC Base Address : 0000000078060000 +[0008] Hyp GIC Base Address : 0000000078040000 +[0004] Virtual GIC Maintenance Interrupt : 00000009 +[0008] RedistBaseAddress : 0000000078010000 +[0008] MPIDR : 0000000000000201
-[0001] Subtable Type : 0B [Generic Interrupt Controller] -[0001] Length : 28 -[0002] Reserved : 0000 -[0004] Local GIC Hardware ID : 00000006 -[0004] Processor UID : 00000006 -[0004] Flags (decoded below) : 00000001 - Processor Enabled : 1 -[0004] Parking Protocol Version : 00000001 -[0004] Performance Interrupt : 00000000 -[0008] Parked Address : 000000400000e000 -[0008] Base Address : 0000000078020000 +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 4C +[0002] Reserved : 0000 +[0004] CPU Interface Number : 00000000 +[0004] Processor UID : 00000300 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[0004] Parking Protocol Version : 00000001 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 000000400000F000 +[0008] Base Address : 0000000078020000 +[0008] Virtual GIC Base Address : 0000000078060000 +[0008] Hyp GIC Base Address : 0000000078040000 +[0004] Virtual GIC Maintenance Interrupt : 00000009 +[0008] RedistBaseAddress : 0000000078010000 +[0008] MPIDR : 0000000000000300
-[0001] Subtable Type : 0B [Generic Interrupt Controller] -[0001] Length : 28 -[0002] Reserved : 0000 -[0004] Local GIC Hardware ID : 00000007 -[0004] Processor UID : 00000007 -[0004] Flags (decoded below) : 00000001 - Processor Enabled : 1 -[0004] Parking Protocol Version : 00000001 -[0004] Performance Interrupt : 00000000 -[0008] Parked Address : 000000400000f000 -[0008] Base Address : 0000000078020000 +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 4C +[0002] Reserved : 0000 +[0004] CPU Interface Number : 00000000 +[0004] Processor UID : 00000301 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[0004] Parking Protocol Version : 00000001 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 000000400000F000 +[0008] Base Address : 0000000078020000 +[0008] Virtual GIC Base Address : 0000000078060000 +[0008] Hyp GIC Base Address : 0000000078040000 +[0004] Virtual GIC Maintenance Interrupt : 00000009 +[0008] RedistBaseAddress : 0000000078010000 +[0008] MPIDR : 0000000000000301
-[0001] Subtable Type : 0C [Generic Interrupt Distributor] -[0001] Length : 18 -[0002] Reserved : 0000 -[0004] Local GIC Hardware ID : 0200143B -[0008] Base Address : 0000000078010000 -[0004] Interrupt Base : 00000000 -[0004] Reserved : 00000000 +[0001] Subtable Type : 0C [Generic Interrupt Distributor] +[0001] Length : 18 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000000 +[0008] Base Address : 0000000078010000 +[0004] Interrupt Base : 00000000 +[0004] Reserved : 00000000 diff --git a/platforms/APMXGene.acpi/Dsdt.asl b/platforms/APMXGene.acpi/Dsdt.asl index 7c31cbd..e709651 100644 --- a/platforms/APMXGene.acpi/Dsdt.asl +++ b/platforms/APMXGene.acpi/Dsdt.asl @@ -132,24 +132,50 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) {
//C states Name(_CST, Package() { - 1, + 2, Package() { //C1 state ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10550014, 3)}, 1, 0, //latency usec 2500 //power mW }, //C1 state + Package() { //C2 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)}, + 2, + 0, //latency usec + 0 //power mW + }, //C2 state /* Package() { //C3 state ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10550018, 3)}, 3, 200000, //latency usec 1800 //power mW - }, //C3 state*/ + }, //C3 state + Package() { //C4 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x1055001C, 3)}, + 4, + 500000, //latency usec + 1000 //power mW + }, //C4 state + Package() { //C5 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)}, + 5, + 0, //latency usec + 0 //power mW + }, //C5 state + Package() { //C6 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10550020, 3)}, + 6, + 10000000, //latency usec + 0 //power mW + }, //C6 state +*/ }) //_CST //C state dependency Name(_CSD, Package() { - Package() {6, 0, 0, 0xFC, 1, 1}, -// Package() {6, 0, 0, 0xFC, 2, 2}, + Package() {6, 0, 1, 0xFC, 2, 2}, + Package() {6, 0, 5, 0xFC, 8, 3}, + Package() {6, 0, 6, 0xFC, 8, 5}, }) //_CSD
}//CPU0 @@ -230,24 +256,50 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) {
//C states Name(_CST, Package() { - 1, + 2, Package() { //C1 state ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10551014, 3)}, 1, 0, //latency usec 2500 //power mW }, //C1 state + Package() { //C2 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)}, + 2, + 0, //latency usec + 0 //power mW + }, //C2 state /* Package() { //C3 state ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10551018, 3)}, 3, 200000, //latency usec 1800 //power mW - }, //C3 state */ + }, //C3 state + Package() { //C4 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x1055101C, 3)}, + 4, + 500000, //latency usec + 1000 //power mW + }, //C4 state + Package() { //C5 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)}, + 5, + 0, //latency usec + 0 //power mW + }, //C5 state + Package() { //C6 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10551020, 3)}, + 6, + 10000000, //latency usec + 0 //power mW + }, //C6 state +*/ }) //_CST //C state dependency Name(_CSD, Package() { - Package() {6, 0, 0, 0xFC, 1, 1}, -// Package() {6, 0, 0, 0xFC, 2, 2}, + Package() {6, 0, 1, 0xFC, 2, 2}, + Package() {6, 0, 5, 0xFC, 8, 3}, + Package() {6, 0, 6, 0xFC, 8, 5}, }) //_CSD
//Return the MADT table @@ -333,24 +385,50 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) {
//C states Name(_CST, Package() { - 1, + 2, Package() { //C1 state ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10552014, 3)}, 1, 0, //latency usec 2500 //power mW }, //C1 state + Package() { //C2 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)}, + 2, + 0, //latency usec + 0 //power mW + }, //C2 state /* Package() { //C3 state ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10552018, 3)}, 3, 200000, //latency usec 1800 //power mW - }, //C3 state */ + }, //C3 state + Package() { //C4 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x1055201C, 3)}, + 4, + 500000, //latency usec + 1000 //power mW + }, //C4 state + Package() { //C5 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)}, + 5, + 0, //latency usec + 0 //power mW + }, //C5 state + Package() { //C6 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10552020, 3)}, + 6, + 10000000, //latency usec + 0 //power mW + }, //C6 state +*/ }) //_CST //C state dependency Name(_CSD, Package() { - Package() {6, 0, 0, 0xFC, 1, 1}, -// Package() {6, 0, 0, 0xFC, 2, 2}, + Package() {6, 0, 2, 0xFC, 2, 2}, + Package() {6, 0, 5, 0xFC, 8, 3}, + Package() {6, 0, 6, 0xFC, 8, 5}, }) //_CSD
//Return the MADT table @@ -436,24 +514,50 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) {
//C states Name(_CST, Package() { - 1, + 2, Package() { //C1 state ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10553014, 3)}, 1, 0, //latency usec 2500 //power mW }, //C1 state + Package() { //C2 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)}, + 2, + 0, //latency usec + 0 //power mW + }, //C2 state /* Package() { //C3 state ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10553018, 3)}, 3, 200000, //latency usec 1800 //power mW - }, //C3 state */ + }, //C3 state + Package() { //C4 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x1055301C, 3)}, + 4, + 500000, //latency usec + 1000 //power mW + }, //C4 state + Package() { //C5 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)}, + 5, + 0, //latency usec + 0 //power mW + }, //C5 state + Package() { //C6 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10553020, 3)}, + 6, + 10000000, //latency usec + 0 //power mW + }, //C6 state +*/ }) //_CST //C state dependency Name(_CSD, Package() { - Package() {6, 0, 0, 0xFC, 1, 1}, -// Package() {6, 0, 0, 0xFC, 2, 2}, + Package() {6, 0, 2, 0xFC, 2, 2}, + Package() {6, 0, 5, 0xFC, 8, 3}, + Package() {6, 0, 6, 0xFC, 8, 5}, }) //_CSD
//Return the MADT table @@ -539,24 +643,50 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) {
//C states Name(_CST, Package() { - 1, + 2, Package() { //C1 state ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10554014, 3)}, 1, 0, //latency usec 2500 //power mW }, //C1 state + Package() { //C2 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)}, + 2, + 0, //latency usec + 0 //power mW + }, //C2 state /* Package() { //C3 state ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10554018, 3)}, 3, 200000, //latency usec 1800 //power mW - }, //C3 state */ + }, //C3 state + Package() { //C4 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x1055401C, 3)}, + 4, + 500000, //latency usec + 1000 //power mW + }, //C4 state + Package() { //C5 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)}, + 5, + 0, //latency usec + 0 //power mW + }, //C5 state + Package() { //C6 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10554020, 3)}, + 6, + 10000000, //latency usec + 0 //power mW + }, //C6 state +*/ }) //_CST //C state dependency Name(_CSD, Package() { - Package() {6, 0, 0, 0xFC, 1, 1}, -// Package() {6, 0, 0, 0xFC, 2, 2}, + Package() {6, 0, 3, 0xFC, 2, 2}, + Package() {6, 0, 5, 0xFC, 8, 3}, + Package() {6, 0, 6, 0xFC, 8, 5}, }) //_CSD
//Return the MADT table @@ -642,24 +772,50 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) {
//C states Name(_CST, Package() { - 1, + 2, Package() { //C1 state ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10555014, 3)}, 1, 0, //latency usec 2500 //power mW }, //C1 state + Package() { //C2 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)}, + 2, + 0, //latency usec + 0 //power mW + }, //C2 state /* Package() { //C3 state ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10555018, 3)}, 3, 200000, //latency usec 1800 //power mW - }, //C3 state */ + }, //C3 state + Package() { //C4 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x1055501C, 3)}, + 4, + 500000, //latency usec + 1000 //power mW + }, //C4 state + Package() { //C5 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)}, + 5, + 0, //latency usec + 0 //power mW + }, //C5 state + Package() { //C6 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10555020, 3)}, + 6, + 10000000, //latency usec + 0 //power mW + }, //C6 state +*/ }) //_CST //C state dependency Name(_CSD, Package() { - Package() {6, 0, 0, 0xFC, 1, 1}, -// Package() {6, 0, 0, 0xFC, 2, 2}, + Package() {6, 0, 3, 0xFC, 2, 2}, + Package() {6, 0, 5, 0xFC, 8, 3}, + Package() {6, 0, 6, 0xFC, 8, 5}, }) //_CSD
//Return the MADT table @@ -745,24 +901,50 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) {
//C states Name(_CST, Package() { - 1, + 2, Package() { //C1 state ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10556014, 3)}, 1, 0, //latency usec 2500 //power mW }, //C1 state + Package() { //C2 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)}, + 2, + 0, //latency usec + 0 //power mW + }, //C2 state /* Package() { //C3 state ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10556018, 3)}, 3, 200000, //latency usec 1800 //power mW - }, //C3 state */ + }, //C3 state + Package() { //C4 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x1055601C, 3)}, + 4, + 500000, //latency usec + 1000 //power mW + }, //C4 state + Package() { //C5 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)}, + 5, + 0, //latency usec + 0 //power mW + }, //C5 state + Package() { //C6 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10556020, 3)}, + 6, + 10000000, //latency usec + 0 //power mW + }, //C6 state +*/ }) //_CST //C state dependency Name(_CSD, Package() { - Package() {6, 0, 0, 0xFC, 1, 1}, -// Package() {6, 0, 0, 0xFC, 2, 2}, + Package() {6, 0, 4, 0xFC, 2, 2}, + Package() {6, 0, 5, 0xFC, 8, 3}, + Package() {6, 0, 6, 0xFC, 8, 5}, }) //_CSD
//Return the MADT table @@ -848,24 +1030,50 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) {
//C states Name(_CST, Package() { - 1, + 2, Package() { //C1 state ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10557014, 3)}, 1, 0, //latency usec 2500 //power mW }, //C1 state + Package() { //C2 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)}, + 2, + 0, //latency usec + 0 //power mW + }, //C2 state /* Package() { //C3 state ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10557018, 3)}, 3, 200000, //latency usec 1800 //power mW - }, //C3 state */ + }, //C3 state + Package() { //C4 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x1055701C, 3)}, + 4, + 500000, //latency usec + 1000 //power mW + }, //C4 state + Package() { //C5 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)}, + 5, + 0, //latency usec + 0 //power mW + }, //C5 state + Package() { //C6 state + ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10557020, 3)}, + 6, + 10000000, //latency usec + 0 //power mW + }, //C6 state +*/ }) //_CST //C state dependency Name(_CSD, Package() { - Package() {6, 0, 0, 0xFC, 1, 1}, -// Package() {6, 0, 0, 0xFC, 2, 2}, + Package() {6, 0, 4, 0xFC, 2, 2}, + Package() {6, 0, 5, 0xFC, 8, 3}, + Package() {6, 0, 6, 0xFC, 8, 5}, }) //_CSD
//Return the MADT table @@ -876,640 +1084,50 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) { }//CPU7
/////////////////////////////////////////////////////////////////////////////// +// Method DTGP + Method (DTGP, 5, NotSerialized) { + If (LEqual (Arg0, Buffer (0x10) { + /* UUID: a706b112-bf0b-48d2-9fa3-95591a3c4c06 */ + /* 0000 */ 0xA7, 0x06, 0xB1, 0x12, 0xBF, 0x0B, 0x48, 0xD2, + /* 0008 */ 0x9f, 0xA3, 0x95, 0x59, 0x1A, 0x3C, 0x4C, 0x06 + })) + + { + If (LEqual (Arg1, 0x01)) { + If (LEqual (Arg2, 0x00)) { + Store (Buffer (0x01) { + 0x03 + }, Arg4) + Return (0x01) + } + If (LEqual (Arg2, 0x01)) { + Return (0x01) + } + } + } + + Store (Buffer (0x01) { + 0x00 + }, Arg4) + Return (0x00) + } + +/////////////////////////////////////////////////////////////////////////////// // PMU - Device(PMU0) { - Name(_HID, "APMC0D0C") // Device Identification Objects + Device(_SB.PMU0) { + Name(_HID, "LNRO0007") // Device Identification Objects Name(_DDN, "PMU0") Name(_UID, "PMU0") Name(_STR, Unicode("PMU")) - Name(_CID, "APMC0D0C") + Name(_CID, "LNRO0007") Name(_CRS, ResourceTemplate() { - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x0C, 0x1 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x1C } }) - } //PMU - -//////////////////////////////////////////////////////////////////////////////// -// SoC Clock - Device(CK00) { - Name(_HID, "APMC0C00") - Name(_CID, 0x00) - Name(_STR, Unicode("Reference Clock")) - Name(_UID, "refclk") // clock-name - Name(CLNM, "refclk") // clock-name - Name(FREQ, 100000000) // clock-frequency - } - Device(CK01) { - Name(_HID, "APMC0C02") - Name(_CID, 0x00) - Name(_STR, Unicode("PCP PLL Clock")) - Name(MM0A, 0x17000100) // MMIO 0 Address - Name(MM0S, 0x20) // MMIO 0 Size - Name(_UID, "pcppll") // clock-name - Name(CLNM, "pcppll") // clock-name - Name(PRNT, "refclk") // parent-clock - } - Device(CK02) { - Name(_HID, "APMC0C03") - Name(_CID, 0x00) - Name(_STR, Unicode("SOC PLL Clock")) - Name(MM0A, 0x17000120) // MMIO 0 Address - Name(MM0S, 0x20) // MMIO 0 Size - Name(_UID, "socpll") // clock-name - Name(CLNM, "socpll") // clock-name - Name(PRNT, "refclk") // parent-clock - } - Device(CK03) { - Name(_HID, "APMC0C01") - Name(_CID, 0x00) - Name(_STR, Unicode("SOC PLL DIV2")) - Name(_UID, "socplldiv2")// clock-name - Name(CLNM, "socplldiv2")// clock-name - Name(PRNT, "socpll") // parent-clock - Name(CMUL, 0x1) // clock-mult - Name(CDIV, 0x2) // clock-div - } - Device(CK04) { - Name(_HID, "APMC0C04") - Name(_CID, 0x00) - Name(_STR, Unicode("QM Lite Clock")) - Name(MM0A, 0x1703C000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "qmlclk") // clock-name - Name(CLNM, "qmlclk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - } - Device(CK05) { - Name(_HID, "APMC0C04") - Name(_CID, 0x01) - Name(_STR, Unicode("Ethernet Clock")) - Name(MM0A, 0x00000000) // MMIO 0 Address - Name(MM0S, 0x0) // MMIO 0 Size - Name(MM1A, 0x17000000) // MMIO 1 Address - Name(MM1S, 0x1000) // MMIO 1 Size - Name(_UID, "ethclk") // clock-name - Name(CLNM, "ethclk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - Name(DIVO, 0x238) // divider-offset - Name(DIVW, 0x9) // divider-width - Name(DIVS, 0x0) // divider-shift - } - Device(CK06) { - Name(_HID, "APMC0C04") - Name(_CID, 0x02) - Name(_STR, Unicode("ETH8 Clock")) - Name(MM0A, 0x1702C000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "eth8clk") // clock-name - Name(CLNM, "eth8clk") // clock-name - Name(PRNT, "ethclk") // parent-clock - } - Device(CK07) { - Name(_HID, "APMC0C04") - Name(_CID, 0x03) - Name(_STR, Unicode("QM1 Clock")) - Name(MM0A, 0x1F20C000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "qm1clk") // clock-name - Name(CLNM, "qm1clk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - } - Device(CK08) { - Name(_HID, "APMC0C04") - Name(_CID, 0x04) - Name(_STR, Unicode("ETH01 Clock")) - Name(MM0A, 0x1F21C000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "eth01clk") // clock-name - Name(CLNM, "eth01clk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - } - Device(CK09) { - Name(_HID, "APMC0C04") - Name(_CID, 0x05) - Name(_STR, Unicode("ETH23 Clock")) - Name(MM0A, 0x1F22C000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "eth23clk") // clock-name - Name(CLNM, "eth23clk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - } - Device(CK0A) { - Name(_HID, "APMC0C04") - Name(_CID, 0x06) - Name(_STR, Unicode("QM XGE0 Clock")) - Name(MM0A, 0x1F60C000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "qmxge0clk") // clock-name - Name(CLNM, "qmxge0clk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - } - Device(CK0B) { - Name(_HID, "APMC0C04") - Name(_CID, 0x07) - Name(_STR, Unicode("XGE0 Clock")) - Name(MM0A, 0x1F61C000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "xge0clk") // clock-name - Name(CLNM, "xge0clk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - } - Device(CK0C) { - Name(_HID, "APMC0C04") - Name(_CID, 0x08) - Name(_STR, Unicode("XGE1 Clock")) - Name(MM0A, 0x1F62C000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "xge1clk") // clock-name - Name(CLNM, "xge1clk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - } - Device(CK0D) { - Name(_HID, "APMC0C04") - Name(_CID, 0x09) - Name(_STR, Unicode("QM XGE1 Clock")) - Name(MM0A, 0x1F70C000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "qmxge1clk") // clock-name - Name(CLNM, "qmxge1clk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - } - Device(CK0E) { - Name(_HID, "APMC0C04") - Name(_CID, 0x0A) - Name(_STR, Unicode("XGE2 Clock")) - Name(MM0A, 0x1F71C000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "xge2clk") // clock-name - Name(CLNM, "xge2clk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - } - Device(CK0F) { - Name(_HID, "APMC0C04") - Name(_CID, 0x0B) - Name(_STR, Unicode("XGE3 Clock")) - Name(MM0A, 0x1F72C000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "xge3clk") // clock-name - Name(CLNM, "xge3clk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - } - Device(CK10) { - Name(_HID, "APMC0C04") - Name(_CID, 0x0C) - Name(_STR, Unicode("PCIE0 Clock")) - Name(MM0A, 0x1F2BC000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "pcie0clk") // clock-name - Name(CLNM, "pcie0clk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - Name(EMSK, 0x0) // enable-mask - } - Device(CK11) { - Name(_HID, "APMC0C04") - Name(_CID, 0x0D) - Name(_STR, Unicode("PCIE1 Clock")) - Name(MM0A, 0x1F2CC000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "pcie1clk") // clock-name - Name(CLNM, "pcie1clk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - Name(EMSK, 0x0) // enable-mask - } - Device(CK12) { - Name(_HID, "APMC0C04") - Name(_CID, 0x0E) - Name(_STR, Unicode("PCIE2 Clock")) - Name(MM0A, 0x1F2DC000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "pcie2clk") // clock-name - Name(CLNM, "pcie2clk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - Name(EMSK, 0x0) // enable-mask - } - Device(CK13) { - Name(_HID, "APMC0C04") - Name(_CID, 0x0F) - Name(_STR, Unicode("PCIE3 Clock")) - Name(MM0A, 0x1F50C000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "pcie3clk") // clock-name - Name(CLNM, "pcie3clk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - Name(EMSK, 0x0) // enable-mask - } - Device(CK14) { - Name(_HID, "APMC0C04") - Name(_CID, 0x10) - Name(_STR, Unicode("PCIE4 Clock")) - Name(MM0A, 0x1F51C000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "pcie4clk") // clock-name - Name(CLNM, "pcie4clk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - Name(EMSK, 0x0) // enable-mask - } - Device(CK16) { - Name(_HID, "APMC0C04") - Name(_CID, 0x11) - Name(_STR, Unicode("USB0 Clock")) - Name(MM0A, 0x1F28C000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "usb0clk") // clock-name - Name(CLNM, "usb0clk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - } - Device(CK17) { - Name(_HID, "APMC0C04") - Name(_CID, 0x12) - Name(_STR, Unicode("USB1 Clock")) - Name(MM0A, 0x1F29C000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "usb1clk") // clock-name - Name(CLNM, "usb1clk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - } - Device(CK18) { - Name(_HID, "APMC0C04") - Name(_CID, 0x13) - Name(_STR, Unicode("Packet DMA Clock")) - Name(MM0A, 0x1F27C000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "pktdmaclk") // clock-name - Name(CLNM, "pktdmaclk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - } - Device(CK19) { - Name(_HID, "APMC0C04") - Name(_CID, 0x14) - Name(_STR, Unicode("AHB Clock")) - Name(MM0A, 0x1F2AC000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x17000000) // MMIO 1 Address - Name(MM1S, 0x1000) // MMIO 1 Size - Name(_UID, "ahbclk") // clock-name - Name(CLNM, "ahbclk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - Name(CSRO, 0x0) // csr-offset - Name(CSRM, 0x1) // csr-mask - Name(EOFF, 0x8) // enable-offset - Name(EMSK, 0x1) // enable-mask - Name(DIVO, 0x164) // divider-offset - Name(DIVW, 0x5) // divider-width - Name(DIVS, 0x0) // divider-shift - } - Device(CK1A) { - Name(_HID, "APMC0C04") - Name(_CID, 0x15) - Name(_STR, Unicode("APB Clock")) - Name(MM0A, 0x1F2AC000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x1F2AC000) // MMIO 1 Address - Name(MM1S, 0x1000) // MMIO 1 Size - Name(_UID, "apbclk") // clock-name - Name(CLNM, "apbclk") // clock-name - Name(PRNT, "ahbclk") // parent-clock - Name(CSRO, 0x0) // csr-offset - Name(CSRM, 0x200) // csr-mask - Name(EOFF, 0x8) // enable-offset - Name(EMSK, 0x200) // enable-mask - Name(DIVO, 0x10) // divider-offset - Name(DIVW, 0x2) // divider-width - Name(DIVS, 0x0) // divider-shift - } - Device(CK1B) { - Name(_HID, "APMC0C04") - Name(_CID, 0x16) - Name(_STR, Unicode("SPI0 Clock")) - Name(MM0A, 0x1F2AC000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "spi0clk") // clock-name - Name(CLNM, "spi0clk") // clock-name - Name(PRNT, "apbclk") // parent-clock - Name(CSRO, 0x0) // csr-offset - Name(CSRM, 0x100) // csr-mask - Name(EOFF, 0x8) // enable-offset - Name(EMSK, 0x100) // enable-mask - } - Device(CK1C) { - Name(_HID, "APMC0C04") - Name(_CID, 0x17) - Name(_STR, Unicode("SPI1 Clock")) - Name(MM0A, 0x1F2AC000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "spi1clk") // clock-name - Name(CLNM, "spi1clk") // clock-name - Name(PRNT, "apbclk") // parent-clock - Name(CSRO, 0x0) // csr-offset - Name(CSRM, 0x80) // csr-mask - Name(EOFF, 0x8) // enable-offset - Name(EMSK, 0x80) // enable-mask - } - Device(CK1D) { - Name(_HID, "APMC0C04") - Name(_CID, 0x18) - Name(_STR, Unicode("SDIO Clock")) - Name(MM0A, 0x1F2AC000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x17000000) // MMIO 1 Address - Name(MM1S, 0x1000) // MMIO 1 Size - Name(_UID, "sdioclk") // clock-name - Name(CLNM, "sdioclk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - Name(CSRO, 0x0) // csr-offset - Name(CSRM, 0x2) // csr-mask - Name(EOFF, 0x8) // enable-offset - Name(EMSK, 0x2) // enable-mask - Name(DIVO, 0x178) // divider-offset - Name(DIVW, 0x8) // divider-width - Name(DIVS, 0x0) // divider-shift - } - Device(CK1E) { - Name(_HID, "APMC0C04") - Name(_CID, 0x19) - Name(_STR, Unicode("UART0 Clock")) - Name(MM0A, 0x1F2AC000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "uart0clk") // clock-name - Name(CLNM, "uart0clk") // clock-name - Name(PRNT, "ahbclk") // parent-clock - Name(CSRO, 0x0) // csr-offset - Name(CSRM, 0x8) // csr-mask - Name(EOFF, 0x8) // enable-offset - Name(EMSK, 0x8) // enable-mask - } - Device(CK1F) { - Name(_HID, "APMC0C04") - Name(_CID, 0x1A) - Name(_STR, Unicode("UART1 Clock")) - Name(MM0A, 0x1F2AC000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "uart1clk") // clock-name - Name(CLNM, "uart1clk") // clock-name - Name(PRNT, "ahbclk") // parent-clock - Name(CSRO, 0x0) // csr-offset - Name(CSRM, 0x10) // csr-mask - Name(EOFF, 0x8) // enable-offset - Name(EMSK, 0x10) // enable-mask - } - Device(CK20) { - Name(_HID, "APMC0C04") - Name(_CID, 0x1B) - Name(_STR, Unicode("UART2 Clock")) - Name(MM0A, 0x1F2AC000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "uart2clk") // clock-name - Name(CLNM, "uart2clk") // clock-name - Name(PRNT, "ahbclk") // parent-clock - Name(CSRO, 0x0) // csr-offset - Name(CSRM, 0x20) // csr-mask - Name(EOFF, 0x8) // enable-offset - Name(EMSK, 0x20) // enable-mask - } - Device(CK21) { - Name(_HID, "APMC0C04") - Name(_CID, 0x1C) - Name(_STR, Unicode("UART3 Clock")) - Name(MM0A, 0x1F2AC000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "uart3clk") // clock-name - Name(CLNM, "uart3clk") // clock-name - Name(PRNT, "ahbclk") // parent-clock - Name(CSRO, 0x0) // csr-offset - Name(CSRM, 0x40) // csr-mask - Name(EOFF, 0x8) // enable-offset - Name(EMSK, 0x40) // enable-mask - } - Device(CK22) { - Name(_HID, "APMC0C04") - Name(_CID, 0x1D) - Name(_STR, Unicode("GPIO Clock")) - Name(MM0A, 0x1F2AC000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "gpioclk") // clock-name - Name(CLNM, "gpioclk") // clock-name - Name(PRNT, "ahbclk") // parent-clock - Name(CSRO, 0x0) // csr-offset - Name(CSRM, 0x4) // csr-mask - Name(EOFF, 0x8) // enable-offset - Name(EMSK, 0x4) // enable-mask - } - Device(CK23) { - Name(_HID, "APMC0C04") - Name(_CID, 0x1E) - Name(_STR, Unicode("I2C Clock")) - Name(MM0A, 0x17000000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "i2cclk") // clock-name - Name(CLNM, "i2cclk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - Name(CSRO, 0x0) // csr-offset - Name(CSRM, 0x2) // csr-mask - Name(EOFF, 0x10) // enable-offset - Name(EMSK, 0x4) // enable-mask - Name(DIVO, 0x168) // divider-offset - Name(DIVW, 0x5) // divider-width - Name(DIVS, 0x0) // divider-shift - } - Device(CK24) { - Name(_HID, "APMC0C04") - Name(_CID, 0x1F) - Name(_STR, Unicode("RTC Clock")) - Name(MM0A, 0x17000000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "rtcclk") // clock-name - Name(CLNM, "rtcclk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - Name(CSRO, 0xc) // csr-offset - Name(CSRM, 0x2) // csr-mask - Name(EOFF, 0x10) // enable-offset - Name(EMSK, 0x2) // enable-mask - } - Device(CK25) { - Name(_HID, "APMC0C04") - Name(_CID, 0x20) - Name(_STR, Unicode("TRNG PKA Clock")) - Name(MM0A, 0x17000000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "trngpkaclk")// clock-name - Name(CLNM, "trngpkaclk")// clock-name - Name(PRNT, "socplldiv2")// parent-clock - Name(CSRO, 0xc) // csr-offset - Name(CSRM, 0x10) // csr-mask - Name(EOFF, 0x10) // enable-offset - Name(EMSK, 0x10) // enable-mask - } - Device(CK26) { - Name(_HID, "APMC0C04") - Name(_CID, 0x21) - Name(_STR, Unicode("SATA01 PHY Clock")) - Name(MM0A, 0x1F21C000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "sataphy1clk") // clock-name - Name(CLNM, "sataphy1clk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - Name(CSRO, 0x4) // csr-offset - Name(CSRM, 0x3A) // csr-mask - Name(EOFF, 0x00) // enable-offset - Name(EMSK, 0x06) // enable-mask } - Device(CK27) { - Name(_HID, "APMC0C04") - Name(_CID, 0x22) - Name(_STR, Unicode("SATA23 PHY Clock")) - Name(MM0A, 0x1F22C000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "sataphy2clk") // clock-name - Name(CLNM, "sataphy2clk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - Name(CSRO, 0x4) // csr-offset - Name(CSRM, 0x3A) // csr-mask - Name(EOFF, 0x00) // enable-offset - Name(EMSK, 0x06) // enable-mask - } - Device(CK28) { - Name(_HID, "APMC0C04") - Name(_CID, 0x23) - Name(_STR, Unicode("SATA45 PHY Clock")) - Name(MM0A, 0x1F23C000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "sataphy3clk") // clock-name - Name(CLNM, "sataphy3clk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - Name(CSRO, 0x4) // csr-offset - Name(CSRM, 0x3A) // csr-mask - Name(EOFF, 0x00) // enable-offset - Name(EMSK, 0x06) // enable-mask - } - Device(CK29) { - Name(_HID, "APMC0C04") - Name(_CID, 0x24) - Name(_STR, Unicode("SATA01 Clock")) - Name(MM0A, 0x1F21C000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "sata01clk") // clock-name - Name(CLNM, "sata01clk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - Name(CSRO, 0x4) // csr-offset - Name(CSRM, 0x05) // csr-mask - Name(EOFF, 0x00) // enable-offset - Name(EMSK, 0x39) // enable-mask - } - Device(CK30) { - Name(_HID, "APMC0C04") - Name(_CID, 0x25) - Name(_STR, Unicode("SATA23 Clock")) - Name(MM0A, 0x1F22C000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "sata23clk") // clock-name - Name(CLNM, "sata23clk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - Name(CSRO, 0x4) // csr-offset - Name(CSRM, 0x05) // csr-mask - Name(EOFF, 0x00) // enable-offset - Name(EMSK, 0x39) // enable-mask - } - Device(CK31) { - Name(_HID, "APMC0C04") - Name(_CID, 0x26) - Name(_STR, Unicode("SATA45 Clock")) - Name(MM0A, 0x1F23C000) // MMIO 0 Address - Name(MM0S, 0x1000) // MMIO 0 Size - Name(MM1A, 0x00000000) // MMIO 1 Address - Name(MM1S, 0x0) // MMIO 1 Size - Name(_UID, "sata45clk") // clock-name - Name(CLNM, "sata45clk") // clock-name - Name(PRNT, "socplldiv2")// parent-clock - Name(CSRO, 0x4) // csr-offset - Name(CSRM, 0x05) // csr-mask - Name(EOFF, 0x00) // enable-offset - Name(EMSK, 0x39) // enable-mask - } - -/////////////////////////////////////////////////////////////////////////////// -// Reboot Device - Device(SRBD) { - Name(_HID, "APMC0D08") // Device Identification Objects - Name(_DDN, "SRD0") - Name(_UID, "SRD0") - Name(_STR, Unicode("System Reboot Device")) - Name(_ADR, 0x17000014) - Name(_CID, "SRBD0000") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0x17000014, 0x00000100, ) - }) - } //REBOOT
/////////////////////////////////////////////////////////////////////////////// // SLIMpro Device - Device(SLIM) { + Device(_SB.SLIM) { Name(_HID, "APMC0D01") // Device Identification Objects Name(_DDN, "SLIM") Name(_UID, "SLIM") @@ -1519,16 +1137,14 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) { Memory32Fixed(ReadWrite, 0x10540000, 0xa100, ) Memory32Fixed(ReadWrite, 0x17000000, 0x1000, ) Memory32Fixed(ReadWrite, 0x17001000, 0x1000, ) - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x0 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x1 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x2 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x3 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x4 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x5 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x6 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x7 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x8 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x9 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x20 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x21 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x22 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x23 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x24 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x25 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x26 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x27 } }) Name(DBST, 0x0000) // Doorbell start index Name(DBEN, 0x0007) // Doorbell end index @@ -1539,7 +1155,7 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) {
/////////////////////////////////////////////////////////////////////////////// // PCP Bus Device - Device(PCPD) { + Device(_SB.PCPD) { Name(_HID, "APMC0D02") // Device Identification Objects Name(_DDN, "PCP0") Name(_UID, "PCP0") @@ -1552,15 +1168,15 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) { Memory32Fixed(ReadWrite, 0x7C000000, 0x4000000, ) Memory32Fixed(ReadWrite, 0x7E200200, 0x1000, ) Memory32Fixed(ReadWrite, 0x7E600000, 0x1000, ) - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x20 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x21 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x27 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x40 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x41 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x47 } }) } //PCP Bus Device
/////////////////////////////////////////////////////////////////////////////// // GPIO - Device(GP00) { + Device(_SB.GP00) { Name(_HID, "APMC0D07") // Device Identification Objects Name(_CID, "APMC0D07") Name(_UID, "GPIO0") @@ -1575,9 +1191,11 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) { /////////////////////////////////////////////////////////////////////////////// //AHBC Bus // AHBC Device - Device(AHBC) { + Device(_SB.AHBC) { OperationRegion(SRST, SystemMemory, 0x1F2AC000, 4) OperationRegion(CLKE, SystemMemory, 0x1F2AC004, 4) + OperationRegion(SRRM, SystemMemory, 0x1F2AD070, 4) + OperationRegion(RD2F, SystemMemory, 0x1F2AE014, 4) Field(SRST, DWordAcc, NoLock, Preserve) { ACSR, 1, SDRS, 1, @@ -1602,6 +1220,14 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) { S1CE, 1, APCE, 1 } + Field(SRRM, DWordAcc, NoLock, Preserve) { + RMSH, 32 + } + Field(RD2F, DWordAcc, NoLock, Preserve) { + RSV9, 1, + RDFL, 1, + RSVA, 30 + }
// Device Identification Objects Name(_HID, "APMC0D06") @@ -1631,10 +1257,10 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) { //UART0 Device Controller Device(URT0) { //Device Identification Objects - Name(_HID, "UART0000") + Name(_HID, "APMC0D08") Name(_DDN, "URT0") Name(_UID, "URT0") - Name(_STR, Unicode("APM88xxxx UART0 Controller")) + Name(_STR, Unicode("APM X-Gene UART0 Controller"))
Name(_ADR, 0x1C020000) Name(_CID, "NS16550") @@ -1676,11 +1302,15 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) { Name(_PR0, Package() {SCVR}) //Can be put to D3 state when in S1 state Name(_S1D, 3) + //Lowest D-State supported in S1 to support wakeup + Name(_S1W, 0) + //Inform OSPM to use _S1W instead of _S1D when used for wake up + Name(_PRW, Package() { 0x0, 0x3 })
//Device Current Resource Settings //UART0 Generates an interrupt Name(_CRS, ResourceTemplate() { - Register(SystemMemory, 32, 0, 0x1C020000, 3) + Memory32Fixed(ReadWrite, 0x1C020000, 0x100) UARTSerialBus( 115200, //Baud Rate DataBitsEight, //Bits-per-byte @@ -1704,7 +1334,7 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) { //UART1 Device Controller Device(URT1) { //Device Identification Objects - Name(_HID, "UART0000") + Name(_HID, "APMC0D08") Name(_DDN, "URT1") Name(_UID, "URT1") Name(_STR, Unicode("APM88xxxx UART1 Controller")) @@ -1749,11 +1379,15 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) { Name(_PR0, Package() {SCVR}) //Can be put to D3 state when in S1 state Name(_S1D, 3) + //Lowest D-State supported in S1 to support wakeup + Name(_S1W, 0) + //Inform OSPM to use _S1W instead of _S1D when used for wake up + Name(_PRW, Package() { 0x0, 0x3 })
//Device Current Resource Settings //UART1 Generates an interrupt Name(_CRS, ResourceTemplate() { - Register(SystemMemory, 32, 0, 0x1C021000, 3) + Memory32Fixed(ReadWrite, 0x1C021000, 0x100) UARTSerialBus( 115200, //Baud Rate DataBitsEight, //Bits-per-byte @@ -1770,7 +1404,7 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) { U1DT ) Interrupt(ResourceProducer, Level, ActiveHigh, - Exclusive) {108} + Exclusive) {109} }) } //URT1 //============================================================================== @@ -1986,12 +1620,158 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) { ResourceConsumer, ) })//SP12 + + // SDIO0 + Device(SDM0) { + Name(_HID, "APMC0D0C") // Device Identification Objects + Name(_CID, "APMC0D0C") + Name(_STR, Unicode("APM X-Gene SDHCI Controller")) + + Method(_STA) { + Return (One) + } + + Name(_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x1C000000, 0x100) + Memory32Fixed (ReadWrite, 0x1f2a0000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake) { 0x69 } + }) + + OperationRegion(CPL0, SystemMemory, 0x1F2A0024, 4) + OperationRegion(CPH0, SystemMemory, 0x1F2A0028, 4) + OperationRegion(CFG0, SystemMemory, 0x1F2A0000, 4) + Field(CPL0, DWordAcc, NoLock, Preserve) { + TOCF, 6, + TOCU, 1, + BACF, 8, + MXBL, 2, + EMBS, 1, + ADM2, 1, + RSV1, 1, + HSST, 1, + SDMA, 1, + SURS, 1, + VS33, 1, + VS30, 1, + VS18, 1, + BS64, 1, + ASIS, 1, + SLTY, 2, + RSV2, 2 + } + Field(CPH0, DWordAcc, NoLock, Preserve) { + DTAS, 1, + DTCS, 1, + DTDS, 1, + TCRT, 4, + TU50, 1, + MODE, 2, + CLMU, 8, + SPIM, 1, + SPIB, 1, + RSV3, 12 + } + Field(CFG0, DWordAcc, NoLock, Preserve) { + RXWG, 4, + TXWG, 4, + PWMO, 4, + RSV4, 3, + WBRD, 1, + RSV5, 1, + RDPR, 2, + RDCH, 1, + RSV6, 1, + WRPR, 2, + WRCH, 1, + RSV7, 8 + } + + // Device Power Management Methods + // D0 State, ON + Method(_PS0) { + // Configure the capability of the core + Store(0x30, TOCF) // Time out 48MHz + Store(One, TOCU) // Clock unit MHz + Store(50, BACF) // 50MHz clock + Store(Zero, MXBL) // 512B block size + Store(Zero, EMBS) // No extend media support + Store(Zero, ADM2) // No ADMA2 support + Store(Zero, RSV1) + Store(One, HSST) // High speed support + Store(One, SDMA) // SDMA support + Store(One, SURS) // Suspend/resume support + Store(One, VS33) // 3.3 voltage support + Store(One, VS30) // 3.0 voltage support + Store(Zero, VS18) // No 1.8 voltage support + Store(Zero, BS64) // No 64-bit + Store(Zero, ASIS) // Async Int + Store(Zero, SLTY) // Removable media + Store(0, RSV2) + + Store(One, DTAS) // Type A support + Store(One, DTCS) // Type C support + Store(One, DTDS) // Type D support + Store(One, TCRT) // 1 seconds timer counter + Store(One, TU50) // SDR50 tuning + Store(Zero, MODE) // Return mode 1 + Store(Zero, CLMU) // Clock multipler + Store(Zero, SPIM) // No SPI mode + Store(Zero, SPIB) // No SPI block mode + Store(Zero, RSV3) // Reserved + + // Configure coherency + Store(0xf, RXWG) // Tx weight + Store(0xf, TXWG) // Tx weight + Store(0x1, PWMO) // PW Max outstanding + Store(0x0, RSV4) // Reserved + Store(0x1, WBRD) // Write block Read + Store(0x0, RSV5) // Reserved + Store(0x2, RDPR) // Read AXI sideband prio + Store(0x1, RDCH) // Read Coherent + Store(0x0, RSV6) // Reserved + Store(0x2, WRPR) // Write AXI sideband prio + Store(0x1, WRCH) // Write Coherent + Store(0x0, RSV7) // Reserved + + // Configure PIN Mux + // NOTE: Default for GPIO is SD function + + // Enable clock and CSR + Store(One, SDCE) // Enable the clock + Store(Zero, SDRS) // Enable the CSR + + // Enable AHBC read to flush + Store(1, RDFL) // Enable read to flush + + // Remove RAM from shutdown + Store(Zero, RMSH) // Release from shutdown + Sleep(1) // Sleep 1 ms + } + + // D3 State, OFF + // NOTE: This is only possible if you only enable 1 + // slot as both slot share the same clock and + // etc. + Method(_PS3) { + Store(One, SDRS) + Store(Zero, SDCE) + } + + // Current Power State + Method(_PSC) { + if (LOr(NAnd(U0RS, One), LEqual(U0CE, Zero))) { + Return (3) + } + Return (0) + } + } + //============================================================================== } //AHBC //////////////////////////////////////////////////////////////////////////////// // I2C1 VRM Bus
- Device(I2CS) { + Device(_SB.I2CS) { //Device Identification Objects Name(_HID, "I2CS0001") Name(_DDN, "I2CS") @@ -2078,7 +1858,7 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) {
/////////////////////////////////////////////////////////////////////////////// // SATA Devices - Device(PHY1) { + Device(_SB.PHY1) { Name(_HID, "APMC0D0A") // Device Identification Objects Name(_UID, 1) Name(_STR, Unicode("X-Gene PHY")) @@ -2088,45 +1868,18 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) { Name(_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x1F21A000, 0x100) }) - // Tx Booster/Gain - Name(TBG0, Buffer() { 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e }) - // Tx Booster/Gain SSD - Name(TBG1, Buffer() { 0x2, 0x2, 0x2, 0x2, 0x2, 0x2 }) - // Tx Eye Tuning - Name(TET0, Buffer() { 0x2, 0xa, 0xa, 0x2, 0xa, 0xa }) - // Tx Booster/Gain - pre-A3 chip - Name(TBGA, Buffer() { 0x2, 0x2, 0x2, 0x2, 0x2, 0x2 }) - // Tx Booster/Gain SSD - pre-A3 chip - Name(TBGB, Buffer() { 0x2, 0x2, 0x2, 0x2, 0x2, 0x2 }) - // Tx Eye Tuning - pre-A3 chip - Name(TETA, Buffer() { 0xa, 0xa, 0xa, 0xa, 0xa, 0xa }) - // Tx Speed - pre-A3 chip - Name(TSPA, Buffer() { 0x1, 0x3, 0x5}) - // Tx pre-cursor1 - pre-A3 chip (4 bytes - mV) - Name(TC1A, Buffer() { 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0 }) - // Tx post-cursor - pre-A3 chip (4 bytes - mV) - Name(TPCA, Buffer() { 0x0, 0x4, 0x2A, 0x68, - 0x0, 0x4, 0x2A, 0x68, - 0x0, 0x4, 0x2A, 0x68, - 0x0, 0x4, 0x2A, 0x68, - 0x0, 0x4, 0x2A, 0x68, - 0x0, 0x4, 0x2A, 0x68 }) - // Tx Amptitude - pre-A3 chip (4 bytes - mV) - Name(TAPA, Buffer() { 0x0, 0x3, 0x0B, 0x4C, - 0x0, 0x3, 0x0B, 0x4C, - 0x0, 0x3, 0x0B, 0x4C, - 0x0, 0x3, 0x0B, 0x4C, - 0x0, 0x3, 0x0B, 0x4C, - 0x0, 0x3, 0x0B, 0x4C }) - Name(CONS, "APMC0D00:00") - NAME(CLNM, "sataphy1clk") // clock-names + Method(_DSM, 4, NotSerialized) { + Store (Package (8) { + "consumer", "APMC0D00:00", + "apm,tx-boost-gain", "30 30 30 30 30 30", + "apm,tx-boost-gain-ssd", "2 2 2 2 2 2", + "apm,tx-eye-tuning", "2 10 10 2 10 10", + }, Local0) + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } }; - Device(PHY2) { + Device(_SB.PHY2) { Name(_HID, "APMC0D0A") // Device Identification Objects Name(_UID, 2) Name(_STR, Unicode("X-Gene PHY")) @@ -2136,45 +1889,18 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) { Name(_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x1F22A000, 0x100) }) - // Tx Booster/Gain - Name(TBG0, Buffer() { 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e }) - // Tx Booster/Gain SSD - Name(TBG1, Buffer() { 0x2, 0x2, 0x2, 0x2, 0x2, 0x2 }) - // Tx Eye Tuning - Name(TET0, Buffer() { 0x1, 0xa, 0xa, 0x2, 0xa, 0xa }) - // Tx Booster/Gain - pre-A3 chip - Name(TBGA, Buffer() { 0x2, 0x2, 0x2, 0x2, 0x2, 0x2 }) - // Tx Booster/Gain SSD - pre-A3 chip - Name(TBGB, Buffer() { 0x2, 0x2, 0x2, 0x2, 0x2, 0x2 }) - // Tx Eye Tuning - pre-A3 chip - Name(TETA, Buffer() { 0x1, 0xa, 0xa, 0x2, 0xa, 0xa }) - // Tx Speed - pre-A3 chip - Name(TSPA, Buffer() { 0x1, 0x3, 0x5}) - // Tx pre-cursor1 - pre-A3 chip (4 bytes - mV) - Name(TC1A, Buffer() { 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0 }) - // Tx post-cursor - pre-A3 chip (4 bytes - mV) - Name(TPCA, Buffer() { 0x0, 0x4, 0x2A, 0x68, - 0x0, 0x4, 0x2A, 0x68, - 0x0, 0x4, 0x2A, 0x68, - 0x0, 0x4, 0x2A, 0x68, - 0x0, 0x4, 0x2A, 0x68, - 0x0, 0x4, 0x2A, 0x68 }) - // Tx Amptitude - pre-A3 chip (4 bytes - mV) - Name(TAPA, Buffer() { 0x0, 0x3, 0x0B, 0x4C, - 0x0, 0x3, 0x0B, 0x4C, - 0x0, 0x3, 0x0B, 0x4C, - 0x0, 0x3, 0x0B, 0x4C, - 0x0, 0x3, 0x0B, 0x4C, - 0x0, 0x3, 0x0B, 0x4C }) - Name(CONS, "APMC0D0D:00") - NAME(CLNM, "sataphy2clk") // clock-names + Method(_DSM, 4, NotSerialized) { + Store (Package (8) { + "consumer", "APMC0D0D:00", + "apm,tx-boost-gain", "30 30 30 30 30 30", + "apm,tx-boost-gain-ssd", "2 2 2 2 2 2", + "apm,tx-eye-tuning", "1 10 10 2 10 10", + }, Local0) + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } }; - Device(PHY3) { + Device(_SB.PHY3) { Name(_HID, "APMC0D0B") // Device Identification Objects Name(_UID, 3) Name(_STR, Unicode("X-Gene PHY")) @@ -2185,135 +1911,109 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) { Memory32Fixed (ReadWrite, 0x1F23A000, 0x100) Memory32Fixed (ReadWrite, 0x1F2D0000, 0x100) }) - // Tx Booster/Gain - Name(TBG0, Buffer() { 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f }) - // Tx Booster/Gain SSD - Name(TBG1, Buffer() { 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 }) - // Tx Eye Tuning - Name(TET0, Buffer() { 0x2, 0xa, 0xa, 0x2, 0xa, 0xa }) - // Tx Booster/Gain - pre-A3 chip - Name(TBGA, Buffer() { 0x2, 0x2, 0x2, 0x2, 0x2, 0x2 }) - // Tx Booster/Gain SSD - pre-A3 chip - Name(TBGB, Buffer() { 0x2, 0x2, 0x2, 0x2, 0x2, 0x2 }) - // Tx Eye Tuning - pre-A3 chip - Name(TETA, Buffer() { 0xa, 0xa, 0xa, 0xa, 0xa, 0xa }) - // Tx Speed - pre-A3 chip - Name(TSPA, Buffer() { 0x1, 0x3, 0x5}) - // Tx pre-cursor1 - pre-A3 chip (4 bytes - mV) - Name(TC1A, Buffer() { 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0 }) - // Tx post-cursor - pre-A3 chip (4 bytes - mV) - Name(TPCA, Buffer() { 0x0, 0x4, 0x2A, 0x68, - 0x0, 0x4, 0x2A, 0x68, - 0x0, 0x4, 0x2A, 0x68, - 0x0, 0x4, 0x2A, 0x68, - 0x0, 0x4, 0x2A, 0x68, - 0x0, 0x4, 0x2A, 0x68 }) - // Tx Amptitude - pre-A3 chip (4 bytes - mV) - Name(TAPA, Buffer() { 0x0, 0x3, 0x0B, 0x4C, - 0x0, 0x3, 0x0B, 0x4C, - 0x0, 0x3, 0x0B, 0x4C, - 0x0, 0x3, 0x0B, 0x4C, - 0x0, 0x3, 0x0B, 0x4C, - 0x0, 0x3, 0x0B, 0x4C }) - Name(CONS, "APMC0D09:00") - NAME(CLNM, "sataphy3clk") // clock-names + Method(_DSM, 4, NotSerialized) { + Store (Package (8) { + "consumer", "APMC0D09:00", + "apm,tx-boost-gain", "31 31 31 31 31 31", + "apm,tx-boost-gain-ssd", "3 3 3 3 3 3", + "apm,tx-eye-tuning", "2 10 10 2 10 10", + }, Local0) + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } }; - Device(SAT0) { + Device(_SB.SAT0) { Name(_HID, "APMC0D00") // Device Identification Objects Name(_UID, 1) Name(_STR, Unicode("X-Gene SATA")) - Method(_STA, 0, NotSerialized) { + Method(_STA, 0, NotSerialized) + { Return (0x0) - } + } Name(_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x1A000000, 0x1000) - Memory32Fixed (ReadWrite, 0x1F210000, 0x10000) - Memory32Fixed (ReadWrite, 0x1F2A0000, 0x10000) + Memory32Fixed (ReadWrite, 0x1F210000, 0x1000) + Memory32Fixed (ReadWrite, 0x1F21D000, 0x1000) + Memory32Fixed (ReadWrite, 0x1F21E000, 0x1000) Memory32Fixed (ReadWrite, 0x1C000200, 0x100) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x86} + Memory32Fixed (ReadWrite, 0x1f217000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0xA6} }) - NAME(CLNM, "sata01clk") // clock-names } //SAT0 - Device(SAT1) { + Device(_SB.SAT1) { Name(_HID, "APMC0D0D") // Device Identification Objects Name(_UID, 2) Name(_STR, Unicode("X-Gene SATA")) - Method(_STA, 0, NotSerialized) { + Method(_STA, 0, NotSerialized) + { Return (0x1) - } + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x1A400000, 0x1000) - Memory32Fixed (ReadWrite, 0x1F220000, 0x10000) - Memory32Fixed (ReadWrite, 0x1F2A0000, 0x10000) + Memory32Fixed (ReadWrite, 0x1F220000, 0x1000) + Memory32Fixed (ReadWrite, 0x1F22D000, 0x1000) + Memory32Fixed (ReadWrite, 0x1F22E000, 0x1000) Memory32Fixed (ReadWrite, 0x1C000200, 0x100) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x87} + Memory32Fixed (ReadWrite, 0x1f227000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0xA7} }) - NAME(CLNM, "sata23clk") // clock-names } //SAT1 - Device(SAT2) { + Device(_SB.SAT2) { Name(_HID, "APMC0D09") // Device Identification Objects Name(_UID, 3) Name(_STR, Unicode("X-Gene SATA")) - Method(_STA, 0, NotSerialized) { + Method(_STA, 0, NotSerialized) + { Return (0x1) - } + } Name(_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x1A800000, 0x1000) - Memory32Fixed (ReadWrite, 0x1F230000, 0x10000) - Memory32Fixed (ReadWrite, 0x1F2A0000, 0x10000) + Memory32Fixed (ReadWrite, 0x1F230000, 0x1000) + Memory32Fixed (ReadWrite, 0x1F23D000, 0x1000) + Memory32Fixed (ReadWrite, 0x1F23E000, 0x1000) Memory32Fixed (ReadWrite, 0x1C000200, 0x100) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x88} + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0xA8} }) - NAME(CLNM, "sata45clk") // clock-names } //SAT2
/////////////////////////////////////////////////////////////////////////////// // USB Devices - Device(USB0) { + Device(_SB.USB0) { Name(_HID, "APMC0D03") Name(_DDN, "USB0") Name(_UID, "USB0") - Name(_STR, Unicode("APM88xxxx USB")) - Name(_CID, "APMC0D03") + Name(_STR, Unicode("X-Gene USB")) + Method(_STA, 0, NotSerialized) + { + Return (0x1) + } + Name(_CID, "PNP0D10") Name(_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x19000000, 0x100000) Memory32Fixed (ReadWrite, 0x1F280000, 0x10000) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x89} + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0xA9} }) - NAME(CLNM, "usb0clk") // clock-names - Name(STAT, "ok") // status - NAME(SDCL, 0x0) // serdes-diff-clk - NAME(GENS, 0x3) // gen-sel - NAME(OVCE, 0x0) // Overcur Enable - NAME(OVCI, 0x0) // Overcur Invert } //USB0 - Device(USB1) { + Device(_SB.USB1) { Name(_HID, "APMC0D03") Name(_DDN, "USB1") Name(_UID, "USB1") - Name(_STR, Unicode("APM88xxxx USB")) - Name(_CID, "APMC0D03") + Name(_STR, Unicode("X-Gene USB")) + Method(_STA, 0, NotSerialized) + { + Return (0x1) + } + Name(_CID, "PNP0D10") Name(_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x19800000, 0x100000) Memory32Fixed (ReadWrite, 0x1F290000, 0x10000) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x8a} + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0xAA} }) - NAME(CLNM, "usb1clk") // clock-names - Name(STAT, "ok") // status - NAME(SDCL, 0x0) // serdes-diff-clk - NAME(GENS, 0x3) // gen-sel - NAME(OVCE, 0x0) // Overcur Enable - NAME(OVCI, 0x0) // Overcur Invert } //USB1
/////////////////////////////////////////////////////////////////////////////// // QM Device - Device(QM03) { + Device(_SB.QM03) { Name(_HID, "APMC0D04") // Device Identification Objects Name(_DDN, "QM03") Name(_UID, "QM03") @@ -2322,161 +2022,272 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) { Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0x17030000, 0x10000, ) Memory32Fixed(ReadWrite, 0x10000000, 0x400000, ) - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x40 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x3c } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x60 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x5C } }) - Name(CLNM, "qmlclk") // clock-names - Name(DVID, 0x03) // Device ID - Name(MQID, 0x400) // Max QID - Name(SLNM, "CPU_QMTM3") // Slave name - Name(SLIF, Buffer() { 0x03, 0x00, 0x01, 0x20, 0x01 }) // Slave info + OperationRegion(CLKQ, SystemMemory, 0x1703c008, 4) + Field(CLKQ, DWordAcc, NoLock, Preserve) { + CLKE, 2, + } + Method(_INI, 0, NotSerialized) { + Store(0x3, CLKE) + Stall(100) + } + Method(_DSM, 4, NotSerialized) { + Store (Package (8) { + "max_queues", "1024", + "devid", "3", + "slave_name", "CPU_QMTM3", + "slave_info", "3 0 1 32 1", + }, Local0) + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } } // QM03
- Device(QM01) { + Device(_SB.QM01) { Name(_HID, "APMC0D04") // Device Identification Objects Name(_DDN, "QM01") Name(_UID, "QM01") Name(_STR, Unicode("QM 1 Device")) Name(_CID, "APMC0D04") + Method(_STA, 0, NotSerialized) { + Return (0x1) + } Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0x1f200000, 0x10000, ) Memory32Fixed(ReadWrite, 0x1b000000, 0x400000, ) + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xe0 } Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xc0 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xa0 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xa1 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xa2 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xa3 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xa4 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xa5 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xa6 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xa7 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xa8 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xa9 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xaa } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xab } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xac } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xad } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xae } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xaf } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xb0 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xb1 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xb2 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xb3 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xb4 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xb5 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xb6 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xb7 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xb8 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xb9 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xba } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xbb } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xbc } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xbd } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xbe } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xbf } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xc1 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xc2 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xc3 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xc4 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xc5 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xc6 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xc7 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xc8 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xc9 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xca } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xcb } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xcc } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xcd } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xce } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xcf } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xd0 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xd1 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xd2 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xd3 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xd4 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xd5 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xd6 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xd7 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xd8 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xd9 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xda } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xdb } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xdc } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xdd } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xde } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xdf } }) - Name(CLNM, "qm1clk") // clock-names - Name(DVID, 0x01) // Device ID - Name(MQID, 0x400) // Max QID - Name(SLNM, "CPU_QMTM1") // Slave name - Name(SLIF, Buffer() { 0x01, 0x00, 0x20, 0x20, 0x20 }) // Slave info + OperationRegion(CLKQ, SystemMemory, 0x1f20c008, 4) + Field(CLKQ, DWordAcc, NoLock, Preserve) { + CLKE, 2, + } + Method(_INI, 0, NotSerialized) { + Store(0x3, CLKE) + Stall(100) + } + Method(_DSM, 4, NotSerialized) { + Store (Package (8) { + "max_queues", "1024", + "devid", "1", + "slave_name", "CPU_QMTM1", + "slave_info", "1 0 32 32 32", + }, Local0) + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } } // QM01
- Device(QM00) { + Device(_SB.QM00) { Name(_HID, "APMC0D04") // Device Identification Objects Name(_DDN, "QM00") Name(_UID, "QM00") Name(_STR, Unicode("QM 0 Device")) Name(_CID, "APMC0D04") + Method(_STA, 0, NotSerialized) { + Return (0x1) + } Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0x1f600000, 0x10000, ) Memory32Fixed(ReadWrite, 0x18000000, 0x400000, ) + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xA0 } Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x80 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x60 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x61 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x62 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x63 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x64 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x65 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x66 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x67 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x68 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x69 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x6a } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x6b } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x6c } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x6d } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x6e } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x6f } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x81 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x82 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x83 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x84 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x85 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x86 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x87 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x88 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x89 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x8a } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x8b } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x8c } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x8d } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x8e } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x8f } }) - Name(CLNM, "qmxge0clk") // clock-names - Name(DVID, 0x00) // Device ID - Name(MQID, 0x400) // Max QID - Name(SLNM, "CPU_QMTM0") // Slave name - Name(SLIF, Buffer() { 0x00, 0x00, 0x10, 0x20, 0x10 }) // Slave info + OperationRegion(CLKQ, SystemMemory, 0x1f60c008, 4) + Field(CLKQ, DWordAcc, NoLock, Preserve) { + CLKE, 2, + } + Method(_INI, 0, NotSerialized) { + Store(0x3, CLKE) + Stall(100) + } + Method(_DSM, 4, NotSerialized) { + Store (Package (8) { + "max_queues", "1024", + "devid", "0", + "slave_name", "CPU_QMTM0", + "slave_info", "0 0 16 32 16", + }, Local0) + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } } // QM00
- Device(QM02) { + Device(_SB.QM02) { Name(_HID, "APMC0D04") // Device Identification Objects Name(_DDN, "QM02") Name(_UID, "QM02") Name(_STR, Unicode("QM 2 Device")) Name(_CID, "APMC0D04") + Method(_STA, 0, NotSerialized) { + Return (0x1) + } Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0x1f700000, 0x10000, ) Memory32Fixed(ReadWrite, 0x1e000000, 0x400000, ) - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xc1 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x70 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x71 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x72 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x73 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x74 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x75 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x76 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x77 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x78 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x79 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x7a } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x7b } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x7c } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x7d } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x7e } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x7f } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xE1 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x90 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x91 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x92 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x93 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x94 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x95 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x96 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x97 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x98 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x99 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x9a } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x9b } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x9c } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x9d } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x9e } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x9f } }) - Name(CLNM, "qmxge1clk") // clock-names - Name(DVID, 0x02) // Device ID - Name(MQID, 0x400) // Max QID - Name(SLNM, "CPU_QMTM2") // Slave name - Name(SLIF, Buffer() { 0x02, 0x10, 0x10, 0x30, 0x10 }) // Slave info + OperationRegion(CLKQ, SystemMemory, 0x1f70c008, 4) + Field(CLKQ, DWordAcc, NoLock, Preserve) { + CLKE, 2, + } + Method(_INI, 0, NotSerialized) { + Store(0x3, CLKE) + Stall(100) + } + Method(_DSM, 4, NotSerialized) { + Store (Package (8) { + "max_queues", "1024", + "devid", "2", + "slave_name", "CPU_QMTM2", + "slave_info", "2 16 16 48 16", + }, Local0) + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } } //QM02 - +/////////////////////////////////////////////////////////////////////////////// +//SOC PLL and ETH Divider Fields +//Operation Region For Eth Speed Control + OperationRegion(\SOCP, SystemMemory, 0x17000120, 4) + Field(\SOCP, DWordAcc, NoLock, Preserve) { + CLKF, 9, + RSV1, 11, + CLOD, 2, + RSV2, 2, + CLKR, 3, + RSV3, 5 + } /////////////////////////////////////////////////////////////////////////////// // Ethernet Device - Device(ET08) { + Device(_SB.ET08) { Name(_HID, "APMC0D05") // Device Identification Objects Name(_DDN, "ET08") Name(_UID, "ET08") Name(_STR, Unicode("Ethernet RGMII Device")) Name(_CID, "APMC0D05") + Method(_STA, 0, NotSerialized) { + Return (0x1) + } Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0x17020000, 0x30, ) Memory32Fixed(ReadWrite, 0x17020000, 0x10000, ) Memory32Fixed(ReadWrite, 0x17020000, 0x20, ) - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x38 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x39 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x3a } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x58 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x59 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x5a } }) - Name(CLNM, "eth8clk") // clock-names - Name(DVID, 0x08) // Device ID - Name(SLNM, "RGMII") - Name(SLIF, Buffer() { 0x03, 0x00, 0x04, 0x20, 0x04 }) - Name(FMSZ, 0x233a) // Frame-size - Name(PHID, 0x03) // Phy ID - Name(PHMD, "rgmii") // PHY mode - Name(MAC0, Buffer() { 0x00, 0x11, 0x3a, 0x8a, 0x5a, 0x78 }) // MAC Address + + OperationRegion(\ETHD, SystemMemory, 0x17000238, 4) + Field(\ETHD, DWordAcc, NoLock, Preserve) { + NDIV, 9, + } + Method(S10, 0, NotSerialized) { + // 10Mbps requires 2.5MHz clock + // SOC DIV 2 = REF * (CLKF/((CLKR+1) * (CLKD+1))) + // NDIV = (SOC DIV 2)/2500000 + Store(Divide(Divide(Multiply(100000000, Divide(CLKF, Multiply(Add(CLKR, One), Add(CLOD, One)))), 2), 2500000), NDIV) + } + Method(S100, 0, NotSerialized) { + // 100Mbps requires 25MHz clock + // SOC DIV 2 = REF * (CLKF/((CLKR+1) * (CLKD+1))) + // 100Mbps = (SOC DIV 2)/25000000 + Store(Divide(Divide(Multiply(100000000, Divide(CLKF, Multiply(Add(CLKR, One), Add(CLOD, One)))), 2), 25000000), NDIV) + } + Method(S1G, 0, NotSerialized) { + // 1Gbps requires 125MHz clock + // SOC DIV 2 = REF * (CLKF/((CLKR+1) * (CLKD+1))) + // NDIV = (SOC DIV 2)/125000000 + Store(Divide(Divide(Multiply(100000000, Divide(CLKF, Multiply(Add(CLKR, One), Add(CLOD, One)))), 2), 125000000), NDIV) + } + OperationRegion(CLKQ, SystemMemory, 0x1702c008, 4) + Field(CLKQ, DWordAcc, NoLock, Preserve) { + CLKE, 2, + } + Method(_INI, 0, NotSerialized) { + Store(0x2, CLKE) + Stall(100) + } + Method(_DSM, 4, NotSerialized) { + Store (Package (14) { + "devid", "8", + "slave_name", "RGMII", + "slave_info", "3 0 4 32 4", + "max-frame-size", "9018", + "phyid", "3", + "phy-mode", "rgmii", + "local-mac-address", "00:00:00:00:00:00" + }, Local0) + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } }
- Device(ET00) { + Device(_SB.ET00) { Name(_HID, "APMC0D05") // Device Identification Objects Name(_DDN, "ET00") Name(_UID, "ET00") @@ -2489,21 +2300,34 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) { Memory32Fixed(ReadWrite, 0x1f210000, 0x30, ) Memory32Fixed(ReadWrite, 0x1f210000, 0x10000, ) Memory32Fixed(ReadWrite, 0x17020000, 0x10000, ) - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x8c } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x8d } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x90 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xac } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xad } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xb0 } }) - Name(CLNM, "eth01clk") // clock-names - Name(DVID, 0x00) // Device ID - Name(SLNM, "SGMII0") - Name(SLIF, Buffer() { 0x01, 0x00, 0x08, 0x20, 0x08 }) - Name(FMSZ, 0x233a) // Frame-size - Name(PHID, 0x1e) // Phy ID - Name(PHMD, "sgmii") // PHY mode - Name(MAC0, Buffer() { 0x00, 0x11, 0x3a, 0x8a, 0x5a, 0x6c }) // MAC Address + OperationRegion(CLKQ, SystemMemory, 0x1f21c008, 4) + Field(CLKQ, DWordAcc, NoLock, Preserve) { + CLKE, 4, + } + Method(_INI, 0, NotSerialized) { + Store(0xf, CLKE) + Stall(100) + } + Method(_DSM, 4, NotSerialized) { + Store (Package (14) { + "devid", "0", + "slave_name", "SGMII0", + "slave_info", "1 0 8 32 8", + "max-frame-size", "9018", + "phyid", "30", + "phy-mode", "sgmii", + "local-mac-address", "00:00:00:00:00:00" + }, Local0) + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } }
- Device(ET01) { + Device(_SB.ET01) { Name(_HID, "APMC0D05") // Device Identification Objects Name(_DDN, "ET01") Name(_UID, "ET01") @@ -2516,21 +2340,34 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) { Memory32Fixed(ReadWrite, 0x1f210030, 0x30, ) Memory32Fixed(ReadWrite, 0x1f210000, 0x10000, ) Memory32Fixed(ReadWrite, 0x17020000, 0x10000, ) - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x8c } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x8d } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x90 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xac } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xad } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xb0 } }) - Name(CLNM, "eth01clk") // clock-names - Name(DVID, 0x01) // Device ID - Name(SLNM, "SGMII1") - Name(SLIF, Buffer() { 0x01, 0x08, 0x08, 0x28, 0x08 }) - Name(FMSZ, 0x233a) // Frame-size - Name(PHID, 0x1e) // Phy ID - Name(PHMD, "sgmii") // PHY mode - Name(MAC0, Buffer() { 0x00, 0x11, 0x3a, 0x8a, 0x5a, 0x6d }) // MAC Address + OperationRegion(CLKQ, SystemMemory, 0x1f21c008, 4) + Field(CLKQ, DWordAcc, NoLock, Preserve) { + CLKE, 4, + } + Method(_INI, 0, NotSerialized) { + Store(0xf, CLKE) + Stall(100) + } + Method(_DSM, 4, NotSerialized) { + Store (Package (14) { + "devid", "1", + "slave_name", "SGMII1", + "slave_info", "1 8 8 40 8", + "max-frame-size", "9018", + "phyid", "30", + "phy-mode", "sgmii", + "local-mac-address", "00:00:00:00:00:00" + }, Local0) + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } }
- Device(ET04) { + Device(_SB.ET04) { Name(_HID, "APMC0D05") // Device Identification Objects Name(_DDN, "ET04") Name(_UID, "ET04") @@ -2542,22 +2379,35 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) { Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0x1f610000, 0x30, ) Memory32Fixed(ReadWrite, 0x1f610000, 0x10000, ) - Memory32Fixed(ReadWrite, 0x1f610000, 0x10000, ) - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x50 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x51 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x52 } + Memory32Fixed(ReadWrite, 0x17020000, 0x10000, ) + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x70 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x71 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x72 } }) - Name(CLNM, "xge0clk") // clock-names - Name(DVID, 0x04) // Device ID - Name(SLNM, "SXGMII0") - Name(SLIF, Buffer() { 0x00, 0x00, 0x08, 0x20, 0x08 }) - Name(FMSZ, 0x233a) // Frame-size - Name(PHID, 0x01) // Phy ID - Name(PHMD, "xgmii") // PHY mode - Name(MAC0, Buffer() { 0x00, 0x11, 0x3a, 0x8a, 0x5a, 0x74}) // MAC Address + OperationRegion(CLKQ, SystemMemory, 0x1f61c008, 4) + Field(CLKQ, DWordAcc, NoLock, Preserve) { + CLKE, 2, + } + Method(_INI, 0, NotSerialized) { + Store(0x3, CLKE) + Stall(100) + } + Method(_DSM, 4, NotSerialized) { + Store (Package (14) { + "devid", "4", + "slave_name", "SXGMII0", + "slave_info", "0 0 8 32 8", + "max-frame-size", "9018", + "phyid", "1", + "phy-mode", "xgmii", + "local-mac-address", "00:00:00:00:00:00" + }, Local0) + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } }
- Device(ET05) { + Device(_SB.ET05) { Name(_HID, "APMC0D05") // Device Identification Objects Name(_DDN, "ET05") Name(_UID, "ET05") @@ -2569,19 +2419,408 @@ DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) { Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0x1f620000, 0x30, ) Memory32Fixed(ReadWrite, 0x1f620000, 0x10000, ) - Memory32Fixed(ReadWrite, 0x1f620000, 0x10000, ) - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x53 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x54 } - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x55 } + Memory32Fixed(ReadWrite, 0x17020000, 0x10000, ) + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x73 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x74 } + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x75 } + }) + OperationRegion(CLKQ, SystemMemory, 0x1f61c008, 4) + Field(CLKQ, DWordAcc, NoLock, Preserve) { + CLKE, 2, + } + Method(_INI, 0, NotSerialized) { + Store(0x3, CLKE) + Stall(100) + } + Method(_DSM, 4, NotSerialized) { + Store (Package (14) { + "devid", "5", + "slave_name", "SXGMII1", + "slave_info", "0 0 8 32 8", + "max-frame-size", "9018", + "phyid", "1", + "phy-mode", "xgmii", + "local-mac-address", "00:00:00:00:00:00" + }, Local0) + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } +/////////////////////////////////////////////////////////////////////////////// +//PCIe0 + Device(_SB.PCI0) { + // + // Hardware ID must be PNP0A08, which maps to a PCIe root complex. + // Section 6.1.5 + // + + Name(_HID,"PNP0A08") + + // + // Optionally, include a compatible ID of PNP0A03, which maps to a PCI + // root complex for use with pre-PCIe operating systems. + // Section 6.1.2 + // + + Name(_CID,"PNP0A03") + + // + // Declare the segment number of this root complex. Most systems only + // have one segment, which is numbered 0. + // Section 6.5.6 + // + + Name(_SEG, 0) + + // + // Declare the base bus number, which is the bus number of the root + // bus in this root complex. This is usually 0, but need not be. + // For root complexes supporting multiple root busses, this should + // be the lowest numbered root bus. + // Section 6.5.5 + // + + Name(_BBN, 0) + + // + // The _UID value provides a way of uniquely identifying a device + // in the case where more than one instance of a specific device + // is implemented with the same _HID/_CID. For systems with a + // single root complex, this is usually just 0. For systems with + // multiple root complexes, this should be different for each + // root complex. + // Section 6.1.12 + // + + Name(_UID, "PCI0") + Name(_STR, Unicode("PCIe 0 Device")) + + // + // Declare the PCI Routing Table. + // This defines SPI mappings of the four line-based interrupts + // associated with the root complex and hierarchy below it. + // Section 6.2.12 + // + + Name(_PRT, Package() { + + // + // Routing for device 0, all functions. + // Note: ARM doesn't support LNK nodes, so the third param + // is 0 and the fourth param is the SPI number of the interrupt + // line. In this example, the A/B/C/D interrupts are wired to + // SPI lines 100/101/102/103 respectively. + // + + Package() {0x0000FFFF, 0, 0, 226}, + Package() {0x0000FFFF, 1, 0, 227}, + Package() {0x0000FFFF, 2, 0, 228}, + Package() {0x0000FFFF, 3, 0, 229}, + }) + + // + // Declare the resources assigned to this root complex. + // Section 6.2.2 + // + Method (_CBA, 0, Serialized) { + Return (0xE0D0000000) + } + Method (_CRS, 0, Serialized) { + + // + // Declare a ResourceTemplate buffer to return the resource + // requirements from _CRS. + // Section 19.5.109 + // + + Name (RBUF, ResourceTemplate () { + + // + // Declare the range of bus numbers assigned to this root + // complex. In this example, the minimum bus number will be + // 0, the maximum bus number will be 0xFF, supporting + // 256 busses total. + // Section 19.5.141 + // + + WordBusNumber ( + ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + PosDecode, // Decode + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256) // RangeLength - Number of Busses + + // + // Declare the memory range to be used for BAR memory + // windows. This declares a 4GB region starting at + // 0x4000000000. + // Section 19.5.80 + // + Memory32Fixed(ReadWrite, 0x1F2B0000, 0x10000, ) + +// QWordIO( +// ResourceConsumer, +// MinFixed, +// MaxFixed, +// PosDecode, +// EntireRange, +// 0x0000000000000000, +// 0x0000000010000000, +// 0x000000001000FFFF, +// 0x000000E000000000, +// 0x0000000000010000 +// ) + QWordMemory( + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0000000000000000, + 0x0000000030000000, + 0x0000000030FFFFFF, + 0x000000E000000000, + 0x0000000001000000 + ) + QWordMemory( + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0000000000000000, + 0x000000e100000000, + 0x000000e13FFFFFFF, + 0x0000000000000000, + 0x0000000040000000 + ) + }) + + Return (RBUF) + } + + // + // Declare an _OSC (OS Control Handoff) method which takes 4 arguments. + // + // Argments: + // Arg0 A Buffer containing a UUID + // Arg1 An Integer containing a Revision ID of the buffer format + // Arg2 An Integer containing a count of entries in Arg3 + // Arg3 A Buffer containing a list of DWORD capabilities + // Return Value: + // A Buffer containing a list of capabilities + // See the APCI spec, Section 6.2.10, + // and the PCI FW spec, Section 4.5. + // + // The following is an example, and may need modification for + // specific implementations. + // + + Name(SUPP,0) // PCI _OSC Support Field value + Name(CTRL,0) // PCI _OSC Control Field value + Method(_OSC, 4) { + + // + // Look for the PCI Host Bridge Interface UUID. + // Section 6.2.10.3 + // + + // + // Create DWord-adressable fields from the Capabilities Buffer + // Create CDW1 outside the test as it's used in the else clause. + // + + CreateDWordField(Arg3,0,CDW1) + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + CreateDWordField(Arg3,4,CDW2) + CreateDWordField(Arg3,8,CDW3) + + // + // Save Capabilities DWord 2 & 3 + // + + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports: + // ASPM + // Clock PM + // MSI/MSI-X + // + + // Storm, no hotplug, but still return bit 0 set + // because win won't be happy. + And(CTRL,0x1D,CTRL) + + //If(LNotEqual(And(SUPP, 0x16), 0x16)) { + + // + // Mask bit 0 (and undefined bits) + // + + // And(CTRL,0x1E,CTRL) + //} + + // + // Always allow native PME, AER (no dependencies). + // Never allow SHPC (no SHPC controller in this system). + // + + And(CTRL,0x1D,CTRL) + + // + // Check for unknown revision. + // + + If(LNotEqual(Arg1,One)) { + Or(CDW1,0x08,CDW1) + } + + // + // Check if capabilities bits were masked. + // + + If(LNotEqual(CDW3,CTRL)) { + Or(CDW1,0x10,CDW1) + } + + // + // Update DWORD3 in the buffer. + // + + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + + // + // Unrecognized UUID + // + + Or(CDW1,4,CDW1) + Return(Arg3) + } + } // End _OSC + + // + // Declare a _DSM method for various functions called by the OS. + // See the APCI spec, Section 9.14.1, + // and the PCI FW spec, Section 4.6. + // See also: + // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac... + // + + Method(_DSM, 0x4, Serialized) { + + // + // Match against the _DSM PCI GUID. + // + + If(LEqual(Arg0,ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) { + + switch(ToInteger(Arg2)) + { + // + // Function 0: Return supported functions as a bitfield + // with one bit for each supported function. + // Bit 0 must always be set, as that represents + // function 0 (which is what is being called here). + // Support for different functions may depend on + // the revision ID of the interface, passed as Arg1. + // + + case(0) { + + // + // Functions 0-7 are supported. + // + + return (Buffer() {0x01}) + } + + + } + } + + // + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + // + + return(Buffer(){0}) + } + + // + // Root Port 0 Device within the Root Complex. + // + + Device(RP0) { + + // + // Device 0, Function 0. + // + + Name(_ADR, 0x00000000) + + // + // Power resources required for D0. + // + + Name(_PR0, Package() {SCVR}) + + // + // Power resources required for D3Hot. + // + + Name(_PR3, Package(){SCVR}) + } + } // PCI0 + +/////////////////////////////////////////////////////////////////////////////// +// MSI + Device(_SB.MSIX) { + Name(_HID, "APMC0D0E") // Device Identification Objects + Name(_UID, 0) + Name(_STR, Unicode("X-Gene MSI/MSIX")) + Method(_STA, 0, NotSerialized) + { + Return (One) + } + Name(_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x79000000, 0x900000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x30} + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x31} + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x32} + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x33} + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x34} + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x35} + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x36} + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x37} + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x38} + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x39} + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x3A} + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x3B} + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x3C} + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x3D} + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x3E} + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x3F} }) - Name(CLNM, "xge0clk") // clock-names - Name(SLNM, "SXGMII1") - Name(SLIF, Buffer() { 0x00, 0x00, 0x08, 0x20, 0x08 }) - Name(FMSZ, 0x233a) // Frame-size - Name(PHID, 0x01) // Phy ID - Name(PHMD, "xgmii") // PHY mode - Name(DVID, 0x05) // Device ID - Name(MAC0, Buffer() { 0x00, 0x11, 0x3a, 0x8a, 0x5a, 0x75}) // MAC Address + Method(_DSM, 4, NotSerialized) { + Store (Package (2) { + "msi-available-ranges", "0x0 0x1000", + }, Local0) + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } }
+/////////////////////////////////////////////////////////////////////////////// }//DSDT diff --git a/platforms/APMXGene.acpi/Facp.asl b/platforms/APMXGene.acpi/Facp.asl index 53aac23..06035bd 100644 --- a/platforms/APMXGene.acpi/Facp.asl +++ b/platforms/APMXGene.acpi/Facp.asl @@ -1,10 +1,10 @@ /** * Copyright (c) 2013, AppliedMicro Corp. All rights reserved. * - * This program and the accompanying materials - * are licensed and made available under the terms and conditions of the BSD License - * which accompanies this distribution. The full text of the license may be found at - * http://opensource.org/licenses/bsd-license.php + * This program and the accompanying materials are licensed and made + * available under the terms and conditions of the BSD License which + * accompanies this distribution. The full text of the license may be + * found at * http://opensource.org/licenses/bsd-license.php * * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. @@ -20,13 +20,13 @@ [0001] Revision : 05 [0001] Checksum : 18 [0006] Oem ID : "APM " -[0008] Oem Table ID : "APMACPI " -[0004] Oem Revision : 00000000 +[0008] Oem Table ID : "XGENE " +[0004] Oem Revision : 00000003 [0004] Asl Compiler ID : "INTL" [0004] Asl Compiler Revision : 20111123
[0004] FACS Address : 00000000 -[0004] DSDT Address : 85000340 +[0004] DSDT Address : FFFFFFFF [0001] Model : 00 [0001] PM Profile : 00 [Unspecified] [0002] SCI Interrupt : 0000 @@ -37,16 +37,16 @@ [0001] P-State Control : 00 [0004] PM1A Event Block Address : 00000000 [0004] PM1B Event Block Address : 00000000 -[0004] PM1A Control Block Address : 10558008 +[0004] PM1A Control Block Address : 00000000 [0004] PM1B Control Block Address : 00000000 [0004] PM2 Control Block Address : 00000000 -[0004] PM Timer Block Address : 10559000 +[0004] PM Timer Block Address : 00000000 [0004] GPE0 Block Address : 00000000 [0004] GPE1 Block Address : 00000000 -[0001] PM1 Event Block Length : 08 -[0001] PM1 Control Block Length : 04 +[0001] PM1 Event Block Length : 00 +[0001] PM1 Control Block Length : 00 [0001] PM2 Control Block Length : 00 -[0001] PM Timer Block Length : 04 +[0001] PM Timer Block Length : 00 [0001] GPE0 Block Length : 00 [0001] GPE1 Block Length : 00 [0001] GPE1 Base Offset : 00 @@ -77,7 +77,7 @@ Control Method Sleep Button (V1) : 0 RTC wake not in fixed reg space (V1) : 0 RTC can wake system from S4 (V1) : 0 - 32-bit PM Timer (V1) : 1 + 32-bit PM Timer (V1) : 0 Docking Supported (V1) : 0 Reset Register Supported (V2) : 0 Sealed Case (V3) : 0 @@ -100,15 +100,18 @@ [0008] Address : 0000000000000000
[0001] Value to cause reset : 00 -[0003] Reserved : 000000 -[0008] FACS Address : 0000000085001EC0 -[0008] DSDT Address : 0000000085000340 +[0002] ARM_BOOT_ARCH (decoded below) : 0000 + Use PSCI 0.2+ : 0 + PSCI Use HVC : 0 +[0001] FADT Minor Revision : 01 +[0008] FACS Address : 0000000000000000 +[0008] DSDT Address : 0000000000000010 [0012] PM1A Event Block : [Generic Address Structure] [0001] Space ID : 00 [SystemIO] -[0001] Bit Width : 40 +[0001] Bit Width : 00 [0001] Bit Offset : 00 -[0001] Encoded Access Width : 04 [Word Access:16] -[0008] Address : 0000000010558000 +[0001] Encoded Access Width : 00 [Word Access:16] +[0008] Address : 0000000000000000
[0012] PM1B Event Block : [Generic Address Structure] [0001] Space ID : 00 [SystemIO] @@ -119,10 +122,10 @@
[0012] PM1A Control Block : [Generic Address Structure] [0001] Space ID : 00 [SystemIO] -[0001] Bit Width : 40 +[0001] Bit Width : 00 [0001] Bit Offset : 00 -[0001] Encoded Access Width : 04 [Word Access:16] -[0008] Address : 0000000010558008 +[0001] Encoded Access Width : 00 [Word Access:16] +[0008] Address : 0000000000000000
[0012] PM1B Control Block : [Generic Address Structure] [0001] Space ID : 00 [SystemIO] @@ -133,23 +136,23 @@
[0012] PM2 Control Block : [Generic Address Structure] [0001] Space ID : 00 [SystemIO] -[0001] Bit Width : 08 +[0001] Bit Width : 00 [0001] Bit Offset : 00 [0001] Encoded Access Width : 00 [Undefined/Legacy] [0008] Address : 0000000000000000
[0012] PM Timer Block : [Generic Address Structure] [0001] Space ID : 00 [SystemIO] -[0001] Bit Width : 20 +[0001] Bit Width : 00 [0001] Bit Offset : 00 -[0001] Encoded Access Width : 03 [DWord Access:32] -[0008] Address : 0000000010559000 +[0001] Encoded Access Width : 00 [DWord Access:32] +[0008] Address : 0000000000000000
[0012] GPE0 Block : [Generic Address Structure] [0001] Space ID : 00 [SystemIO] [0001] Bit Width : 00 [0001] Bit Offset : 00 -[0001] Encoded Access Width : 01 [Byte Access:8] +[0001] Encoded Access Width : 00 [Byte Access:8] [0008] Address : 0000000000000000
[0012] GPE1 Block : [Generic Address Structure] diff --git a/platforms/APMXGene.acpi/Gtdt.asl b/platforms/APMXGene.acpi/Gtdt.asl index ce8fab3..6d3a7d0 100644 --- a/platforms/APMXGene.acpi/Gtdt.asl +++ b/platforms/APMXGene.acpi/Gtdt.asl @@ -16,35 +16,92 @@ **/
[0004] Signature : "GTDT" [Generic Timer Description Table] -[0004] Table Length : 00000050 -[0001] Revision : 01 -[0001] Checksum : 00 +[0004] Table Length : 000000E0 +[0001] Revision : 02 +[0001] Checksum : B0 [0006] Oem ID : "APM " -[0008] Oem Table ID : "APMACPI " +[0008] Oem Table ID : "XGENE " [0004] Oem Revision : 00000001 [0004] Asl Compiler ID : "INTL" -[0004] Asl Compiler Revision : 20110623 +[0004] Asl Compiler Revision : 20140424
-[0008] Timer Address : 0000000002FAF080 -[0004] Flags (decoded below) : 00000001 - Memory Present : 1 +[0008] Counter Block Address : 0000000000000000 +[0004] Reserved : 00000000
-[0004] Secure PL1 Interrupt : 00000000 -[0004] SPL1 Flags (decoded below) : 00000000 +[0004] Secure EL1 Interrupt : 00000010 +[0004] EL1 Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 + Always On : 0
-[0004] Non-Secure PL1 Interrupt : 0000000D -[0004] NSPL1 Flags (decoded below) : 00000000 +[0004] Non-Secure EL1 Interrupt : 0000001D +[0004] NEL1 Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 + Always On : 0
-[0004] Virtual Timer Interrupt : 00000000 +[0004] Virtual Timer Interrupt : 0000001E [0004] VT Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 + Always On : 0
-[0004] Non-Secure PL2 Interrupt : 00000000 -[0004] NSPL2 Flags (decoded below) : 00000000 +[0004] Non-Secure EL2 Interrupt : 0000001F +[0004] NEL2 Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 + Always On : 0 +[0008] Counter Read Block Address : 0000000000000000 + +[0004] Platform Timer Count : 00000002 +[0004] Platform Timer Offset : 00000060 + +[0001] Subtable Type : 00 [GT Block] +[0001] Length : 64 +[0002] Reserved : 0000 +[0008] GT Block Address : 0000000000000000 +[0004] GT Block Count : 00000002 +[0004] GT Block Offset : 00000014 + +[0001] GT Frame Number : 00 +[0003] Reserved : 000000 +[0008] GTx Address : 0000000000000000 +[0008] GTx EL0 Address : 0000000000000000 +[0004] GTx Timer Interrupt : 00000000 +[0004] GTx Timer Flags (decoded below) : 00000001 + Trigger Mode : 1 + Polarity : 0 +[0004] GTx Virtual Timer Interrupt : 00000000 +[0004] GTx Virtual Timer Flags (decoded below) : 00000001 + Trigger Mode : 1 + Polarity : 0 +[0004] GTx Common Flags (decoded below) : 00000000 + Secure : 0 + Always On : 0 + +[0001] GT Frame Number : 01 +[0003] Reserved : 000000 +[0008] GTx Address : 0000000000000000 +[0008] GTx EL0 Address : 0000000000000000 +[0004] GTx Timer Interrupt : 00000000 +[0004] GTx Timer Flags (decoded below) : 00000001 + Trigger Mode : 1 + Polarity : 0 +[0004] GTx Virtual Timer Interrupt : 00000000 +[0004] GTx Virtual Timer Flags (decoded below) : 00000001 + Trigger Mode : 1 + Polarity : 0 +[0004] GTx Common Flags (decoded below) : 00000000 + Secure : 0 + Always On : 0 + +[0001] Subtable Type : 01 [SBSA Generic Watchdog] +[0001] Length : 1C +[0002] Reserved : 0000 +[0008] Refresh Frame Address : 0000000000000000 +[0008] Control Frame Address : 0000000000000000 +[0004] Timer Interrupt : 00000000 +[0004] Timer Flags (decoded below) : 00000001 + Trigger Mode : 1 + Polarity : 0 + Secure : 0
From: Al Stone al.stone@linaro.org
Signed-off-by: Al Stone al.stone@linaro.org --- platforms/APMXGene.acpi/APMXGene.manifest | 1 + platforms/APMXGene.acpi/Ssdt.asl | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 platforms/APMXGene.acpi/Ssdt.asl
diff --git a/platforms/APMXGene.acpi/APMXGene.manifest b/platforms/APMXGene.acpi/APMXGene.manifest index d02def8..0997735 100644 --- a/platforms/APMXGene.acpi/APMXGene.manifest +++ b/platforms/APMXGene.acpi/APMXGene.manifest @@ -45,4 +45,5 @@ apic: Apic.asl dbg2: Dbg2.asl gtdt: Gtdt.asl spcr: Spcr.asl +ssdt: Ssdt.asl
diff --git a/platforms/APMXGene.acpi/Ssdt.asl b/platforms/APMXGene.acpi/Ssdt.asl new file mode 100644 index 0000000..f5ce1d0 --- /dev/null +++ b/platforms/APMXGene.acpi/Ssdt.asl @@ -0,0 +1,21 @@ +/** + * Copyright (c) 2013, AppliedMicro Corp. All rights reserved. + * + * This program and the accompanying materials + * are licensed and made available under the terms and conditions of the BSD License + * which accompanies this distribution. The full text of the license may be found at + * http://opensource.org/licenses/bsd-license.php + * + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + * + **/ + +DefinitionBlock("Ssdt.aml", "SSDT", 2, "APM ", "XGENE ", 0x00000001) +{ + Method (MAIN, 0, NotSerialized) + { + Return (Zero) + } +} +
Should we actually be maintaining these as linaro-ed2k topic branches now?
Graeme
On 24/07/2014 19:44, al.stone@linaro.org wrote:
From: Al Stone al.stone@linaro.org
These patches are my best guess at initial ACPI tables for XGene, in accordance with the new ACPI 5.1 specification.
These have not been fully tested yet but that process has been started.
Al Stone (3): APM / XGene: Minor cleanup of some of the basics APM / XGene: Update core tables to replace ACPI 5.1 changes APM / XGene: Add in empty SSDT for future use in developing complete tables
platforms/APMXGene.acpi/APMXGene.manifest | 1 + platforms/APMXGene.acpi/Apic.asl | 262 ++-- platforms/APMXGene.acpi/Dsdt.asl | 2215 ++++++++++++++++------------- platforms/APMXGene.acpi/Facp.asl | 57 +- platforms/APMXGene.acpi/Gtdt.asl | 87 +- platforms/APMXGene.acpi/Rsdp.asl | 2 +- platforms/APMXGene.acpi/Ssdt.asl | 21 + platforms/APMXGene.acpi/Xsdt.asl | 10 +- 8 files changed, 1508 insertions(+), 1147 deletions(-) create mode 100644 platforms/APMXGene.acpi/Ssdt.asl
On 07/24/2014 01:10 PM, Graeme Gregory wrote:
Should we actually be maintaining these as linaro-ed2k topic branches now?
Graeme
Hrm. Probably. I've done these just for completeness. There is no topic branch for APM at the moment and while I could do that, it seems like that should be APM's prerogative (and a serious distraction for me).
On 24/07/2014 19:44, al.stone@linaro.org wrote:
From: Al Stone al.stone@linaro.org
These patches are my best guess at initial ACPI tables for XGene, in accordance with the new ACPI 5.1 specification.
These have not been fully tested yet but that process has been started.
Al Stone (3): APM / XGene: Minor cleanup of some of the basics APM / XGene: Update core tables to replace ACPI 5.1 changes APM / XGene: Add in empty SSDT for future use in developing complete tables
platforms/APMXGene.acpi/APMXGene.manifest | 1 + platforms/APMXGene.acpi/Apic.asl | 262 ++-- platforms/APMXGene.acpi/Dsdt.asl | 2215 ++++++++++++++++------------- platforms/APMXGene.acpi/Facp.asl | 57 +- platforms/APMXGene.acpi/Gtdt.asl | 87 +- platforms/APMXGene.acpi/Rsdp.asl | 2 +- platforms/APMXGene.acpi/Ssdt.asl | 21 + platforms/APMXGene.acpi/Xsdt.asl | 10 +- 8 files changed, 1508 insertions(+), 1147 deletions(-) create mode 100644 platforms/APMXGene.acpi/Ssdt.asl
Linaro-acpi mailing list Linaro-acpi@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-acpi
On 24/07/2014 20:31, Al Stone wrote:
On 07/24/2014 01:10 PM, Graeme Gregory wrote:
Should we actually be maintaining these as linaro-ed2k topic branches now?
Graeme
Hrm. Probably. I've done these just for completeness. There is no topic branch for APM at the moment and while I could do that, it seems like that should be APM's prerogative (and a serious distraction for me).
Ah, I thought they had submitted a topic already!
G
On 24/07/2014 19:44, al.stone@linaro.org wrote:
From: Al Stone al.stone@linaro.org
These patches are my best guess at initial ACPI tables for XGene, in accordance with the new ACPI 5.1 specification.
These have not been fully tested yet but that process has been started.
Al Stone (3): APM / XGene: Minor cleanup of some of the basics APM / XGene: Update core tables to replace ACPI 5.1 changes APM / XGene: Add in empty SSDT for future use in developing complete tables
platforms/APMXGene.acpi/APMXGene.manifest | 1 + platforms/APMXGene.acpi/Apic.asl | 262 ++-- platforms/APMXGene.acpi/Dsdt.asl | 2215 ++++++++++++++++------------- platforms/APMXGene.acpi/Facp.asl | 57 +- platforms/APMXGene.acpi/Gtdt.asl | 87 +- platforms/APMXGene.acpi/Rsdp.asl | 2 +- platforms/APMXGene.acpi/Ssdt.asl | 21 + platforms/APMXGene.acpi/Xsdt.asl | 10 +- 8 files changed, 1508 insertions(+), 1147 deletions(-) create mode 100644 platforms/APMXGene.acpi/Ssdt.asl
Linaro-acpi mailing list Linaro-acpi@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-acpi
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Al Stone -
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Graeme Gregory