This patch adds a basic support of Exynos5433 SoC to EAS.
Signed-off-by: Lukasz Luba l.luba@partner.samsung.com --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 8 ++ arch/arm64/kernel/energy_model.h | 119 +++++++++++++++++++++ 2 files changed, 127 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index bee00ead0a7b..4bbd6ae1ab49 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -72,6 +72,7 @@ clock-names = "apolloclk"; operating-points-v2 = <&cluster_a53_opp_table>; #cooling-cells = <2>; + capacity-dmips-mhz = <512>; };
cpu1: cpu@101 { @@ -82,6 +83,7 @@ clock-frequency = <1300000000>; operating-points-v2 = <&cluster_a53_opp_table>; #cooling-cells = <2>; + capacity-dmips-mhz = <512>; };
cpu2: cpu@102 { @@ -92,6 +94,7 @@ clock-frequency = <1300000000>; operating-points-v2 = <&cluster_a53_opp_table>; #cooling-cells = <2>; + capacity-dmips-mhz = <512>; };
cpu3: cpu@103 { @@ -102,6 +105,7 @@ clock-frequency = <1300000000>; operating-points-v2 = <&cluster_a53_opp_table>; #cooling-cells = <2>; + capacity-dmips-mhz = <512>; };
cpu4: cpu@0 { @@ -114,6 +118,7 @@ clock-names = "atlasclk"; operating-points-v2 = <&cluster_a57_opp_table>; #cooling-cells = <2>; + capacity-dmips-mhz = <1024>; };
cpu5: cpu@1 { @@ -124,6 +129,7 @@ clock-frequency = <1900000000>; operating-points-v2 = <&cluster_a57_opp_table>; #cooling-cells = <2>; + capacity-dmips-mhz = <1024>; };
cpu6: cpu@2 { @@ -134,6 +140,7 @@ clock-frequency = <1900000000>; operating-points-v2 = <&cluster_a57_opp_table>; #cooling-cells = <2>; + capacity-dmips-mhz = <1024>; };
cpu7: cpu@3 { @@ -144,6 +151,7 @@ clock-frequency = <1900000000>; operating-points-v2 = <&cluster_a57_opp_table>; #cooling-cells = <2>; + capacity-dmips-mhz = <1024>; }; };
diff --git a/arch/arm64/kernel/energy_model.h b/arch/arm64/kernel/energy_model.h index 0623bd01905c..349ea307b3a0 100644 --- a/arch/arm64/kernel/energy_model.h +++ b/arch/arm64/kernel/energy_model.h @@ -263,6 +263,118 @@ static struct sched_group_energy energy_core_hikey960_a72 = { .cap_states = cap_states_core_hikey960_a72, };
+/* exynos5433 */ + +static struct idle_state idle_states_cluster_exynos5433_a53[] = { + { .power = 16 }, /* arch_cpu_idle() (active idle) = WFI */ + { .power = 0 }, /* cluster-sleep */ +}; + +static struct idle_state idle_states_cluster_exynos5433_a57[] = { + { .power = 150 }, /* arch_cpu_idle() (active idle) = WFI */ + { .power = 0 }, /* cluster-sleep */ +}; + +static struct capacity_state cap_states_cluster_exynos5433_a53[] = { + { .cap = 194, .power = 13, }, /* 400 MHz */ + { .cap = 242, .power = 17, }, /* 500 MHz */ + { .cap = 292, .power = 22, }, /* 600 MHz */ + { .cap = 339, .power = 27, }, /* 700 MHz */ + { .cap = 388, .power = 32, }, /* 800 MHz */ + { .cap = 436, .power = 38, }, /* 900 MHz */ + { .cap = 485, .power = 45, }, /* 1000 MHz */ + { .cap = 533, .power = 52, }, /* 1100 MHz */ + { .cap = 581, .power = 59, }, /* 1200 MHz */ + { .cap = 630, .power = 67, }, /* 1300 MHz */ +}; + +static struct capacity_state cap_states_cluster_exynos5433_a57[] = { + { .cap = 269, .power = 22, }, /* 500MHz */ + { .cap = 323, .power = 26, }, /* 600MHz */ + { .cap = 377, .power = 32, }, /* 700MHz */ + { .cap = 431, .power = 36, }, /* 800MHz */ + { .cap = 485, .power = 43, }, /* 900MHz */ + { .cap = 538, .power = 51, }, /* 1000MHz */ + { .cap = 592, .power = 61, }, /* 1100MHz */ + { .cap = 646, .power = 70, }, /* 1200MHz */ + { .cap = 700, .power = 79, }, /* 1300MHz */ + { .cap = 754, .power = 90, }, /* 1400MHz */ + { .cap = 808, .power = 103, }, /* 1500MHz */ + { .cap = 861, .power = 112, }, /* 1600MHz */ + { .cap = 915, .power = 127, }, /* 1700MHz */ + { .cap = 969, .power = 143, }, /* 1800MHz */ + { .cap = 1023, .power = 164, }, /* 1900MHz */ +}; + +static struct sched_group_energy energy_cluster_exynos5433_a53 = { + .nr_idle_states = ARRAY_SIZE(idle_states_cluster_exynos5433_a53), + .idle_states = idle_states_cluster_exynos5433_a53, + .nr_cap_states = ARRAY_SIZE(cap_states_cluster_exynos5433_a53), + .cap_states = cap_states_cluster_exynos5433_a53, +}; + +static struct sched_group_energy energy_cluster_exynos5433_a57 = { + .nr_idle_states = ARRAY_SIZE(idle_states_cluster_exynos5433_a57), + .idle_states = idle_states_cluster_exynos5433_a57, + .nr_cap_states = ARRAY_SIZE(cap_states_cluster_exynos5433_a57), + .cap_states = cap_states_cluster_exynos5433_a57, +}; + +static struct idle_state idle_states_core_exynos5433_a53[] = { + { .power = 14 }, /* arch_cpu_idle() (active idle) = WFI */ + { .power = 0 }, /* cluster-sleep */ +}; + +static struct idle_state idle_states_core_exynos5433_a57[] = { + { .power = 50 }, /* arch_cpu_idle() (active idle) = WFI */ + { .power = 0 }, /* cluster-sleep */ +}; + +static struct capacity_state cap_states_core_exynos5433_a53[] = { + { .cap = 194, .power = 82, }, /* 400 MHz */ + { .cap = 242, .power = 108, }, /* 500 MHz */ + { .cap = 292, .power = 137, }, /* 600 MHz */ + { .cap = 339, .power = 169, }, /* 700 MHz */ + { .cap = 388, .power = 203, }, /* 800 MHz */ + { .cap = 436, .power = 240, }, /* 900 MHz */ + { .cap = 485, .power = 280, }, /* 1000 MHz */ + { .cap = 533, .power = 322, }, /* 1100 MHz */ + { .cap = 581, .power = 368, }, /* 1200 MHz */ + { .cap = 630, .power = 417, }, /* 1300 MHz */ +}; + +static struct capacity_state cap_states_core_exynos5433_a57[] = { + { .cap = 269, .power = 137, }, /* 500MHz */ + { .cap = 323, .power = 164, }, /* 600MHz */ + { .cap = 377, .power = 197, }, /* 700MHz */ + { .cap = 431, .power = 225, }, /* 800MHz */ + { .cap = 485, .power = 268, }, /* 900MHz */ + { .cap = 538, .power = 322, }, /* 1000MHz */ + { .cap = 592, .power = 381, }, /* 1100MHz */ + { .cap = 646, .power = 437, }, /* 1200MHz */ + { .cap = 700, .power = 496, }, /* 1300MHz */ + { .cap = 754, .power = 560, }, /* 1400MHz */ + { .cap = 808, .power = 642, }, /* 1500MHz */ + { .cap = 861, .power = 700, }, /* 1600MHz */ + { .cap = 915, .power = 793, }, /* 1700MHz */ + { .cap = 969, .power = 894, }, /* 1800MHz */ + { .cap = 1023, .power = 1023, }, /* 1900MHz */ +}; + +static struct sched_group_energy energy_core_exynos5433_a53 = { + .nr_idle_states = ARRAY_SIZE(idle_states_core_exynos5433_a53), + .idle_states = idle_states_core_exynos5433_a53, + .nr_cap_states = ARRAY_SIZE(cap_states_core_exynos5433_a53), + .cap_states = cap_states_core_exynos5433_a53, +}; + +static struct sched_group_energy energy_core_exynos5433_a57 = { + .nr_idle_states = ARRAY_SIZE(idle_states_core_exynos5433_a57), + .idle_states = idle_states_core_exynos5433_a57, + .nr_cap_states = ARRAY_SIZE(cap_states_core_exynos5433_a57), + .cap_states = cap_states_core_exynos5433_a57, +}; + /* An energy model contains core, cluster and system sched group energy * for 2 clusters (cluster id 0 and 1). set_energy_model() relies on * this feature. It is enforced by a BUG_ON in energy(). @@ -292,10 +404,17 @@ static struct energy_model hikey960_model = { {}, };
+static struct energy_model exynos5433_model = { + { &energy_core_exynos5433_a53, &energy_core_exynos5433_a57, }, + { &energy_cluster_exynos5433_a53, &energy_cluster_exynos5433_a57, }, + {}, +}; + static struct of_device_id model_matches[] = { { .compatible = "arm,juno", .data = &juno_model }, { .compatible = "hisilicon,hi6220-hikey", .data = &hikey_model }, { .compatible = "hisilicon,hi3660-hikey960", .data = &hikey960_model }, + { .compatible = "samsung,exynos5433", .data = &exynos5433_model }, {}, };