- Linaro-acpi - lists.linaro.org

[V2 PATCH 0/5] Introduce ACPI _CCA support and device_dma_is_coherent API

by Suravee Suthikulpanit

This patch series introduce support for _CCA object, which is currently used mainly by ARM64 platform to specify DMA coherency attribute for devices when booting with ACPI. A copy of ACPIv6 can be found here: http://www.uefi.org/sites/default/files/resources/ACPI_6.0.pdf This patch also introduces 2 new APIS: 1. acpi_dma_is_coherent() as part of ACPI API. 2. device_dma_is_coherent() as part of unified device property API. This simplifies the logic in device drivers to determine device coherency attribute regardless of booting with DT vs ACPI. This has been tested on AMD-Seattle platform, which implements _CCA object as described in the AMD Opteron A1100 Series Processor ACPI Porting Guide: http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2012/10/Seattle_ACPI… Changes from V1 (https://lkml.org/lkml/2015/4/29/290): * Remove supports for 32-bit ARM since doesn't currently supporting ACPI (Per Catalin suggestions.) * Do not call arch_setup_dma_ops() and when _CCA is missing. (per Arnd suggestion) * Add CONFIG_ACPI_SUPPORT_CCA_ZERO kernel config flag to allow architectures to specify the behavior when _CCA=0. * Add dummy_dma_ops for ARM64 (per Catalin suggestions). * Fixed build error when ACPI is not configured by defining acpi_dma_is_coherent() for when CONFIG_ACPI is not set. * Introduce device_dma_is_coherent(). * Use device_dma_is_coherent in crypto/ccp and amd-xgbe driver. Changes from RFC: (https://lkml.org/lkml/2015/4/1/389) * New logic for deriving and propagating coherent attribute from parent devices. (by Mark) * Introducing acpi_dma_is_coherent() API (Per Tom suggestion) * Introducing CONFIG_ACPI_MUST_HAVE_CCA kernel configuration. * Rebased to linux-4.1-rc1 Suravee Suthikulpanit (5): ACPI / scan: Parse _CCA and setup device coherency arm64 : Introduce support for ACPI _CCA object device property: Introduces device_dma_is_coherent() crypto: ccp - Unify coherency checking logic with device_dma_is_coherent() amd-xgbe: Unify coherency checking logic with device_dma_is_coherent() arch/arm64/Kconfig | 2 + arch/arm64/include/asm/dma-mapping.h | 18 +++++- arch/arm64/mm/dma-mapping.c | 104 ++++++++++++++++++++++++++++++ drivers/acpi/Kconfig | 6 ++ drivers/acpi/acpi_platform.c | 4 +- drivers/acpi/scan.c | 62 ++++++++++++++++++ drivers/base/property.c | 12 ++++ drivers/crypto/ccp/ccp-platform.c | 60 +---------------- drivers/net/ethernet/amd/xgbe/xgbe-main.c | 27 +------- include/acpi/acpi_bus.h | 11 +++- include/linux/acpi.h | 5 ++ include/linux/property.h | 2 + 12 files changed, 224 insertions(+), 89 deletions(-) -- 2.1.0

11 years

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23
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[RFC PATCH 0/9] Add self-probe infrastructure and stacked irqdomain support for ACPI based GICv2/3 init

by Hanjun Guo

This patch set introduce self-probe infrastructure to init IRQ controllers and stacked irqdomain support for ACPI based GICv2/3 init. The self-probe infrastructure for ACPI GIC init is similar as IRQCHIP_DECLARE() and based on the GIC version support in ACPI MADT table. We introduce acpi_irq_domain for GICv2/3 core domain to support stacked irqdomain, and pass the gsi (global system interrupt) as the agument (void *arg) for gic_irq_domain_alloc(), then we can alloc virqs via acpi_register_gsi() with stacked irqdomain. I already compiled this patch set ok with both ACPI=on/off on ARM64 and also compiled ok on x86, tested with GICv2 init on FVP model and it boot successfully. Next step I would consolidate all the ACPI GIC init into one file -- drivers/irqchip/irq-gic-acpi.c, and introduce ITS and IORT support. please comment on this patchset to see if we are on the right direction. Hanjun Guo (6): irqchip / gic: Add GIC version support in ACPI MADT irqchip: gic: ACPI: Use IRQCHIP_ACPI_DECLARE to simplify GICv2 init code irqchip / gic: Add stacked irqdomain support for ACPI based GICv2 init ACPI / gsi: Add gsi_mutex to synchronize acpi_register_gsi()/acpi_unregister_gsi() irqchip / GICv3: Add ACPI support for GICv3+ initialization irqchip / GICv3: Add stacked irqdomain support for ACPI based init Tomasz Nowicki (3): ACPICA: Introduce GIC version for arm based system ACPI / irqchip: Add self-probe infrastructure to initialize IRQ controller irqchip / GICv3: Refactor gic_of_init() for GICv3 driver arch/arm64/Kconfig | 1 + arch/arm64/include/asm/irq.h | 13 -- arch/arm64/kernel/acpi.c | 25 ---- drivers/acpi/Makefile | 1 + drivers/acpi/gsi.c | 39 ++--- drivers/acpi/irq.c | 40 ++++++ drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-gic-acpi.c | 116 +++++++++++++++ drivers/irqchip/irq-gic-v3.c | 267 ++++++++++++++++++++++++++++------- drivers/irqchip/irq-gic.c | 38 ++--- drivers/irqchip/irqchip.h | 12 ++ include/acpi/actbl1.h | 17 ++- include/asm-generic/vmlinux.lds.h | 13 ++ include/linux/acpi.h | 14 ++ include/linux/acpi_irq.h | 4 +- include/linux/irqchip/arm-gic-acpi.h | 12 +- include/linux/mod_devicetable.h | 7 + 18 files changed, 489 insertions(+), 134 deletions(-) create mode 100644 drivers/acpi/irq.c create mode 100644 drivers/irqchip/irq-gic-acpi.c -- 1.9.1

11 years

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leg-kernel tag leg-20150505.0 released

by Graeme Gregory

The leg-kernel release has been made and tagged as leg-20150505.0 This is based on mainline kernel v4.1-rc2 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: https://git.linaro.org/leg/acpi/leg-kernel.git/commit/61210b29cad788fdbf625… Notes :-

11 years

1
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[PATCH 0/7] minor cleanups for ACPI processor driver

by Hanjun Guo

This patch set are some minor cleanups for ACPI processor driver to address the comments which raised by Rafael in ARM64 ACPI core patches, so this patch set is on top of ARM64 ACPI core patches the git tree is git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git branch for-next/acpi. Rafael, I assume this patchset will be taken with your tree if it makes sense, any rebase work needed please let me know. the last patch - ACPI / processor: Introduce invalid_phys_cpuid() will cut u64 mpidr to int, but I think it is ok for error values, correct me if I'm wrong. Comments are welcomed. Hanjun Guo (7): ACPI / processor: remove cpu_index in acpi_processor_get_info() ACPI / processor: remove phys_id in acpi_processor_get_info() ACPI / processor: Introduce invalid_logical_cpuid() Xen / ACPI / processor: use invalid_logical_cpuid() Xen / ACPI / processor: Remove unneeded NULL check in xen_acpi_processor_enable() ACPI / processor: return specific error instead of -1 ACPI / processor: Introduce invalid_phys_cpuid() drivers/acpi/acpi_processor.c | 20 +++++++++----------- drivers/acpi/processor_core.c | 10 +++++----- drivers/acpi/processor_pdc.c | 5 +---- drivers/xen/xen-acpi-cpuhotplug.c | 12 +++--------- include/linux/acpi.h | 10 ++++++++++ 5 files changed, 28 insertions(+), 29 deletions(-) -- 1.9.1

11 years

3
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[RFC][PATCH 0/1] SBSA watchdog driver

by fu.wei＠linaro.org

From: Fu Wei <fu.wei(a)linaro.org> This driver is designed for ARM AArch64 HW originally. Now It's tested on Foundation model with Linux watchdog deamon. It support two stages watch period, and will trigger a SPI after first timeout. Fu Wei (1): Watchdog: add SBSA watchdog driver (1)use linux kernel watchdog framework (2)support getting info from ACPI GTDT table drivers/watchdog/Kconfig | 10 + drivers/watchdog/Makefile | 1 + drivers/watchdog/sbsa_gwdt.c | 805 +++++++++++++++++++++++++++++++++++++++++++ include/linux/sbsa_gwdt.h | 134 +++++++ 4 files changed, 950 insertions(+) create mode 100644 drivers/watchdog/sbsa_gwdt.c create mode 100644 include/linux/sbsa_gwdt.h -- 1.9.1

11 years

3
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Re: [Linaro-acpi] [PATCH] watchdog: introduce the ARM64 SBSA watchdog driver

by Timur Tabi

On 04/30/2015 10:30 PM, Guenter Roeck wrote: >> +/* Watchdog Refresh Frame */ >> +struct arm_sbsa_watchdog_refresh { >> + uint32_t wrr; /* Watchdog Refresh Register */ >> + uint8_t res1[0xFCC - 0x004]; >> + struct arm_sbsa_watchdog_ident ident; >> +}; >> + >> +/* Watchdog Control Frame */ >> +struct arm_sbsa_watchdog_control { >> + uint32_t wcs; >> + uint32_t res1; >> + uint32_t wor; >> + uint32_t res2; >> + uint64_t wcv; >> + uint8_t res3[0xFCC - 0x018]; >> + struct arm_sbsa_watchdog_ident ident; >> +}; >> + > > Why not just use defines instead of all those structures ? I like structures. I think hardware register blocks should be defined with structures that provide type checking. >> +static int arm_sbsa_wdt_set_timeout(struct watchdog_device *wdev, >> + unsigned int timeout) >> +{ >> + struct arm_sbsa_watchdog_data *data = >> + container_of(wdev, struct arm_sbsa_watchdog_data, wdev); >> + >> + wdev->timeout = timeout; >> + writel(arch_timer_get_rate() * wdev->timeout, &data->control->wor); > > Do you also have to reset the counter ? No. Programming a new timeout automatically resets the timer. >> +static int __init arm_sbsa_wdt_probe(struct platform_device *pdev) >> +{ >> + struct arm_sbsa_watchdog_data *data; >> + struct resource *res; >> + uint32_t iidr; >> + int ret; >> + >> + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); >> + if (!data) >> + return -ENOMEM; >> + >> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); >> + if (!res || !res->start) { >> + dev_err(&pdev->dev, "could not get control address\n"); >> + return -ENOMEM; >> + } >> + > devm_ioremap_resource already prints an error message if res is NULL. > And res->start can not be 0 unless there is a severe infrastructure > problem. Will fix. >> + data->control = devm_ioremap_resource(&pdev->dev, res); >> + if (!data->control) >> + return -ENOMEM; >> + >> + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); >> + if (!res || !res->start) { >> + dev_err(&pdev->dev, "could not get refresh address\n"); >> + return -ENOMEM; >> + } > Same here. > >> + data->refresh = devm_ioremap_resource(&pdev->dev, res); >> + if (!data->refresh) >> + return -ENOMEM; >> + >> + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); >> + if (!res || !res->start) { > > res->start checking is unnecessary. On a side note, irq == 0 might be a > valid > interrupt number. Will fix. > >> + dev_err(&pdev->dev, "could not get interrupt\n"); >> + return -ENOMEM; >> + } >> + >> + iidr = readl(&data->control->ident.w_iidr); >> + >> + /* We only support architecture version 0 */ >> + if (((iidr >> 16) & 0xf) != 0) { >> + dev_info(&pdev->dev, "only architecture version 0 is >> supported\n"); >> + return -ENODEV; >> + } >> + >> + ret = devm_request_irq(&pdev->dev, res->start, >> arm_sbsa_wdt_interrupt, >> + 0, DRV_NAME, NULL); > > Please align continuation lines with '('. Will fix. >> + if (ret < 0) { >> + dev_err(&pdev->dev, "could not request irq %u (ret=%i)\n", >> + (unsigned int)res->start, ret); >> + return ret; >> + } >> + >> + data->wdev.info = &arm_sbsa_wdt_info; >> + data->wdev.ops = &arm_sbsa_wdt_ops; >> + data->wdev.min_timeout = 1; >> + data->wdev.status = WATCHDOG_NOWAYOUT_INIT_STATUS; >> + >> + /* Calculate the maximum timeout in seconds that we can support */ >> + data->wdev.max_timeout = U32_MAX / arch_timer_get_rate(); >> + >> + ret = watchdog_register_device(&data->wdev); >> + if (ret < 0) { >> + dev_err(&pdev->dev, >> + "could not register watchdog device (ret=%i)\n", ret); >> + return ret; >> + } >> + >> + dev_info(&pdev->dev, "implementer code is %03x, max timeout is %u >> seconds\n", >> + (iidr & 0xf00) >> 1 | (iidr & 0x7f), data->wdev.max_timeout); > > "Implementer code" sounds very much like a debug message to me. > It means nothing to me, and it won't mean anything to a user. Fair enough. I thought it would be a handy way to know that the driver found the hardware, but I'll move it to a pr_debug(). >> + >> + /* >> + * Bits [15:12] are an implementation-defined revision number >> + * for the component. >> + */ >> + arm_sbsa_wdt_info.firmware_version = (iidr >> 12) & 0xf; >> + > It might make sense to set that prior to registering the driver. Ok. >> +static struct platform_device *arm_sbsa_wdt_pdev; >> + >> +static int __init arm_sbsa_wdt_parse_gtdt(struct acpi_subtable_header >> *header, >> + const unsigned long end) >> +{ >> + struct acpi_gtdt_watchdog *wdg = (struct acpi_gtdt_watchdog >> *)header; >> + struct platform_device *arm_sbsa_wdt_pdev; > > That is an interesting one. Makes me wonder if you ever tried to unload > this driver. > Did you ? The driver can only be compiled in-kernel. >> + struct resource res[3] = {}; >> + int trigger, polarity; >> + int ret; >> + >> + if (!header || > > That error check is kind of weird. Sure, 0 is an invalid address, but so > are many other > addresses. Is there any reason to believe that acpi_get_table_with_size > would return > a NULL pointer (but not some other invalid address) ? If the table is uninitialized, then all the values are probably zero. I was trying to come up with something. These are the only tests I could come up with I know work. >> + (unsigned long)header + sizeof(*wdg) > end || >> + header->length < sizeof(*wdg)) { > > So I really wonder how this is supposed to work. > > struct acpi_subtable_header { > u8 type; > u8 length; > }; > > struct acpi_gtdt_watchdog { > struct acpi_gtdt_header header; > ... > > struct acpi_gtdt_header { > u8 type; > u16 length; > }; > > Either the length is 16 bit or 8 bit. But both ??? > Or is it just luck and the value happens to be stored as little endian > value and the length is less than 256 bytes ? > > I understand this seems to be copied from BAD_MADT_ENTRY or similar code, > but it is still odd. It's the best I could come up with. Sure it seems weird, but it works, and since it's copied from BAD_MADT_ENTRY, I figured it was acceptable. > >> + pr_err("malformed subtable entry\n"); >> + return -EINVAL; >> + } >> + >> + if (!wdg->control_frame_address || !wdg->refresh_frame_address) { >> + pr_err("invalid control or refresh address\n"); >> + return -ENXIO; >> + } >> + >> + arm_sbsa_wdt_pdev = platform_device_alloc(DRV_NAME, 0); >> + if (!arm_sbsa_wdt_pdev) >> + return -ENOMEM; >> + >> + res[0].name = "control"; >> + res[0].flags = IORESOURCE_MEM; >> + res[0].start = wdg->control_frame_address; >> + res[0].end = res[0].start + sizeof(struct >> arm_sbsa_watchdog_control); > > Really ? Or should there be a -1 somewhere ? You're right. >> + >> + res[1].name = "refresh"; >> + res[1].flags = IORESOURCE_MEM; >> + res[1].start = wdg->refresh_frame_address; >> + res[1].end = res[1].start + sizeof(struct >> arm_sbsa_watchdog_refresh); > > Same here. Ok. >> + trigger = (wdg->timer_flags & ACPI_GTDT_WATCHDOG_IRQ_MODE) ? >> + ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; >> + >> + polarity = (wdg->timer_flags & ACPI_GTDT_WATCHDOG_IRQ_POLARITY) ? >> + ACPI_ACTIVE_LOW : ACPI_ACTIVE_HIGH; >> + >> + /* This should be the WS0 interrupt */ >> + ret = acpi_register_gsi(&arm_sbsa_wdt_pdev->dev, >> wdg->timer_interrupt, >> + trigger, polarity); >> + if (ret <= 0) { > > 0 is not an error (the interrupt number could be 0). Ok. >> +static int __init arm_sbsa_wdt_init(void) >> +{ >> + struct acpi_table_header *table; >> + acpi_size tbl_size; >> + acpi_status status; >> + int count; >> + >> + pr_info("ARM Server Base System Architecture watchdog driver\n"); >> + > This seems to assume that the watchdog is always supported, which is > quite unlikely. I'll make it a pr_debug. >> + status = acpi_get_table_with_size(ACPI_SIG_GTDT, 0, &table, >> &tbl_size); >> + if (ACPI_FAILURE(status)) { >> + pr_err("cannot locate GTDT table\n"); >> + return -EINVAL; >> + } > > I am kind of completely unhappy with the noisiness here and below. > Is this how acpi detection is supposed to happen ? > And is it really an _error_ if the device isn't there, > or does it just mean that the device isn't there ? I think the GTDT is required. Most likely, the kernel will fail to boot long before we get to this point if the GTDT is missing or corrupt. However, I'm not an ACPI expert by any means. I'm hoping that someone who knows a lot more than I do will review it. This driver was reviewed and approved by some of our internal ACPI experts, so I presume that it is correct. >> + count = acpi_parse_entries(ACPI_SIG_GTDT, sizeof(struct >> acpi_table_gtdt), >> + arm_sbsa_wdt_parse_gtdt, table, ACPI_GTDT_TYPE_WATCHDOG, 0); >> + if (count <= 0) { >> + pr_err("no watchdog subtables found\n"); >> + return -EINVAL; >> + } >> + >> + return platform_driver_probe(&arm_sbsa_wdt_driver, >> arm_sbsa_wdt_probe); > > Another oddity. Is this how acpi device instantiation is supposed to > happen ? > > I thought there are functions to register acpi drivers, such as > acpi_bus_register_driver(). > Why doesn't this work here ? I can't use acpi_bus_register_driver() because there are no ACPI IDs to probe on. Watchdog information is stored as a subtable of the GTDT table, and there's nothing in the ACPI layer that automatically creates platforms from subtables. I have to create the platform from scratch, which is why the code looks so messy. -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.

11 years

3
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Re: [Linaro-acpi] [PATCH] watchdog: introduce the ARM64 SBSA watchdog driver

by Ashwin Chaugule

+ Linaro-acpi On 29 April 2015 at 15:33, Timur Tabi <timur(a)codeaurora.org> wrote: > The ARM Server Base System Architecture is a specification for ARM-based > server systems. Among other things, it defines the behavior and register > interface for a watchdog timer. > > Signed-off-by: Timur Tabi <timur(a)codeaurora.org> > --- > drivers/watchdog/Kconfig | 10 ++ > drivers/watchdog/Makefile | 1 + > drivers/watchdog/arm_sbsa_wdt.c | 368 ++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 379 insertions(+) > create mode 100644 drivers/watchdog/arm_sbsa_wdt.c > > diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig > index e5e7c55..a2a133f 100644 > --- a/drivers/watchdog/Kconfig > +++ b/drivers/watchdog/Kconfig > @@ -514,6 +514,16 @@ config MEDIATEK_WATCHDOG > To compile this driver as a module, choose M here: the > module will be called mtk_wdt. > > +config ARM_SBSA_WDT > + bool "ARM Server Base System Architecture watchdog" > + depends on ACPI > + depends on ARM64 > + depends on ARM_ARCH_TIMER > + select WATCHDOG_CORE > + help > + Say Y here to include watchdog timer support for ARM Server Base > + System Architecture (SBSA) systems. > + > # AVR32 Architecture > > config AT32AP700X_WDT > diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile > index 5c19294..063ab8c 100644 > --- a/drivers/watchdog/Makefile > +++ b/drivers/watchdog/Makefile > @@ -64,6 +64,7 @@ obj-$(CONFIG_BCM_KONA_WDT) += bcm_kona_wdt.o > obj-$(CONFIG_TEGRA_WATCHDOG) += tegra_wdt.o > obj-$(CONFIG_MESON_WATCHDOG) += meson_wdt.o > obj-$(CONFIG_MEDIATEK_WATCHDOG) += mtk_wdt.o > +obj-$(CONFIG_ARM_SBSA_WDT) += arm_sbsa_wdt.o > > # AVR32 Architecture > obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o > diff --git a/drivers/watchdog/arm_sbsa_wdt.c b/drivers/watchdog/arm_sbsa_wdt.c > new file mode 100644 > index 0000000..2a2be40 > --- /dev/null > +++ b/drivers/watchdog/arm_sbsa_wdt.c > @@ -0,0 +1,368 @@ > +/* > + * Watchdog driver for SBSA-compliant watchdog timers > + * > + * Copyright (c) 2015, The Linux Foundation. All rights reserved. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 and > + * only version 2 as published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * ARM Server Base System Architecture watchdog driver. > + * > + * Register descriptions are taken from the ARM Server Base System > + * Architecture document (ARM-DEN-0029) > + */ > + > +#define DRV_NAME "arm-sbsa-wdt" > +#define pr_fmt(fmt) DRV_NAME ": " fmt > + > +#include <linux/module.h> > +#include <linux/watchdog.h> > +#include <linux/platform_device.h> > +#include <linux/device.h> > +#include <linux/io.h> > + > +#include <linux/irqdomain.h> > +#include <linux/interrupt.h> > +#include <linux/reboot.h> > + > +#include <clocksource/arm_arch_timer.h> > +#include <linux/acpi.h> > + > +/* Watchdog Interface Identification Registers */ > +struct arm_sbsa_watchdog_ident { > + uint32_t w_iidr; /* Watchdog Interface Identification Register */ > + uint8_t res2[0xFE8 - 0xFD0]; > + uint32_t w_pidr2; /* Peripheral ID2 Register */ > +}; > + > +/* Watchdog Refresh Frame */ > +struct arm_sbsa_watchdog_refresh { > + uint32_t wrr; /* Watchdog Refresh Register */ > + uint8_t res1[0xFCC - 0x004]; > + struct arm_sbsa_watchdog_ident ident; > +}; > + > +/* Watchdog Control Frame */ > +struct arm_sbsa_watchdog_control { > + uint32_t wcs; > + uint32_t res1; > + uint32_t wor; > + uint32_t res2; > + uint64_t wcv; > + uint8_t res3[0xFCC - 0x018]; > + struct arm_sbsa_watchdog_ident ident; > +}; > + > +struct arm_sbsa_watchdog_data { > + struct watchdog_device wdev; > + struct arm_sbsa_watchdog_refresh __iomem *refresh; > + struct arm_sbsa_watchdog_control __iomem *control; > +}; > + > +static int arm_sbsa_wdt_start(struct watchdog_device *wdev) > +{ > + struct arm_sbsa_watchdog_data *data = > + container_of(wdev, struct arm_sbsa_watchdog_data, wdev); > + > + /* Writing to the control register will also reset the counter */ > + writel(1, &data->control->wcs); > + > + return 0; > +} > + > +static int arm_sbsa_wdt_stop(struct watchdog_device *wdev) > +{ > + struct arm_sbsa_watchdog_data *data = > + container_of(wdev, struct arm_sbsa_watchdog_data, wdev); > + > + writel(0, &data->control->wcs); > + > + return 0; > +} > + > +static int arm_sbsa_wdt_set_timeout(struct watchdog_device *wdev, > + unsigned int timeout) > +{ > + struct arm_sbsa_watchdog_data *data = > + container_of(wdev, struct arm_sbsa_watchdog_data, wdev); > + > + wdev->timeout = timeout; > + writel(arch_timer_get_rate() * wdev->timeout, &data->control->wor); > + > + return 0; > +} > + > +static int arm_sbsa_wdt_ping(struct watchdog_device *wdev) > +{ > + struct arm_sbsa_watchdog_data *data = > + container_of(wdev, struct arm_sbsa_watchdog_data, wdev); > + > + writel(1, &data->refresh->wrr); > + > + return 0; > +} > + > +static unsigned int arm_sbsa_wdt_status(struct watchdog_device *wdev) > +{ > + struct arm_sbsa_watchdog_data *data = > + container_of(wdev, struct arm_sbsa_watchdog_data, wdev); > + > + return (readl(&data->control->wcs) & 1) << WDOG_ACTIVE; > +} > + > +static unsigned int arm_sbsa_wdt_timeleft(struct watchdog_device *wdev) > +{ > + struct arm_sbsa_watchdog_data *data = > + container_of(wdev, struct arm_sbsa_watchdog_data, wdev); > + > + uint64_t diff = readq(&data->control->wcv) - arch_timer_read_counter(); > + > + return diff / arch_timer_get_rate(); > +} > + > +static struct watchdog_info arm_sbsa_wdt_info = { > + .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, > + .identity = "ARM SBSA watchdog", > +}; > + > +static struct watchdog_ops arm_sbsa_wdt_ops = { > + .owner = THIS_MODULE, > + .start = arm_sbsa_wdt_start, > + .stop = arm_sbsa_wdt_stop, > + .ping = arm_sbsa_wdt_ping, > + .set_timeout = arm_sbsa_wdt_set_timeout, > + .status = arm_sbsa_wdt_status, > + .get_timeleft = arm_sbsa_wdt_timeleft, > +}; > + > +static irqreturn_t arm_sbsa_wdt_interrupt(int irq, void *p) > +{ > + /* > + * The WS0 interrupt occurs after the first timeout, so we attempt > + * a manual reboot. If this doesn't work, the WS1 timeout will > + * cause a hardware reset. > + */ > + emergency_restart(); > + > + return IRQ_HANDLED; > +} > + > +static int __init arm_sbsa_wdt_probe(struct platform_device *pdev) > +{ > + struct arm_sbsa_watchdog_data *data; > + struct resource *res; > + uint32_t iidr; > + int ret; > + > + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); > + if (!data) > + return -ENOMEM; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (!res || !res->start) { > + dev_err(&pdev->dev, "could not get control address\n"); > + return -ENOMEM; > + } > + > + data->control = devm_ioremap_resource(&pdev->dev, res); > + if (!data->control) > + return -ENOMEM; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); > + if (!res || !res->start) { > + dev_err(&pdev->dev, "could not get refresh address\n"); > + return -ENOMEM; > + } > + data->refresh = devm_ioremap_resource(&pdev->dev, res); > + if (!data->refresh) > + return -ENOMEM; > + > + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); > + if (!res || !res->start) { > + dev_err(&pdev->dev, "could not get interrupt\n"); > + return -ENOMEM; > + } > + > + iidr = readl(&data->control->ident.w_iidr); > + > + /* We only support architecture version 0 */ > + if (((iidr >> 16) & 0xf) != 0) { > + dev_info(&pdev->dev, "only architecture version 0 is supported\n"); > + return -ENODEV; > + } > + > + ret = devm_request_irq(&pdev->dev, res->start, arm_sbsa_wdt_interrupt, > + 0, DRV_NAME, NULL); > + if (ret < 0) { > + dev_err(&pdev->dev, "could not request irq %u (ret=%i)\n", > + (unsigned int)res->start, ret); > + return ret; > + } > + > + data->wdev.info = &arm_sbsa_wdt_info; > + data->wdev.ops = &arm_sbsa_wdt_ops; > + data->wdev.min_timeout = 1; > + data->wdev.status = WATCHDOG_NOWAYOUT_INIT_STATUS; > + > + /* Calculate the maximum timeout in seconds that we can support */ > + data->wdev.max_timeout = U32_MAX / arch_timer_get_rate(); > + > + ret = watchdog_register_device(&data->wdev); > + if (ret < 0) { > + dev_err(&pdev->dev, > + "could not register watchdog device (ret=%i)\n", ret); > + return ret; > + } > + > + dev_info(&pdev->dev, "implementer code is %03x, max timeout is %u seconds\n", > + (iidr & 0xf00) >> 1 | (iidr & 0x7f), data->wdev.max_timeout); > + > + /* > + * Bits [15:12] are an implementation-defined revision number > + * for the component. > + */ > + arm_sbsa_wdt_info.firmware_version = (iidr >> 12) & 0xf; > + > + platform_set_drvdata(pdev, data); > + > + return 0; > +} > + > +static int __exit arm_sbsa_wdt_remove(struct platform_device *pdev) > +{ > + struct arm_sbsa_watchdog_data *data = platform_get_drvdata(pdev); > + > + watchdog_unregister_device(&data->wdev); > + > + return 0; > +} > + > +static struct platform_device *arm_sbsa_wdt_pdev; > + > +static int __init arm_sbsa_wdt_parse_gtdt(struct acpi_subtable_header *header, > + const unsigned long end) > +{ > + struct acpi_gtdt_watchdog *wdg = (struct acpi_gtdt_watchdog *)header; > + struct platform_device *arm_sbsa_wdt_pdev; > + struct resource res[3] = {}; > + int trigger, polarity; > + int ret; > + > + if (!header || > + (unsigned long)header + sizeof(*wdg) > end || > + header->length < sizeof(*wdg)) { > + pr_err("malformed subtable entry\n"); > + return -EINVAL; > + } > + > + if (!wdg->control_frame_address || !wdg->refresh_frame_address) { > + pr_err("invalid control or refresh address\n"); > + return -ENXIO; > + } > + > + arm_sbsa_wdt_pdev = platform_device_alloc(DRV_NAME, 0); > + if (!arm_sbsa_wdt_pdev) > + return -ENOMEM; > + > + res[0].name = "control"; > + res[0].flags = IORESOURCE_MEM; > + res[0].start = wdg->control_frame_address; > + res[0].end = res[0].start + sizeof(struct arm_sbsa_watchdog_control); > + > + res[1].name = "refresh"; > + res[1].flags = IORESOURCE_MEM; > + res[1].start = wdg->refresh_frame_address; > + res[1].end = res[1].start + sizeof(struct arm_sbsa_watchdog_refresh); > + > + trigger = (wdg->timer_flags & ACPI_GTDT_WATCHDOG_IRQ_MODE) ? > + ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; > + > + polarity = (wdg->timer_flags & ACPI_GTDT_WATCHDOG_IRQ_POLARITY) ? > + ACPI_ACTIVE_LOW : ACPI_ACTIVE_HIGH; > + > + /* This should be the WS0 interrupt */ > + ret = acpi_register_gsi(&arm_sbsa_wdt_pdev->dev, wdg->timer_interrupt, > + trigger, polarity); > + if (ret <= 0) { > + pr_err("could not obtain interrupt\n"); > + goto error_platform; > + } > + > + res[2].name = "irq"; > + res[2].flags = IORESOURCE_IRQ; > + res[2].start = ret; > + res[2].end = res[2].start; > + > + ret = platform_device_add_resources(arm_sbsa_wdt_pdev, res, > + ARRAY_SIZE(res)); > + if (ret) { > + pr_err("could not add platform resources\n"); > + goto error_acpi; > + } > + > + ret = platform_device_add(arm_sbsa_wdt_pdev); > + if (ret) { > + pr_err("could not add platform device\n"); > + goto error_acpi; > + } > + > + return 0; > + > +error_acpi: > + acpi_unregister_gsi(res[2].start); > + > +error_platform: > + platform_device_put(arm_sbsa_wdt_pdev); > + > + return ret; > +} > + > +static struct platform_driver arm_sbsa_wdt_driver = { > + .remove = __exit_p(arm_sbsa_wdt_remove), > + .driver = { > + .name = DRV_NAME, > + .owner = THIS_MODULE, > + }, > +}; > + > +static int __init arm_sbsa_wdt_init(void) > +{ > + struct acpi_table_header *table; > + acpi_size tbl_size; > + acpi_status status; > + int count; > + > + pr_info("ARM Server Base System Architecture watchdog driver\n"); > + > + status = acpi_get_table_with_size(ACPI_SIG_GTDT, 0, &table, &tbl_size); > + if (ACPI_FAILURE(status)) { > + pr_err("cannot locate GTDT table\n"); > + return -EINVAL; > + } > + count = acpi_parse_entries(ACPI_SIG_GTDT, sizeof(struct acpi_table_gtdt), > + arm_sbsa_wdt_parse_gtdt, table, ACPI_GTDT_TYPE_WATCHDOG, 0); > + if (count <= 0) { > + pr_err("no watchdog subtables found\n"); > + return -EINVAL; > + } > + > + return platform_driver_probe(&arm_sbsa_wdt_driver, arm_sbsa_wdt_probe); > +} > + > +static void __exit arm_sbsa_wdt_exit(void) > +{ > + platform_device_unregister(arm_sbsa_wdt_pdev); > + platform_driver_unregister(&arm_sbsa_wdt_driver); > +} > + > +module_init(arm_sbsa_wdt_init); > +module_exit(arm_sbsa_wdt_exit); > + > +MODULE_DESCRIPTION("ARM Server Base System Architecture Watchdog Driver"); > +MODULE_LICENSE("GPL v2"); > -- > Qualcomm Innovation Center, Inc. > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project. >

11 years

1
0
0 0

[PATCH v3] ArmPlatformPkg: fix gtdt.asl for ArmVExpressPkg

by fu.wei＠linaro.org

From: Fu Wei <fu.wei(a)linaro.org> Add Memory-mapped GT and SBSA Generic Watchdog timer info base on Foundation Model Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Wei <fu.wei(a)linaro.org> --- .../AcpiTables/rtsm_ve-aemv8a/gtdt.asl | 67 +++++++++++++++++----- 1 file changed, 53 insertions(+), 14 deletions(-) diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl index d304243..11d5f89 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl @@ -36,16 +36,16 @@ */ [0004] Signature : "GTDT" -[0004] Table Length : 00000050 +[0004] Table Length : 000000D8 [0001] Revision : 02 [0001] Checksum : F1 [0006] Oem ID : "LINARO" [0008] Oem Table ID : "RTSMVEV8" -[0004] Oem Revision : 00000001 +[0004] Oem Revision : 00000002 [0004] Asl Compiler ID : "INTL" [0004] Asl Compiler Revision : 20110623 -[0008] Counter Block Address : 0000000000000000 +[0008] Counter Block Address : 000000002a430000 [0004] Reserved : 00000000 /* In RTSM model's dts file, the last cell of interrupts @@ -83,26 +83,35 @@ Always-on : 0 /* The 64-bit physical address at which the Counter Read block is located */ -[0008] CntReadBase Physical address : 0000000000000000 +[0008] CntReadBase Physical address : 000000002a800000 -[0004] Platform Timer Count : 00000001 -[0004] Platform Timer Offset : 0000005C +[0004] Platform Timer Count : 00000002 +[0004] Platform Timer Offset : 00000060 /* Memory-mapped GT (Generic Timer) structures */ [0001] Subtable Type : 00 [0002] Length : 0064 [0001] Reserved : 000000 [0008] Block Address : 000000002a810000 -[0004] Timer Count : 00000001 -[0004] Timer Offset : 00000010 +[0004] Timer Count : 00000002 +[0004] Timer Offset : 00000014 -/* One frame is available */ +/* Two frames are available + * In FVP base model's dts file, the last cell of interrupts + * is 0x04, it means its trigger type is 4 = active high level-sensitive. + * + * So in ACPI the Trigger Mode is 0 - Level triggered, and + * Polarity is 0 - Active high as ACPI spec describled. + * + * Using direct mapping for hwirqs, it means that we using IRQ ID: + * (SPI offset + 32), not SPI offset used in FDT. + */ [0001] Frame Number : 00 [0003] Reserved : 000000 [0008] Base Address : 000000002a820000 -[0008] EL0 Base Address : FFFFFFFFFFFFFFFF -[0004] Timer Interrupt : 00000029 /* 25+16 */ -[0004] Timer Flags (decoded below) : 00000000 /* Active high level-sensitive */ +[0008] EL0 Base Address : 000000002a820000 +[0004] Timer Interrupt : 00000039 /* 25(SPI)+32 */ +[0004] Timer Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 /* No virtual timer */ @@ -110,7 +119,37 @@ [0004] Virtual Timer Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 -[0004] Common Flags (decoded below) : 00000000 - Secure : 0 +/* CNTPSIRQ Secure physical timer event.*/ +[0004] Common Flags (decoded below) : 00000001 + Secure : 1 + Always On : 0 + +[0001] Frame Number : 01 +[0003] Reserved : 000000 +[0008] Base Address : 000000002a830000 +[0008] EL0 Base Address : 000000002a830000 +[0004] Timer Interrupt : 0000003A /* 26(SPI)+32 */ +[0004] Timer Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 +/* No virtual timer */ +[0004] Virtual Timer Interrupt : 00000000 +[0004] Virtual Timer Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 +/* CNTPSIRQ1 Secure physical timer event.*/ +[0004] Common Flags (decoded below) : 00000001 + Secure : 1 Always On : 0 +/* One EL2 SBSA Generic Watchdog timer is available */ +[0001] Subtable Type : 01 [SBSA Generic Watchdog] +[0001] Length : 1C +[0002] Reserved : 0000 +[0008] Refresh Frame Address : 000000002a450000 +[0008] Control Frame Address : 000000002a440000 +[0004] Timer Interrupt : 0000003B /* 27(SPI)+32 */ +[0004] Timer Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Secure : 0 -- 1.8.3.1

11 years

3
2
0 0

[V9 PATCH 0/3] Introduce ACPI support for ahci_platform driver

by Suravee Suthikulpanit

This patch series introduce ACPI support for AHCI platform driver. Existing ACPI support for AHCI assumes the device controller is a PCI device. Since there is no ACPI _CID for generic AHCI controller, the driver could not use it for matching devices. Therefore, this patch introduces a mechanism for drivers to match devices using ACPI _CLS method. _CLS contains PCI-defined class-code. This patch series also modifies ACPI modalias to add class-code to the exisiting format, which currently only uses _HID and _CIDs. This is required to support loadable modules w/ _CLS. This is rebased from and tested with linux-4.1-rc1 This topic was discussed earlier here (as part of introducing support for AMD Seattle SATA controller): http://marc.info/?l=linux-arm-kernel&m=141083492521584&w=2 Changes from V8 (https://lkml.org/lkml/2015/3/30/729) * Rebased to 4.1-rc1 * [1/3] Misc changes for ACPICA: - Re-organized certain parts from patch 2 since it should have been part of the ACPICA. - Modified logic for copying class code string (Lv) - Add changes and signed-off-by Lv Zheng * [2/3] Rebased due to added PRP001 matching code Changes from V7 (https://lkml.org/lkml/2015/3/26/592) * [1/3] Return AE_AML_OPERAND_TYPE when _CLS package containing invalid type (per Robert Moore suggestion). * [2/3] Fixed build error due missing ACPI_DEVICE_CLASS definition when disabling ACPI. Changes from V6 (https://lkml.org/lkml/2015/3/25/797) * Adding Acked-by Mika, and Reviewed-by Hanjun * Minor clen up to use lower case 0xffffff for cls_msk (per Mika suggestions). * Modify the ACPI_DEVICE_CLASS macro to use designated initializer (per Mika suggestions). Changes from V5 (https://lkml.org/lkml/2015/3/6/24) * Rebased and tested with acpi-5.1-v11 * Splitting up the ACPICA changes into a separate patch [1/3]. (per Mika suggestion) * Adding class-code mask support (per Mika suggestion) * Use macro to define struct acpi_device_id entry (per Mika suggestion) * Note: Mika also recommend reordering the member of struct acpi_device_id and define a macro to be used for declaring each table entry. This is a large amount of changes, and will be done separtely from this patch series. Changes from V4 (https://lkml.org/lkml/2015/3/2/56) * [1/2] Bug fixed: Reorder the declaration of struct acpi_pnp_device_id cls in the struct acpi_device_info (include/acpi/actypes.h) since compatible_id_list must be last one. * [2/2] Added Acked-by: Tejun Heo <tj(a)kernel.org> Changes from V3 (https://lkml.org/lkml/2015/2/8/106) * Instead of introducing new structure acpi_device_cls, add cls into the acpi_device_id, and modify the __acpi_match_device to also match for cls. (per Mika suggestion.) * Add loadable module support, which requires changes in ACPI modalias. (per Mika suggestion.) * Rebased and tested with acpi-5.1-v9 Changes from V2 (https://lkml.org/lkml/2015/1/5/662) * Update with review comment from Rafael in patch 1/2 * Rebased and tested with acpi-5.1-v8 Changes from V1 (https://lkml.org/lkml/2014/12/19/345) * Rebased to 3.19.0-rc2 * Change from acpi_cls in device_driver to acpi_match_cls (Hanjun comment) * Change the matching logic in acpi_driver_match_device() due to the new special PRP0001 _HID. * Simplify the return type of acpi_match_device_cls() to boolean. Changes from RFC (https://lkml.org/lkml/2014/12/17/446) * Remove #ifdef and make non-ACPI version of the acpi_match_device_cls as inline. (per Arnd) * Simplify logic to retrieve and evaluate _CLS handle. (per Hanjun) Suravee Suthikulpanit (3): ACPICA: Utilities: Add _CLS processing ACPI / scan: Add support for ACPI _CLS device matching ata: ahci_platform: Add ACPI _CLS matching drivers/acpi/acpica/acinterp.h | 2 + drivers/acpi/acpica/acutils.h | 4 ++ drivers/acpi/acpica/exutils.c | 32 ++++++++++++++ drivers/acpi/acpica/nsxfname.c | 23 ++++++++-- drivers/acpi/acpica/utids.c | 91 ++++++++++++++++++++++++++++++++++++++- drivers/acpi/scan.c | 32 +++++++++++++- drivers/ata/Kconfig | 2 +- drivers/ata/ahci_platform.c | 9 ++++ include/acpi/acnames.h | 1 + include/acpi/actypes.h | 24 +++++++---- include/linux/acpi.h | 14 ++++++ include/linux/mod_devicetable.h | 2 + scripts/mod/devicetable-offsets.c | 2 + scripts/mod/file2alias.c | 32 +++++++++++++- 14 files changed, 252 insertions(+), 18 deletions(-) -- 2.1.0

11 years

1
3
0 0

[V8 PATCH 0/3] Introduce ACPI support for ahci_platform driver

by Suravee Suthikulpanit

This patch series introduce ACPI support for AHCI platform driver. Existing ACPI support for AHCI assumes the device controller is a PCI device. Since there is no ACPI _CID for generic AHCI controller, the driver could not use it for matching devices. Therefore, this patch introduces a mechanism for drivers to match devices using ACPI _CLS method. _CLS contains PCI-defined class-code. This patch series also modifies ACPI modalias to add class-code to the exisiting format, which currently only uses _HID and _CIDs. This is required to support loadable modules w/ _CLS. This is rebased from and tested with: http://git.linaro.org/leg/acpi/acpi.git acpi-5.1-v11 This topic was discussed earlier here (as part of introducing support for AMD Seattle SATA controller): http://marc.info/?l=linux-arm-kernel&m=141083492521584&w=2 Changes from V7 (https://lkml.org/lkml/2015/3/26/592) * [1/3] Return AE_AML_OPERAND_TYPE when _CLS package containing invalid type (per Robert Moore suggestion). * [2/3] Fixed build error due missing ACPI_DEVICE_CLASS definition when disabling ACPI. Changes from V6 (https://lkml.org/lkml/2015/3/25/797) * Adding Acked-by Mika, and Reviewed-by Hanjun * Minor clen up to use lower case 0xffffff for cls_msk (per Mika suggestions). * Modify the ACPI_DEVICE_CLASS macro to use designated initializer (per Mika suggestions). Changes from V5 (https://lkml.org/lkml/2015/3/6/24) * Rebased and tested with acpi-5.1-v11 * Splitting up the ACPICA changes into a separate patch [1/3]. (per Mika suggestion) * Adding class-code mask support (per Mika suggestion) * Use macro to define struct acpi_device_id entry (per Mika suggestion) * Note: Mika also recommend reordering the member of struct acpi_device_id and define a macro to be used for declaring each table entry. This is a large amount of changes, and will be done separtely from this patch series. Changes from V4 (https://lkml.org/lkml/2015/3/2/56) * [1/2] Bug fixed: Reorder the declaration of struct acpi_pnp_device_id cls in the struct acpi_device_info (include/acpi/actypes.h) since compatible_id_list must be last one. * [2/2] Added Acked-by: Tejun Heo <tj(a)kernel.org> Changes from V3 (https://lkml.org/lkml/2015/2/8/106) * Instead of introducing new structure acpi_device_cls, add cls into the acpi_device_id, and modify the __acpi_match_device to also match for cls. (per Mika suggestion.) * Add loadable module support, which requires changes in ACPI modalias. (per Mika suggestion.) * Rebased and tested with acpi-5.1-v9 Changes from V2 (https://lkml.org/lkml/2015/1/5/662) * Update with review comment from Rafael in patch 1/2 * Rebased and tested with acpi-5.1-v8 Changes from V1 (https://lkml.org/lkml/2014/12/19/345) * Rebased to 3.19.0-rc2 * Change from acpi_cls in device_driver to acpi_match_cls (Hanjun comment) * Change the matching logic in acpi_driver_match_device() due to the new special PRP0001 _HID. * Simplify the return type of acpi_match_device_cls() to boolean. Changes from RFC (https://lkml.org/lkml/2014/12/17/446) * Remove #ifdef and make non-ACPI version of the acpi_match_device_cls as inline. (per Arnd) * Simplify logic to retrieve and evaluate _CLS handle. (per Hanjun) Suravee Suthikulpanit (3): ACPICA: Add ACPI _CLS processing ACPI / scan: Add support for ACPI _CLS device matching ata: ahci_platform: Add ACPI _CLS matching drivers/acpi/acpica/acutils.h | 3 ++ drivers/acpi/acpica/nsxfname.c | 21 +++++++++-- drivers/acpi/acpica/utids.c | 73 +++++++++++++++++++++++++++++++++++++++ drivers/acpi/scan.c | 36 ++++++++++++++++--- drivers/ata/Kconfig | 2 +- drivers/ata/ahci_platform.c | 9 +++++ include/acpi/acnames.h | 1 + include/acpi/actypes.h | 4 ++- include/linux/acpi.h | 14 ++++++++ include/linux/mod_devicetable.h | 2 ++ scripts/mod/devicetable-offsets.c | 2 ++ scripts/mod/file2alias.c | 32 +++++++++++++++-- 12 files changed, 189 insertions(+), 10 deletions(-) -- 2.1.0

11 years

7
15
0 0

[PATCH v5 0/9] PCI: MMCONFIG clean up

by Tomasz Nowicki

MCFG ACPI table and PCI ECAM standard have no arch dependencies so it can be used across all architectures. Currently MMCONFIG related code resides in arch/x86 directories. This patch set is going to isolate non-architecture specific code and make it accessible for all architectures. v4 -> v5 changes: - improvements for Makefile logic - provide arch-specific checks for MCFG entry - fix MCFG injection logic (support absence of _CBA() method) v3 -> v4 changes: - bug fixes after kbuild test robot report - add asm/io.h header for ecam.c - rename mmcfg -> ecam for drivers/xen/pci.c and arch/x86/pci/numachip.c - rework Kconfig logic v2 -> v3 changes: - rebase patch set v2 to v4.0-rc1 v1 -> v2 changes: - use generic readb/readw etc. accessors instead of AMD Fam10h workaround - separate ACPI and ECAM code - improve ECAM code naming Tomasz Nowicki (9): x86, pci: Clean up comment about buggy MMIO config space access for AMD Fam10h CPUs. x86, pci: Abstract PCI config accessors and use AMD Fam10h workaround exclusively. x86, pci: Reorder logic of pci_mmconfig_insert() function x86, pci, acpi: Move arch-agnostic MMCONFIG (aka ECAM) and ACPI code out of arch/x86/ directory pci, acpi, mcfg: Provide generic implementation of MCFG code initialization. x86, pci: mmconfig_{32,64}.c code refactoring - remove code duplication. x86, pci, ecam: mmconfig_64.c becomes default implementation for ECAM driver. pci, acpi, mcfg: Share ACPI PCI config space accessors. pci, ecam: Improve naming for ecam.c content and areas where it is used. arch/x86/Kconfig | 4 + arch/x86/include/asm/pci_x86.h | 34 +--- arch/x86/pci/Makefile | 5 +- arch/x86/pci/acpi.c | 3 +- arch/x86/pci/mmconfig-shared.c | 346 +++++++++++---------------------------- arch/x86/pci/mmconfig_32.c | 47 ++---- arch/x86/pci/mmconfig_64.c | 153 ------------------ arch/x86/pci/numachip.c | 29 +--- drivers/acpi/Makefile | 1 + drivers/acpi/mcfg.c | 121 ++++++++++++++ drivers/pci/Kconfig | 10 ++ drivers/pci/Makefile | 5 + drivers/pci/ecam.c | 358 +++++++++++++++++++++++++++++++++++++++++ drivers/xen/pci.c | 7 +- include/linux/ecam.h | 56 +++++++ 15 files changed, 679 insertions(+), 500 deletions(-) delete mode 100644 arch/x86/pci/mmconfig_64.c create mode 100644 drivers/acpi/mcfg.c create mode 100644 drivers/pci/ecam.c create mode 100644 include/linux/ecam.h -- 1.9.1

11 years

1
9
0 0

[PATCHv2 0/2] Add SPCR/DBG2 tables for kernel testing/debug

by Graeme Gregory

These patches add the DBG2/SPCR tables for FVP/Juno for kernel testing. They allow a kernel to find a serial console without console= line. They have been tested using the Redhat patches for SPCR support which are work in progress! Thanks Changes since v1 Ryan pointed out I had used RTSM in the JUNO tables - fixed.

11 years

3
6
0 0

leg-kernel tag leg-20150415.0 released

by Graeme Gregory

The leg-kernel release has been made and tagged as leg-20150415.0 This is based on mainline kernel v4.0 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: https://git.linaro.org/leg/acpi/leg-kernel.git/commit/afdd440a8c69eea7f1365… Notes :- 1) Much improved Seattle support thanks to patches from Redhat. 2) This release incorporates the SBSA UART support for pl011 driver from Andre Przywara. This means that your console will become ttyAMA0 (console=ttyAMA0) on Juno/FVP. It also means to run FVP model you need these options :- -C bp.pl011_uart0.untimed_fifos=0 -C bp.pl011_uart0.revision="r1p5" 3) First release of leg-kernel where all preperation was done on a Seattle running this release of leg-kernel.

11 years, 1 month

2
1
0 0

leg-kernel tag leg-20150414.0 released

by Graeme Gregory

The leg-kernel release has been made and tagged as leg-20150414.0 This is based on mainline kernel v4.0 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: https://git.linaro.org/leg/acpi/leg-kernel.git/commit/afdd440a8c69eea7f1365… Notes :- 1) This release restores support for AMD Seattle. 2) This release incorporates the SBSA UART support for pl011 driver from Andre Przywara. This means that your console will become ttyAMA0 (console=ttyAMA0) on Juno/FVP. It also means to run FVP model you need these options :- -C bp.pl011_uart0.untimed_fifos=0 -C bp.pl011_uart0.revision="r1p5"

11 years, 1 month

1
0
0 0

LINA, Problems with item delivery, n.000253016

by FedEx International Ground

Dear Lina, Courier was unable to deliver the parcel to you. Please, open email attachment to print shipment label. Thanks and best regards, Brad Ritchie, FedEx Operation Manager.

11 years, 1 month

1
0
0 0

LINA, Notice to Appear in Court

by District Court

Dear Lina, You have to appear in the Court on the April 15. Please, prepare all the documents relating to the case and bring them to Court on the specified date. Note: The case will be heard by the judge in your absence if you do not come. The Court Notice is attached to this email. Sincerely, Donald Galloway, District Clerk.

11 years, 1 month

1
0
0 0

[RFC PATCH] ACPI / scan: Introduce _CCA parsing logic and setting up device coherency

by Suravee Suthikulpanit

ACPI v5.1 introduced _CCA object for specifying cache coherency attribute for devices. This patch implements a logic, which traverses device namespace to parse the coherency information, and calling the corresponded arch_setup_dma_ops(). It checks the _CCA during ACPI scan, and setup coherency during acpi_device creation. Then, this is propagted to the platform_device when it is created at later time. CC: Mark Salter <msalter(a)redhat.com> CC: Hanjun Guo <hanjun.guo(a)linaro.org> CC: Al Stone <al.stone(a)linaro.org> Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit(a)amd.com> --- NOTE: The original patch has been submitted by Mark Salter, and discussed here: * http://comments.gmane.org/gmane.linux.acpi.devel/70424 One of the reveiw comment was dissusing whether we need the do/while loop for travesing parents of the device. AFAIK, there are no APIs that would do upsearch from a particular node. The acpi_get_handle() is the closest one, but it is using ACPI_NS_NO_UPSEARCH. This has been rebased and tested with: * http://git.linaro.org/leg/acpi/acpi.git acpi-5.1-v11 * [V8 PATCH 0/3] Introduce ACPI support for ahci_platform driver (https://lkml.org/lkml/2015/3/30/729) drivers/acpi/acpi_platform.c | 5 +++- drivers/acpi/scan.c | 56 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+), 1 deletion(-) diff --git a/drivers/acpi/acpi_platform.c b/drivers/acpi/acpi_platform.c index 1284138..47e37a8 100644 --- a/drivers/acpi/acpi_platform.c +++ b/drivers/acpi/acpi_platform.c @@ -108,9 +108,12 @@ struct platform_device *acpi_create_platform_device(struct acpi_device *adev) if (IS_ERR(pdev)) dev_err(&adev->dev, "platform device creation failed: %ld\n", PTR_ERR(pdev)); - else + else { + arch_setup_dma_ops(&pdev->dev, 0, 0, NULL, + is_device_dma_coherent(&adev->dev)); dev_dbg(&adev->dev, "created platform device %s\n", dev_name(&pdev->dev)); + } kfree(resources); return pdev; diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 230ec983..4d81c55 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -11,6 +11,7 @@ #include <linux/kthread.h> #include <linux/dmi.h> #include <linux/nls.h> +#include <linux/dma-mapping.h> #include <asm/pgtable.h> @@ -57,6 +58,9 @@ struct acpi_device_bus_id{ struct list_head node; }; +static int acpi_bus_type_and_status(acpi_handle handle, int *type, + unsigned long long *sta); + void acpi_scan_lock_acquire(void) { mutex_lock(&acpi_scan_lock); @@ -1327,6 +1331,51 @@ void acpi_bus_put_acpi_device(struct acpi_device *adev) put_device(&adev->dev); } +/** + * acpi_check_and_set_coherency - check and set cache coherency of a device + * @device: ACPI device + * + * Search a device and its parents for a _CCA method and calculate + * the effective coherency property of the device. If found, set up + * appropriate dma_ops for the device. + * + * Note From ACPIv5.1 spec: + * If used _CCA must be included under all bus-master-capable + * devices defined as children of \_SB. The value of _CCA is inherited + * by all descendants of these devices, so it need not be repeated for + * their children devices and will be ignored by OSPM if it is provided + * there. + */ +static int acpi_check_and_set_coherency(struct acpi_device *device) +{ + acpi_status status; + unsigned long long eff_cca = ~0ULL; + acpi_handle tmp, handle = device->handle; + + /* Calculate effective _CCA from all parents of this device */ + do { + unsigned long cca; + + status = acpi_get_handle(handle, "_CCA", &tmp); + if (ACPI_SUCCESS(status)) { + status = acpi_evaluate_integer(tmp, "_CCA", NULL, &cca); + /* Other values besides 0 and 1 are reserved */ + if (ACPI_FAILURE(status) || (cca != 0 && cca != 1)) + return -EINVAL; + eff_cca = cca; + } + + status = acpi_get_parent(handle, &handle); + if (ACPI_FAILURE(status)) + break; + } while (ACPI_SUCCESS(status)); + + if (eff_cca != ~0ULL) + arch_setup_dma_ops(&device->dev, 0, 0, NULL, eff_cca); + + return 0; +} + int acpi_device_add(struct acpi_device *device, void (*release)(struct device *)) { @@ -1398,6 +1447,13 @@ int acpi_device_add(struct acpi_device *device, device->dev.parent = &device->parent->dev; device->dev.bus = &acpi_bus_type; device->dev.release = release; + + result = acpi_check_and_set_coherency(device); + if (result) { + dev_err(&device->dev, "Error getting device _CCA information\n"); + goto err; + } + result = device_add(&device->dev); if (result) { dev_err(&device->dev, "Error registering device\n"); -- 2.1.0

11 years, 1 month

4
3
0 0

leg-kernel tag leg-20150408.0 released

by Graeme Gregory

The leg-kernel release has been made and tagged as leg-20150408.0 This is based on mainline kernel v4.0-rc7 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: https://git.linaro.org/leg/acpi/leg-kernel.git/commit/4a93b8470719866b46d92… Notes :- 1) This release restores support for AMD Seattle. 2) This release incorporates the SBSA UART support for pl011 driver from Andre Przywara. This means that your console will become ttyAMA0 (console=ttyAMA0) on Juno/FVP. It also means to run FVP model you need these options :- -C bp.pl011_uart0.untimed_fifos=0 -C bp.pl011_uart0.revision="r1p5"

11 years, 1 month

1
0
0 0

[PATCH v2] ArmPlatformPkg: fix gtdt.asl for ArmVExpressPkg

by fu.wei＠linaro.org

From: Fu Wei <fu.wei(a)linaro.org> Add Memory-mapped GT and SBSA Generic Watchdog timer info base on Foundation Model Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Wei <fu.wei(a)linaro.org> --- .../AcpiTables/rtsm_ve-aemv8a/gtdt.asl | 67 +++++++++++++++++----- 1 file changed, 53 insertions(+), 14 deletions(-) diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl index d304243..11d5f89 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl @@ -36,16 +36,16 @@ */ [0004] Signature : "GTDT" -[0004] Table Length : 00000050 +[0004] Table Length : 000000D8 [0001] Revision : 02 [0001] Checksum : F1 [0006] Oem ID : "LINARO" [0008] Oem Table ID : "RTSMVEV8" -[0004] Oem Revision : 00000001 +[0004] Oem Revision : 00000002 [0004] Asl Compiler ID : "INTL" [0004] Asl Compiler Revision : 20110623 -[0008] Counter Block Address : 0000000000000000 +[0008] Counter Block Address : 000000002a430000 [0004] Reserved : 00000000 /* In RTSM model's dts file, the last cell of interrupts @@ -83,26 +83,35 @@ Always-on : 0 /* The 64-bit physical address at which the Counter Read block is located */ -[0008] CntReadBase Physical address : 0000000000000000 +[0008] CntReadBase Physical address : 000000002a800000 -[0004] Platform Timer Count : 00000001 -[0004] Platform Timer Offset : 0000005C +[0004] Platform Timer Count : 00000002 +[0004] Platform Timer Offset : 00000060 /* Memory-mapped GT (Generic Timer) structures */ [0001] Subtable Type : 00 [0002] Length : 0064 [0001] Reserved : 000000 [0008] Block Address : 000000002a810000 -[0004] Timer Count : 00000001 -[0004] Timer Offset : 00000010 +[0004] Timer Count : 00000002 +[0004] Timer Offset : 00000014 -/* One frame is available */ +/* Two frames is available + * In FVP base model's dts file, the last cell of interrupts + * is 0x04, it means its trigger type is 4 = active high level-sensitive. + * + * So in ACPI the Trigger Mode is 0 - Level triggered, and + * Polarity is 0 - Active high as ACPI spec describled. + * + * Using direct mapping for hwirqs, it means that we using IRQ ID: + * (SPI offset + 32), not SPI offset used in FDT. + */ [0001] Frame Number : 00 [0003] Reserved : 000000 [0008] Base Address : 000000002a820000 -[0008] EL0 Base Address : FFFFFFFFFFFFFFFF -[0004] Timer Interrupt : 00000029 /* 25+16 */ -[0004] Timer Flags (decoded below) : 00000000 /* Active high level-sensitive */ +[0008] EL0 Base Address : 000000002a820000 +[0004] Timer Interrupt : 00000039 /* 25(SPI)+32 */ +[0004] Timer Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 /* No virtual timer */ @@ -110,7 +119,37 @@ [0004] Virtual Timer Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 -[0004] Common Flags (decoded below) : 00000000 - Secure : 0 +/* CNTPSIRQ Secure physical timer event.*/ +[0004] Common Flags (decoded below) : 00000001 + Secure : 1 + Always On : 0 + +[0001] Frame Number : 01 +[0003] Reserved : 000000 +[0008] Base Address : 000000002a830000 +[0008] EL0 Base Address : 000000002a830000 +[0004] Timer Interrupt : 0000003A /* 26(SPI)+32 */ +[0004] Timer Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 +/* No virtual timer */ +[0004] Virtual Timer Interrupt : 00000000 +[0004] Virtual Timer Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 +/* CNTPSIRQ1 Secure physical timer event.*/ +[0004] Common Flags (decoded below) : 00000001 + Secure : 1 Always On : 0 +/* One EL2 SBSA Generic Watchdog timer is available */ +[0001] Subtable Type : 01 [SBSA Generic Watchdog] +[0001] Length : 1C +[0002] Reserved : 0000 +[0008] Refresh Frame Address : 000000002a450000 +[0008] Control Frame Address : 000000002a440000 +[0004] Timer Interrupt : 0000003B /* 27(SPI)+32 */ +[0004] Timer Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Secure : 0 -- 1.8.3.1

11 years, 1 month

1
0
0 0

[PATCH] ArmPlatformPkg: fix gtdt.asl for ArmVExpressPkg

by fu.wei＠linaro.org

From: Fu Wei <fu.wei(a)linaro.org> Add Memory-mapped GT and SBSA Generic Watchdog timer info base on Foundation Model Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Wei <fu.wei(a)linaro.org> --- .../AcpiTables/rtsm_ve-aemv8a/gtdt.asl | 54 +++++++++++++++++----- 1 file changed, 42 insertions(+), 12 deletions(-) diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl index d304243..8adf7b6 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl @@ -36,16 +36,16 @@ */ [0004] Signature : "GTDT" -[0004] Table Length : 00000050 +[0004] Table Length : 000000D8 [0001] Revision : 02 [0001] Checksum : F1 [0006] Oem ID : "LINARO" [0008] Oem Table ID : "RTSMVEV8" -[0004] Oem Revision : 00000001 +[0004] Oem Revision : 00000002 [0004] Asl Compiler ID : "INTL" [0004] Asl Compiler Revision : 20110623 -[0008] Counter Block Address : 0000000000000000 +[0008] Counter Block Address : 000000002a430000 [0004] Reserved : 00000000 /* In RTSM model's dts file, the last cell of interrupts @@ -83,34 +83,64 @@ Always-on : 0 /* The 64-bit physical address at which the Counter Read block is located */ -[0008] CntReadBase Physical address : 0000000000000000 +[0008] CntReadBase Physical address : 000000002a800000 -[0004] Platform Timer Count : 00000001 -[0004] Platform Timer Offset : 0000005C +[0004] Platform Timer Count : 00000002 +[0004] Platform Timer Offset : 00000060 /* Memory-mapped GT (Generic Timer) structures */ [0001] Subtable Type : 00 [0002] Length : 0064 [0001] Reserved : 000000 [0008] Block Address : 000000002a810000 -[0004] Timer Count : 00000001 -[0004] Timer Offset : 00000010 +[0004] Timer Count : 00000002 +[0004] Timer Offset : 00000014 -/* One frame is available */ +/* two frames is available */ [0001] Frame Number : 00 [0003] Reserved : 000000 [0008] Base Address : 000000002a820000 -[0008] EL0 Base Address : FFFFFFFFFFFFFFFF -[0004] Timer Interrupt : 00000029 /* 25+16 */ +[0008] EL0 Base Address : 000000002a820000 +[0004] Timer Interrupt : 00000039 /* 25+32 */ [0004] Timer Flags (decoded below) : 00000000 /* Active high level-sensitive */ + Trigger Mode : 1 + Polarity : 0 +/* No virtual timer */ +[0004] Virtual Timer Interrupt : 00000000 +[0004] Virtual Timer Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 + +[0004] Common Flags (decoded below) : 00000000 + Secure : 1 + Always On : 0 + +[0001] Frame Number : 01 +[0003] Reserved : 000000 +[0008] Base Address : 000000002a830000 +[0008] EL0 Base Address : 000000002a830000 +[0004] Timer Interrupt : 0000003A /* 26+32 */ +[0004] Timer Flags (decoded below) : 00000000 /* Active high level-sensitive */ + Trigger Mode : 1 + Polarity : 0 /* No virtual timer */ [0004] Virtual Timer Interrupt : 00000000 [0004] Virtual Timer Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 + [0004] Common Flags (decoded below) : 00000000 - Secure : 0 + Secure : 1 Always On : 0 +/* one EL2 SBSA Generic Watchdog timer is available */ +[0001] Subtable Type : 01 [SBSA Generic Watchdog] +[0001] Length : 1C +[0002] Reserved : 0000 +[0008] Refresh Frame Address : 000000002a450000 +[0008] Control Frame Address : 000000002a440000 +[0004] Timer Interrupt : 0000003B /* 27+32 */ +[0004] Timer Flags (decoded below) : 00000001 + Trigger Mode : 1 + Polarity : 0 + Secure : 0 -- 1.8.3.1

11 years, 1 month

2
1
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LINA, Notice to Appear

by State Court

Dear Lina, You have to appear in the Court on the April 11. You are kindly asked to prepare and bring the documents relating to the case to Court on the specified date. Note: The case will be heard by the judge in your absence if you do not come. The Court Notice is attached to this email. Kind regards, Alfred Moran, Clerk of Court.

11 years, 1 month

1
0
0 0

Re: [Linaro-acpi] [PATCH v4 0/9] PCI: MMCONFIG clean up

by Bjorn Helgaas

On Fri, Apr 3, 2015 at 7:06 AM, Tomasz Nowicki <tomasz.nowicki(a)linaro.org> wrote: > Hi Bjorn, > > Any comments before I post next version ? Nope. I've been on vacation for a week and am just trying to catch up. Haven't had time to do any more than build-test your v4 series. Bjorn > On 11.03.2015 15:12, Tomasz Nowicki wrote: >> >> MCFG ACPI table and PCI ECAM standard have no arch dependencies so it can >> be >> used across all architectures. Currently MMCONFIG related code resides in >> arch/x86 directories. This patch set is going to isolate non-architecture >> specific code and make it accessible for all architectures. >> >> v3 -> v4 changes: >> - bug fixes after kbuild test robot report >> - add asm/io.h header for ecam.c >> - rename mmcfg -> ecam for drivers/xen/pci.c and >> arch/x86/pci/numachip.c >> - rework Kconfig logic >> >> v2 -> v3 changes: >> - rebase patch set v2 to v4.0-rc1 >> >> v1 -> v2 changes: >> - use generic readb/readw etc. accessors instead of AMD Fam10h workaround >> - separate ACPI and ECAM code >> - improve ECAM code naming >> >> Tomasz Nowicki (9): >> x86, pci: Clean up comment about buggy MMIO config space access for >> AMD Fam10h CPUs. >> x86, pci: Abstract PCI config accessors and use AMD Fam10h workaround >> exclusively. >> x86, pci: Reorder logic of pci_mmconfig_insert() function >> x86, pci, acpi: Move arch-agnostic MMCONFIG (aka ECAM) and ACPI code >> out of arch/x86/ directory >> pci, acpi, mcfg: Provide generic implementation of MCFG code >> initialization. >> x86, pci: mmconfig_{32,64}.c code refactoring - remove code >> duplication. >> x86, pci, ecam: mmconfig_64.c becomes default implementation for ECAM >> driver. >> pci, acpi, mcfg: Share ACPI PCI config space accessors. >> pci, ecam: Improve naming for ecam.c content and areas where it is >> used. >> >> arch/x86/Kconfig | 4 + >> arch/x86/include/asm/pci_x86.h | 34 +--- >> arch/x86/pci/Makefile | 5 +- >> arch/x86/pci/acpi.c | 3 +- >> arch/x86/pci/mmconfig-shared.c | 346 >> +++++++++++---------------------------- >> arch/x86/pci/mmconfig_32.c | 47 ++---- >> arch/x86/pci/mmconfig_64.c | 153 ------------------ >> arch/x86/pci/numachip.c | 29 +--- >> drivers/acpi/Makefile | 1 + >> drivers/acpi/mcfg.c | 121 ++++++++++++++ >> drivers/pci/Kconfig | 10 ++ >> drivers/pci/Makefile | 5 + >> drivers/pci/ecam.c | 358 >> +++++++++++++++++++++++++++++++++++++++++ >> drivers/xen/pci.c | 7 +- >> include/linux/ecam.h | 56 +++++++ >> 15 files changed, 679 insertions(+), 500 deletions(-) >> delete mode 100644 arch/x86/pci/mmconfig_64.c >> create mode 100644 drivers/acpi/mcfg.c >> create mode 100644 drivers/pci/ecam.c >> create mode 100644 include/linux/ecam.h >> >

11 years, 1 month

1
0
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current state of the Seattle topic branch

by Al Stone

Slowly but surely, the Seattle topic branch is coming back to life. I pushed up a version today to acpi.git that has the console working (and earlycon) via SPCR, AHCI works so the SATA drive will come up, and the PMU will start, and the secondary CPUs will come up via the parking protocol. GICv2 support seems to be working. too. I recommend that you have version 73C or 74D firmware; anything earlier is sketchy. This is all in acpi-topic-seattle, which is based on the v9 version of the patches (and hence 4.0-rc1, too). It's enough I can get to a shell prompt/login and do useful things. Things that still need work: -- Reboot doesn't work; there's a patch for this but not applied just yet -- The XGBE NIC is weird. If you have the B0 rev of the board, it may work fine. I have an A0 which requires a slightly different driver that is not working (it causes a hang that I'm trying to figure out); this may just be because of 4.0. -- Need to add in PCI support, plus things like USB, I2C, IPMI, and so on -- all the other stuff currently listed in the DT. There are patches for all of this, but it's a mess because of what we can and cannot release just yet -- and, well, because I find PCI confusing, too :). -- KVM would be good to have (yes, it does need a mod for ACPI). I'd like to at least get PCI working before notifying LKML. Anything you have time to help with is greatly appreciated.... -- ciao, al ----------------------------------- Al Stone Software Engineer Linaro Enterprise Group al.stone(a)linaro.org -----------------------------------

11 years, 1 month

2
5
0 0

[patch v11 00/23] Introduce ACPI for ARM64 based on ACPI 5.1

by Hanjun Guo

Some fixes since last version: - Add a patch 19/23 for disabling ACPI for Xen on ARM64 for now to fix compile errors on XEN ACPI, Stefano and Julien are ok with this temporary solution. - Add patch "ARM64 / ACPI: Don't unflatten device tree if acpi=force is passed", which will fix the problem that the device tree will be unflattened even if acpi=force passed, that will not obey the policy. - update patch "irqchip: Add GICv2 specific ACPI boot support", which will cause compile error on i386 with both DT and ACPI enabled: All error/warnings: In file included from include/linux/acpi_irq.h:4:0, from drivers/irqchip/irqchip.c:11: arch/x86/include/asm/irq.h:35:8: error: unknown type name 'bool' extern bool handle_irq(unsigned irq, struct pt_regs *regs); ^ arch/x86/include/asm/irq.h:35:45: warning: 'struct pt_regs' declared inside parameter list extern bool handle_irq(unsigned irq, struct pt_regs *regs); ^ arch/x86/include/asm/irq.h:35:45: warning: its scope is only this definition or declaration, which is probably not what you want .... That's because of I include the <asm/irq.h> in <linux/acpi_irq.h>, and <linux/acpi_irq.h> will be put on the top of all head files, so use <linux/irq.h> instead of <asm/irq.h> in acpi_irq.h (in <linux/irq.h>, it will include <linux/*.h> before include <asm/irq.h>), this is the only update for this patch. Lorenzo will send some cleanup patches on top of this one soon. Thanks Hanjun Al Stone (4): ARM64 / ACPI: Get RSDP and ACPI boot-time tables ARM64 / ACPI: Introduce early_param "acpi=" to enable/disable ACPI ARM64 / ACPI: Select ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled on ARM64 ARM64 / ACPI: additions of ACPI documentation for arm64 Graeme Gregory (6): ACPI: add arm64 to the platforms that use ioremap ACPI / sleep: Introduce CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT ARM64 / ACPI: If we chose to boot from acpi then disable FDT ARM64 / ACPI: Get PSCI flags in FADT for PSCI init ARM64 / ACPI: Enable ARM64 in Kconfig Documentation: ACPI for ARM64 Hanjun Guo (10): ACPI / table: Use pr_debug() instead of pr_info() for MADT table scanning ARM64 / ACPI: Introduce PCI stub functions for ACPI ACPI / table: Print GIC information when MADT is parsed ARM64 / ACPI: Parse MADT for SMP initialization ACPI / processor: Introduce phys_cpuid_t for CPU hardware ID ACPI / processor: Make it possible to get CPU hardware ID via GICC ARM64 / ACPI: Introduce ACPI_IRQ_MODEL_GIC and register device's gsi clocksource / arch_timer: Parse GTDT to initialize arch timer XEN / ACPI: Make XEN ACPI depend on X86 ARM64 / ACPI: Don't unflatten device tree if acpi=force is passed Mark Salter (2): ARM64: allow late use of early_ioremap ACPI: fix acpi_os_ioremap for arm64 Tomasz Nowicki (1): irqchip: Add GICv2 specific ACPI boot support Documentation/arm64/acpi_object_usage.txt | 593 ++++++++++++++++++++++++++++++ Documentation/arm64/arm-acpi.txt | 505 +++++++++++++++++++++++++ Documentation/kernel-parameters.txt | 3 +- arch/arm64/Kconfig | 3 + arch/arm64/include/asm/acenv.h | 18 + arch/arm64/include/asm/acpi.h | 99 +++++ arch/arm64/include/asm/cpu_ops.h | 1 + arch/arm64/include/asm/fixmap.h | 3 + arch/arm64/include/asm/irq.h | 13 + arch/arm64/include/asm/pci.h | 6 + arch/arm64/include/asm/psci.h | 3 +- arch/arm64/include/asm/smp.h | 5 +- arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/acpi.c | 392 ++++++++++++++++++++ arch/arm64/kernel/cpu_ops.c | 2 +- arch/arm64/kernel/pci.c | 25 ++ arch/arm64/kernel/psci.c | 78 ++-- arch/arm64/kernel/setup.c | 21 +- arch/arm64/kernel/smp.c | 2 +- arch/arm64/kernel/time.c | 7 + arch/ia64/Kconfig | 1 + arch/ia64/kernel/acpi.c | 2 +- arch/x86/Kconfig | 1 + arch/x86/kernel/acpi/boot.c | 2 +- drivers/acpi/Kconfig | 7 +- drivers/acpi/Makefile | 2 +- drivers/acpi/acpi_processor.c | 7 +- drivers/acpi/bus.c | 3 + drivers/acpi/internal.h | 4 + drivers/acpi/osl.c | 6 +- drivers/acpi/processor_core.c | 60 ++- drivers/acpi/tables.c | 52 ++- drivers/clocksource/arm_arch_timer.c | 132 +++++-- drivers/irqchip/irq-gic.c | 102 +++++ drivers/irqchip/irqchip.c | 3 + drivers/xen/Kconfig | 4 + drivers/xen/Makefile | 2 +- include/acpi/acpi_io.h | 4 + include/acpi/processor.h | 6 +- include/linux/acpi.h | 8 +- include/linux/acpi_irq.h | 10 + include/linux/clocksource.h | 6 + include/linux/irqchip/arm-gic-acpi.h | 31 ++ 43 files changed, 2129 insertions(+), 106 deletions(-) create mode 100644 Documentation/arm64/acpi_object_usage.txt create mode 100644 Documentation/arm64/arm-acpi.txt create mode 100644 arch/arm64/include/asm/acenv.h create mode 100644 arch/arm64/include/asm/acpi.h create mode 100644 arch/arm64/kernel/acpi.c create mode 100644 include/linux/acpi_irq.h create mode 100644 include/linux/irqchip/arm-gic-acpi.h -- 1.9.1

11 years, 1 month

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[PATCH 1/2] ARM64 / ACPI: Ignore the return error value of acpi_map_gic_cpu_interface()

by Hanjun Guo

MADT table scannig will stopped once it gets the errors returned by the handler, which is acpi_map_gic_cpu_interface() in for ARM64, so Ignore the return error value to search for all enabled CPUs for SMP init. Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org> --- arch/arm64/kernel/acpi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c index 07649e4..c263cba 100644 --- a/arch/arm64/kernel/acpi.c +++ b/arch/arm64/kernel/acpi.c @@ -181,7 +181,8 @@ acpi_parse_gic_cpu_interface(struct acpi_subtable_header *header, return -EINVAL; acpi_table_print_madt_entry(header); - return acpi_map_gic_cpu_interface(processor); + acpi_map_gic_cpu_interface(processor); + return 0; } /* Parse GIC cpu interface entries in MADT for SMP init */ -- 1.9.1

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