- Linaro-acpi - lists.linaro.org

[PATCH v4 00/13] Enable ACPI on ARM64 in Kconfig

by Hanjun Guo

This patch set is the first part of ARM64 ACPI core patches to running ACPI on ARM64, it just handle some compile errors when ACPI is introduced to ARM64 platform and enable ACPI on ARM64 in Kconfig. Following core patch sets for ACPI based SMP/GIC/Arch Timer initialization to enable ACPI on ARM64 are under interally review and will send out when ACPI 5.1 is released. patch 1~3 are cleanups for ACPI core; patch 4~13 are arch dependent code for ARM64 ACPI; This patch set is based on linux-next branch of Rafael's linux-pm tree, and PCI patches for ARM64 from Liviu: Support for creating generic host_bridge from device tree https://lkml.org/lkml/2014/3/14/279 Add support for PCI in AArch64 http://comments.gmane.org/gmane.linux.ports.arm.kernel/309392 Changes since v3: - Introduce three new patches - acpi: arm64 does not have a BIOS add config for BIOS table scan - ACPI: Don't use acpi_lapic in ACPI core code - ARM64 / ACPI: if we chose to boot from acpi then disable FDT - Rebase on the latest linux-next branch of Rafael's tree, and introduce asm/acenv.h for ARM64; - Introduce ARCH_HAS_ACPI_PDC to move all the _PDC related code to a single place and make x86 and ia64 select ARCH_HAS_ACPI_PDC; - Fix some checpatch warning; - Fix broken Signed-off-by chain; - Remove duplicate interface macros for ACPICA pointed out by Mark Rutland and Zheng Lv; - Redefine ACPI_FLUSH_CPU_CACHE(); - Stub out some PCI functions suggested by Arnd and already merged into 3.16 Comments still need to be addressed: - Empty PCI implementation in arch/arm64 which suggested by Arnd; - suspend and sleep on ARM64 platform pointed out by Lorenzo; Changes since v2: - Make ACPI depend on PCI on ARM64 - rework all the patches and seperate some of the patches into fine-grained, and add some comments and changelog to make it easier for review. Al Stone (3): ARM64 / ACPI: Introduce arm-core.c and its related head file ARM64 / ACPI: Introduce early_param for "acpi" ARM64 / ACPI: Select ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled on ARM64 Graeme Gregory (6): acpi: arm64 does not have a BIOS add config for BIOS table scan. ACPI: Don't use acpi_lapic in ACPI core code ARM64 : Add dummy asm/cpu.h ARM64 / ACPI: Introduce lowlevel suspend function ARM64 / ACPI: if we chose to boot from acpi then disable FDT ARM64 / ACPI: Enable ARM64 in Kconfig Hanjun Guo (4): ACPI / processor: Introduce ARCH_HAS_ACPI_PDC ARM64 / ACPI: Introduce arch_fix_phys_package_id() for cpu topology ARM64 / ACPI: Introduce PCI functions for ACPI on ARM64 ACPI: Make EC debugfs depend on X86 || IA64 in Kconfig Documentation/kernel-parameters.txt | 3 +- arch/arm64/Kconfig | 3 + arch/arm64/include/asm/acenv.h | 18 +++ arch/arm64/include/asm/acpi.h | 61 +++++++++++ arch/arm64/include/asm/cpu.h | 11 ++ arch/arm64/include/asm/pci.h | 6 + arch/arm64/include/asm/topology.h | 2 + arch/arm64/kernel/pci.c | 28 +++++ arch/arm64/kernel/setup.c | 7 +- arch/arm64/kernel/topology.c | 14 +++ arch/ia64/Kconfig | 2 + arch/ia64/include/asm/acpi.h | 5 + arch/x86/Kconfig | 2 + arch/x86/include/asm/acpi.h | 5 + drivers/acpi/Kconfig | 19 +++- drivers/acpi/Makefile | 3 + drivers/acpi/acpi_processor.c | 2 +- drivers/acpi/internal.h | 5 + drivers/acpi/osl.c | 4 +- drivers/acpi/plat/Makefile | 1 + drivers/acpi/plat/arm-core.c | 138 +++++++++++++++++++++++ drivers/acpi/processor_core.c | 198 --------------------------------- drivers/acpi/processor_pdc.c | 206 +++++++++++++++++++++++++++++++++++ 23 files changed, 539 insertions(+), 204 deletions(-) create mode 100644 arch/arm64/include/asm/acenv.h create mode 100644 arch/arm64/include/asm/acpi.h create mode 100644 arch/arm64/include/asm/cpu.h create mode 100644 drivers/acpi/plat/Makefile create mode 100644 drivers/acpi/plat/arm-core.c create mode 100644 drivers/acpi/processor_pdc.c -- 1.7.9.5

11 years, 1 month

5
23
0 0

[RFC v2 0/3] ACPI Platform Communication Channel driver

by Ashwin Chaugule

Hello, This patchset adds initial support for the PCC (Platform Communication Channel) interface as described in the current ACPI 5.0a spec. See Section 14 of the ACPI spec - http://acpi.info/DOWNLOADS/ACPI_5_Errata%20A.pdf for more details on how PCC works. In brief PCC (Platform Communication Channel) is a generic means for PCC clients, to talk to the firmware. The PCC register space is typically memory mapped IO and uses a doorbell mechanism to communicate synchronously from the OS to the firmware. The PCC driver is completely agnostic to the protocol implemented by the PCC clients. It only implements the enumeration of PCC channels and the low level transport mechanism and leaves the rest to the PCC clients. The PCC is meant to be useable in the future by clients such as CPPC (Collaborative Processor Performance Control), RAS (Reliability, Availability and Serviceability) and MPST (Memory Power State Tables) and possibly others. While the PCC clients will come as following patches whenever they're ready, I wanted to get feedback on this common driver and hope that it could be merged upstream. This should hopefully help various folks that are working on drivers that rely on the PCC interface. Cheers, Ashwin === Testing Methodology === The PCC test driver in [2/2] is a simple driver that was used to demonstrate how PCC clients would use the PCC driver. The PCC driver was tested by sending multiple PCC READS and PCC WRITES across a shared memory region on an MSM ARMv7 platform. This memory is shared between an apps processor and a power controller processor. So, one end of the PCC channel is the PCC test driver running on the apps processor and the other end is a debugger script (running on a JTAG debugger) thats attached to the power processor. The debugger script is busy looping on the doorbell address waiting for a bit to flip. This bit indicates a synchronous communication from the apps processor. The doorbell is rung when the OS sends a PCC READ or PCC WRITE command. The PCC communication channel is simply a few fake 32 bit registers that are incremented by the OS and the debugger script. The OS increments the registers and then sends the PCC WRITE command. On a PCC READ, the script increments these registers and then OS reads them back. The values are always incremented by 1 by either end, so we know what value to expect for each PCC READ/WRITE. === Changelog === Changes since V1: - Integration with Mailbox framework - https://lkml.org/lkml/2014/5/15/49 Ashwin Chaugule (3): Mailbox: Add support for ACPI ACPI: Add support for Platform Communication Channel PCC test driver drivers/acpi/Makefile | 2 +- drivers/acpi/pcc-test.c | 208 ++++++++++++++++++++++++++++++++++ drivers/acpi/pcc.c | 225 +++++++++++++++++++++++++++++++++++++ drivers/mailbox/Kconfig | 11 ++ drivers/mailbox/mailbox.c | 155 ++++++++++++++++--------- include/linux/mailbox_client.h | 3 + include/linux/mailbox_controller.h | 6 + 7 files changed, 557 insertions(+), 53 deletions(-) create mode 100644 drivers/acpi/pcc-test.c create mode 100644 drivers/acpi/pcc.c -- 1.8.3.2

11 years, 1 month

2
21
0 0

[PATCH v3 0/5] APEI: Make APEI architecture independent.

by Tomasz Nowicki

APEI is currently implemented so that it depends on x86 hardware. The primary dependency is that GHES uses the x86 NMI for hardware error notification and MCE for memory error handling. These patches remove that dependency. Other APEI features such as error reporting via external IRQ, error serialization, or error injection, do not require changes to use them on non-x86 architectures. The following patch set eliminates the APEI Kconfig x86 dependency by making these changes: - treat NMI notification as GHES feature - ARCH_HAS_ACPI_APEI_NMI - reorganize GHES notification type init/deinitialization so that we can decide in run time whether NMI is supported or not - identify architectural boxes and abstract it accordingly (NMI and MCE) - rework ioremap for both IRQ and NMI context NMI code is kept in ghes.c file since NMI and IRQ context are tightly coupled. Note, these patches introduce no functional changes for x86. The NMI notification feature is hard selected for x86. Architectures that want to use this feature should also provide NMI code infrastructure. V1->V2 - address Borislav's comment - abstract arch-specific calls instead of wrapping into the #ifdef V2->V3 - address Robert's comment - disable ACPI_APEI_NMI selection so that it is hard selected by arch Kconfig - rename ACPI_APEI_NMI to ARCH_HAS_ACPI_APEI_NMI Tomasz Nowicki (5): apei, mce: Factor out APEI architecture specific MCE calls. acpi, apei, ghes: Introduce ARCH_HAS_ACPI_APEI_NMI to make NMI error notification a GHES feature. acpi, apei, ghes: Introduce more generic mechanism to init/deinit GHES error notifications. apei, ghes, nmi: Factor out NMI arch-specific calls. acpi, apei, ghes: Factor out ioremap virtual memory for IRQ and NMI context. arch/x86/Kconfig | 1 + arch/x86/kernel/acpi/Makefile | 1 + arch/x86/kernel/acpi/apei.c | 87 ++++++++++++ drivers/acpi/apei/Kconfig | 8 +- drivers/acpi/apei/apei-base.c | 32 +++++ drivers/acpi/apei/ghes.c | 301 +++++++++++++++++++++++++---------------- drivers/acpi/apei/hest.c | 29 +--- include/acpi/apei.h | 11 ++ 8 files changed, 327 insertions(+), 143 deletions(-) create mode 100644 arch/x86/kernel/acpi/apei.c -- 1.7.9.5

11 years, 1 month

3
18
0 0

leg-kernel tag leg-20140614.0 released

by Graeme Gregory

The leg-kernel release has been made and tagged as leg-20140614.0 This is based on mainline kernel v3.15 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: https://git.linaro.org/leg/acpi/leg-kernel.git/commit/380fd57c0626a74594446… Notes :-

11 years, 2 months

1
0
0 0

[PATCH v2 0/5] APEI: Make APEI architecture independent.

by Tomasz Nowicki

APEI is currently implemented so that it depends on x86 hardware. The primary dependency is that GHES uses the x86 NMI for hardware error notification and MCE for memory error handling. These patches remove that dependency. Other APEI features such as error reporting via external IRQ, error serialization, or error injection, do not require changes to use them on non-x86 architectures. The following patch set eliminates the APEI Kconfig x86 dependency by making these changes: - treat NMI notification as GHES feature - CONFIG_ACPI_APEI_NMI - reorganize GHES notification type init/deinitialization so that we can decide in run time whether NMI is supported or not - identify architectural boxes and abstract it accordingly (NMI and MCE) - rework ioremap for both IRQ and NMI context NMI code is kept in ghes.c file since NMI and IRQ context are tightly coupled. Note, these patches introduce no functional changes for x86. The NMI notification feature is selected for x86 by default. Architectures that want to use this feature should also provide NMI code infrastructure. V1->V2 - address Borislav comment - abstract arch-specific calls instead of wrapping into the #ifdef Tomasz Nowicki (5): apei, mce: Factor out APEI architecture specific MCE calls. acpi, apei, ghes: Introduce ACPI_APEI_NMI to make NMI error notification a GHES feature. acpi, apei, ghes: Introduce more generic mechanism to init/deinit GHES error notifications. apei, ghes, nmi: Factor out NMI arch-specific calls. acpi, apei, ghes: Factor out ioremap virtual memory for IRQ and NMI context. arch/x86/kernel/acpi/Makefile | 1 + arch/x86/kernel/acpi/apei.c | 87 ++++++++++++ drivers/acpi/apei/Kconfig | 10 +- drivers/acpi/apei/apei-base.c | 32 +++++ drivers/acpi/apei/ghes.c | 301 +++++++++++++++++++++++++---------------- drivers/acpi/apei/hest.c | 26 +--- include/acpi/apei.h | 11 ++ 7 files changed, 328 insertions(+), 140 deletions(-) create mode 100644 arch/x86/kernel/acpi/apei.c -- 1.7.9.5

11 years, 2 months

2
10
0 0

[RFC PATCH 0/3] ACPI: Add vexpress-sysreg

by naresh.bhat＠linaro.org

From: Naresh Bhat <naresh.bhat(a)linaro.org> Add vexpress sysreg probe support, platform ID and remove dts binding. Logs on the v8 model are as below root@genericarmv8:/sys# find . -name LINA0009* ./bus/acpi/devices/LINA0009:00 ./bus/platform/devices/LINA0009:00 ./bus/platform/drivers/vexpress-sysreg/LINA0009:00 ./devices/platform/LINA0009:00 ./devices/LNXSYSTM:00/device:00/ACPI0004:01/ACPI0004:02/LINA0009:00 root@genericarmv8:/sys# Naresh Bhat (3): v2m_sysreg: Add ACPI probing for SYSREG ACPI: Add vexpress sysreg platform ID arm64: dts: remove the vexpress-sysreg binding arch/arm64/boot/dts/foundation-v8-acpi.dts | 6 +++--- drivers/acpi/acpi_platform.c | 3 ++- drivers/mfd/vexpress-sysreg.c | 9 +++++++++ 3 files changed, 14 insertions(+), 4 deletions(-) -- 1.7.9.5

11 years, 2 months

5
7
0 0

[PATCH] acpi: arm64 does not have a BIOS add config for BIOS table scan.

by Graeme Gregory

With the addition of ARM64 that does not have a traditional BIOS to scan add a config option which is selected on x86 and ia64 to do the traditional BIOS scanning for tables. Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org> --- arch/ia64/Kconfig | 1 + arch/x86/Kconfig | 1 + drivers/acpi/Kconfig | 3 +++ drivers/acpi/osl.c | 4 +++- 4 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index 12c3afe..42a210f6 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig @@ -46,6 +46,7 @@ config IA64 select MODULES_USE_ELF_RELA select ARCH_USE_CMPXCHG_LOCKREF select HAVE_ARCH_AUDITSYSCALL + select ACPI_SCAN_BIOS_NOT_EFI default y help The Itanium Processor Family is Intel's 64-bit successor to diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 25d2c6f..d89c6060 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -130,6 +130,7 @@ config X86 select HAVE_CC_STACKPROTECTOR select GENERIC_CPU_AUTOPROBE select HAVE_ARCH_AUDITSYSCALL + select ACPI_SCAN_BIOS_NOT_EFI config INSTRUCTION_DECODER def_bool y diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index d726e17..1550ea8 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -40,6 +40,9 @@ menuconfig ACPI <http://www.acpi.info> <http://www.uefi.org/acpi/specs> +config ACPI_SCAN_BIOS_NOT_EFI + bool + if ACPI config ACPI_SLEEP diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c index 147bc1b..54f8247 100644 --- a/drivers/acpi/osl.c +++ b/drivers/acpi/osl.c @@ -258,12 +258,14 @@ acpi_physical_address __init acpi_os_get_root_pointer(void) "System description tables not found\n"); return 0; } - } else { + } else if (IS_ENABLED(CONFIG_ACPI_SCAN_BIOS_NOT_EFI)) { acpi_physical_address pa = 0; acpi_find_root_pointer(&pa); return pa; } + + return 0; } /* Must be called with 'acpi_ioremap_lock' or RCU read lock held. */ -- 2.0.0

11 years, 2 months

3
3
0 0

leg-kernel tag leg-20140603.0 released

by Graeme Gregory

The leg-kernel release has been made and tagged as leg-20140603.0 This is based on mainline kernel v3.15-rc8 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: http://git.linaro.org/leg/acpi/leg-kernel.git/commit/379f632a429b7d9768efd0… Notes :- This release contains the PCC driver written by Ashwin Chaugule for testing.

11 years, 2 months

1
0
0 0

[RFC 0/2] Experimental support for PCC and CPPC

by Ashwin Chaugule

This series contains experimental patchwork for PCC and CPPC as defined in the current ACPI5.0a spec. The PCC patch was tested on an ARMv7 platform and on a hacked up PCC emulator. The CPPC part is only compile tested. Both are very much a WIP. Any feedback and help with testing would be highly appreciated! Ashwin Chaugule (2): ACPI: Add support for Platform Communication Channel CPPC: Initial support for Collaborative Processor Performance Control arch/arm64/Kconfig | 2 + drivers/acpi/Kconfig | 10 ++ drivers/acpi/Makefile | 2 +- drivers/acpi/pcc.c | 209 +++++++++++++++++++++++++++++ drivers/cpufreq/Kconfig | 11 +- drivers/cpufreq/Makefile | 1 + drivers/cpufreq/cppc-cpufreq.c | 298 +++++++++++++++++++++++++++++++++++++++++ 7 files changed, 531 insertions(+), 2 deletions(-) create mode 100644 drivers/acpi/pcc.c create mode 100644 drivers/cpufreq/cppc-cpufreq.c -- 1.8.3.2

11 years, 2 months

3
6
0 0

[RFC 0/2] ACPI Platform Communication Channel driver

by Ashwin Chaugule

Hello, This patchset adds initial support for the PCC (Platform Communication Channel) interface as described in the current ACPI 5.0a spec. See Section 14 of the ACPI spec - http://acpi.info/DOWNLOADS/ACPI_5_Errata%20A.pdf for more details on how PCC works. In brief PCC (Platform Communication Channel) is a generic means for PCC clients, to talk to the firmware. The PCC register space is typically memory mapped IO and uses a doorbell mechanism to communicate synchronously from the OS to the firmware. The PCC driver is completely agnostic to the protocol implemented by the PCC clients. It only implements the enumeration of PCC channels and the low level transport mechanism and leaves the rest to the PCC clients. The PCC is meant to be useable in the future by clients such as CPPC (Collaborative Processor Performance Control), RAS (Reliability, Availability and Serviceability) and MPST (Memory Power State Tables) and possibly others. While the PCC clients will come as following patches whenever they're ready, I wanted to get feedback on this common driver and hope that it could be merged upstream. This should hopefully help various folks that are working on drivers that rely on the PCC interface. Cheers, Ashwin === Testing Methodology === The PCC test driver in [2/2] is a simple driver that was used to demonstrate how PCC clients would use the PCC driver. The PCC driver was tested by sending multiple PCC READS and PCC WRITES across a shared memory region on an MSM ARMv7 platform. This memory is shared between an apps processor and a power controller processor. So, one end of the PCC channel is the PCC test driver running on the apps processor and the other end is a debugger script (running on a JTAG debugger) thats attached to the power processor. The debugger script is busy looping on the doorbell address waiting for a bit to flip. This bit indicates a synchronous communication from the apps processor. The doorbell is rung when the OS sends a PCC READ or PCC WRITE command. The PCC communication channel is simply a few fake 32 bit registers that are incremented by the OS and the debugger script. The OS increments the registers and then sends the PCC WRITE command. On a PCC READ, the script increments these registers and then OS reads them back. The values are always incremented by 1 by either end, so we know what value to expect for each PCC READ/WRITE. Ashwin Chaugule (2): ACPI: Add support for Platform Communication Channel PCC Test driver drivers/acpi/Kconfig | 10 +++ drivers/acpi/Makefile | 2 +- drivers/acpi/pcc-test.c | 172 +++++++++++++++++++++++++++++++++++++++++++ drivers/acpi/pcc.c | 192 ++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 375 insertions(+), 1 deletion(-) create mode 100644 drivers/acpi/pcc-test.c create mode 100644 drivers/acpi/pcc.c -- 1.8.3.2

11 years, 2 months

4
7
0 0

[PATCH] PCI: Turn pcibios_penalize_isa_irq() into __weak function

by Hanjun Guo

pcibios_penalize_isa_irq() is only useful for x86 now, and legacy ISA is not used by some architectures, so make pcibios_penalize_isa_irq() as __weak function to simplify the code, this will prevent new platform from introducing dummy stub function for pcibios_penalize_isa_irq() too. Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org> --- arch/alpha/include/asm/pci.h | 5 ----- arch/arm/include/asm/pci.h | 5 ----- arch/blackfin/include/asm/pci.h | 5 ----- arch/cris/include/asm/pci.h | 1 - arch/frv/include/asm/pci.h | 2 -- arch/frv/mb93090-mb00/pci-irq.c | 4 ---- arch/ia64/include/asm/pci.h | 6 ------ arch/microblaze/include/asm/pci.h | 5 ----- arch/mips/include/asm/pci.h | 5 ----- arch/mn10300/include/asm/pci.h | 1 - arch/mn10300/unit-asb2305/pci-irq.c | 4 ---- arch/parisc/include/asm/pci.h | 5 ----- arch/powerpc/include/asm/pci.h | 5 ----- arch/sh/include/asm/pci.h | 5 ----- arch/sparc/include/asm/pci_32.h | 5 ----- arch/sparc/include/asm/pci_64.h | 5 ----- arch/unicore32/include/asm/pci.h | 5 ----- arch/x86/include/asm/pci.h | 1 - arch/xtensa/include/asm/pci.h | 5 ----- drivers/pci/pci.c | 11 +++++++++++ include/linux/pci.h | 1 + 21 files changed, 12 insertions(+), 79 deletions(-) diff --git a/arch/alpha/include/asm/pci.h b/arch/alpha/include/asm/pci.h index d01afb7..f7f680f 100644 --- a/arch/alpha/include/asm/pci.h +++ b/arch/alpha/include/asm/pci.h @@ -59,11 +59,6 @@ struct pci_controller { extern void pcibios_set_master(struct pci_dev *dev); -extern inline void pcibios_penalize_isa_irq(int irq, int active) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - /* IOMMU controls. */ /* The PCI address space does not equal the physical memory address space. diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h index 680a83e..7e95d85 100644 --- a/arch/arm/include/asm/pci.h +++ b/arch/arm/include/asm/pci.h @@ -31,11 +31,6 @@ static inline int pci_proc_domain(struct pci_bus *bus) } #endif /* CONFIG_PCI_DOMAINS */ -static inline void pcibios_penalize_isa_irq(int irq, int active) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - /* * The PCI address space does equal the physical memory address space. * The networking and block device layers use this boolean for bounce diff --git a/arch/blackfin/include/asm/pci.h b/arch/blackfin/include/asm/pci.h index 74352c4..c737909 100644 --- a/arch/blackfin/include/asm/pci.h +++ b/arch/blackfin/include/asm/pci.h @@ -10,9 +10,4 @@ #define PCIBIOS_MIN_IO 0x00001000 #define PCIBIOS_MIN_MEM 0x10000000 -static inline void pcibios_penalize_isa_irq(int irq) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - #endif /* _ASM_BFIN_PCI_H */ diff --git a/arch/cris/include/asm/pci.h b/arch/cris/include/asm/pci.h index f666734..cc2399c 100644 --- a/arch/cris/include/asm/pci.h +++ b/arch/cris/include/asm/pci.h @@ -20,7 +20,6 @@ void pcibios_config_init(void); struct pci_bus * pcibios_scan_root(int bus); void pcibios_set_master(struct pci_dev *dev); -void pcibios_penalize_isa_irq(int irq); struct irq_routing_table *pcibios_get_irq_routing_table(void); int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq); diff --git a/arch/frv/include/asm/pci.h b/arch/frv/include/asm/pci.h index ef03baf..2035a4d 100644 --- a/arch/frv/include/asm/pci.h +++ b/arch/frv/include/asm/pci.h @@ -24,8 +24,6 @@ struct pci_dev; extern void pcibios_set_master(struct pci_dev *dev); -extern void pcibios_penalize_isa_irq(int irq); - #ifdef CONFIG_MMU extern void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *dma_handle); extern void consistent_free(void *vaddr); diff --git a/arch/frv/mb93090-mb00/pci-irq.c b/arch/frv/mb93090-mb00/pci-irq.c index c677b9d..1c35c93 100644 --- a/arch/frv/mb93090-mb00/pci-irq.c +++ b/arch/frv/mb93090-mb00/pci-irq.c @@ -55,10 +55,6 @@ void __init pcibios_fixup_irqs(void) } } -void __init pcibios_penalize_isa_irq(int irq) -{ -} - void pcibios_enable_irq(struct pci_dev *dev) { pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); diff --git a/arch/ia64/include/asm/pci.h b/arch/ia64/include/asm/pci.h index 7d41cc0..52af5ed 100644 --- a/arch/ia64/include/asm/pci.h +++ b/arch/ia64/include/asm/pci.h @@ -50,12 +50,6 @@ struct pci_dev; extern unsigned long ia64_max_iommu_merge_mask; #define PCI_DMA_BUS_IS_PHYS (ia64_max_iommu_merge_mask == ~0UL) -static inline void -pcibios_penalize_isa_irq (int irq, int active) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - #include <asm-generic/pci-dma-compat.h> #ifdef CONFIG_PCI diff --git a/arch/microblaze/include/asm/pci.h b/arch/microblaze/include/asm/pci.h index 935f9be..3355240 100644 --- a/arch/microblaze/include/asm/pci.h +++ b/arch/microblaze/include/asm/pci.h @@ -44,11 +44,6 @@ struct pci_dev; */ #define pcibios_assign_all_busses() 0 -static inline void pcibios_penalize_isa_irq(int irq, int active) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - #ifdef CONFIG_PCI extern void set_pci_dma_ops(struct dma_map_ops *dma_ops); extern struct dma_map_ops *get_pci_dma_ops(void); diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index 12d6842..974b0e3 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h @@ -73,11 +73,6 @@ extern unsigned long PCIBIOS_MIN_MEM; extern void pcibios_set_master(struct pci_dev *dev); -static inline void pcibios_penalize_isa_irq(int irq, int active) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - #define HAVE_PCI_MMAP extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, diff --git a/arch/mn10300/include/asm/pci.h b/arch/mn10300/include/asm/pci.h index 1663238..5f70af2 100644 --- a/arch/mn10300/include/asm/pci.h +++ b/arch/mn10300/include/asm/pci.h @@ -48,7 +48,6 @@ extern void unit_pci_init(void); #define PCIBIOS_MIN_MEM 0xB8000000 void pcibios_set_master(struct pci_dev *dev); -void pcibios_penalize_isa_irq(int irq); /* Dynamic DMA mapping stuff. * i386 has everything mapped statically. diff --git a/arch/mn10300/unit-asb2305/pci-irq.c b/arch/mn10300/unit-asb2305/pci-irq.c index 77439da..fcb28ce 100644 --- a/arch/mn10300/unit-asb2305/pci-irq.c +++ b/arch/mn10300/unit-asb2305/pci-irq.c @@ -40,10 +40,6 @@ void __init pcibios_fixup_irqs(void) } } -void __init pcibios_penalize_isa_irq(int irq) -{ -} - void pcibios_enable_irq(struct pci_dev *dev) { pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); diff --git a/arch/parisc/include/asm/pci.h b/arch/parisc/include/asm/pci.h index 4651540..20df2b0 100644 --- a/arch/parisc/include/asm/pci.h +++ b/arch/parisc/include/asm/pci.h @@ -215,11 +215,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, } #endif -static inline void pcibios_penalize_isa_irq(int irq, int active) -{ - /* We don't need to penalize isa irq's */ -} - static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) { return channel ? 15 : 14; diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h index 95145a1..1b0739b 100644 --- a/arch/powerpc/include/asm/pci.h +++ b/arch/powerpc/include/asm/pci.h @@ -46,11 +46,6 @@ struct pci_dev; #define pcibios_assign_all_busses() \ (pci_has_flag(PCI_REASSIGN_ALL_BUS)) -static inline void pcibios_penalize_isa_irq(int irq, int active) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - #define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) { diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h index bff96c2..5b45115 100644 --- a/arch/sh/include/asm/pci.h +++ b/arch/sh/include/asm/pci.h @@ -70,11 +70,6 @@ extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, enum pci_mmap_state mmap_state, int write_combine); extern void pcibios_set_master(struct pci_dev *dev); -static inline void pcibios_penalize_isa_irq(int irq, int active) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - /* Dynamic DMA mapping stuff. * SuperH has everything mapped statically like x86. */ diff --git a/arch/sparc/include/asm/pci_32.h b/arch/sparc/include/asm/pci_32.h index dc50329..53e9b49 100644 --- a/arch/sparc/include/asm/pci_32.h +++ b/arch/sparc/include/asm/pci_32.h @@ -16,11 +16,6 @@ #define PCI_IRQ_NONE 0xffffffff -static inline void pcibios_penalize_isa_irq(int irq, int active) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - /* Dynamic DMA mapping stuff. */ #define PCI_DMA_BUS_IS_PHYS (0) diff --git a/arch/sparc/include/asm/pci_64.h b/arch/sparc/include/asm/pci_64.h index 1633b71..c6c7396 100644 --- a/arch/sparc/include/asm/pci_64.h +++ b/arch/sparc/include/asm/pci_64.h @@ -16,11 +16,6 @@ #define PCI_IRQ_NONE 0xffffffff -static inline void pcibios_penalize_isa_irq(int irq, int active) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - /* The PCI address space does not equal the physical memory * address space. The networking and block device layers use * this boolean for bounce buffer decisions. diff --git a/arch/unicore32/include/asm/pci.h b/arch/unicore32/include/asm/pci.h index f5e108f..654407e 100644 --- a/arch/unicore32/include/asm/pci.h +++ b/arch/unicore32/include/asm/pci.h @@ -18,11 +18,6 @@ #include <asm-generic/pci.h> #include <mach/hardware.h> /* for PCIBIOS_MIN_* */ -static inline void pcibios_penalize_isa_irq(int irq, int active) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - #ifdef CONFIG_PCI static inline void pci_dma_burst_advice(struct pci_dev *pdev, enum pci_dma_burst_strategy *strat, diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index 96ae4f4..0892ea0 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -68,7 +68,6 @@ void pcibios_config_init(void); void pcibios_scan_root(int bus); void pcibios_set_master(struct pci_dev *dev); -void pcibios_penalize_isa_irq(int irq, int active); struct irq_routing_table *pcibios_get_irq_routing_table(void); int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq); diff --git a/arch/xtensa/include/asm/pci.h b/arch/xtensa/include/asm/pci.h index 614be03..5d52dc4 100644 --- a/arch/xtensa/include/asm/pci.h +++ b/arch/xtensa/include/asm/pci.h @@ -22,11 +22,6 @@ extern struct pci_controller* pcibios_alloc_controller(void); -static inline void pcibios_penalize_isa_irq(int irq) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - /* Assume some values. (We should revise them, if necessary) */ #define PCIBIOS_MIN_IO 0x2000 diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 7325d43..57c330f 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1468,6 +1468,17 @@ void __weak pcibios_release_device(struct pci_dev *dev) {} */ void __weak pcibios_disable_device (struct pci_dev *dev) {} +/** + * pcibios_penalize_isa_irq - provide arch specific hooks when penalize isa irq + * @irq: isa irq to penalize + * @active: irq active or not + * + * Permits the platform to provide architecture specific functionality when + * penalize isa irq. This is the default implementation. Architecture + * implementations can override this. + */ +void __weak pcibios_penalize_isa_irq(int irq, int active) {} + static void do_pci_disable_device(struct pci_dev *dev) { u16 pci_command; diff --git a/include/linux/pci.h b/include/linux/pci.h index aab57b4..da8f7d5 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1579,6 +1579,7 @@ int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); int pcibios_add_device(struct pci_dev *dev); void pcibios_release_device(struct pci_dev *dev); +void pcibios_penalize_isa_irq(int irq, int active); #ifdef CONFIG_HIBERNATE_CALLBACKS extern struct dev_pm_ops pcibios_pm_ops; -- 1.7.9.5

11 years, 2 months

3
3
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[PATCH 0/7] APEI: Make APEI architecture independent.

by Tomasz Nowicki

APEI is currently implemented so that it depends on x86 hardware. The primary dependency is that GHES uses the x86 NMI for hardware error notification. These patches remove that dependency. Other APEI features such as error reporting via external IRQ, error serialization, or error injection, do not require changes to use them on non-x86 architectures. The following patch set eliminates the APEI Kconfig x86 dependency by making these changes: - replace arch specific calls with more generic one - treat NMI notification as GHES feature - CONFIG_ACPI_APEI_NMI - isolate NMI related code - reorganize function logic NMI code is kept in ghes.c file since NMI and IRQ context are tightly coupled. Note, these patches introduce no functional changes for x86. The NMI notification feature is selected for x86 by default. Architectures that want to use this feature should also provide NMI code infrastructure. Tomasz Nowicki (7): apei, mce: Call MCE-specific code only for X86 architecture. acpi, apei, ghes: Introduce more generic mechanism to init/deinit GHES error notifications. ACPI, APEI, GHES: Introduce ACPI_NMI to make NMI error notification a GHES feature. acpi, apei, ghes: Factor out NMI error notification context. acpi, apei, ghes: Attach NMI init/deinit functions while CONFIG_ACPI_NMI is enabled. acpi, apei, ghes: Make unmapping functionality independent from architecture. acpi, apei, ghes: Factor out ioremap virtual memory for IRQ and NMI context. drivers/acpi/apei/Kconfig | 10 +- drivers/acpi/apei/ghes.c | 329 ++++++++++++++++++++++++++++----------------- drivers/acpi/apei/hest.c | 8 +- 3 files changed, 218 insertions(+), 129 deletions(-) -- 1.7.9.5

11 years, 2 months

4
32
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[GIT PULL] PSCI v0.2 support and DT bindings

by Ashwin Chaugule

Hi Christoffer, Marc Please pull in the ARM and ARM64 PSCIv0.2 patchwork from the git branch below. These patches have been under review on LKAML since early March and are now ACK'd. Also, since these patches are dependent on the UAPI header file (uapi/linux/psci.h) added by the KVM PSCIv0.2 patchwork, it makes sense to submit the whole PSCIv0.2 patchwork (KVM and core) as one set. Cheers, Ashwin The following changes since commit 4447a208f7fc2e2dff8c6a8df2a1fd6dd72fb3e2: ARM/ARM64: KVM: Advertise KVM_CAP_ARM_PSCI_0_2 to user space (2014-04-30 04:18:58 -0700) are available in the git repository at: git://git.linaro.org/people/ashwin.chaugule/leg-kernel.git kvm-next-psci-v0.2 for you to fetch changes up to c814ca029e1015bb0ecec312f4bb9751ba1a711a: ARM: Check if a CPU has gone offline (2014-05-15 10:16:30 -0400) ---------------------------------------------------------------- Ashwin Chaugule (3): PSCI: Add initial support for PSCIv0.2 functions Documentation: devicetree: Add new binding for PSCIv0.2 ARM: Check if a CPU has gone offline Documentation/devicetree/bindings/arm/psci.txt | 37 +++- arch/arm/include/asm/psci.h | 7 +- arch/arm/kernel/psci.c | 196 +++++++++++++++++---- arch/arm/kernel/psci_smp.c | 33 ++++ arch/arm64/include/asm/cpu_ops.h | 2 + arch/arm64/include/asm/psci.h | 2 +- arch/arm64/kernel/psci.c | 231 +++++++++++++++++++++---- arch/arm64/kernel/smp.c | 22 +++ 8 files changed, 452 insertions(+), 78 deletions(-)

11 years, 2 months

3
2
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[PATCH v10 0/3] PSCI v0.2 support and DT bindings

by Ashwin Chaugule

This patchset introduces some functions as defined in the PSCI v0.2 spec and a corresponding DT binding to differentiate it from previous PSCI versions. Since PSCIv0.2 has standard function IDs, it is possible to statically assign them rather than depend on values from DT. This patchset depends on the PSCI header (/uapi/linux/psci.h) introduced by http://www.spinics.net/lists/arm-kernel/msg319712.html which is now merged in the ARM KVM tree next branch. Changes in v10: - Documented explicit use of case dual PSCI bindings for hypervisors. - Corrected POWER_STATE macros as per new definitions. - Added arm64 cpu_kill cpu-op and tied it to psci affinity info. - Misc cleanups in prints. Changes in v9: - Rebased on top of KVM "next" - https://git.kernel.org/cgit/linux/kernel/git/kvmarm/kvmarm.git/log/?h=next Changes in v8: - Replace msleep(100) with 10 x msleep(10) Changes in v7: - Add two new functions: SYSTEM_OFF and SYSTEM_RESET as defined in PSCIv0.2. - Added a delay before calling cpu_kill to avoid race with cpu_die. Changes in v6: - rebase on top of uapi/linux/psci.h introduced by Anups patch http://www.spinics.net/lists/arm-kernel/msg319712.html - rebase on top of Catalins tree tip. Changes in v5: - Add uapi/linux/psci.h to kbuild - ret with err if PSCI_ID_VERSION is not implemented. Changes in v4: - Correct copyright banner format. - Check if PSCI Version ID is supported. - Add all PSCI RET codes in uapi header. - Explicitely ret 1 from psci_cpu_kill() Changes in v3: - Roll up common functionality for getting conduit method. - Remove #defines for ARM32 and ARM64 in uapi/linux/psci.h - Remove functions not supported by PSCI v0.1 - Misc cleanups. - Add PSCI_AFFINITY_INFO return types in uapi header. - Changed function names for PSCI v0.1 and PSCI v0.2 - Added copyright info to uapi header. - Fixed args to affinity_info call. - Fix typo in psci_init definition when PSCI is not defined. Changes in v2: - Add AFFINITY_INFO and MIGRATE_INFO_TYPE functions. - Add binding Documentation. - Add function to get PSCI version. - Add common #defines in uapi/linux/psci.h - Implement cpu_kill and check if CPU is dead via AFFINITY_INFO. - Misc cleanups. Changes in v1: - Add new binding "arm, psci-0.2" - Separate conduit and PSCI function assignment methods. Ashwin Chaugule (3): PSCI: Add initial support for PSCIv0.2 functions Documentation: devicetree: Add new binding for PSCIv0.2 ARM: Check if a CPU has gone offline Documentation/devicetree/bindings/arm/psci.txt | 37 +++- arch/arm/include/asm/psci.h | 7 +- arch/arm/kernel/psci.c | 196 +++++++++++++++++---- arch/arm/kernel/psci_smp.c | 33 ++++ arch/arm64/include/asm/cpu_ops.h | 2 + arch/arm64/include/asm/psci.h | 2 +- arch/arm64/kernel/psci.c | 231 +++++++++++++++++++++---- arch/arm64/kernel/smp.c | 22 +++ 8 files changed, 452 insertions(+), 78 deletions(-) -- 1.8.3.2

11 years, 3 months

2
6
0 0

[PATCH v9 0/3] PSCI v0.2 support and DT bindings

by Ashwin Chaugule

This patchset introduces some functions as defined in the PSCI v0.2 spec and a corresponding DT binding to differentiate it from previous PSCI versions. Since PSCIv0.2 has standard function IDs, it is possible to statically assign them rather than depend on values from DT. This patchset depends on the PSCI header (/uapi/linux/psci.h) introduced by http://www.spinics.net/lists/arm-kernel/msg319712.html which is now merged in the ARM KVM tree next branch. Changes in v9: - Rebased on top of KVM "next" - https://git.kernel.org/cgit/linux/kernel/git/kvmarm/kvmarm.git/log/?h=next Changes in v8: - Replace msleep(100) with 10 x msleep(10) Changes in v7: - Add two new functions: SYSTEM_OFF and SYSTEM_RESET as defined in PSCIv0.2. - Added a delay before calling cpu_kill to avoid race with cpu_die. Changes in v6: - rebase on top of uapi/linux/psci.h introduced by Anups patch http://www.spinics.net/lists/arm-kernel/msg319712.html - rebase on top of Catalins tree tip. Changes in v5: - Add uapi/linux/psci.h to kbuild - ret with err if PSCI_ID_VERSION is not implemented. Changes in v4: - Correct copyright banner format. - Check if PSCI Version ID is supported. - Add all PSCI RET codes in uapi header. - Explicitely ret 1 from psci_cpu_kill() Changes in v3: - Roll up common functionality for getting conduit method. - Remove #defines for ARM32 and ARM64 in uapi/linux/psci.h - Remove functions not supported by PSCI v0.1 - Misc cleanups. - Add PSCI_AFFINITY_INFO return types in uapi header. - Changed function names for PSCI v0.1 and PSCI v0.2 - Added copyright info to uapi header. - Fixed args to affinity_info call. - Fix typo in psci_init definition when PSCI is not defined. Changes in v2: - Add AFFINITY_INFO and MIGRATE_INFO_TYPE functions. - Add binding Documentation. - Add function to get PSCI version. - Add common #defines in uapi/linux/psci.h - Implement cpu_kill and check if CPU is dead via AFFINITY_INFO. - Misc cleanups. Changes in v1: - Add new binding "arm, psci-0.2" - Separate conduit and PSCI function assignment methods. Ashwin Chaugule (3): PSCI: Add initial support for PSCIv0.2 functions Documentation: devicetree: Add new binding for PSCIv0.2 ARM: Check if a CPU has gone offline Documentation/devicetree/bindings/arm/psci.txt | 35 ++++- arch/arm/include/asm/psci.h | 7 +- arch/arm/kernel/psci.c | 196 +++++++++++++++++++----- arch/arm/kernel/psci_smp.c | 31 ++++ arch/arm64/include/asm/psci.h | 2 +- arch/arm64/kernel/psci.c | 200 ++++++++++++++++++++----- 6 files changed, 393 insertions(+), 78 deletions(-) -- 1.8.3.2

11 years, 3 months

4
13
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leg-kernel tag leg-20140430.0 released

by Graeme Gregory

The leg-kernel release has been made and tagged as leg-20140430.0 This is based on mainline kernel v3.15-rc3 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: https://git.linaro.org/leg/acpi/leg-kernel.git/commit/0a612ef9e654e1a94f65a… Notes :-

11 years, 3 months

3
4
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leg-kernel tag leg-20140513.0 released

by Graeme Gregory

The leg-kernel release has been made and tagged as leg-20140513.0 This is based on mainline kernel v3.15-rc5 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: https://git.linaro.org/leg/acpi/leg-kernel.git/commit/4bfbe91b10e1d6438cdf7… Notes :-

11 years, 3 months

1
0
0 0

Re: [Linaro-acpi] [RFC 2/2] CPPC: Initial support for Collaborative Processor Performance Control

by Jonghwan Choi

Does it need a hardware change for using CPPC? > +static int cppc_cpufreq_target(struct cpufreq_policy *policy, > + unsigned int target_freq, > + unsigned int relation) > +{ > + unsigned int cpu = policy->cpu; > + struct cpc_desc *current_cpu_cpc = per_cpu(cpc_desc, cpu); > + struct cpufreq_freqs freqs; > + u16 status; > + > + freqs.old = policy->cur; > + freqs.new = target_freq; > + > + cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE); > + > + /* Set CPU Perf thresholds and current desired perf value. */ > + acpi_write(policy->max, &current_cpu_cpc->pcc_regs[MAX_PERF]); > + > + acpi_write(policy->min, &current_cpu_cpc->pcc_regs[MIN_PERF]); > + > + acpi_write(target_freq, &current_cpu_cpc->pcc_regs[DESIRED_PERF]); > + > + status = send_pcc_cmd(CMD_WRITE, 0, PCC_SUBSPACE_IDX, > comm_base_addr); > + if (status & CMD_COMPLETE) { > + pr_debug("Failed to set target CPU perf for CPU:%d, > status:%d\n", > + cpu, status); > + return -EINVAL; > + } > + > + return 0; > +} -> Don't need cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE)? > + /* Base address returned from PCC subspace desc needs to ioremap'd. > + * Used by the client to send/recv data from platform. > + */ > + comm_base_addr = ioremap_nocache(pcc_comm_base_addr, len); > + > + if (comm_base_addr) { ->Should be if (!comm_base_addr) ? > + pr_err("Could not map PCC communicate channel\n"); > + ret = -ENOMEM; > + goto out_err; > + } > + Thanks Best Regards.

11 years, 3 months

3
3
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Question about FADT length

by Hanjun Guo

Hi, I ran into some compile errors when I was prototyping the code for the proposals in ASWG, it turns out that some field in FADT is changed and "reserved4[0]" used in ACPI_FADT_V2_SIZE will cause the error. So my question is that the length of very version of FADT is fixed, why not use a constant value for this puspose? Here is the code: /* * Sizes of the various flavors of FADT. We need to look closely * at the FADT length because the version number essentially tells * us nothing because of many BIOS bugs where the version does not * match the expected length. In other words, the length of the * FADT is the bottom line as to what the version really is. * * For reference, the values below are as follows: * FADT V1 size: 0x074 * FADT V2 size: 0x084 * FADT V3 size: 0x0F4 * FADT V4 size: 0x0F4 * FADT V5 size: 0x10C */ #define ACPI_FADT_V1_SIZE (u32) (ACPI_FADT_OFFSET (flags) + 4) #define ACPI_FADT_V2_SIZE (u32) (ACPI_FADT_OFFSET (reserved4[0]) + 3) #define ACPI_FADT_V3_SIZE (u32) (ACPI_FADT_OFFSET (sleep_control)) #define ACPI_FADT_V5_SIZE (u32) (sizeof (struct acpi_table_fadt)) Why not #define ACPI_FADT_V1_SIZE 0x074 ? Did I miss something? any clarify will be appreciated :) Thanks Hanjun

11 years, 3 months

2
3
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[PATCH] ACPI / PCI: Stub out pci_acpi_crs_quirks() and make it x86 specific

by Hanjun Guo

For pci_acpi_crs_quirks(), ia64 already doesn't use it, and we can not foresee it should be used in ARM64, so stub out pci_acpi_crs_quirks() to avoid introducing platform specific dummy stub function. Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org> --- arch/ia64/include/asm/acpi.h | 1 - include/acpi/acpi_drivers.h | 5 +++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/ia64/include/asm/acpi.h b/arch/ia64/include/asm/acpi.h index d651102..97cb160 100644 --- a/arch/ia64/include/asm/acpi.h +++ b/arch/ia64/include/asm/acpi.h @@ -92,7 +92,6 @@ ia64_acpi_release_global_lock (unsigned int *lock) #endif #define acpi_processor_cstate_check(x) (x) /* no idle limits on IA64 :) */ static inline void disable_acpi(void) { } -static inline void pci_acpi_crs_quirks(void) { } #ifdef CONFIG_IA64_GENERIC const char *acpi_get_sysname (void); diff --git a/include/acpi/acpi_drivers.h b/include/acpi/acpi_drivers.h index d504613..ea6428b 100644 --- a/include/acpi/acpi_drivers.h +++ b/include/acpi/acpi_drivers.h @@ -96,7 +96,12 @@ struct pci_dev *acpi_get_pci_dev(acpi_handle); /* Arch-defined function to add a bus to the system */ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root); + +#ifdef CONFIG_X86 void pci_acpi_crs_quirks(void); +#else +static inline void pci_acpi_crs_quirks(void) { } +#endif /* -------------------------------------------------------------------------- Processor -- 1.7.9.5

11 years, 3 months

3
3
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[PATCH v3 part1 00/11] Enable ACPI on ARM64 in Kconfig

by Hanjun Guo

This patch set is the first part of ARM64 ACPI core patches to running ACPI on ARM64, it just handle some compile errors when ACPI is introduced to ARM64 platform and enable ACPI on ARM64 in Kconfig. Following core patch sets for ACPI based SMP/GIC/Arch Timer initialization to enable ACPI on ARM64 are still waited untill some ACPI proposals approved by ASWG. This patch set is based on 3.15-rc2 and PCI patches for ARM64 from Liviu: Support for creating generic host_bridge from device tree https://lkml.org/lkml/2014/3/14/279 Add support for PCI in AArch64 http://comments.gmane.org/gmane.linux.ports.arm.kernel/309392 We did 3 review cycles inside linaro ACPI team, and I had compiled all the patches ok on arm64 with: - CONFIG_ACPI=n and CONFIG_PCI=n; - CONFIG_ACPI=n and CONFIG_PCI=y; - CONFIG_ACPI=y and CONFIG_PCI=y; And compiled ok on x86. Changes since v2: - Make ACPI depend on PCI on ARM64 - rework all the patches and seperate some of the patches into fine-grained, and add some comments and changelog to make it easier for review. Hanjun Guo (11): ACPI / processor: Rework _PDC related stuff to make it more arch-independent ARM64 / ACPI: Introduce the skeleton of _PDC related for ARM64 ARM64 : Add dummy asm/cpu.h ARM64 / ACPI: Introduce arm-core.c and its related head file ARM64 / ACPI: Introduce early_param for "acpi" ARM64 / ACPI: Introduce lowlevel suspend function ARM64 / ACPI: Introduce arch_fix_phys_package_id() for cpu topology ARM64 / ACPI: Introduce PCI functions for ACPI on ARM64 ARM64 / ACPI: Enable ARM64 in Kconfig ARM64 / ACPI: Select ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled on ARM64 ACPI: Make EC depend on X86 || IA64 in Kconfig arch/arm64/Kconfig | 3 + arch/arm64/include/asm/acpi.h | 94 +++++++++++++++++++++++++ arch/arm64/include/asm/cpu.h | 11 +++ arch/arm64/include/asm/pci.h | 11 +++ arch/arm64/include/asm/topology.h | 2 + arch/arm64/kernel/pci.c | 34 +++++++++ arch/arm64/kernel/setup.c | 4 ++ arch/arm64/kernel/topology.c | 14 ++++ arch/ia64/include/asm/acpi.h | 5 +- arch/ia64/kernel/acpi.c | 15 ++++ arch/x86/include/asm/acpi.h | 19 +---- arch/x86/kernel/acpi/cstate.c | 27 ++++++++ drivers/acpi/Kconfig | 6 +- drivers/acpi/Makefile | 2 + drivers/acpi/plat/Makefile | 1 + drivers/acpi/plat/arm-core.c | 138 +++++++++++++++++++++++++++++++++++++ drivers/acpi/processor_core.c | 19 +---- 17 files changed, 363 insertions(+), 42 deletions(-) create mode 100644 arch/arm64/include/asm/acpi.h create mode 100644 arch/arm64/include/asm/cpu.h create mode 100644 drivers/acpi/plat/Makefile create mode 100644 drivers/acpi/plat/arm-core.c -- 1.7.9.5

11 years, 3 months

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[PATCH linaro-acpi] [RFC 7/7] acpi: Allow ACPI_PROCESSOR for ARM64

by Jonghwan Choi

Enable C-State support for ARM64. Signed-off-by: Jonghwan Choi <jhbird.choi(a)samsung.com> --- drivers/acpi/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index ff5c83c..e434a3e 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -143,7 +143,7 @@ config ACPI_PROCESSOR tristate "Processor" select THERMAL select CPU_IDLE - depends on X86 || IA64 + depends on X86 || IA64 || ARM64 default y help This driver installs ACPI as the idle handler for Linux and uses -- 1.7.10.4

11 years, 3 months

1
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[PATCH linaro-acpi] [RFC 6/7] acpi: Add ACPI cpuidle support for ARM

by Jonghwan Choi

To support C-State for arm64, added arch-specific function and FFH(Functional Fixed Hardware) related function. Signed-off-by: Jonghwan Choi <jhbird.choi(a)samsung.com> --- arch/arm64/include/asm/acpi.h | 12 +++++++ arch/arm64/include/asm/irqflags.h | 6 ++++ arch/arm64/include/asm/processor.h | 3 ++ arch/arm64/kernel/Makefile | 4 +++ arch/arm64/kernel/cstate.c | 67 ++++++++++++++++++++++++++++++++++++ arch/arm64/kernel/process.c | 6 ++++ drivers/acpi/processor_idle.c | 14 -------- 7 files changed, 98 insertions(+), 14 deletions(-) create mode 100644 arch/arm64/kernel/cstate.c diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h index dff95da..34e591a 100644 --- a/arch/arm64/include/asm/acpi.h +++ b/arch/arm64/include/asm/acpi.h @@ -92,6 +92,14 @@ extern int arm_cpu_to_apicid[NR_CPUS]; extern int gic_acpi_init(void); extern int cpu_acpi_read_ops(int cpu); +/* + * Check if the CPU can handle C2 and deeper + */ +static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate) +{ + return max_cstate; +} + #else /* !CONFIG_ACPI */ #define acpi_disabled 1 /* ACPI sometimes enabled on ARM */ #define acpi_noirq 1 /* ACPI sometimes enabled on ARM */ @@ -110,4 +118,8 @@ static inline int cpu_acpi_read_ops(int cpu) #endif +#define ARCH_HAS_POWER_INIT 1 + +#define acpi_unlazy_tlb(x) + #endif /*_ASM_ARM64_ACPI_H*/ diff --git a/arch/arm64/include/asm/irqflags.h b/arch/arm64/include/asm/irqflags.h index 11cc941..8ab3bd7 100644 --- a/arch/arm64/include/asm/irqflags.h +++ b/arch/arm64/include/asm/irqflags.h @@ -19,6 +19,7 @@ #ifdef __KERNEL__ #include <asm/ptrace.h> +#include <asm/barrier.h> /* * CPU interrupt mask handling. @@ -113,5 +114,10 @@ static inline int arch_irqs_disabled_flags(unsigned long flags) #define local_dbg_enable() asm("msr daifclr, #8" : : : "memory") #define local_dbg_disable() asm("msr daifset, #8" : : : "memory") +static inline void arch_safe_halt(void) +{ + arch_local_irq_enable(); + wfi(); +} #endif #endif diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index 50ce951..dca0939 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -47,6 +47,9 @@ #define ARCH_LOW_ADDRESS_LIMIT PHYS_MASK #endif /* __KERNEL__ */ +enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, + IDLE_POLL}; + struct debug_info { /* Have we suspended stepping by a debugger? */ int suspended_step; diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index db63a0a..b829268 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -26,6 +26,10 @@ arm64-obj-$(CONFIG_JUMP_LABEL) += jump_label.o arm64-obj-$(CONFIG_KGDB) += kgdb.o arm64-obj-$(CONFIG_EFI) += efi.o efi-stub.o efi-entry.o +ifneq ($(CONFIG_ACPI_PROCESSOR),) +arm64-obj-y += cstate.o +endif + obj-y += $(arm64-obj-y) vdso/ obj-m += $(arm64-obj-m) head-y := head.o diff --git a/arch/arm64/kernel/cstate.c b/arch/arm64/kernel/cstate.c new file mode 100644 index 0000000..00c22cd --- /dev/null +++ b/arch/arm64/kernel/cstate.c @@ -0,0 +1,67 @@ +/* + * Based on arch/x86/kernel/acpi/cstate.c + * + * Copyright (C) 2005 Intel Corporation + * Venkatesh Pallipadi <venkatesh.pallipadi(a)intel.com> + * - Added _PDC for SMP C-states on Intel CPUs + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/acpi.h> +#include <linux/cpu.h> +#include <linux/cpu_pm.h> + +#include <acpi/processor.h> +#include <asm/acpi.h> +#include <asm/cpu.h> +#include <asm/suspend.h> + +/* + * Initialize bm_flags based on the CPU cache properties + * On SMP it depends on cache configuration + * - When cache is not shared among all CPUs, we flush cache + * before entering C3. + * - When cache is shared among all CPUs, we use bm_check + * mechanism as in UP case + * + * This routine is called only after all the CPUs are online + */ +void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags, + unsigned int cpu) +{ + struct cpuinfo_arm *c = &cpu_data(cpu); + + flags->bm_check = 0; + flags->bm_control = 0; + + /* To Do */ +} +EXPORT_SYMBOL(acpi_processor_power_init_bm_check); + +int acpi_processor_ffh_cstate_probe(unsigned int cpu, + struct acpi_processor_cx *cx, struct acpi_power_register *reg) +{ + /* To Do */ + return 0; +} +EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe); + +void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cx) +{ + cpu_pm_enter(); + /* + * Pass idle state index to cpu_suspend which in turn will call + * the CPU ops suspend protocol with idle index as a parameter. + * + * Some states would not require context to be saved and flushed + * to DRAM, so calling cpu_suspend would not be stricly necessary. + * When power domains specifications for ARM CPUs are finalized then + * this code can be optimized to prevent saving registers if not + * needed. + */ + cpu_suspend(cx->type); + + cpu_pm_exit(); +} +EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_enter); diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 6391485..8ce1610 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -94,6 +94,12 @@ void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd); EXPORT_SYMBOL_GPL(arm_pm_restart); /* + * Idle related variables and functions + */ +unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; +EXPORT_SYMBOL(boot_option_idle_override); + +/* * This is our default idle handler. */ void arch_cpu_idle(void) diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index fae22f4..3dca36d 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -70,10 +70,8 @@ static DEFINE_PER_CPU(struct acpi_processor_cx * [CPUIDLE_STATE_MAX], static int disabled_by_idle_boot_param(void) { -#ifdef CONFIG_X86 return boot_option_idle_override == IDLE_POLL || boot_option_idle_override == IDLE_HALT; -#endif } /* @@ -120,9 +118,7 @@ static struct dmi_system_id processor_power_dmi_table[] = { static void acpi_safe_halt(void) { if (!tif_need_resched()) { -#ifdef CONFIG_X86 safe_halt(); -#endif local_irq_disable(); } } @@ -437,7 +433,6 @@ static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) } else { continue; } -#ifdef CONFIG_X86 if (cx.type == ACPI_STATE_C1 && (boot_option_idle_override == IDLE_NOMWAIT)) { /* @@ -453,7 +448,6 @@ static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) cx.entry_method = ACPI_CSTATE_HALT; snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); } -#endif } else { snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x", cx.address); @@ -754,11 +748,7 @@ static int acpi_idle_play_dead(struct cpuidle_device *dev, int index) while (1) { if (cx->entry_method == ACPI_CSTATE_HALT) -#ifdef CONFIG_X86 safe_halt(); -#else - ; -#endif else if (cx->entry_method == ACPI_CSTATE_SYSTEMIO) { inb(cx->address); /* See comment in acpi_idle_do_entry() */ @@ -853,9 +843,7 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev, } } -#ifdef CONFIG_X86 acpi_unlazy_tlb(smp_processor_id()); -#endif /* Tell the scheduler that we are going deep-idle: */ sched_clock_idle_sleep_event(); @@ -1133,9 +1121,7 @@ int acpi_processor_power_init(struct acpi_processor *pr) if (!first_run) { dmi_check_system(processor_power_dmi_table); -#ifdef CONFIG_X86 max_cstate = acpi_processor_cstate_check(max_cstate); -#endif if (max_cstate < ACPI_C_STATES_MAX) printk(KERN_NOTICE "ACPI: processor limited to max C-state %d\n", -- 1.7.10.4

11 years, 3 months

1
0
0 0

[PATCH linaro-acpi] [RFC 5/7] cpufreq: Add ACPI cpufreq support for ARM

by Jonghwan Choi

Separated acpi-cpufreq into 3 parts. acpi-cpufreq has a common code for both x86 and arm. acpi-cpufreq_x86 is for x86-specific codes and acpi-cpufreq_arm is for arm-specific codes. Signed-off-by: Jonghwan Choi <jhbird.choi(a)samsung.com> --- drivers/cpufreq/Makefile | 6 + drivers/cpufreq/acpi-cpufreq.c | 394 +++++------------------------------- drivers/cpufreq/acpi-cpufreq.h | 69 +++++++ drivers/cpufreq/acpi-cpufreq_arm.c | 46 +++++ drivers/cpufreq/acpi-cpufreq_x86.c | 300 +++++++++++++++++++++++++++ 5 files changed, 471 insertions(+), 344 deletions(-) create mode 100644 drivers/cpufreq/acpi-cpufreq.h create mode 100644 drivers/cpufreq/acpi-cpufreq_arm.c create mode 100644 drivers/cpufreq/acpi-cpufreq_x86.c diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index bfeb0fb..eda425a 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -14,6 +14,12 @@ obj-$(CONFIG_CPU_FREQ_GOV_COMMON) += cpufreq_governor.o obj-$(CONFIG_GENERIC_CPUFREQ_CPU0) += cpufreq-cpu0.o obj-$(CONFIG_ACPI_CPUFREQ) += acpi-cpufreq.o +ifdef CONFIG_X86 +obj-$(CONFIG_ACPI_CPUFREQ) += acpi-cpufreq_x86.o +endif +ifdef CONFIG_ARM64 +obj-$(CONFIG_ACPI_CPUFREQ) += acpi-cpufreq_arm.o +endif ############################################################################ ###### # x86 drivers. diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c index 80662b1..6f9749b 100644 --- a/drivers/cpufreq/acpi-cpufreq.c +++ b/drivers/cpufreq/acpi-cpufreq.c @@ -42,39 +42,17 @@ #include <acpi/processor.h> -#ifdef CONFIG_X86 -#include <asm/msr.h> -#endif +#include <asm/cpu.h> #include <asm/processor.h> -#include <asm/cpufeature.h> + +#include "acpi-cpufreq.h" MODULE_AUTHOR("Paul Diefenbaugh, Dominik Brodowski"); MODULE_DESCRIPTION("ACPI Processor P-States Driver"); MODULE_LICENSE("GPL"); -#define PFX "acpi-cpufreq: " - -enum { - UNDEFINED_CAPABLE = 0, - SYSTEM_INTEL_MSR_CAPABLE, - SYSTEM_AMD_MSR_CAPABLE, - SYSTEM_IO_CAPABLE, -}; - -#define INTEL_MSR_RANGE (0xffff) -#define AMD_MSR_RANGE (0x7) - -#define MSR_K7_HWCR_CPB_DIS (1ULL << 25) - -struct acpi_cpufreq_data { - struct acpi_processor_performance *acpi_data; - struct cpufreq_frequency_table *freq_table; - unsigned int resume; - unsigned int cpu_feature; - cpumask_var_t freqdomain_cpus; -}; - static DEFINE_PER_CPU(struct acpi_cpufreq_data *, acfreq_data); +static struct acpi_cpufreq_common *acpi; /* acpi_perf_data is a pointer to percpu data. */ static struct acpi_processor_performance __percpu *acpi_perf_data; @@ -82,66 +60,12 @@ static struct acpi_processor_performance __percpu *acpi_perf_data; static struct cpufreq_driver acpi_cpufreq_driver; static unsigned int acpi_pstate_strict; -static struct msr __percpu *msrs; - -static bool boost_state(unsigned int cpu) -{ -#ifdef CONFIG_X86 - u32 lo, hi; - u64 msr; - - switch (boot_cpu_data.x86_vendor) { - case X86_VENDOR_INTEL: - rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi); - msr = lo | ((u64)hi << 32); - return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); - case X86_VENDOR_AMD: - rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi); - msr = lo | ((u64)hi << 32); - return !(msr & MSR_K7_HWCR_CPB_DIS); - } -#endif - return false; -} - -static void boost_set_msrs(bool enable, const struct cpumask *cpumask) -{ - u32 cpu; - u32 msr_addr; - u64 msr_mask; - -#ifdef CONFIG_X86 - switch (boot_cpu_data.x86_vendor) { - case X86_VENDOR_INTEL: - msr_addr = MSR_IA32_MISC_ENABLE; - msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE; - break; - case X86_VENDOR_AMD: - msr_addr = MSR_K7_HWCR; - msr_mask = MSR_K7_HWCR_CPB_DIS; - break; - default: - return; - } - - rdmsr_on_cpus(cpumask, msr_addr, msrs); - - for_each_cpu(cpu, cpumask) { - struct msr *reg = per_cpu_ptr(msrs, cpu); - if (enable) - reg->q &= ~msr_mask; - else - reg->q |= msr_mask; - } - - wrmsr_on_cpus(cpumask, msr_addr, msrs); -#endif -} static int _store_boost(int val) { get_online_cpus(); - boost_set_msrs(val, cpu_online_mask); + if (acpi->ops->update_boost) + acpi->ops->update_boost(val, cpu_online_mask); put_online_cpus(); pr_debug("Core Boosting %sabled.\n", val ? "en" : "dis"); @@ -157,13 +81,12 @@ static ssize_t show_freqdomain_cpus(struct cpufreq_policy *policy, char *buf) cpufreq_freq_attr_ro(freqdomain_cpus); -#ifdef CONFIG_X86_ACPI_CPUFREQ_CPB static ssize_t store_boost(const char *buf, size_t count) { int ret; unsigned long val = 0; - if (!acpi_cpufreq_driver.boost_supported) + if (!acpi->boost_supported) return -EINVAL; ret = kstrtoul(buf, 10, &val); @@ -187,25 +110,6 @@ static ssize_t show_cpb(struct cpufreq_policy *policy, char *buf) } cpufreq_freq_attr_rw(cpb); -#endif - -static int check_est_cpu(unsigned int cpuid) -{ -#ifdef CONFIG_X86 - struct cpuinfo_x86 *cpu = &cpu_data(cpuid); - - return cpu_has(cpu, X86_FEATURE_EST); -#endif -} - -static int check_amd_hwpstate_cpu(unsigned int cpuid) -{ -#ifdef CONFIG_X86 - struct cpuinfo_x86 *cpu = &cpu_data(cpuid); - - return cpu_has(cpu, X86_FEATURE_HW_PSTATE); -#endif -} static unsigned extract_io(u32 value, struct acpi_cpufreq_data *data) { @@ -221,75 +125,39 @@ static unsigned extract_io(u32 value, struct acpi_cpufreq_data *data) return 0; } -static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data) -{ - int i; - struct acpi_processor_performance *perf; -#ifdef CONFIG_X86 - if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) - msr &= AMD_MSR_RANGE; - else - msr &= INTEL_MSR_RANGE; -#endif - - perf = data->acpi_data; - - for (i = 0; data->freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { - if (msr == perf->states[data->freq_table[i].driver_data].status) - return data->freq_table[i].frequency; - } - return data->freq_table[0].frequency; -} static unsigned extract_freq(u32 val, struct acpi_cpufreq_data *data) { switch (data->cpu_feature) { case SYSTEM_INTEL_MSR_CAPABLE: case SYSTEM_AMD_MSR_CAPABLE: - return extract_msr(val, data); + return acpi->ops->extract_freq(val, data); case SYSTEM_IO_CAPABLE: + case SYSTEM_MEMORY_CAPABLE: return extract_io(val, data); default: return 0; } } -struct msr_addr { - u32 reg; -}; - -struct io_addr { - u16 port; - u8 bit_width; -}; - -struct drv_cmd { - unsigned int type; - const struct cpumask *mask; - union { - struct msr_addr msr; - struct io_addr io; - } addr; - u32 val; -}; - /* Called via smp_call_function_single(), on the target CPU */ static void do_drv_read(void *_cmd) { struct drv_cmd *cmd = _cmd; - u32 h; switch (cmd->type) { case SYSTEM_INTEL_MSR_CAPABLE: case SYSTEM_AMD_MSR_CAPABLE: -#ifdef CONFIG_X86 - rdmsr(cmd->addr.msr.reg, cmd->val, h); -#endif + acpi->ops->drv_read(cmd); break; case SYSTEM_IO_CAPABLE: acpi_os_read_port((acpi_io_address)cmd->addr.io.port, &cmd->val, (u32)cmd->addr.io.bit_width); + case SYSTEM_MEMORY_CAPABLE: + acpi_os_read_memory((acpi_physical_address)cmd->addr.mem.addr, + (u64*)&cmd->val, + cmd->addr.mem.bit_width); break; default: break; @@ -300,25 +168,20 @@ static void do_drv_read(void *_cmd) static void do_drv_write(void *_cmd) { struct drv_cmd *cmd = _cmd; - u32 lo, hi; switch (cmd->type) { case SYSTEM_INTEL_MSR_CAPABLE: -#ifdef CONFIG_X86 - rdmsr(cmd->addr.msr.reg, lo, hi); - lo = (lo & ~INTEL_MSR_RANGE) | (cmd->val & INTEL_MSR_RANGE); - wrmsr(cmd->addr.msr.reg, lo, hi); -#endif - break; case SYSTEM_AMD_MSR_CAPABLE: -#ifdef CONFIG_X86 - wrmsr(cmd->addr.msr.reg, cmd->val, 0); -#endif + acpi->ops->drv_write(cmd); break; case SYSTEM_IO_CAPABLE: acpi_os_write_port((acpi_io_address)cmd->addr.io.port, cmd->val, (u32)cmd->addr.io.bit_width); + case SYSTEM_MEMORY_CAPABLE: + acpi_os_write_memory((acpi_physical_address)cmd->addr.mem.addr, + (u64)cmd->val, + cmd->addr.mem.bit_width); break; default: break; @@ -347,34 +210,13 @@ static void drv_write(struct drv_cmd *cmd) static u32 get_cur_val(const struct cpumask *mask) { - struct acpi_processor_performance *perf; struct drv_cmd cmd; if (unlikely(cpumask_empty(mask))) return 0; - switch (per_cpu(acfreq_data, cpumask_first(mask))->cpu_feature) { -#ifdef CONFIG_X86 - case SYSTEM_INTEL_MSR_CAPABLE: - cmd.type = SYSTEM_INTEL_MSR_CAPABLE; - cmd.addr.msr.reg = MSR_IA32_PERF_CTL; - break; - case SYSTEM_AMD_MSR_CAPABLE: - cmd.type = SYSTEM_AMD_MSR_CAPABLE; - cmd.addr.msr.reg = MSR_AMD_PERF_CTL; - break; -#endif - case SYSTEM_IO_CAPABLE: - cmd.type = SYSTEM_IO_CAPABLE; - perf = per_cpu(acfreq_data, cpumask_first(mask))->acpi_data; - cmd.addr.io.port = perf->control_register.address; - cmd.addr.io.bit_width = perf->control_register.bit_width; - break; - default: - return 0; - } - cmd.mask = mask; + drv_read(&cmd); pr_debug("get_cur_val = %u\n", cmd.val); @@ -453,36 +295,14 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy, } } - switch (data->cpu_feature) { -#ifdef CONFIG_X86 - case SYSTEM_INTEL_MSR_CAPABLE: - cmd.type = SYSTEM_INTEL_MSR_CAPABLE; - cmd.addr.msr.reg = MSR_IA32_PERF_CTL; - cmd.val = (u32) perf->states[next_perf_state].control; - break; - case SYSTEM_AMD_MSR_CAPABLE: - cmd.type = SYSTEM_AMD_MSR_CAPABLE; - cmd.addr.msr.reg = MSR_AMD_PERF_CTL; - cmd.val = (u32) perf->states[next_perf_state].control; - break; -#endif - case SYSTEM_IO_CAPABLE: - cmd.type = SYSTEM_IO_CAPABLE; - cmd.addr.io.port = perf->control_register.address; - cmd.addr.io.bit_width = perf->control_register.bit_width; - cmd.val = (u32) perf->states[next_perf_state].control; - break; - default: - result = -ENODEV; - goto out; - } - /* cpufreq holds the hotplug lock, so we are safe from here on */ if (policy->shared_type != CPUFREQ_SHARED_TYPE_ANY) cmd.mask = policy->cpus; else cmd.mask = cpumask_of(policy->cpu); + cmd.val = (u32) perf->states[next_perf_state].control; + drv_write(&cmd); if (acpi_pstate_strict) { @@ -540,44 +360,6 @@ static void free_acpi_perf_data(void) free_percpu(acpi_perf_data); } -static int boost_notify(struct notifier_block *nb, unsigned long action, - void *hcpu) -{ - unsigned cpu = (long)hcpu; - const struct cpumask *cpumask; - - cpumask = get_cpu_mask(cpu); - - /* - * Clear the boost-disable bit on the CPU_DOWN path so that - * this cpu cannot block the remaining ones from boosting. On - * the CPU_UP path we simply keep the boost-disable flag in - * sync with the current global state. - */ - - switch (action) { - case CPU_UP_PREPARE: - case CPU_UP_PREPARE_FROZEN: - boost_set_msrs(acpi_cpufreq_driver.boost_enabled, cpumask); - break; - - case CPU_DOWN_PREPARE: - case CPU_DOWN_PREPARE_FROZEN: - boost_set_msrs(1, cpumask); - break; - - default: - break; - } - - return NOTIFY_OK; -} - - -static struct notifier_block boost_nb = { - .notifier_call = boost_notify, -}; - /* * acpi_cpufreq_early_init - initialize ACPI P-States library * @@ -639,29 +421,6 @@ static const struct dmi_system_id sw_any_bug_dmi_table[] = { }, { } }; - -static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c) -{ - /* Intel Xeon Processor 7100 Series Specification Update - * http://www.intel.com/Assets/PDF/specupdate/314554.pdf - * AL30: A Machine Check Exception (MCE) Occurring during an - * Enhanced Intel SpeedStep Technology Ratio Change May Cause - * Both Processor Cores to Lock Up. */ -#ifdef CONFIG_X86 - if (c->x86_vendor == X86_VENDOR_INTEL) { - if ((c->x86 == 15) && - (c->x86_model == 6) && - (c->x86_mask == 8)) { - printk(KERN_INFO "acpi-cpufreq: Intel(R) " - "Xeon(R) 7100 Errata AL30, processors may " - "lock up on frequency changes: disabling " - "acpi-cpufreq.\n"); - return -ENODEV; - } - } -#endif - return 0; -} #endif static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) @@ -671,11 +430,7 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) unsigned int cpu = policy->cpu; struct acpi_cpufreq_data *data; unsigned int result = 0; -#ifdef CONFIG_X86 - struct cpuinfo_x86 *c = &cpu_data(policy->cpu); -#else - struct cpuinfo_x86 *c = NULL; -#endif + void *c = &cpu_data(policy->cpu); struct acpi_processor_performance *perf; #ifdef CONFIG_SMP static int blacklisted; @@ -686,9 +441,11 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) #ifdef CONFIG_SMP if (blacklisted) return blacklisted; - blacklisted = acpi_cpufreq_blacklist(c); - if (blacklisted) - return blacklisted; + if (acpi->ops->arch_check) { + blacklisted = acpi->ops->arch_check(c); + if (blacklisted) + return blacklisted; + } #endif data = kzalloc(sizeof(*data), GFP_KERNEL); @@ -703,10 +460,8 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) data->acpi_data = per_cpu_ptr(acpi_perf_data, cpu); per_cpu(acfreq_data, cpu) = data; -#ifdef CONFIG_X86 - if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) + if (acpi->const_loops) acpi_cpufreq_driver.flags |= CPUFREQ_CONST_LOOPS; -#endif result = acpi_processor_register_performance(data->acpi_data, cpu); if (result) @@ -734,7 +489,7 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) #endif } - if (check_amd_hwpstate_cpu(cpu) && !acpi_pstate_strict) { + if (acpi->feature_hw_pstate && !acpi_pstate_strict) { cpumask_clear(policy->cpus); cpumask_set_cpu(cpu, policy->cpus); #ifdef CONFIG_X86 @@ -757,34 +512,7 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) goto err_unreg; } - switch (perf->control_register.space_id) { - case ACPI_ADR_SPACE_SYSTEM_IO: -#ifdef CONFIG_X86 - if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && - boot_cpu_data.x86 == 0xf) { - pr_debug("AMD K8 systems must use native drivers.\n"); - result = -ENODEV; - goto err_unreg; - } -#endif - pr_debug("SYSTEM IO addr space\n"); - data->cpu_feature = SYSTEM_IO_CAPABLE; - break; - case ACPI_ADR_SPACE_FIXED_HARDWARE: - pr_debug("HARDWARE addr space\n"); - if (check_est_cpu(cpu)) { - data->cpu_feature = SYSTEM_INTEL_MSR_CAPABLE; - break; - } - if (check_amd_hwpstate_cpu(cpu)) { - data->cpu_feature = SYSTEM_AMD_MSR_CAPABLE; - break; - } - result = -ENODEV; - goto err_unreg; - default: - pr_debug("Unknown addr space %d\n", - (u32) (perf->control_register.space_id)); + if (acpi->ops->arch_feature(data)) { result = -ENODEV; goto err_unreg; } @@ -933,39 +661,14 @@ static struct cpufreq_driver acpi_cpufreq_driver = { static void __init acpi_cpufreq_boost_init(void) { -#ifdef CONFIG_X86 - if (boot_cpu_has(X86_FEATURE_CPB) || boot_cpu_has(X86_FEATURE_IDA)) { - msrs = msrs_alloc(); - - if (!msrs) - return; - - acpi_cpufreq_driver.boost_supported = true; - acpi_cpufreq_driver.boost_enabled = boost_state(0); - - cpu_notifier_register_begin(); - - /* Force all MSRs to the same value */ - boost_set_msrs(acpi_cpufreq_driver.boost_enabled, - cpu_online_mask); - - __register_cpu_notifier(&boost_nb); - - cpu_notifier_register_done(); - } -#endif + if (acpi->ops->arch_boost_init) + acpi->ops->arch_boost_init(acpi); } static void acpi_cpufreq_boost_exit(void) { -#ifdef CONFIG_X86 - if (msrs) { - unregister_cpu_notifier(&boost_nb); - - msrs_free(msrs); - msrs = NULL; - } -#endif + if (acpi->ops->arch_boost_exit) + acpi->ops->arch_boost_exit(); } static int __init acpi_cpufreq_init(void) @@ -985,14 +688,23 @@ static int __init acpi_cpufreq_init(void) if (ret) return ret; -#ifdef CONFIG_X86_ACPI_CPUFREQ_CPB + acpi = kzalloc(sizeof(*acpi), GFP_KERNEL); + if (!acpi) + return -ENOMEM; + + if (arch_acpi_cpufreq_init(acpi)) { + kfree(acpi); + return -ENOMEM; + } + + /* this is a sysfs file with a strange name and an even stranger * semantic - per CPU instantiation, but system global effect. * Lets enable it only on AMD CPUs for compatibility reasons and * only if configured. This is considered legacy code, which * will probably be removed at some point in the future. */ - if (check_amd_hwpstate_cpu(0)) { + if (acpi->feature_hw_pstate) { struct freq_attr **iter; pr_debug("adding sysfs entry for cpb\n"); @@ -1004,11 +716,12 @@ static int __init acpi_cpufreq_init(void) if (iter[1] == NULL) *iter = &cpb; } -#endif + acpi_cpufreq_boost_init(); ret = cpufreq_register_driver(&acpi_cpufreq_driver); if (ret) { + kfree(acpi); free_acpi_perf_data(); acpi_cpufreq_boost_exit(); } @@ -1024,6 +737,8 @@ static void __exit acpi_cpufreq_exit(void) cpufreq_unregister_driver(&acpi_cpufreq_driver); free_acpi_perf_data(); + + kfree(acpi); } module_param(acpi_pstate_strict, uint, 0644); @@ -1034,15 +749,6 @@ MODULE_PARM_DESC(acpi_pstate_strict, late_initcall(acpi_cpufreq_init); module_exit(acpi_cpufreq_exit); -#ifdef CONFIG_X86 -static const struct x86_cpu_id acpi_cpufreq_ids[] = { - X86_FEATURE_MATCH(X86_FEATURE_ACPI), - X86_FEATURE_MATCH(X86_FEATURE_HW_PSTATE), - {} -}; -MODULE_DEVICE_TABLE(x86cpu, acpi_cpufreq_ids); -#endif - static const struct acpi_device_id processor_device_ids[] = { {ACPI_PROCESSOR_OBJECT_HID, }, {ACPI_PROCESSOR_DEVICE_HID, }, diff --git a/drivers/cpufreq/acpi-cpufreq.h b/drivers/cpufreq/acpi-cpufreq.h new file mode 100644 index 0000000..ddef14f --- /dev/null +++ b/drivers/cpufreq/acpi-cpufreq.h @@ -0,0 +1,69 @@ +#ifndef _ACPI_CPUFREQ_H +#define _ACPI_CPUFREQ_H + +#define PFX "acpi-cpufreq: " + +enum { + UNDEFINED_CAPABLE = 0, + SYSTEM_INTEL_MSR_CAPABLE, + SYSTEM_AMD_MSR_CAPABLE, + SYSTEM_IO_CAPABLE, + SYSTEM_MEMORY_CAPABLE, +}; + +struct msr_addr { + u32 reg; +}; + +struct io_addr { + u16 port; + u32 bit_width; +}; + +struct mem_addr { + u64 addr; + u32 bit_width; +}; + +struct drv_cmd { + unsigned int type; + const struct cpumask *mask; + union { + struct msr_addr msr; + struct io_addr io; + struct mem_addr mem; + } addr; + u32 val; +}; + +struct acpi_cpufreq_data; +struct acpi_cpufreq_common; + +struct acpi_cpufreq_ops { + int (*arch_check)(void *info); + int (*arch_feature)(struct acpi_cpufreq_data *data); + void (*arch_boost_init)(struct acpi_cpufreq_common *acpi); + void (*arch_boost_exit)(void); + void (*drv_read)(struct drv_cmd *cmd); + void (*drv_write)(struct drv_cmd *cmd); + void (*update_boost)(bool enable, const struct cpumask *cpumask); + unsigned (*extract_freq)(u32 val, struct acpi_cpufreq_data *data); +}; + +struct acpi_cpufreq_data { + struct acpi_processor_performance *acpi_data; + struct cpufreq_frequency_table *freq_table; + unsigned int resume; + unsigned int cpu_feature; + cpumask_var_t freqdomain_cpus; +}; + +struct acpi_cpufreq_common { + struct acpi_cpufreq_ops *ops; + bool boost_supported; + bool feature_hw_pstate; + bool const_loops; +}; + +int arch_acpi_cpufreq_init(struct acpi_cpufreq_common *common); +#endif /* _ACPI_CPUFREQ_H */ diff --git a/drivers/cpufreq/acpi-cpufreq_arm.c b/drivers/cpufreq/acpi-cpufreq_arm.c new file mode 100644 index 0000000..60ec8aa --- /dev/null +++ b/drivers/cpufreq/acpi-cpufreq_arm.c @@ -0,0 +1,46 @@ +#include <linux/acpi.h> +#include <linux/cpu.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/uaccess.h> + +#include <acpi/processor.h> + +#include <asm/cpu.h> +#include <asm/processor.h> + +#include "acpi-cpufreq.h" + +static int arm_arch_feature(struct acpi_cpufreq_data *data) +{ + struct acpi_processor_performance *perf; + int result = 0; + + perf = data->acpi_data; + + switch (perf->control_register.space_id) { + case ACPI_ADR_SPACE_SYSTEM_MEMORY: + pr_debug("SYSTEM Memory addr space\n"); + data->cpu_feature = SYSTEM_MEMORY_CAPABLE; + break; + default: + pr_debug("Unknown addr space %d\n", + (u32) (perf->control_register.space_id)); + result = -ENODEV; + break; + } + + return result; +} + +static struct acpi_cpufreq_ops arm_ops = { + .arch_feature = arm_arch_feature, +}; + +int arch_acpi_cpufreq_init(struct acpi_cpufreq_common *common) +{ + common->ops = &arm_ops; + + return 0; +} + diff --git a/drivers/cpufreq/acpi-cpufreq_x86.c b/drivers/cpufreq/acpi-cpufreq_x86.c new file mode 100644 index 0000000..5fe36e4 --- /dev/null +++ b/drivers/cpufreq/acpi-cpufreq_x86.c @@ -0,0 +1,300 @@ +#include <linux/module.h> +#include <linux/acpi.h> +#include <linux/cpu.h> +#include <linux/cpufreq.h> +#include <linux/io.h> + +#include <acpi/processor.h> + +#include <asm/msr.h> +#include <asm/cpufeature.h> +#include <asm/processor.h> + +#include "acpi-cpufreq.h" + +#define INTEL_MSR_RANGE (0xffff) +#define AMD_MSR_RANGE (0x7) + +#define MSR_K7_HWCR_CPB_DIS (1ULL << 25) + +static struct msr __percpu *msrs; + +static void x86_boost_set_msrs(bool enable, const struct cpumask *cpumask) +{ + u32 cpu; + u32 msr_addr; + u64 msr_mask; + + switch (boot_cpu_data.x86_vendor) { + case X86_VENDOR_INTEL: + msr_addr = MSR_IA32_MISC_ENABLE; + msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE; + break; + case X86_VENDOR_AMD: + msr_addr = MSR_K7_HWCR; + msr_mask = MSR_K7_HWCR_CPB_DIS; + break; + default: + return; + } + + rdmsr_on_cpus(cpumask, msr_addr, msrs); + + for_each_cpu(cpu, cpumask) { + struct msr *reg = per_cpu_ptr(msrs, cpu); + if (enable) + reg->q &= ~msr_mask; + else + reg->q |= msr_mask; + } + + wrmsr_on_cpus(cpumask, msr_addr, msrs); +} + +static bool boost_state(unsigned int cpu) +{ + u32 lo, hi; + u64 msr; + + switch (boot_cpu_data.x86_vendor) { + case X86_VENDOR_INTEL: + rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi); + msr = lo | ((u64)hi << 32); + return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); + case X86_VENDOR_AMD: + rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi); + msr = lo | ((u64)hi << 32); + return !(msr & MSR_K7_HWCR_CPB_DIS); + } + return false; +} + +#ifdef CONFIG_SMP +static int x86_arch_check(void *data) +{ + struct cpuinfo_x86 *c = data; + /* Intel Xeon Processor 7100 Series Specification Update + * http://www.intel.com/Assets/PDF/specupdate/314554.pdf + * AL30: A Machine Check Exception (MCE) Occurring during an + * Enhanced Intel SpeedStep Technology Ratio Change May Cause + * Both Processor Cores to Lock Up. */ + if (c->x86_vendor == X86_VENDOR_INTEL) { + if ((c->x86 == 15) && + (c->x86_model == 6) && + (c->x86_mask == 8)) { + printk(KERN_INFO "acpi-cpufreq: Intel(R) " + "Xeon(R) 7100 Errata AL30, processors may " + "lock up on frequency changes: disabling " + "acpi-cpufreq.\n"); + return -ENODEV; + } + } + return 0; +} +#else +#define x86_arch_check NULL +#endif + +static void x86_do_drv_read(struct drv_cmd *cmd) +{ + u32 h; + + switch (cmd->type) { + case SYSTEM_INTEL_MSR_CAPABLE: + cmd->addr.msr.reg = MSR_IA32_PERF_CTL; + rdmsr(cmd->addr.msr.reg, cmd->val, h); + break; + case SYSTEM_AMD_MSR_CAPABLE: + cmd->addr.msr.reg = MSR_AMD_PERF_CTL; + rdmsr(cmd->addr.msr.reg, cmd->val, h); + break; + default: + break; + } +} + +/* Called via smp_call_function_many(), on the target CPUs */ +static void x86_do_drv_write(struct drv_cmd *cmd) +{ + u32 lo, hi; + + switch (cmd->type) { + case SYSTEM_INTEL_MSR_CAPABLE: + cmd->addr.msr.reg = MSR_IA32_PERF_CTL; + rdmsr(cmd->addr.msr.reg, lo, hi); + lo = (lo & ~INTEL_MSR_RANGE) | (cmd->val & INTEL_MSR_RANGE); + wrmsr(cmd->addr.msr.reg, lo, hi); + break; + case SYSTEM_AMD_MSR_CAPABLE: + cmd->addr.msr.reg = MSR_AMD_PERF_CTL; + wrmsr(cmd->addr.msr.reg, cmd->val, 0); + break; + default: + break; + } +} + +static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data) +{ + int i; + struct acpi_processor_performance *perf; + + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) + msr &= AMD_MSR_RANGE; + else + msr &= INTEL_MSR_RANGE; + + perf = data->acpi_data; + + for (i = 0; data->freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { + if (msr == perf->states[data->freq_table[i].driver_data].status) + return data->freq_table[i].frequency; + } + return data->freq_table[0].frequency; +} + +unsigned x86_extract_freq(u32 val, struct acpi_cpufreq_data *data) +{ + switch (data->cpu_feature) { + case SYSTEM_INTEL_MSR_CAPABLE: + case SYSTEM_AMD_MSR_CAPABLE: + return extract_msr(val, data); + default: + return 0; + } +} + +static int boost_notify(struct notifier_block *nb, unsigned long action, + void *hcpu) +{ + unsigned cpu = (long)hcpu; + const struct cpumask *cpumask; + + cpumask = get_cpu_mask(cpu); + + /* + * Clear the boost-disable bit on the CPU_DOWN path so that + * this cpu cannot block the remaining ones from boosting. On + * the CPU_UP path we simply keep the boost-disable flag in + * sync with the current global state. + */ + + switch (action) { + case CPU_UP_PREPARE: + case CPU_UP_PREPARE_FROZEN: + x86_boost_set_msrs(boost_state(0), cpumask); + break; + + case CPU_DOWN_PREPARE: + case CPU_DOWN_PREPARE_FROZEN: + x86_boost_set_msrs(1, cpumask); + break; + + default: + break; + } + + return NOTIFY_OK; +} + +static struct notifier_block boost_nb = { + .notifier_call = boost_notify, +}; + +static void x86_arch_boost_init(struct acpi_cpufreq_common *acpi) +{ + if (boot_cpu_has(X86_FEATURE_CPB) || boot_cpu_has(X86_FEATURE_IDA)) { + msrs = msrs_alloc(); + + if (!msrs) + return; + + acpi->boost_supported = true; + + get_online_cpus(); + + x86_boost_set_msrs(boost_state(0), cpu_online_mask); + + register_cpu_notifier(&boost_nb); + + put_online_cpus(); + } +} + +static void x86_arch_boost_exit(void) +{ + if (msrs) { + unregister_cpu_notifier(&boost_nb); + + msrs_free(msrs); + msrs = NULL; + } +} + +static int x86_arch_feature(struct acpi_cpufreq_data *data) +{ + struct acpi_processor_performance *perf; + int result = 0; + + perf = data->acpi_data; + + switch (perf->control_register.space_id) { + case ACPI_ADR_SPACE_SYSTEM_IO: + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && + boot_cpu_data.x86 == 0xf) { + pr_debug("AMD K8 systems must use native drivers.\n"); + result = -ENODEV; + break; + } + pr_debug("SYSTEM IO addr space\n"); + data->cpu_feature = SYSTEM_IO_CAPABLE; + break; + case ACPI_ADR_SPACE_FIXED_HARDWARE: + pr_debug("HARDWARE addr space\n"); + if (boot_cpu_has(X86_FEATURE_EST)) { + data->cpu_feature = SYSTEM_INTEL_MSR_CAPABLE; + break; + } + if (boot_cpu_has(X86_FEATURE_HW_PSTATE)) { + data->cpu_feature = SYSTEM_AMD_MSR_CAPABLE; + break; + } + result = -ENODEV; + break; + default: + pr_debug("Unknown addr space %d\n", + (u32) (perf->control_register.space_id)); + result = -ENODEV; + break; + } + + return result; +} + +static struct acpi_cpufreq_ops x86_ops = { + .arch_check = x86_arch_check, + .arch_feature = x86_arch_feature, + .arch_boost_init = x86_arch_boost_init, + .arch_boost_exit = x86_arch_boost_exit, + .drv_read = x86_do_drv_read, + .drv_write = x86_do_drv_write, + .update_boost = x86_boost_set_msrs, + .extract_freq = x86_extract_freq, +}; + +int __init arch_acpi_cpufreq_init(struct acpi_cpufreq_common *acpi) +{ + acpi->ops = &x86_ops; + + acpi->feature_hw_pstate = boot_cpu_has(X86_FEATURE_HW_PSTATE); + acpi->const_loops = boot_cpu_has(X86_FEATURE_CONSTANT_TSC); + + return 0; +} + +static const struct x86_cpu_id acpi_cpufreq_ids[] = { + X86_FEATURE_MATCH(X86_FEATURE_ACPI), + X86_FEATURE_MATCH(X86_FEATURE_HW_PSTATE), + {} +}; +MODULE_DEVICE_TABLE(x86cpu, acpi_cpufreq_ids); -- 1.7.10.4

11 years, 3 months

1
0
0 0

[PATCH linaro-acpi] [RFC 3/7] acpi: Use Hacks to allow compilation on arm environment

by Jonghwan Choi

To allow compilation of drivers & acpi with arm, use some hacks, Later, these hacks will be replaced with proper solutions. Signed-off-by: Jonghwan Choi <jhbird.choi(a)samsung.com> --- drivers/acpi/acpi_processor.c | 4 +++ drivers/acpi/processor_idle.c | 14 +++++++++++ drivers/cpufreq/acpi-cpufreq.c | 53 +++++++++++++++++++++++++++++++++++----- 3 files changed, 65 insertions(+), 6 deletions(-) diff --git a/drivers/acpi/acpi_processor.c b/drivers/acpi/acpi_processor.c index c29c2c3..6a89856 100644 --- a/drivers/acpi/acpi_processor.c +++ b/drivers/acpi/acpi_processor.c @@ -177,6 +177,7 @@ static int acpi_processor_hotadd_init(struct acpi_processor *pr) cpu_maps_update_begin(); cpu_hotplug_begin(); +#ifdef CONFIG_X86 ret = acpi_map_lsapic(pr->handle, pr->apic_id, &pr->id); if (ret) goto out; @@ -186,6 +187,7 @@ static int acpi_processor_hotadd_init(struct acpi_processor *pr) acpi_unmap_lsapic(pr->id); goto out; } +#endif /* * CPU got hot-added, but cpu_data is not initialized yet. Set a flag @@ -457,8 +459,10 @@ static void acpi_processor_remove(struct acpi_device *device) cpu_hotplug_begin(); /* Remove the CPU. */ +#ifdef CONFIG_X86 arch_unregister_cpu(pr->id); acpi_unmap_lsapic(pr->id); +#endif cpu_hotplug_done(); cpu_maps_update_done(); diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index 3dca36d..fae22f4 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -70,8 +70,10 @@ static DEFINE_PER_CPU(struct acpi_processor_cx * [CPUIDLE_STATE_MAX], static int disabled_by_idle_boot_param(void) { +#ifdef CONFIG_X86 return boot_option_idle_override == IDLE_POLL || boot_option_idle_override == IDLE_HALT; +#endif } /* @@ -118,7 +120,9 @@ static struct dmi_system_id processor_power_dmi_table[] = { static void acpi_safe_halt(void) { if (!tif_need_resched()) { +#ifdef CONFIG_X86 safe_halt(); +#endif local_irq_disable(); } } @@ -433,6 +437,7 @@ static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) } else { continue; } +#ifdef CONFIG_X86 if (cx.type == ACPI_STATE_C1 && (boot_option_idle_override == IDLE_NOMWAIT)) { /* @@ -448,6 +453,7 @@ static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) cx.entry_method = ACPI_CSTATE_HALT; snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); } +#endif } else { snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x", cx.address); @@ -748,7 +754,11 @@ static int acpi_idle_play_dead(struct cpuidle_device *dev, int index) while (1) { if (cx->entry_method == ACPI_CSTATE_HALT) +#ifdef CONFIG_X86 safe_halt(); +#else + ; +#endif else if (cx->entry_method == ACPI_CSTATE_SYSTEMIO) { inb(cx->address); /* See comment in acpi_idle_do_entry() */ @@ -843,7 +853,9 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev, } } +#ifdef CONFIG_X86 acpi_unlazy_tlb(smp_processor_id()); +#endif /* Tell the scheduler that we are going deep-idle: */ sched_clock_idle_sleep_event(); @@ -1121,7 +1133,9 @@ int acpi_processor_power_init(struct acpi_processor *pr) if (!first_run) { dmi_check_system(processor_power_dmi_table); +#ifdef CONFIG_X86 max_cstate = acpi_processor_cstate_check(max_cstate); +#endif if (max_cstate < ACPI_C_STATES_MAX) printk(KERN_NOTICE "ACPI: processor limited to max C-state %d\n", diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c index 000e4e0..80662b1 100644 --- a/drivers/cpufreq/acpi-cpufreq.c +++ b/drivers/cpufreq/acpi-cpufreq.c @@ -42,7 +42,9 @@ #include <acpi/processor.h> +#ifdef CONFIG_X86 #include <asm/msr.h> +#endif #include <asm/processor.h> #include <asm/cpufeature.h> @@ -84,6 +86,7 @@ static struct msr __percpu *msrs; static bool boost_state(unsigned int cpu) { +#ifdef CONFIG_X86 u32 lo, hi; u64 msr; @@ -97,6 +100,7 @@ static bool boost_state(unsigned int cpu) msr = lo | ((u64)hi << 32); return !(msr & MSR_K7_HWCR_CPB_DIS); } +#endif return false; } @@ -106,6 +110,7 @@ static void boost_set_msrs(bool enable, const struct cpumask *cpumask) u32 msr_addr; u64 msr_mask; +#ifdef CONFIG_X86 switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_INTEL: msr_addr = MSR_IA32_MISC_ENABLE; @@ -130,6 +135,7 @@ static void boost_set_msrs(bool enable, const struct cpumask *cpumask) } wrmsr_on_cpus(cpumask, msr_addr, msrs); +#endif } static int _store_boost(int val) @@ -185,16 +191,20 @@ cpufreq_freq_attr_rw(cpb); static int check_est_cpu(unsigned int cpuid) { +#ifdef CONFIG_X86 struct cpuinfo_x86 *cpu = &cpu_data(cpuid); return cpu_has(cpu, X86_FEATURE_EST); +#endif } static int check_amd_hwpstate_cpu(unsigned int cpuid) { +#ifdef CONFIG_X86 struct cpuinfo_x86 *cpu = &cpu_data(cpuid); return cpu_has(cpu, X86_FEATURE_HW_PSTATE); +#endif } static unsigned extract_io(u32 value, struct acpi_cpufreq_data *data) @@ -215,11 +225,12 @@ static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data) { int i; struct acpi_processor_performance *perf; - +#ifdef CONFIG_X86 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) msr &= AMD_MSR_RANGE; else msr &= INTEL_MSR_RANGE; +#endif perf = data->acpi_data; @@ -271,7 +282,9 @@ static void do_drv_read(void *_cmd) switch (cmd->type) { case SYSTEM_INTEL_MSR_CAPABLE: case SYSTEM_AMD_MSR_CAPABLE: +#ifdef CONFIG_X86 rdmsr(cmd->addr.msr.reg, cmd->val, h); +#endif break; case SYSTEM_IO_CAPABLE: acpi_os_read_port((acpi_io_address)cmd->addr.io.port, @@ -291,12 +304,16 @@ static void do_drv_write(void *_cmd) switch (cmd->type) { case SYSTEM_INTEL_MSR_CAPABLE: +#ifdef CONFIG_X86 rdmsr(cmd->addr.msr.reg, lo, hi); lo = (lo & ~INTEL_MSR_RANGE) | (cmd->val & INTEL_MSR_RANGE); wrmsr(cmd->addr.msr.reg, lo, hi); +#endif break; case SYSTEM_AMD_MSR_CAPABLE: +#ifdef CONFIG_X86 wrmsr(cmd->addr.msr.reg, cmd->val, 0); +#endif break; case SYSTEM_IO_CAPABLE: acpi_os_write_port((acpi_io_address)cmd->addr.io.port, @@ -337,6 +354,7 @@ static u32 get_cur_val(const struct cpumask *mask) return 0; switch (per_cpu(acfreq_data, cpumask_first(mask))->cpu_feature) { +#ifdef CONFIG_X86 case SYSTEM_INTEL_MSR_CAPABLE: cmd.type = SYSTEM_INTEL_MSR_CAPABLE; cmd.addr.msr.reg = MSR_IA32_PERF_CTL; @@ -345,6 +363,7 @@ static u32 get_cur_val(const struct cpumask *mask) cmd.type = SYSTEM_AMD_MSR_CAPABLE; cmd.addr.msr.reg = MSR_AMD_PERF_CTL; break; +#endif case SYSTEM_IO_CAPABLE: cmd.type = SYSTEM_IO_CAPABLE; perf = per_cpu(acfreq_data, cpumask_first(mask))->acpi_data; @@ -435,6 +454,7 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy, } switch (data->cpu_feature) { +#ifdef CONFIG_X86 case SYSTEM_INTEL_MSR_CAPABLE: cmd.type = SYSTEM_INTEL_MSR_CAPABLE; cmd.addr.msr.reg = MSR_IA32_PERF_CTL; @@ -445,6 +465,7 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy, cmd.addr.msr.reg = MSR_AMD_PERF_CTL; cmd.val = (u32) perf->states[next_perf_state].control; break; +#endif case SYSTEM_IO_CAPABLE: cmd.type = SYSTEM_IO_CAPABLE; cmd.addr.io.port = perf->control_register.address; @@ -484,7 +505,7 @@ static unsigned long acpi_cpufreq_guess_freq(struct acpi_cpufreq_data *data, unsigned int cpu) { struct acpi_processor_performance *perf = data->acpi_data; - +#ifdef CONFIG_X86 if (cpu_khz) { /* search the closest match to cpu_khz */ unsigned int i; @@ -501,11 +522,11 @@ acpi_cpufreq_guess_freq(struct acpi_cpufreq_data *data, unsigned int cpu) } perf->state = perf->state_count-1; return freqn; - } else { - /* assume CPU is at P0... */ - perf->state = 0; - return perf->states[0].core_frequency * 1000; } +#endif + /* assume CPU is at P0... */ + perf->state = 0; + return perf->states[0].core_frequency * 1000; } static void free_acpi_perf_data(void) @@ -626,6 +647,7 @@ static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c) * AL30: A Machine Check Exception (MCE) Occurring during an * Enhanced Intel SpeedStep Technology Ratio Change May Cause * Both Processor Cores to Lock Up. */ +#ifdef CONFIG_X86 if (c->x86_vendor == X86_VENDOR_INTEL) { if ((c->x86 == 15) && (c->x86_model == 6) && @@ -637,6 +659,7 @@ static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c) return -ENODEV; } } +#endif return 0; } #endif @@ -648,7 +671,11 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) unsigned int cpu = policy->cpu; struct acpi_cpufreq_data *data; unsigned int result = 0; +#ifdef CONFIG_X86 struct cpuinfo_x86 *c = &cpu_data(policy->cpu); +#else + struct cpuinfo_x86 *c = NULL; +#endif struct acpi_processor_performance *perf; #ifdef CONFIG_SMP static int blacklisted; @@ -676,8 +703,10 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) data->acpi_data = per_cpu_ptr(acpi_perf_data, cpu); per_cpu(acfreq_data, cpu) = data; +#ifdef CONFIG_X86 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) acpi_cpufreq_driver.flags |= CPUFREQ_CONST_LOOPS; +#endif result = acpi_processor_register_performance(data->acpi_data, cpu); if (result) @@ -700,13 +729,17 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) dmi_check_system(sw_any_bug_dmi_table); if (bios_with_sw_any_bug && !policy_is_shared(policy)) { policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; +#ifdef CONFIG_X86 cpumask_copy(policy->cpus, cpu_core_mask(cpu)); +#endif } if (check_amd_hwpstate_cpu(cpu) && !acpi_pstate_strict) { cpumask_clear(policy->cpus); cpumask_set_cpu(cpu, policy->cpus); +#ifdef CONFIG_X86 cpumask_copy(data->freqdomain_cpus, cpu_sibling_mask(cpu)); +#endif policy->shared_type = CPUFREQ_SHARED_TYPE_HW; pr_info_once(PFX "overriding BIOS provided _PSD data\n"); } @@ -726,12 +759,14 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) switch (perf->control_register.space_id) { case ACPI_ADR_SPACE_SYSTEM_IO: +#ifdef CONFIG_X86 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && boot_cpu_data.x86 == 0xf) { pr_debug("AMD K8 systems must use native drivers.\n"); result = -ENODEV; goto err_unreg; } +#endif pr_debug("SYSTEM IO addr space\n"); data->cpu_feature = SYSTEM_IO_CAPABLE; break; @@ -898,6 +933,7 @@ static struct cpufreq_driver acpi_cpufreq_driver = { static void __init acpi_cpufreq_boost_init(void) { +#ifdef CONFIG_X86 if (boot_cpu_has(X86_FEATURE_CPB) || boot_cpu_has(X86_FEATURE_IDA)) { msrs = msrs_alloc(); @@ -917,16 +953,19 @@ static void __init acpi_cpufreq_boost_init(void) cpu_notifier_register_done(); } +#endif } static void acpi_cpufreq_boost_exit(void) { +#ifdef CONFIG_X86 if (msrs) { unregister_cpu_notifier(&boost_nb); msrs_free(msrs); msrs = NULL; } +#endif } static int __init acpi_cpufreq_init(void) @@ -995,12 +1034,14 @@ MODULE_PARM_DESC(acpi_pstate_strict, late_initcall(acpi_cpufreq_init); module_exit(acpi_cpufreq_exit); +#ifdef CONFIG_X86 static const struct x86_cpu_id acpi_cpufreq_ids[] = { X86_FEATURE_MATCH(X86_FEATURE_ACPI), X86_FEATURE_MATCH(X86_FEATURE_HW_PSTATE), {} }; MODULE_DEVICE_TABLE(x86cpu, acpi_cpufreq_ids); +#endif static const struct acpi_device_id processor_device_ids[] = { {ACPI_PROCESSOR_OBJECT_HID, }, -- 1.7.10.4

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