Linaro-acpi

linaro-acpi@lists.linaro.org

820 discussions

[PATCH] arm64: dts: add acpi version of ve-aemv8a model dts

by Graeme Gregory

This performs the same function but we shall remove devices as probing is converted to ACPI. Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org> --- arch/arm64/boot/dts/rtsm_ve-aemv8a-acpi.dts | 159 ++++++++++++++ arch/arm64/boot/dts/rtsm_ve-motherboard-acpi.dtsi | 238 +++++++++++++++++++++ 2 files changed, 397 insertions(+) create mode 100644 arch/arm64/boot/dts/rtsm_ve-aemv8a-acpi.dts create mode 100644 arch/arm64/boot/dts/rtsm_ve-motherboard-acpi.dtsi diff --git a/arch/arm64/boot/dts/rtsm_ve-aemv8a-acpi.dts b/arch/arm64/boot/dts/rtsm_ve-aemv8a-acpi.dts new file mode 100644 index 0000000..aa68353 --- /dev/null +++ b/arch/arm64/boot/dts/rtsm_ve-aemv8a-acpi.dts @@ -0,0 +1,159 @@ +/* + * ARM Ltd. Fast Models + * + * Architecture Envelope Model (AEM) ARMv8-A + * ARMAEMv8AMPCT + * + * RTSM_VE_AEMv8A.lisa + */ + +/dts-v1/; + +/memreserve/ 0x80000000 0x00010000; + +/ { + model = "RTSM_VE_AEMv8A"; + compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x80000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; + + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x2c001000 0 0x1000>, + <0x0 0x2c002000 0 0x1000>, + <0x0 0x2c004000 0 0x2000>, + <0x0 0x2c006000 0 0x2000>; + interrupts = <1 9 0xf04>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <100000000>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + smb { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + + /include/ "rtsm_ve-motherboard-acpi.dtsi" + }; +}; diff --git a/arch/arm64/boot/dts/rtsm_ve-motherboard-acpi.dtsi b/arch/arm64/boot/dts/rtsm_ve-motherboard-acpi.dtsi new file mode 100644 index 0000000..bbaaa8e --- /dev/null +++ b/arch/arm64/boot/dts/rtsm_ve-motherboard-acpi.dtsi @@ -0,0 +1,238 @@ +/* + * ARM Ltd. Fast Models + * + * Versatile Express (VE) system model + * Motherboard component + * + * VEMotherBoard.lisa + */ + + motherboard { + arm,v2m-memory-map = "rs1"; + compatible = "arm,vexpress,v2m-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + flash@0,00000000 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>, + <4 0x00000000 0x04000000>; + bank-width = <4>; + }; + + vram@2,00000000 { + compatible = "arm,vexpress-vram"; + reg = <2 0x00000000 0x00800000>; + }; + + /* + * Removed for ACPI + * + ethernet@2,02000000 { + compatible = "smsc,lan91c111"; + reg = <2 0x02000000 0x10000>; + interrupts = <15>; + }; + */ + + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + iofpga@3,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x200000>; + + v2m_sysreg: sysreg@010000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x010000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_sysctl: sysctl@020000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + }; + + aaci@040000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x040000 0x1000>; + interrupts = <11>; + clocks = <&v2m_clk24mhz>; + clock-names = "apb_pclk"; + }; + + mmci@050000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x050000 0x1000>; + interrupts = <9 10>; + cd-gpios = <&v2m_sysreg 0 0>; + wp-gpios = <&v2m_sysreg 1 0>; + max-frequency = <12000000>; + vmmc-supply = <&v2m_fixed_3v3>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "mclk", "apb_pclk"; + }; + + kmi@060000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x060000 0x1000>; + interrupts = <12>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi@070000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x070000 0x1000>; + interrupts = <13>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + v2m_serial0: uart@090000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x090000 0x1000>; + interrupts = <5>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial1: uart@0a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a0000 0x1000>; + interrupts = <6>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial2: uart@0b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b0000 0x1000>; + interrupts = <7>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial3: uart@0c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c0000 0x1000>; + interrupts = <8>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + wdt@0f0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f0000 0x1000>; + interrupts = <0>; + clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; + clock-names = "wdogclk", "apb_pclk"; + }; + + v2m_timer01: timer@110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x110000 0x1000>; + interrupts = <2>; + clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + v2m_timer23: timer@120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x120000 0x1000>; + interrupts = <3>; + clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + rtc@170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x170000 0x1000>; + interrupts = <4>; + clocks = <&v2m_clk24mhz>; + clock-names = "apb_pclk"; + }; + + clcd@1f0000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f0000 0x1000>; + interrupts = <14>; + clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; + clock-names = "clcdclk", "apb_pclk"; + }; + }; + + v2m_fixed_3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + mcc { + compatible = "arm,vexpress,config-bus", "simple-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + v2m_oscclk1: osc@1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 63500000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; + + reset@0 { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; + }; + + muxfpga@0 { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + shutdown@0 { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; + + reboot@0 { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; + + dvimode@0 { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; + }; -- 1.7.10.4

11 years, 8 months

[PATCH] platforms: add rtsm_ve-aemv8a.acpi

by Graeme Gregory

There are enough differences between this model and foundation model I think it is ok to be a different platform. Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org> --- platforms/rtsm_ve-aemv8a.acpi/.gitignore | 3 + platforms/rtsm_ve-aemv8a.acpi/apic.asl | 126 +++++++++ platforms/rtsm_ve-aemv8a.acpi/asf!.asl | 80 ++++++ platforms/rtsm_ve-aemv8a.acpi/bert.asl | 21 ++ platforms/rtsm_ve-aemv8a.acpi/bgrt.asl | 25 ++ platforms/rtsm_ve-aemv8a.acpi/boot.asl | 21 ++ platforms/rtsm_ve-aemv8a.acpi/cpep.asl | 26 ++ platforms/rtsm_ve-aemv8a.acpi/csrt.asl | 143 ++++++++++ platforms/rtsm_ve-aemv8a.acpi/dbgp.asl | 29 ++ platforms/rtsm_ve-aemv8a.acpi/dmar.asl | 68 +++++ platforms/rtsm_ve-aemv8a.acpi/dsdt.asl | 234 ++++++++++++++++ platforms/rtsm_ve-aemv8a.acpi/ecdt.asl | 37 +++ platforms/rtsm_ve-aemv8a.acpi/einj.asl | 151 +++++++++++ platforms/rtsm_ve-aemv8a.acpi/erst.asl | 278 ++++++++++++++++++++ platforms/rtsm_ve-aemv8a.acpi/facp.asl | 167 ++++++++++++ platforms/rtsm_ve-aemv8a.acpi/facs.asl | 21 ++ platforms/rtsm_ve-aemv8a.acpi/fpdt.asl | 35 +++ platforms/rtsm_ve-aemv8a.acpi/gtdt.asl | 42 +++ platforms/rtsm_ve-aemv8a.acpi/hest.asl | 193 ++++++++++++++ platforms/rtsm_ve-aemv8a.acpi/hpet.asl | 33 +++ platforms/rtsm_ve-aemv8a.acpi/ivrs.asl | 86 ++++++ platforms/rtsm_ve-aemv8a.acpi/mcfg.asl | 26 ++ platforms/rtsm_ve-aemv8a.acpi/mchi.asl | 38 +++ platforms/rtsm_ve-aemv8a.acpi/mpst.asl | 87 ++++++ platforms/rtsm_ve-aemv8a.acpi/msct.asl | 51 ++++ platforms/rtsm_ve-aemv8a.acpi/oem0.asl | 18 ++ platforms/rtsm_ve-aemv8a.acpi/pmtt.asl | 105 ++++++++ platforms/rtsm_ve-aemv8a.acpi/rsdp.asl | 17 ++ .../rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest | 34 +++ platforms/rtsm_ve-aemv8a.acpi/s3pt.asl | 26 ++ platforms/rtsm_ve-aemv8a.acpi/sbst.asl | 22 ++ platforms/rtsm_ve-aemv8a.acpi/slic.asl | 56 ++++ platforms/rtsm_ve-aemv8a.acpi/slit.asl | 60 +++++ platforms/rtsm_ve-aemv8a.acpi/spcr.asl | 46 ++++ platforms/rtsm_ve-aemv8a.acpi/spmi.asl | 40 +++ platforms/rtsm_ve-aemv8a.acpi/srat.asl | 57 ++++ platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl | 17 ++ platforms/rtsm_ve-aemv8a.acpi/tcpa.asl | 22 ++ platforms/rtsm_ve-aemv8a.acpi/tpm2.asl | 22 ++ platforms/rtsm_ve-aemv8a.acpi/uefi.asl | 21 ++ platforms/rtsm_ve-aemv8a.acpi/waet.asl | 22 ++ platforms/rtsm_ve-aemv8a.acpi/wdat.asl | 47 ++++ platforms/rtsm_ve-aemv8a.acpi/wddt.asl | 44 ++++ platforms/rtsm_ve-aemv8a.acpi/wdrt.asl | 42 +++ platforms/rtsm_ve-aemv8a.acpi/xsdt.asl | 39 +++ 45 files changed, 2778 insertions(+) create mode 100644 platforms/rtsm_ve-aemv8a.acpi/.gitignore create mode 100644 platforms/rtsm_ve-aemv8a.acpi/apic.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/asf!.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/bert.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/bgrt.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/boot.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/cpep.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/csrt.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/dbgp.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/dmar.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/dsdt.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/ecdt.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/einj.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/erst.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/facp.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/facs.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/fpdt.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/gtdt.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/hest.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/hpet.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/ivrs.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/mcfg.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/mchi.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/mpst.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/msct.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/oem0.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/pmtt.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/rsdp.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest create mode 100644 platforms/rtsm_ve-aemv8a.acpi/s3pt.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/sbst.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/slic.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/slit.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/spcr.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/spmi.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/srat.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/tcpa.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/tpm2.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/uefi.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/waet.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/wdat.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/wddt.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/wdrt.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/xsdt.asl diff --git a/platforms/rtsm_ve-aemv8a.acpi/.gitignore b/platforms/rtsm_ve-aemv8a.acpi/.gitignore new file mode 100644 index 0000000..9585b50 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/.gitignore @@ -0,0 +1,3 @@ +*.aml +*.lst +*.acpi diff --git a/platforms/rtsm_ve-aemv8a.acpi/apic.asl b/platforms/rtsm_ve-aemv8a.acpi/apic.asl new file mode 100644 index 0000000..0df308d --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/apic.asl @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [APIC] Multiple APIC Description Table (MADT) + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "APIC" +[0004] Table Length : 000000F6 +[0001] Revision : 03 +[0001] Checksum : B0 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110623 + +[0004] Local Apic Address : 2C002000 +[0004] Flags (decoded below) : 00000001 + PC-AT Compatibility : 0 + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000000 /* Should be equal to FDT provided or CPU hardware ID */ +[0004] Processor UID : 00000000 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C002000 /* this is the foundation model's GIC address */ + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000001 +[0004] Processor UID : 00000001 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C002000 + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000002 +[0004] Processor UID : 00000002 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C002000 + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000003 +[0004] Processor UID : 00000003 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C002000 + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000004 +[0004] Processor UID : 00000004 +[0004] Flags (decoded below) : 00000000 + Processor Enabled : 0 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C002000 + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000005 +[0004] Processor UID : 00000005 +[0004] Flags (decoded below) : 00000000 + Processor Enabled : 0 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C002000 + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000006 +[0004] Processor UID : 00000006 +[0004] Flags (decoded below) : 00000000 + Processor Enabled : 0 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C002000 + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000007 +[0004] Processor UID : 00000007 +[0004] Flags (decoded below) : 00000000 + Processor Enabled : 0 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C002000 + +[0001] Subtable Type : 0C [Generic Interrupt Distributor] +[0001] Length : 18 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000000 +[0008] Base Address : 000000002C001000 /* armv8 foundation model's GIC distributor base addr */ +[0004] Interrupt Base : 00000000 +[0004] Reserved : 00000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/asf!.asl b/platforms/rtsm_ve-aemv8a.acpi/asf!.asl new file mode 100644 index 0000000..a05f924 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/asf!.asl @@ -0,0 +1,80 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [ASF!] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "ASF!" [Alert Standard Format table] +[0004] Table Length : 00000072 +[0001] Revision : 10 +[0001] Checksum : 0B +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0001] Subtable Type : 00 [ASF Information] +[0001] Reserved : 00 +[0002] Length : 0010 +[0001] Minimum Reset Value : 00 +[0001] Minimum Polling Interval : 00 +[0002] System ID : 0000 +[0004] Manufacturer ID : 00000000 +[0001] Flags : 00 +[0003] Reserved : 000000 + +[0001] Subtable Type : 01 [ASF Alerts] +[0001] Reserved : 00 +[0002] Length : 0014 +[0001] AssertMask : 00 +[0001] DeassertMask : 00 +[0001] Alert Count : 01 +[0001] Alert Data Length : 0C + +[0001] Address : 00 +[0001] Command : 00 +[0001] Mask : 00 +[0001] Value : 00 +[0001] SensorType : 00 +[0001] Type : 00 +[0001] Offset : 00 +[0001] SourceType : 00 +[0001] Severity : 00 +[0001] SensorNumber : 00 +[0001] Entity : 00 +[0001] Instance : 00 + +[0001] Subtable Type : 02 [ASF Remote Control] +[0001] Reserved : 00 +[0002] Length : 000C +[0001] Control Count : 01 +[0001] Control Data Length : 04 +[0002] Reserved : 0000 + +[0001] Function : 00 +[0001] Address : 00 +[0001] Command : 00 +[0001] Value : 00 + +[0001] Subtable Type : 03 [ASF RMCP Boot Options] +[0001] Reserved : 00 +[0002] Length : 0017 +[0007] Capabilities : 00 00 00 00 00 00 00 +[0001] Completion Code : 00 +[0004] Enterprise ID : 00000000 +[0001] Command : 00 +[0002] Parameter : 0000 +[0002] Boot Options : 0000 +[0002] Oem Parameters : 0000 + +[0001] Subtable Type : 84 [ASF Address] +[0001] Reserved : 00 +[0002] Length : 0007 +[0001] Eprom Address : 00 +[0001] Device Count : 01 +[0001] Addresses : 00 + diff --git a/platforms/rtsm_ve-aemv8a.acpi/bert.asl b/platforms/rtsm_ve-aemv8a.acpi/bert.asl new file mode 100644 index 0000000..6cb628c --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/bert.asl @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [BERT] Boot Error Record Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "BERT" +[0004] Table Length : 00000030 +[0001] Revision : 01 +[0001] Checksum : 15 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Boot Error Region Length : 00000000 +[0008] Boot Error Region Address : 0000000000000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/bgrt.asl b/platforms/rtsm_ve-aemv8a.acpi/bgrt.asl new file mode 100644 index 0000000..c8af10e --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/bgrt.asl @@ -0,0 +1,25 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [BGRT] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "BGRT" [Boot Graphics Resource Table] +[0004] Table Length : 00000038 +[0001] Revision : 01 +[0001] Checksum : 0D +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110623 + +[0002] Version : 0001 +[0001] Status : 00 +[0001] Image Type : 00 +[0008] Image Address : 0000000000000000 +[0004] Image OffsetX : 00000000 +[0004] Image OffsetY : 00000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/boot.asl b/platforms/rtsm_ve-aemv8a.acpi/boot.asl new file mode 100644 index 0000000..5a567fb --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/boot.asl @@ -0,0 +1,21 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [BOOT] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "BOOT" [Simple Boot Flag Table] +[0004] Table Length : 00000028 +[0001] Revision : 01 +[0001] Checksum : 0D +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 06040000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0001] Boot Register Index : 00 +[0003] Reserved : 000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/cpep.asl b/platforms/rtsm_ve-aemv8a.acpi/cpep.asl new file mode 100644 index 0000000..8f6b3b2 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/cpep.asl @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [CPEP] Corrected Platform Error Polling Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "CPEP" +[0004] Table Length : 00000034 +[0001] Revision : 01 +[0001] Checksum : 0F +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0008] Reserved : 0000000000000000 + +[0001] Subtable Type : 00 +[0001] Length : 08 +[0001] Processor ID : 00 +[0001] Processor EID : 00 +[0004] Polling Interval : 00000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/csrt.asl b/platforms/rtsm_ve-aemv8a.acpi/csrt.asl new file mode 100644 index 0000000..ab43ea5 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/csrt.asl @@ -0,0 +1,143 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [CSRT] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "CSRT" [Core System Resource Table] +[0004] Table Length : 0000014C +[0001] Revision : 01 +[0001] Checksum : 0D +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20121114 + + +[0004] Length : 00000088 +[0004] Vendor ID : 4C544E49 +[0004] Subvendor ID : 00000000 +[0002] Device ID : 9C60 +[0002] Subdevice ID : 0000 +[0002] Revision : 0002 +[0002] Reserved : 0000 +[0004] Shared Info Length : 0000001C + +[0002] Major Version : 0001 +[0002] Minor Version : 0000 +[0004] MMIO Base Address Low : B3A00000 +[0004] MMIO Base Address High : 00000000 +[0004] GSI Interrupt : 0000002A +[0001] Interrupt Polarity : 02 +[0001] Interrupt Mode : 00 +[0001] Num Channels : 06 +[0001] DMA Address Width : 20 +[0002] Base Request Line : 0000 +[0002] Num Handshake Signals : 0010 +[0004] Max Block Size : 00000FFF + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0001 +[0004] UID : 20495053 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 30414843 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 31414843 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 32414843 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 33414843 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 34414843 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 35414843 + +[0004] Length : 000000A0 +[0004] Vendor ID : 4C544E49 +[0004] Subvendor ID : 00000000 +[0002] Device ID : 9C60 +[0002] Subdevice ID : 0000 +[0002] Revision : 0003 +[0002] Reserved : 0000 +[0004] Shared Info Length : 0000001C + +[0002] Major Version : 0001 +[0002] Minor Version : 0000 +[0004] MMIO Base Address Low : 00000000 +[0004] MMIO Base Address High : 00000000 +[0004] GSI Interrupt : 0000002B +[0001] Interrupt Polarity : 02 +[0001] Interrupt Mode : 00 +[0001] Num Channels : 08 +[0001] DMA Address Width : 20 +[0002] Base Request Line : 0010 +[0002] Num Handshake Signals : 0010 +[0004] Max Block Size : 00000FFF + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0001 +[0004] UID : 20433249 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 30414843 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 31414843 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 32414843 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 33414843 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 34414843 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 35414843 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 36414843 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 37414843 diff --git a/platforms/rtsm_ve-aemv8a.acpi/dbgp.asl b/platforms/rtsm_ve-aemv8a.acpi/dbgp.asl new file mode 100644 index 0000000..d1a826f --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/dbgp.asl @@ -0,0 +1,29 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [DBGP] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "DBGP" [Debug Port table] +[0004] Table Length : 00000034 +[0001] Revision : 01 +[0001] Checksum : 1A +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0001] Interface Type : 00 +[0003] Reserved : 000000 + +[0012] Debug Port Register : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + diff --git a/platforms/rtsm_ve-aemv8a.acpi/dmar.asl b/platforms/rtsm_ve-aemv8a.acpi/dmar.asl new file mode 100644 index 0000000..e10c8c3 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/dmar.asl @@ -0,0 +1,68 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [DMAR] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "DMAR" [DMA Remapping table] +[0004] Table Length : 0000008C +[0001] Revision : 01 +[0001] Checksum : 15 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0001] Host Address Width : 2F +[0001] Flags : 01 + +[0002] Subtable Type : 0000 [Hardware Unit Definition] +[0002] Length : 0018 +[0001] Flags : 01 +[0001] Reserved : 00 +[0002] PCI Segment Number : 0000 +[0008] Register Base Address : 00000000FD020000 + +[0001] Device Scope Entry Type : 03 +[0001] Entry Length : 08 +[0002] Reserved : 0000 +[0001] Enumeration ID : 08 +[0001] PCI Bus Number : F0 +[0002] PCI Path : 1F,07 + +[0002] Subtable Type : 0001 [Reserved Memory Region] +[0002] Length : 0020 +[0002] Reserved : 0000 +[0002] PCI Segment Number : 0000 +[0008] Base Address : 0000000078C21000 +[0008] End Address (limit) : 0000000078C23FFF + +[0001] Device Scope Entry Type : 01 +[0001] Entry Length : 08 +[0002] Reserved : 0000 +[0001] Enumeration ID : 00 +[0001] PCI Bus Number : 00 +[0002] PCI Path : 1D,00 + +[0002] Subtable Type : 0002 [Root Port ATS Capability] +[0002] Length : 0010 +[0001] Flags : 00 +[0001] Reserved : 00 +[0002] PCI Segment Number : 0000 + +[0001] Device Scope Entry Type : 02 +[0001] Entry Length : 08 +[0002] Reserved : 0000 +[0001] Enumeration ID : 00 +[0001] PCI Bus Number : 00 +[0002] PCI Path : 01,00 + +[0002] Subtable Type : 0003 [Remapping Hardware Static Affinity] +[0002] Length : 0014 +[0004] Reserved : 00000000 +[0008] Base Address : 00000000FD020000 +[0004] Proximity Domain : 00000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/dsdt.asl b/platforms/rtsm_ve-aemv8a.acpi/dsdt.asl new file mode 100644 index 0000000..daefcd8 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/dsdt.asl @@ -0,0 +1,234 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [DSDT] Description of the Arndale board (exynos5250) + * + * This source is released under the terms of the GPLv2. + */ + +DefinitionBlock ( + "dsdt.aml", // output filename + "DSDT", // table signature + 1, // DSDT compliance revision + "LINARO", // OEM ID + "RTSMVEV8", // table ID + 0x00000002) // OEM revision +{ + Scope (\_SB) + { + Device (SCK0) + { + Name (_HID, "ACPI0004") + Name (_UID, 0x00) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Device (PRC0) + { + Name (_HID, "ACPI0007") + Name (_UID, 0x00) + + /* CPU0 will be always present */ + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (MAT0, Buffer (0x28) + { + /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* type, len, reserved, gic_id */ + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, /* uid, flags */ + /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* parking_version, performance_interrupt */ + /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* parked_address */ + /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* base_address */ + }) + + Name (MAT1, Buffer (0x28) + { + /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }) + + Method (_MAT, 0, NotSerialized) + { + If (_STA()) + { + Return (MAT0) + } + Else + { + Return (MAT1) + } + } + } + + Device (PRC1) + { + Name (_HID, "ACPI0007") + Name (_UID, 0x01) + + Name (STA1, 0x0F) + Method (_STA, 0, NotSerialized) + { + Return (STA1) + } + + Method (_EJ0, 1, NotSerialized) + { + If (LEqual (STA1, 0x0F)) + { + Store (0x00, STA1) + } + } + + Name (MAT0, Buffer (0x28) + { + /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + /* 0008 */ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, + /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }) + + Name (MAT1, Buffer (0x28) + { + /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + /* 0008 */ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }) + + Method (_MAT, 0, NotSerialized) + { + If (_STA()) + { + Return (MAT0) + } + Else + { + Return (MAT1) + } + } + } + + Device (PRC2) + { + Name (_HID, "ACPI0007") + Name (_UID, 0x02) + + Name (STA2, 0x0F) + Method (_STA, 0, NotSerialized) + { + Return (STA2) + } + + Method (_EJ0, 1, NotSerialized) + { + If (LEqual (STA2, 0x0F)) + { + Store (0x00, STA2) + } + } + + Name (MAT0, Buffer (0x28) + { + /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, + /* 0008 */ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, + /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }) + + Name (MAT1, Buffer (0x28) + { + /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, + /* 0008 */ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, + /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }) + + Method (_MAT, 0, NotSerialized) + { + If (_STA()) + { + Return (MAT0) + } + Else + { + Return (MAT1) + } + } + } + + Device (PRC3) + { + Name (_HID, "ACPI0007") + Name (_UID, 0x03) + + Name (STA3, 0x0F) + Method (_STA, 0, NotSerialized) + { + Return (STA3) + } + + Method (_EJ0, 1, NotSerialized) + { + If (LEqual (STA3, 0x0F)) + { + Store (0x00, STA3) + } + } + + Name (MAT0, Buffer (0x28) + { + /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, + /* 0008 */ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01, + /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }) + + Name (MAT1, Buffer (0x28) + { + /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, + /* 0008 */ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, + /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }) + + Method (_MAT, 0, NotSerialized) + { + If (_STA()) + { + Return (MAT0) + } + Else + { + Return (MAT1) + } + } + } + } + + Device (NET0) { + Name (_HID, "LINA0003") + Name (_UID, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x1a000000, 0x00010000) + Interrupt (ResourceConsumer, Edge, ActiveBoth, Exclusive, , , ) {0x2F} + }) + Return (RBUF) + } + } + } +} diff --git a/platforms/rtsm_ve-aemv8a.acpi/ecdt.asl b/platforms/rtsm_ve-aemv8a.acpi/ecdt.asl new file mode 100644 index 0000000..75ffdc4 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/ecdt.asl @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [ECDT] Embedded Controller Boot Resources Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "ECDT" +[0004] Table Length : 00000042 +[0001] Revision : 01 +[0001] Checksum : 2D +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + + +[0012] Command/Status Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000066 + +[0012] Data Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000062 + +[0004] UID : 00000000 +[0001] GPE Number : 09 +[0001] Namepath : "" diff --git a/platforms/rtsm_ve-aemv8a.acpi/einj.asl b/platforms/rtsm_ve-aemv8a.acpi/einj.asl new file mode 100644 index 0000000..e2d3f5e --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/einj.asl @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [EINJ] Error Injection Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source released under the terms of the GPLv2. + */ + +[0004] Signature : "EINJ" +[0004] Table Length : 00000130 +[0001] Revision : 01 +[0001] Checksum : 09 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Injection Header Length : 00000030 +[0001] Flags : 00 +[0003] Reserved : 000000 +[0004] Injection Entry Count : 0000000A + +[0001] Action : 00 [Begin Operation] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 01 [Get Trigger Table] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 02 [Set Error Type] +[0001] Instruction : 02 [Write Register] +[0001] Flags (decoded below) : 01 + Preserve Register Bits : 1 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 03 [Get Error Type] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 04 [End Operation] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 01 + Preserve Register Bits : 1 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 05 [Execute Operation] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 01 + Preserve Register Bits : 1 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 10 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 02 [Word Access:16] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 06 [Check Busy Status] +[0001] Instruction : 01 [Read Register Value] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 07 [Get Command Status] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 01 + Preserve Register Bits : 1 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF diff --git a/platforms/rtsm_ve-aemv8a.acpi/erst.asl b/platforms/rtsm_ve-aemv8a.acpi/erst.asl new file mode 100644 index 0000000..a453eab --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/erst.asl @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [ERST] Error Record Serialization Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source released under the terms of the GPLv2. + */ + +[0004] Signature : "ERST" +[0004] Table Length : 00000230 +[0001] Revision : 01 +[0001] Checksum : AB +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Serialization Header Length : 00000030 +[0004] Reserved : 00000000 +[0004] Instruction Entry Count : 00000010 + +[0001] Action : 00 [Begin Write Operation] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 01 [Begin Read Operation] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 02 [Begin Clear Operation] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 03 [End Operation] +[0001] Instruction : 04 [Noop] +[0001] Flags (decoded below) : 01 + Preserve Register Bits : 1 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 04 [Set Record Offset] +[0001] Instruction : 02 [Write Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 05 [Execute Operation] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 06 [Check Busy Status] +[0001] Instruction : 01 [Read Register Value] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 07 [Get Command Status] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 08 [Get Record Identifier] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 09 [Set Record Identifier] +[0001] Instruction : 02 [Write Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 0A [Get Record Count] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 0B [Begin Dummy Write] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 0C [Unused/Unknown Action] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 0D [Get Error Address Range] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 0E [Get Error Address Length] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 0F [Get Error Attributes] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF diff --git a/platforms/rtsm_ve-aemv8a.acpi/facp.asl b/platforms/rtsm_ve-aemv8a.acpi/facp.asl new file mode 100644 index 0000000..c4713fe --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/facp.asl @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [FACP] ACPI Table + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "FACP" +[0004] Table Length : 0000010C +[0001] Revision : 05 +[0001] Checksum : 18 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20111123 + +[0004] FACS Address : 00000000 +[0004] DSDT Address : 00000010 +[0001] Model : 00 +[0001] PM Profile : 04 /* Enterprise Server */ +[0002] SCI Interrupt : 0000 +[0004] SMI Command Port : 00000000 +[0001] ACPI Enable Value : 00 +[0001] ACPI Disable Value : 00 +[0001] S4BIOS Command : 00 +[0001] P-State Control : 00 +[0004] PM1A Event Block Address : 00000001 +[0004] PM1B Event Block Address : 00000000 +[0004] PM1A Control Block Address : 00000001 +[0004] PM1B Control Block Address : 00000000 +[0004] PM2 Control Block Address : 00000001 +[0004] PM Timer Block Address : 00000001 +[0004] GPE0 Block Address : 00000001 +[0004] GPE1 Block Address : 00000000 +[0001] PM1 Event Block Length : 04 +[0001] PM1 Control Block Length : 02 +[0001] PM2 Control Block Length : 01 +[0001] PM Timer Block Length : 04 +[0001] GPE0 Block Length : 08 +[0001] GPE1 Block Length : 00 +[0001] GPE1 Base Offset : 00 +[0001] _CST Support : 00 +[0002] C2 Latency : 0000 +[0002] C3 Latency : 0000 +[0002] CPU Cache Size : 0000 +[0002] Cache Flush Stride : 0000 +[0001] Duty Cycle Offset : 00 +[0001] Duty Cycle Width : 00 +[0001] RTC Day Alarm Index : 00 +[0001] RTC Month Alarm Index : 00 +[0001] RTC Century Index : 00 +[0002] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[0001] Reserved : 00 +[0004] Flags (decoded below) : 00000000 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 1 + All CPUs support C1 (V1) : 0 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 1 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 0 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 1 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 0 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 1 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 1 + Low Power S0 Idle (V5) : 1 + +[0012] Reset Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000001 + +[0001] Value to cause reset : 00 +[0003] Reserved : 000000 +[0008] FACS Address : 0000000000000000 +[0008] DSDT Address : 0000000000000010 +[0012] PM1A Event Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 20 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 02 [Word Access:16] +[0008] Address : 0000000000000001 + +[0012] PM1B Event Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM1A Control Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 10 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 02 [Word Access:16] +[0008] Address : 0000000000000001 + +[0012] PM1B Control Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM2 Control Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000001 + +[0012] PM Timer Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 20 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 03 [DWord Access:32] +[0008] Address : 0000000000000001 + +[0012] GPE0 Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 80 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000001 + +[0012] GPE1 Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + + +[0012] Sleep Control Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000000 + +[0012] Sleep Status Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000000 + diff --git a/platforms/rtsm_ve-aemv8a.acpi/facs.asl b/platforms/rtsm_ve-aemv8a.acpi/facs.asl new file mode 100644 index 0000000..8d12b41 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/facs.asl @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [FACS] ACPI Table + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "FACS" +[0004] Length : 00000040 +[0004] Hardware Signature : 00000000 +[0004] 32 Firmware Waking Vector : 00000000 +[0004] Global Lock : 00000000 +[0004] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[0008] 64 Firmware Waking Vector : 0000000000000000 +[0001] Version : 02 +[0003] Reserved : 000000 +[0004] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 diff --git a/platforms/rtsm_ve-aemv8a.acpi/fpdt.asl b/platforms/rtsm_ve-aemv8a.acpi/fpdt.asl new file mode 100644 index 0000000..2b691b6 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/fpdt.asl @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [FPDT] Firmware Performance Data Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source released under the terms of the GPLv2. + */ + +[0004] Signature : "FPDT" +[0004] Table Length : 00000064 +[0001] Revision : 01 +[0001] Checksum : BD +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110804 + + +[0002] Subtable Type : 0000 +[0001] Length : 30 +[0001] Revision : 01 +[0004] Reserved : 00000000 +[0008] Reset End : 0000000000000000 +[0008] Load Image Start : 0000000000000000 +[0008] Start Image Start : 0000000000000000 +[0008] Exit Services Entry : 0000000000000000 +[0008] Exit Services Exit : 0000000000000000 + +[0002] Subtable Type : 0001 +[0001] Length : 10 +[0001] Revision : 01 +[0004] Reserved : 00000000 +[0008] S3PT Address : 0000000000000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl b/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl new file mode 100644 index 0000000..ff2c08a --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [GTDT] Generic Timer Description Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "GTDT" +[0004] Table Length : 00000050 +[0001] Revision : 01 +[0001] Checksum : F1 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110623 + +[0008] Timer Address : 0000000000000000 +[0004] Flags (decoded below) : 00000001 + Memory Present : 1 + +[0004] Secure PL1 Interrupt : 00000000 +[0004] SPL1 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + +[0004] Non-Secure PL1 Interrupt : 00000000 +[0004] NSPL1 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + +[0004] Virtual Timer Interrupt : 00000000 +[0004] VT Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + +[0004] Non-Secure PL2 Interrupt : 00000000 +[0004] NSPL2 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 diff --git a/platforms/rtsm_ve-aemv8a.acpi/hest.asl b/platforms/rtsm_ve-aemv8a.acpi/hest.asl new file mode 100644 index 0000000..05ddb24 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/hest.asl @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org + * + * [HEST] Hardware Error Source Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "HEST" +[0004] Table Length : 000001D4 +[0001] Revision : 01 +[0001] Checksum : 20 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Error Source Count : 00000004 + +[0002] Subtable Type : 0000 [IA-32 Machine Check Exception] +[0002] Source Id : 0000 +[0002] Reserved1 : 0000 +[0001] Flags (decoded below) : 00 + Firmware First : 0 +[0001] Enabled : 01 +[0004] Records To Preallocate : 00000001 +[0004] Max Sections Per Record : 00000001 +[0008] Global Capability Data : 0000000000000000 +[0008] Global Control Data : 0000000000000000 +[0001] Num Hardware Banks : 02 +[0007] Reserved2 : 00000000000000 + +[0001] Bank Number : 00 +[0001] Clear Status On Init : 00 +[0001] Status Format : 00 +[0001] Reserved : 00 +[0004] Control Register : 00000000 +[0008] Control Data : 0000000000000000 +[0004] Status Register : 00000000 +[0004] Address Register : 00000000 +[0004] Misc Register : 00000000 + +[0001] Bank Number : 01 +[0001] Clear Status On Init : 00 +[0001] Status Format : 00 +[0001] Reserved : 00 +[0004] Control Register : 00000000 +[0008] Control Data : 0000000000000000 +[0004] Status Register : 00000000 +[0004] Address Register : 00000000 +[0004] Misc Register : 00000000 + +[0002] Subtable Type : 0001 [IA-32 Corrected Machine Check] +[0002] Source Id : 0001 +[0002] Reserved1 : 0000 +[0001] Flags (decoded below) : 00 + Firmware First : 0 +[0001] Enabled : 01 +[0004] Records To Preallocate : 00000001 +[0004] Max Sections Per Record : 00000001 + +[0028] Notify : [Hardware Error Notification Structure] +[0001] Notify Type : 00 [Polled] +[0001] Notify Length : 00 +[0002] Configuration Write Enable : 0000 +[0004] PollInterval : 00000000 +[0004] Vector : 00000000 +[0004] Polling Threshold Value : 00000000 +[0004] Polling Threshold Window : 00000000 +[0004] Error Threshold Value : 00000000 +[0004] Error Threshold Window : 00000000 + +[0001] Num Hardware Banks : 02 +[0003] Reserved2 : 000000 + +[0001] Bank Number : 00 +[0001] Clear Status On Init : 00 +[0001] Status Format : 00 +[0001] Reserved : 00 +[0004] Control Register : 00000000 +[0008] Control Data : 0000000000000000 +[0004] Status Register : 00000000 +[0004] Address Register : 00000000 +[0004] Misc Register : 00000000 + +[0001] Bank Number : 01 +[0001] Clear Status On Init : 00 +[0001] Status Format : 00 +[0001] Reserved : 00 +[0004] Control Register : 00000000 +[0008] Control Data : 0000000000000000 +[0004] Status Register : 00000000 +[0004] Address Register : 00000000 +[0004] Misc Register : 00000000 + +[0002] Subtable Type : 0007 [PCI Express AER (AER Endpoint)] +[0002] Source Id : 0000 +[0002] Reserved : 0000 +[0001] Flags (decoded below) : 00 + Firmware First : 0 +[0001] Enabled : 01 +[0004] Records To Preallocate : 00000001 +[0004] Max Sections Per Record : 00000001 +[0004] Bus : 00000000 +[0002] Device : 0000 +[0002] Function : 0000 +[0002] DeviceControl : 0000 +[0002] Reserved : 0000 +[0004] Uncorrectable Mask : 00000000 +[0004] Uncorrectable Severity : 00000000 +[0004] Correctable Mask : 00000000 +[0004] Advanced Capabilities : 00000000 + +[0002] Subtable Type : 0008 [PCI Express/PCI-X Bridge AER] +[0002] Source Id : 0000 +[0002] Reserved : 0000 +[0001] Flags (decoded below) : 00 + Firmware First : 0 +[0001] Enabled : 01 +[0004] Records To Preallocate : 00000001 +[0004] Max Sections Per Record : 00000001 +[0004] Bus : 00000000 +[0002] Device : 0000 +[0002] Function : 0000 +[0002] DeviceControl : 0000 +[0002] Reserved : 0000 +[0004] Uncorrectable Mask : 00000000 +[0004] Uncorrectable Severity : 00000000 +[0004] Correctable Mask : 00000000 +[0004] Advanced Capabilities : 00000000 +[0004] 2nd Uncorrectable Mask : 00000000 +[0004] 2nd Uncorrectable Severity : 00000000 +[0004] 2nd Advanced Capabilities : 00000000 + +[0002] Subtable Type : 0009 [Generic Hardware Error Source] +[0002] Source Id : 0002 +[0002] Related Source Id : FFFF +[0001] Reserved : 00 +[0001] Enabled : 01 +[0004] Records To Preallocate : 00000001 +[0004] Max Sections Per Record : 00000001 +[0004] Max Raw Data Length : 00001000 + +[0012] Error Status Address : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0028] Notify : [Hardware Error Notification Structure] +[0001] Notify Type : 03 [SCI] +[0001] Notify Length : 1C +[0002] Configuration Write Enable : 0000 +[0004] PollInterval : 00000000 +[0004] Vector : 00000000 +[0004] Polling Threshold Value : 00000000 +[0004] Polling Threshold Window : 00000000 +[0004] Error Threshold Value : 00000000 +[0004] Error Threshold Window : 00000000 + +[0004] Error Status Block Length : 00001000 + +[0002] Subtable Type : 0009 [Generic Hardware Error Source] +[0002] Source Id : 0003 +[0002] Related Source Id : 0000 +[0001] Reserved : 00 +[0001] Enabled : 01 +[0004] Records To Preallocate : 00000001 +[0004] Max Sections Per Record : 00000001 +[0004] Max Raw Data Length : 00001000 + +[0012] Error Status Address : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0028] Notify : [Hardware Error Notification Structure] +[0001] Notify Type : 04 [NMI] +[0001] Notify Length : 1C +[0002] Configuration Write Enable : 0000 +[0004] PollInterval : 00000000 +[0004] Vector : 00000000 +[0004] Polling Threshold Value : 00000000 +[0004] Polling Threshold Window : 00000000 +[0004] Error Threshold Value : 00000000 +[0004] Error Threshold Window : 00000000 + +[0004] Error Status Block Length : 00001000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/hpet.asl b/platforms/rtsm_ve-aemv8a.acpi/hpet.asl new file mode 100644 index 0000000..c150282 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/hpet.asl @@ -0,0 +1,33 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [HPET] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "HPET" [High Precision Event Timer table] +[0004] Table Length : 00000038 +[0001] Revision : 01 +[0001] Checksum : 09 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Hardware Block ID : 00000000 + +[0012] Timer Block Register : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0001] Sequence Number : 00 +[0002] Minimum Clock Ticks : 0000 +[0001] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 diff --git a/platforms/rtsm_ve-aemv8a.acpi/ivrs.asl b/platforms/rtsm_ve-aemv8a.acpi/ivrs.asl new file mode 100644 index 0000000..9f64314 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/ivrs.asl @@ -0,0 +1,86 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [IVRS] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "IVRS" [I/O Virtualization Reporting Structure] +[0004] Table Length : 000000BC +[0001] Revision : 01 +[0001] Checksum : 87 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Virtualization Info : 00000000 +[0008] Reserved : 0000000000000000 + +[0001] Subtable Type : 10 [Hardware Definition Block] +[0001] Flags : 14 +[0002] Length : 0034 +[0002] DeviceId : 0000 + +[0002] Capability Offset : 0000 +[0008] Base Address : 0000000000000000 +[0002] PCI Segment Group : 0000 +[0002] Virtualization Info : 0000 +[0004] Reserved : 00000000 + +[0001] Entry Type : 00 +[0002] Device ID : 0000 +[0001] Data Setting : 00 + +[0001] Entry Type : 40 +[0002] Device ID : 0000 +[0001] Data Setting : 00 +[0004] Extended Data : 00000000 + +[0001] Entry Type : 42 +[0002] Device ID : 0000 +[0001] Data Setting : 00 +[0001] Reserved : 00 +[0002] Source Used Device ID : 0000 +[0001] Reserved : 00 + +[0001] Entry Type : 48 +[0002] Device ID : 0000 +[0001] Data Setting : 00 +[0001] Handle : 00 +[0002] Source Used Device ID : 0000 +[0001] Variety : 00 + +[0001] Subtable Type : 20 [Memory Definition Block] +[0001] Flags : 08 +[0002] Length : 0020 +[0002] DeviceId : 0000 + +[0002] Auxiliary Data : 0000 +[0008] Reserved : 0000000000000000 +[0008] Start Address : 0000000000000000 +[0008] Memory Length : 0000000000000000 + +[0001] Subtable Type : 21 [Memory Definition Block] +[0001] Flags : 04 +[0002] Length : 0020 +[0002] DeviceId : 0000 + +[0002] Auxiliary Data : 0000 +[0008] Reserved : 0000000000000000 +[0008] Start Address : 0000000000000000 +[0008] Memory Length : 0000000000000000 + +[0001] Subtable Type : 10 [Hardware Definition Block] +[0001] Flags : 14 +[0002] Length : 0018 +[0002] DeviceId : 0000 + +[0002] Capability Offset : 0000 +[0008] Base Address : 0000000000000000 +[0002] PCI Segment Group : 0000 +[0002] Virtualization Info : 0000 +[0004] Reserved : 00000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/mcfg.asl b/platforms/rtsm_ve-aemv8a.acpi/mcfg.asl new file mode 100644 index 0000000..cee9d6f --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/mcfg.asl @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [MCFG] PCIe Memory Mapped Configuration Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "MCFG" +[0004] Table Length : 0000003C +[0001] Revision : 01 +[0001] Checksum : 19 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0008] Reserved : 0000000000000000 + +[0008] Base Address : 0000000000000000 +[0002] Segment Group Number : 0000 +[0001] Start Bus Number : 00 +[0001] End Bus Number : 00 +[0004] Reserved : 00000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/mchi.asl b/platforms/rtsm_ve-aemv8a.acpi/mchi.asl new file mode 100644 index 0000000..2154c51 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/mchi.asl @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [MCHI] Management Controller Host Interface Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source released under the terms of the GPLv2. + */ + +[0004] Signature : "MCHI" +[0004] Table Length : 00000045 +[0001] Revision : 01 +[0001] Checksum : E4 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 02000715 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0001] Interface Type : 01 +[0001] Protocol : 00 +[0008] Protocol Data : 0000000000000000 +[0001] Interrupt Type : 00 +[0001] Gpe : 00 +[0001] Pci Device Flag : 00 +[0004] Global Interrupt : 00000000 + +[0012] Control Register : [Generic Address Structure] +[0001] Space ID : 02 [PCI_Config] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0001] Pci Segment : 00 +[0001] Pci Bus : 00 +[0001] Pci Device : 00 +[0001] Pci Function : 00 diff --git a/platforms/rtsm_ve-aemv8a.acpi/mpst.asl b/platforms/rtsm_ve-aemv8a.acpi/mpst.asl new file mode 100644 index 0000000..1c6933b --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/mpst.asl @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [MPST] Memory Power State Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "MPST" +[0004] Table Length : 000000B6 +[0001] Revision : 01 +[0001] Checksum : 77 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20120913 + +[0001] Channel ID : 00 +[0003] Reserved : 000000 +[0002] Power Node Count : 0002 +[0002] Reserved : 0000 + +[0001] Flags (decoded below) : 00 + Node Enabled : 0 + Power Managed : 0 + Hot Plug Capable : 0 +[0001] Reserved : 00 +[0002] Node ID : 0000 +[0004] Length : 00000000 +[0008] Range Address : 0000000000000000 +[0008] Range Length : 0000000000000000 +[0004] Num Power States : 00000002 +[0004] Num Physical Components : 00000003 + +[0001] Power State : 00 +[0001] InfoIndex : 00 + +[0001] Power State : 00 +[0001] InfoIndex : 00 + +[0002] Component Id : 0000 +[0002] Component Id : 0001 +[0002] Component Id : 0002 + +[0001] Flags (decoded below) : 00 + Node Enabled : 0 + Power Managed : 0 + Hot Plug Capable : 0 +[0001] Reserved : 00 +[0002] Node ID : 0000 +[0004] Length : 00000000 +[0008] Range Address : 0000000000000000 +[0008] Range Length : 0000000000000000 +[0004] Num Power States : 00000001 +[0004] Num Physical Components : 00000001 + +[0001] Power State : 00 +[0001] InfoIndex : 00 + +[0002] Component Id : 0000 + +[0002] Characteristics Count : 0002 +[0002] Reserved : 0000 + +[0001] Structure ID : 01 +[0001] Flags (decoded below) : 00 + Memory Preserved : 0 + Auto Entry : 0 + Auto Exit : 0 +[0002] Reserved : 0000 +[0004] Average Power : 00000000 +[0004] Power Saving : 00000000 +[0008] Exit Latency : 0000000000000000 +[0008] Reserved : 0000000000000000 + +[0001] Structure ID : 01 +[0001] Flags (decoded below) : 00 + Memory Preserved : 0 + Auto Entry : 0 + Auto Exit : 0 +[0002] Reserved : 0000 +[0004] Average Power : 00000000 +[0004] Power Saving : 00000000 +[0008] Exit Latency : 0000000000000000 +[0008] Reserved : 0000000000000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/msct.asl b/platforms/rtsm_ve-aemv8a.acpi/msct.asl new file mode 100644 index 0000000..dcaf33f --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/msct.asl @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [MSCT] Maximum System Characteristics Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source released under the terms of the GPLv2. + */ + +[0004] Signature : "MSCT" +[0004] Table Length : 00000090 +[0001] Revision : 01 +[0001] Checksum : B7 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Proximity Offset : 00000038 +[0004] Max Proximity Domains : 00000003 +[0004] Max Clock Domains : 00000000 +[0008] Max Physical Address : 00000FFFFFFFFFFF + +[0001] Revision : 01 +[0001] Length : 16 +[0004] Domain Range Start : 00000000 +[0004] Domain Range End : 00000003 +[0004] Processor Capacity : 00000010 +[0008] Memory Capacity : 0000004000000000 + +[0001] Revision : 01 +[0001] Length : 16 +[0004] Domain Range Start : 00000000 +[0004] Domain Range End : 00000000 +[0004] Processor Capacity : 00000000 +[0008] Memory Capacity : 0000000000000000 + +[0001] Revision : 01 +[0001] Length : 16 +[0004] Domain Range Start : 00000000 +[0004] Domain Range End : 00000000 +[0004] Processor Capacity : 00000000 +[0008] Memory Capacity : 0000000000000000 + +[0001] Revision : 01 +[0001] Length : 16 +[0004] Domain Range Start : 00000000 +[0004] Domain Range End : 00000000 +[0004] Processor Capacity : 00000000 +[0008] Memory Capacity : 0000000000000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/oem0.asl b/platforms/rtsm_ve-aemv8a.acpi/oem0.asl new file mode 100644 index 0000000..570ea27 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/oem0.asl @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [OEMx] OEM Specific Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "OEM0" +[0004] Table Length : 00000024 +[0001] Revision : 01 +[0001] Checksum : 8B +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 0000000A +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 diff --git a/platforms/rtsm_ve-aemv8a.acpi/pmtt.asl b/platforms/rtsm_ve-aemv8a.acpi/pmtt.asl new file mode 100644 index 0000000..a9c5c93 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/pmtt.asl @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [PMTT] Platform Memory Topology Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "PMTT" +[0004] Table Length : 000000B4 +[0001] Revision : 01 +[0001] Checksum : 3A +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110826 + +[0004] Reserved : 00000000 + +[0001] Subtable Type : 00 [Socket] +[0001] Reserved : 00 +[0002] Length : 0080 +[0002] Flags (decoded below) : 0001 + Top-level Device : 1 + Physical Element : 0 + Memory Type : 0 +[0002] Reserved : 0000 +[0002] Socket ID : 0000 +[0002] Reserved : 0000 + +[0001] Subtable Type : 01 [Memory Controller] +[0001] Reserved : 00 +[0002] Length : 0054 +[0002] Flags (decoded below) : 0005 + Top-level Device : 1 + Physical Element : 0 + Memory Type : 1 +[0002] Reserved : 0000 +[0004] Read Latency : 00000000 +[0004] Write Latency : 00000000 +[0004] Read Bandwidth : 00000000 +[0004] Write Bandwidth : 00000000 +[0002] Access Width : 0000 +[0002] Alignment : 0000 +[0002] Reserved : 0000 +[0002] Domain Count : 0003 +[0004] Proximity Domain : 00000000 +[0004] Proximity Domain : 00000000 +[0004] Proximity Domain : 00000000 + +[0001] Subtable Type : 02 [Physical Component (DIMM)] +[0001] Reserved : 00 +[0002] Length : 0014 +[0002] Flags (decoded below) : 0002 + Top-level Device : 0 + Physical Element : 1 + Memory Type : 0 +[0002] Reserved : 0000 +[0002] Component ID : 0000 +[0002] Reserved : 0000 +[0004] Memory Size : 00000000 +[0004] Bios Handle : 00000000 + +[0001] Subtable Type : 02 [Physical Component (DIMM)] +[0001] Reserved : 00 +[0002] Length : 0014 +[0002] Flags (decoded below) : 0002 + Top-level Device : 0 + Physical Element : 1 + Memory Type : 0 +[0002] Reserved : 0000 +[0002] Component ID : 0000 +[0002] Reserved : 0000 +[0004] Memory Size : 00000000 +[0004] Bios Handle : 00000000 + +[0001] Subtable Type : 01 [Memory Controller] +[0001] Reserved : 00 +[0002] Length : 0020 +[0002] Flags (decoded below) : 0001 + Top-level Device : 1 + Physical Element : 0 + Memory Type : 0 +[0002] Reserved : 0000 +[0004] Read Latency : 00000000 +[0004] Write Latency : 00000000 +[0004] Read Bandwidth : 00000000 +[0004] Write Bandwidth : 00000000 +[0002] Access Width : 0000 +[0002] Alignment : 0000 +[0002] Reserved : 0000 +[0002] Domain Count : 0000 + +[0001] Subtable Type : 00 [Socket] +[0001] Reserved : 00 +[0002] Length : 000C +[0002] Flags (decoded below) : 0001 + Top-level Device : 1 + Physical Element : 0 + Memory Type : 0 +[0002] Reserved : 0000 +[0002] Socket ID : 0000 +[0002] Reserved : 0000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/rsdp.asl b/platforms/rtsm_ve-aemv8a.acpi/rsdp.asl new file mode 100644 index 0000000..3460a77 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/rsdp.asl @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [RSDP] ACPI Table + * + * This source is released under the terms of the GPLv2. + */ + +[0008] Signature : "RSD PTR " +[0001] Checksum : 43 +[0006] Oem ID : "LINARO" +[0001] Revision : 02 +[0004] RSDT Address : 00000000 +[0004] Length : 00000024 +[0008] XSDT Address : 0000000000000000 +[0001] Extended Checksum : DC +[0003] Reserved : 000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest b/platforms/rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest new file mode 100644 index 0000000..6b3a743 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest @@ -0,0 +1,34 @@ +# +# Each line is either a comment, white space, or two fields: +# +# <signature> : <ASL file name> +# +# NB: for each file x.asl, an AML file called x.aml will be created +# + +rsdp: rsdp.asl +xsdt: xsdt.asl +facp: facp.asl +dsdt: dsdt.asl +ssdt: ssdt0.asl +bert: bert.asl +ecdt: ecdt.asl +facs: facs.asl +gtdt: gtdt.asl +hest: hest.asl +apic: apic.asl +mcfg: mcfg.asl +mpst: mpst.asl +oem: oem0.asl +pmmt: pmmt.asl +slit: slit.asl +spmi: spmi.asl +srat: srat.asl +uefi: uefi.asl +cpep: cpep.asl +einj: einj.asl +erst: erst.asl +fpdt: fpdt.asl +mchi: mchi.asl +msct: msct.asl + diff --git a/platforms/rtsm_ve-aemv8a.acpi/s3pt.asl b/platforms/rtsm_ve-aemv8a.acpi/s3pt.asl new file mode 100644 index 0000000..694caf7 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/s3pt.asl @@ -0,0 +1,26 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [S3PT] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "S3PT" [S3 Performance Table] +[0004] Length : 00000034 + +[0002] Type : 0000 +[0001] Length : 18 +[0001] Revision : 01 + +[0004] Resume Count : 00000000 +[0008] Full Resume : 0000000000000000 +[0008] Average Resume : 0000000000000000 + +[0002] Type : 0001 +[0001] Length : 14 +[0001] Revision : 01 + +[0008] Suspend Start : 0000000000000000 +[0008] Suspend End : 0000000000000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/sbst.asl b/platforms/rtsm_ve-aemv8a.acpi/sbst.asl new file mode 100644 index 0000000..714b15f --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/sbst.asl @@ -0,0 +1,22 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [SBST] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "SBST" [Smart Battery Specification Table] +[0004] Table Length : 00000030 +[0001] Revision : 01 +[0001] Checksum : 06 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Warning Level : 00000000 +[0004] Low Level : 00000000 +[0004] Critical Level : 00000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/slic.asl b/platforms/rtsm_ve-aemv8a.acpi/slic.asl new file mode 100644 index 0000000..df77bf2 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/slic.asl @@ -0,0 +1,56 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [SLIC] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "SLIC" [Software Licensing Description Table] +[0004] Table Length : 00000176 +[0001] Revision : 01 +[0001] Checksum : 07 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110211 + + +[0004] Subtable Type : 00000000 [Public Key Structure] +[0004] Length : 0000009C + +[0001] Key Type : 06 +[0001] Version : 02 +[0002] Reserved : 0000 +[0004] Algorithm : 00002400 +[0004] Magic : "RSA1" +[0004] BitLength : 00000400 +[0004] Exponent : 00000000 +[0128] Modulus : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +[0004] Subtable Type : 00000001 [Windows Marker Structure] +[0004] Length : 000000B6 + +[0004] Version : 00020000 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0008] Windows Flag : "WINDOWS " +[0004] SLIC Version : 00020001 +[0016] Reserved : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +[0128] Signature : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/platforms/rtsm_ve-aemv8a.acpi/slit.asl b/platforms/rtsm_ve-aemv8a.acpi/slit.asl new file mode 100644 index 0000000..c34e4bb --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/slit.asl @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [SLIT] System Locality Information Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "SLIT" +[0004] Table Length : 000001BC +[0001] Revision : 01 +[0001] Checksum : 00 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110316 + +[0008] Localities : 0000000000000014 +[0020] Locality 0 : 0A 10 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 \ + 24 25 26 27 +[0020] Locality 1 : 10 0A 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 \ + 23 24 25 26 +[0020] Locality 2 : 16 15 0A 10 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 \ + 22 23 24 25 +[0020] Locality 3 : 17 16 10 0A 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 \ + 21 22 23 24 +[0020] Locality 4 : 18 17 16 15 0A 10 16 17 18 19 1A 1B 1C 1D 1E 1F \ + 20 21 22 23 +[0020] Locality 5 : 19 18 17 16 10 0A 15 16 17 18 19 1A 1B 1C 1D 1E \ + 1F 20 21 22 +[0020] Locality 6 : 1A 19 18 17 16 15 0A 10 16 17 18 19 1A 1B 1C 1D \ + 1E 1F 20 21 +[0020] Locality 7 : 1B 1A 19 18 17 16 10 0A 15 16 17 18 19 1A 1B 1C \ + 1D 1E 1F 20 +[0020] Locality 8 : 1C 1B 1A 19 18 17 16 15 0A 10 16 17 18 19 1A 1B \ + 1C 1D 1E 1F +[0020] Locality 9 : 1D 1C 1B 1A 19 18 17 16 10 0A 15 16 17 18 19 1A \ + 1B 1C 1D 1E +[0020] Locality 10 : 1E 1D 1C 1B 1A 19 18 17 16 15 0A 10 16 17 18 19 \ + 1A 1B 1C 1D +[0020] Locality 11 : 1F 1E 1D 1C 1B 1A 19 18 17 16 10 0A 15 16 17 18 \ + 19 1A 1B 1C +[0020] Locality 12 : 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 0A 10 16 17 \ + 18 19 1A 1B +[0020] Locality 13 : 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 10 0A 15 16 \ + 17 18 19 1A +[0020] Locality 14 : 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 0A 10 \ + 16 17 18 19 +[0020] Locality 15 : 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 10 0A \ + 15 16 17 18 +[0020] Locality 16 : 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 \ + 0A 10 16 17 +[0020] Locality 17 : 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 \ + 10 0A 15 16 +[0020] Locality 18 : 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 \ + 16 15 0A 10 +[0020] Locality 19 : 27 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 \ + 17 16 10 0A diff --git a/platforms/rtsm_ve-aemv8a.acpi/spcr.asl b/platforms/rtsm_ve-aemv8a.acpi/spcr.asl new file mode 100644 index 0000000..7998ba8 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/spcr.asl @@ -0,0 +1,46 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [SPCR] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "SPCR" [Serial Port Console Redirection table] +[0004] Table Length : 00000050 +[0001] Revision : 01 +[0001] Checksum : E3 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0001] Interface Type : 00 +[0003] Reserved : 000000 + +[0012] Serial Port Register : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0001] Interrupt Type : 00 +[0001] PCAT-compatible IRQ : 00 +[0004] Interrupt : 00000000 +[0001] Baud Rate : 00 +[0001] Parity : 00 +[0001] Stop Bits : 00 +[0001] Flow Control : 00 +[0001] Terminal Type : 00 +[0001] Reserved : 00 +[0002] PCI Device ID : 0000 +[0002] PCI Vendor ID : 0000 +[0001] PCI Bus : 00 +[0001] PCI Device : 00 +[0001] PCI Function : 00 +[0004] PCI Flags : 00000000 +[0001] PCI Segment : 00 +[0004] Reserved : 00000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/spmi.asl b/platforms/rtsm_ve-aemv8a.acpi/spmi.asl new file mode 100644 index 0000000..a9f244d --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/spmi.asl @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org + * + * [SPMI] Server Platform Management Interface Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "SPMI" +[0004] Table Length : 00000041 +[0001] Revision : 04 +[0001] Checksum : ED +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0001] Interface Type : 00 +[0001] Reserved : 00 +[0002] IPMI Spec Version : 0000 +[0001] Interrupt Type : 00 +[0001] GPE Number : 00 +[0001] Reserved : 00 +[0001] PCI Device Flag : 00 +[0004] Interrupt : 00000000 + +[0012] IPMI Register : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000000 + +[0001] PCI Segment : 00 +[0001] PCI Bus : 00 +[0001] PCI Device : 00 +[0001] PCI Function : 00 +[0001] Reserved : 00 diff --git a/platforms/rtsm_ve-aemv8a.acpi/srat.asl b/platforms/rtsm_ve-aemv8a.acpi/srat.asl new file mode 100644 index 0000000..6d549c3 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/srat.asl @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [SRAT] System Resource Affinity Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "SRAT" +[0004] Table Length : 00000080 +[0001] Revision : 03 +[0001] Checksum : 5A +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Table Revision : 00000001 +[0008] Reserved : 0000000000000000 + +[0001] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[0001] Length : 10 + +[0001] Proximity Domain Low(8) : 00 +[0001] Apic ID : 00 +[0004] Flags (decoded below) : 00000001 + Enabled : 1 +[0001] Local Sapic EID : 00 +[0003] Proximity Domain High(24) : 000000 +[0004] Reserved : 00000000 + +[0001] Subtable Type : 01 [Memory Affinity] +[0001] Length : 28 + +[0004] Proximity Domain : 00000000 +[0002] Reserved1 : 0000 +[0008] Base Address : 0000000000000000 +[0008] Address Length : 000000000009FC00 +[0004] Reserved2 : 00000000 +[0004] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[0008] Reserved3 : 0000000000000000 + +[0001] Subtable Type : 02 [Processor Local x2APIC Affinity] +[0001] Length : 18 + +[0002] Reserved1 : 0000 +[0004] Proximity Domain : 00000000 +[0004] Apic ID : 00000000 +[0004] Flags (decoded below) : 00000001 + Enabled : 1 +[0004] Clock Domain : 00000000 +[0004] Reserved2 : 00000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl b/platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl new file mode 100644 index 0000000..8975977 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [SSDT] Description of the Arndale board (exynos5250) GPIO structure + * + * This source is released under the terms of the GPLv2. + */ + +DefinitionBlock ( + "ssdt0.aml", // output filename + "SSDT", // table signature + 2, // SSDT compliance revision + "LINARO", // OEM ID + "RTSMVEV8", // table ID + 0x00000001) // OEM revision +{ +} diff --git a/platforms/rtsm_ve-aemv8a.acpi/tcpa.asl b/platforms/rtsm_ve-aemv8a.acpi/tcpa.asl new file mode 100644 index 0000000..cfdfa39 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/tcpa.asl @@ -0,0 +1,22 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [TCPA] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "TCPA" [Trusted Computing Platform Alliance table] +[0004] Table Length : 00000032 +[0001] Revision : 01 +[0001] Checksum : 67 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00003180 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0002] Reserved : 0000 +[0004] Max Event Log Length : 00000000 +[0008] Event Log Address : 0000000000000001 diff --git a/platforms/rtsm_ve-aemv8a.acpi/tpm2.asl b/platforms/rtsm_ve-aemv8a.acpi/tpm2.asl new file mode 100644 index 0000000..38cc502 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/tpm2.asl @@ -0,0 +1,22 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [TPM2] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "TPM2" [Trusted Platform Module hardware interface table] +[0004] Table Length : 00000034 +[0001] Revision : 03 +[0001] Checksum : 42 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20121114 + +[0004] Flags : 00000000 +[0008] Control Address : 0011223344556677 +[0004] Start Method : 00000001 diff --git a/platforms/rtsm_ve-aemv8a.acpi/uefi.asl b/platforms/rtsm_ve-aemv8a.acpi/uefi.asl new file mode 100644 index 0000000..855e330 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/uefi.asl @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [UEFI] UEFI Boot Optimization Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "UEFI" +[0004] Table Length : 00000036 +[0001] Revision : 01 +[0001] Checksum : 9B +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0016] UUID Identifier : 03020100-0504-0706-0809-0A0B0C0D0E0F +[0002] Data Offset : 0000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/waet.asl b/platforms/rtsm_ve-aemv8a.acpi/waet.asl new file mode 100644 index 0000000..b459110 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/waet.asl @@ -0,0 +1,22 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [WAET] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[0004] Table Length : 00000028 +[0001] Revision : 01 +[0001] Checksum : 19 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Flags (decoded below) : 00000000 + RTC needs no INT ack : 0 + PM timer, one read only : 0 diff --git a/platforms/rtsm_ve-aemv8a.acpi/wdat.asl b/platforms/rtsm_ve-aemv8a.acpi/wdat.asl new file mode 100644 index 0000000..e49205a --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/wdat.asl @@ -0,0 +1,47 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [WDAT] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "WDAT" [Watchdog Action Table] +[0004] Table Length : 0000005C +[0001] Revision : 01 +[0001] Checksum : E3 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Header Length : 00000020 +[0002] PCI Segment : 00FF +[0001] PCI Bus : FF +[0001] PCI Device : FF +[0001] PCI Function : FF +[0003] Reserved : 000000 +[0004] Timer Period : 00000258 +[0004] Max Count : 000003FF +[0004] Min Count : 00000002 +[0001] Flags (decoded below) : 00 + Enabled : 0 + Stopped When Asleep : 0 +[0003] Reserved : 000000 +[0004] Watchdog Entry Count : 0000000E + +[0001] Watchdog Action : 01 +[0001] Instruction : 02 +[0002] Reserved : 0000 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 10 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 02 [Word Access:16] +[0008] Address : 0000000000000460 + +[0004] Value : 00000001 +[0004] Register Mask : 00000001 diff --git a/platforms/rtsm_ve-aemv8a.acpi/wddt.asl b/platforms/rtsm_ve-aemv8a.acpi/wddt.asl new file mode 100644 index 0000000..a0b039e --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/wddt.asl @@ -0,0 +1,44 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [WDDT] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "WDDT" [Watchdog Description Table] +[0004] Table Length : 00000040 +[0001] Revision : 01 +[0001] Checksum : 00 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0002] Specification Version : 0000 +[0002] Table Version : 0000 +[0002] PCI Vendor ID : 0000 + +[0012] Timer Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : FF +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0002] Max Count : 0000 +[0002] Min Count : 0000 +[0002] Period : 0000 +[0002] Status (decoded below) : 0000 + Available : 0 + Active : 0 + OS Owns : 0 + User Reset : 0 + Timeout Reset : 0 + Power Fail Reset : 0 + Unknown Reset : 0 +[0002] Capability (decoded below) : 0000 + Auto Reset : 0 + Timeout Alert : 0 diff --git a/platforms/rtsm_ve-aemv8a.acpi/wdrt.asl b/platforms/rtsm_ve-aemv8a.acpi/wdrt.asl new file mode 100644 index 0000000..14453c7 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/wdrt.asl @@ -0,0 +1,42 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [WDRT] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "WDRT" [Watchdog Resource Table] +[0004] Table Length : 00000047 +[0001] Revision : 01 +[0001] Checksum : B0 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + + +[0012] Control Register : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 20 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] Count Register : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 20 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0002] PCI Device ID : FFFF +[0002] PCI Vendor ID : FFFF +[0001] PCI Bus : 00 +[0001] PCI Device : 00 +[0001] PCI Function : 00 +[0001] PCI Segment : 00 +[0002] Max Count : FFFF +[0001] Counter Units : 00 diff --git a/platforms/rtsm_ve-aemv8a.acpi/xsdt.asl b/platforms/rtsm_ve-aemv8a.acpi/xsdt.asl new file mode 100644 index 0000000..74f0c70 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/xsdt.asl @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [XSDT] Extended System Description Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "XSDT" +[0004] Table Length : 00000064 +[0001] Revision : 01 +[0001] Checksum : 8B +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000014 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0008] ACPI Table Address 0 : 0000000000000010 +[0008] ACPI Table Address 0 : 0000000000000020 +[0008] ACPI Table Address 0 : 0000000000000030 +[0008] ACPI Table Address 0 : 0000000000000040 +[0008] ACPI Table Address 0 : 0000000000000050 +[0008] ACPI Table Address 0 : 0000000000000060 +[0008] ACPI Table Address 0 : 0000000000000070 +[0008] ACPI Table Address 0 : 0000000000000080 +[0008] ACPI Table Address 0 : 0000000000000090 +[0008] ACPI Table Address 0 : 00000000000000A0 +[0008] ACPI Table Address 0 : 00000000000000B0 +[0008] ACPI Table Address 0 : 00000000000000C0 +[0008] ACPI Table Address 0 : 00000000000000D0 +[0008] ACPI Table Address 0 : 00000000000000E0 +[0008] ACPI Table Address 0 : 00000000000000F0 +[0008] ACPI Table Address 0 : 0000000000000100 +[0008] ACPI Table Address 0 : 0000000000000110 +[0008] ACPI Table Address 0 : 0000000000000120 +[0008] ACPI Table Address 0 : 0000000000000130 +[0008] ACPI Table Address 0 : 0000000000000140 -- 1.7.10.4

11 years, 8 months

[PATCHv2] meta-linaro: acpica: fix style issues

by Graeme Gregory

Fix recipe to be OE compliant with spacing SRCREV and PV. Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org> --- meta-linaro/recipes-extra/acpica/acpica_20130626.bb | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/meta-linaro/recipes-extra/acpica/acpica_20130626.bb b/meta-linaro/recipes-extra/acpica/acpica_20130626.bb index 58d7c4b..e4218fd 100644 --- a/meta-linaro/recipes-extra/acpica/acpica_20130626.bb +++ b/meta-linaro/recipes-extra/acpica/acpica_20130626.bb @@ -1,21 +1,20 @@ +SUMMARY = "ACPICA tools for the development and debug of ACPI tables" DESCRIPTION = "The ACPI Component Architecture (ACPICA) project provides an \ OS-independent reference implementation of the Advanced Configuration and \ Power Interface Specification (ACPI). ACPICA code contains those portions of \ ACPI meant to be directly integrated into the host OS as a kernel-resident \ subsystem, and a small set of tools to assist in developing and debugging \ ACPI tables." -SUMMARY = "ACPICA tools for the development and debug of ACPI tables" HOMEPAGE = "http://www.acpica.org/" SECTION = "console/tools" LICENSE = "BSD | GPLv2" LIC_FILES_CHKSUM = "file://generate/unix/readme.txt;md5=204407e197c1a01154a48f6c6280c3aa" -DEPENDS="bison \ - flex" -COMPATIBLE_HOST = "(i.86|x86_64|arm|aarch64).*-linux" - -PR="r2" +DEPENDS = "bison flex" +SRCREV = "780de9ee36e5a7b4acc29a2ccd43d6bdc5dd5219" +PV = "20130626+git${SRCPV}" +PR = "r3" -SRC_URI="git://git.linaro.org/people/ahs3/acpica-tools.git \ +SRC_URI = "git://git.linaro.org/people/ahs3/acpica-tools.git \ file://fix_ftbfs_debian-kfreebsd.patch \ file://debian-big_endian.patch \ file://debian-unaligned.patch \ @@ -27,8 +26,6 @@ SRC_URI="git://git.linaro.org/people/ahs3/acpica-tools.git \ file://no-werror.patch \ file://fix-parallel-build.patch" -SRCREV = "${AUTOREV}" - S = "${WORKDIR}/git" EXTRA_OEMAKE = "'OPT_CFLAGS=-Wall'" @@ -42,3 +39,6 @@ do_install() { install -D -p -m0755 generate/unix/bin*/acpisrc ${D}${bindir}/acpisrc install -D -p -m0755 generate/unix/bin*/acpixtract ${D}${bindir}/acpixtract } + +COMPATIBLE_HOST = "(i.86|x86_64|arm|aarch64).*-linux" + -- 1.7.10.4

11 years, 8 months

[RFC][PATCH 1/2] ARM64: add cpu topology definition

by Hanjun Guo

Power aware scheduling needs the cpu topology information to improve the cpu scheduler decision making. For ARM64, we can get the topology from the MPIDR register which defines the the affinity of processors. This patch is mainly based on arch/arm/kernel/topology.c written by Vincent Guittot, and replaced the topology array with per cpu variable. Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org> --- arch/arm64/Kconfig | 9 +++ arch/arm64/include/asm/cputype.h | 11 ++++ arch/arm64/include/asm/topology.h | 41 ++++++++++++ arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/smp.c | 6 ++ arch/arm64/kernel/topology.c | 128 +++++++++++++++++++++++++++++++++++++ 6 files changed, 196 insertions(+) create mode 100644 arch/arm64/include/asm/topology.h create mode 100644 arch/arm64/kernel/topology.c diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 9737e97..f0ce91b 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -150,6 +150,15 @@ config SMP If you don't know what to do here, say N. +config ARM64_CPU_TOPOLOGY + bool "Support cpu topology definition" + depends on SMP && ARM64 + default y + help + Support ARM64 cpu topology definition. The MPIDR register defines + affinity between processors which is then used to describe the cpu + topology of an ARM64 System. + config NR_CPUS int "Maximum number of CPUs (2-32)" range 2 32 diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 5fe138e..68b55af 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -30,6 +30,17 @@ #define MPIDR_HWID_BITMASK 0xff00ffffff +#define MPIDR_SMP_BITMASK (0x1 << 30) +#define MPIDR_MT_BITMASK (0x1 << 24) + +#define MPIDR_LEVEL_BITS 8 +#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) + +#define MPIDR_AFFINITY_LEVEL_0(mpidr) ((mpidr) & MPIDR_LEVEL_MASK) +#define MPIDR_AFFINITY_LEVEL_1(mpidr) ((mpidr >> 8) & MPIDR_LEVEL_MASK) +#define MPIDR_AFFINITY_LEVEL_2(mpidr) ((mpidr >> 16) & MPIDR_LEVEL_MASK) +#define MPIDR_AFFINITY_LEVEL_3(mpidr) ((mpidr >> 32) & MPIDR_LEVEL_MASK) + #define read_cpuid(reg) ({ \ u64 __val; \ asm("mrs %0, " reg : "=r" (__val)); \ diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h new file mode 100644 index 0000000..8631808 --- /dev/null +++ b/arch/arm64/include/asm/topology.h @@ -0,0 +1,41 @@ +#ifndef _ASM_ARM64_TOPOLOGY_H +#define _ASM_ARM64_TOPOLOGY_H + +#ifdef CONFIG_ARM64_CPU_TOPOLOGY + +#include <linux/cpumask.h> + +struct cputopo_arm64 { + int thread_id; + int core_id; + int socket_id; + cpumask_t thread_sibling; + cpumask_t core_sibling; +}; + +DECLARE_PER_CPU(struct cputopo_arm64, cpu_topology); + +#define cpu_topo(cpu) per_cpu(cpu_topology, cpu) + +#define topology_physical_package_id(cpu) (cpu_topo(cpu).socket_id) +#define topology_core_id(cpu) (cpu_topo(cpu).core_id) +#define topology_core_cpumask(cpu) (&cpu_topo(cpu).core_sibling) +#define topology_thread_cpumask(cpu) (&cpu_topo(cpu).thread_sibling) + +#define mc_capable() (cpu_topo(0).socket_id != -1) +#define smt_capable() (cpu_topo(0).thread_id != -1) + +void init_cpu_topology(void); +void store_cpu_topology(unsigned int cpuid); +const struct cpumask *cpu_coregroup_mask(int cpu); + +#else + +static inline void init_cpu_topology(void) { } +static inline void store_cpu_topology(unsigned int cpuid) { } + +#endif + +#include <asm-generic/topology.h> + +#endif /* _ASM_ARM64_TOPOLOGY_H */ diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index 7b4b564..a47c359 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -18,6 +18,7 @@ arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o smp_psci.o arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)+= hw_breakpoint.o arm64-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o +arm64-obj-$(CONFIG_ARM64_CPU_TOPOLOGY) += topology.o obj-y += $(arm64-obj-y) vdso/ obj-m += $(arm64-obj-m) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index fee5cce..197b1da 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -39,6 +39,7 @@ #include <asm/atomic.h> #include <asm/cacheflush.h> #include <asm/cputype.h> +#include <asm/topology.h> #include <asm/mmu_context.h> #include <asm/pgtable.h> #include <asm/pgalloc.h> @@ -215,6 +216,8 @@ asmlinkage void secondary_start_kernel(void) local_irq_enable(); local_fiq_enable(); + store_cpu_topology(cpu); + /* * OK, it's off to the idle thread for us */ @@ -387,6 +390,9 @@ void __init smp_prepare_cpus(unsigned int max_cpus) int cpu, err; unsigned int ncores = num_possible_cpus(); + init_cpu_topology(); + store_cpu_topology(smp_processor_id()); + /* * are we trying to boot more cores than exist? */ diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c new file mode 100644 index 0000000..1eb0435 --- /dev/null +++ b/arch/arm64/kernel/topology.c @@ -0,0 +1,128 @@ +/* + * arch/arm64/kernel/topology.c + * + * Copyright (C) 2013 Linaro Limited. + * Written by: Hanjun Guo + * + * based on arch/arm/kernel/topology.c + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/cpu.h> +#include <linux/cpumask.h> +#include <linux/init.h> +#include <linux/percpu.h> +#include <linux/sched.h> + +#include <asm/cputype.h> +#include <asm/topology.h> + +DEFINE_PER_CPU(struct cputopo_arm64, cpu_topology); + +const struct cpumask *cpu_coregroup_mask(int cpu) +{ + return &cpu_topo(cpu).core_sibling; +} + +void update_siblings_masks(unsigned int cpuid) +{ + struct cputopo_arm64 *topo, *cpuid_topo = &cpu_topo(cpuid); + int cpu; + + /* update core and thread sibling masks */ + for_each_possible_cpu(cpu) { + topo = &cpu_topo(cpu); + + if (cpuid_topo->socket_id != topo->socket_id) + continue; + + cpumask_set_cpu(cpuid, &topo->core_sibling); + if (cpu != cpuid) + cpumask_set_cpu(cpu, &cpuid_topo->core_sibling); + + if (cpuid_topo->core_id != topo->core_id) + continue; + + cpumask_set_cpu(cpuid, &topo->thread_sibling); + if (cpu != cpuid) + cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling); + } + smp_wmb(); +} + +/* + * store_cpu_topology is called at boot when only one cpu is running + * and with the mutex cpu_hotplug.lock locked, when several cpus have booted, + * which prevents simultaneous write access to cpu_topology array + */ +void store_cpu_topology(unsigned int cpuid) +{ + struct cputopo_arm64 *cpuid_topo = &cpu_topo(cpuid); + u64 mpidr; + + /* If the cpu topology has been already set, just return */ + if (cpuid_topo->core_id != -1) + return; + + mpidr = read_cpuid_mpidr(); + + /* create cpu topology mapping */ + if (!(mpidr & MPIDR_SMP_BITMASK)) { + /* + * This is a multiprocessor system + * multiprocessor format & multiprocessor mode field are set + */ + + if (mpidr & MPIDR_MT_BITMASK) { + /* core performance interdependency */ + cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL_0(mpidr); + cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL_1(mpidr); + cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL_2(mpidr); + } else { + /* largely independent cores */ + cpuid_topo->thread_id = -1; + cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL_0(mpidr); + cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL_1(mpidr); + } + } else { + /* + * This is an uniprocessor system + * we are in multiprocessor format but uniprocessor system + * or in the old uniprocessor format + */ + cpuid_topo->thread_id = -1; + cpuid_topo->core_id = 0; + cpuid_topo->socket_id = -1; + } + + update_siblings_masks(cpuid); + + printk(KERN_INFO "CPU%u: thread %d, cpu %d, socket %d, mpidr 0x%llx\n", + cpuid, cpu_topo(cpuid).thread_id, + cpu_topo(cpuid).core_id, + cpu_topo(cpuid).socket_id, mpidr); +} + +/* + * init_cpu_topology is called at boot when only one cpu is running + * which prevent simultaneous write access to cpu_topology array + */ +void __init init_cpu_topology(void) +{ + unsigned int cpu; + + /* init core mask */ + for_each_possible_cpu(cpu) { + struct cputopo_arm64 *topo = &cpu_topo(cpu); + + topo->thread_id = -1; + topo->core_id = -1; + topo->socket_id = -1; + cpumask_clear(&topo->core_sibling); + cpumask_clear(&topo->thread_sibling); + } + smp_wmb(); +} -- 1.7.9.5

11 years, 8 months

[PATCH] ACPICA:enable 64bit build for aarch64 architecture

by naresh.bhat＠linaro.org

From: Naresh Bhat <naresh.bhat(a)linaro.org> Signed-off-by: Naresh Bhat <naresh.bhat(a)linaro.org> Enable 64 bit build for aarch64 architecture in ACPICA Linux platform specific defines. --- source/include/platform/aclinux.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/include/platform/aclinux.h b/source/include/platform/aclinux.h index e561292..6b8b1ab 100644 --- a/source/include/platform/aclinux.h +++ b/source/include/platform/aclinux.h @@ -159,7 +159,7 @@ #define ACPI_FLUSH_CPU_CACHE() #define ACPI_CAST_PTHREAD_T(pthread) ((ACPI_THREAD_ID) (pthread)) -#if defined(__ia64__) || defined(__x86_64__) +#if defined(__ia64__) || defined(__x86_64__) || (__aarch64__) #define ACPI_MACHINE_WIDTH 64 #define COMPILER_DEPENDENT_INT64 long #define COMPILER_DEPENDENT_UINT64 unsigned long -- 1.7.9.5

11 years, 8 months

[PATCH] ACPICA:enable 64bit build for aarch64 architecture

by naresh.bhat＠linaro.org

From: Naresh Bhat <naresh.bhat(a)linaro.org> Signed-off-by: Naresh Bhat <naresh.bhat(a)linaro.org> Enable 64 bit build for aarch64 architecture in ACPICA Linux platform specific defines. --- src/acpica/source/include/platform/aclinux.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/acpica/source/include/platform/aclinux.h b/src/acpica/source/include/platform/aclinux.h index e561292..6b8b1ab 100644 --- a/src/acpica/source/include/platform/aclinux.h +++ b/src/acpica/source/include/platform/aclinux.h @@ -159,7 +159,7 @@ #define ACPI_FLUSH_CPU_CACHE() #define ACPI_CAST_PTHREAD_T(pthread) ((ACPI_THREAD_ID) (pthread)) -#if defined(__ia64__) || defined(__x86_64__) +#if defined(__ia64__) || defined(__x86_64__) || (__aarch64__) #define ACPI_MACHINE_WIDTH 64 #define COMPILER_DEPENDENT_INT64 long #define COMPILER_DEPENDENT_UINT64 unsigned long -- 1.7.9.5

11 years, 8 months

[PATCH 0/3] acpi-asl.git: various mab bug repairs

by al.stone＠linaro.org

From: Al Stone <ahs3(a)redhat.com> This is complete reorganization of what used to be "Various fix-ups and additions to mab" patches 3 and 4 (5 has been completely rethought as a seperate series to appear later). What this patch does is add in a change log that should have been there all along, and comment the versioning a little better. The more substantial bug fix is that code that checked whether there was enough room in the XSDT for all the tables being added would only do so when verbose mode was being used. This error check now occurs under all conditions as it should have. Al Stone (3): mab: add in a Changelog to improve documentation mab: report an XSDT error regardless of whether we're verbose or not mab: update version number (and comment it better) tools/mab/Changelog | 9 +++++++++ tools/mab/mab.c | 19 +++++++++++-------- tools/mab/mab.h | 3 ++- 3 files changed, 22 insertions(+), 9 deletions(-) create mode 100644 tools/mab/Changelog -- 1.8.3.1

11 years, 8 months

[PATCH 0/5] Various fix-ups and additions to mab

by al.stone＠linaro.org

From: Al Stone <ahs3(a)redhat.com> These are mostly minor fixups to mab: -- report usage properly -- do not segfault if missing the -p <paddr> parameter -- if the XSDT did not have enough room for tables, it would not discover that or notify anyone unless it was being verbose; now it will always report that error if found -- and just because it wasn't verbose enough, add the final relocated address of the table to the output -- update the version number Al Stone (5): mab: minor cleanup of usage output mab: if -p <paddr> is not given, we would segfault; die more gracefully now mab: update version number mab: report an XSDT error regardless of whether we're verbose or not mab: add final relocated address to verbose output tools/mab/mab.c | 52 ++++++++++++++++++++++++++++++++++++---------------- tools/mab/mab.h | 4 +++- 2 files changed, 39 insertions(+), 17 deletions(-) -- 1.8.3.1

11 years, 8 months

[PATCH] meta-linaro: acpica: fix style issues

by Graeme Gregory

Fix recipe to be OE complient with spacing SRCREV and PV. Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org> --- meta-aarch64/conf/machine/genericarmv8.conf | 8 ++++---- meta-linaro/recipes-extra/acpica/acpica_20130626.bb | 18 +++++++++--------- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/meta-aarch64/conf/machine/genericarmv8.conf b/meta-aarch64/conf/machine/genericarmv8.conf index 6d84e0d..ab8900e 100644 --- a/meta-aarch64/conf/machine/genericarmv8.conf +++ b/meta-aarch64/conf/machine/genericarmv8.conf @@ -23,15 +23,15 @@ PREFERRED_PROVIDER_virtual/kernel ?= "linux-linaro" KERNEL_IMAGETYPE = "Image" # We have to disable SERIAL_CONSOLE due to auto-serial-console -#SERIAL_CONSOLE = "115200 ttyAMA0" +SERIAL_CONSOLE = "115200 ttyAMA0" # Force auto-serial-console to be used by all image types # Ideally this would be part of core oe or as a bbclassappend, # but as we don't have an easy way to append a class, defining # it here -EXTRA_IMAGE_FEATURES += "autoserial" -PACKAGE_GROUP_autoserial = "auto-serial-console" +#EXTRA_IMAGE_FEATURES += "autoserial" +#PACKAGE_GROUP_autoserial = "auto-serial-console" # we do not want to have getty running on tty1 as we run # auto-serial-console there -USE_VT = "0" +#USE_VT = "0" diff --git a/meta-linaro/recipes-extra/acpica/acpica_20130626.bb b/meta-linaro/recipes-extra/acpica/acpica_20130626.bb index 58d7c4b..e4218fd 100644 --- a/meta-linaro/recipes-extra/acpica/acpica_20130626.bb +++ b/meta-linaro/recipes-extra/acpica/acpica_20130626.bb @@ -1,21 +1,20 @@ +SUMMARY = "ACPICA tools for the development and debug of ACPI tables" DESCRIPTION = "The ACPI Component Architecture (ACPICA) project provides an \ OS-independent reference implementation of the Advanced Configuration and \ Power Interface Specification (ACPI). ACPICA code contains those portions of \ ACPI meant to be directly integrated into the host OS as a kernel-resident \ subsystem, and a small set of tools to assist in developing and debugging \ ACPI tables." -SUMMARY = "ACPICA tools for the development and debug of ACPI tables" HOMEPAGE = "http://www.acpica.org/" SECTION = "console/tools" LICENSE = "BSD | GPLv2" LIC_FILES_CHKSUM = "file://generate/unix/readme.txt;md5=204407e197c1a01154a48f6c6280c3aa" -DEPENDS="bison \ - flex" -COMPATIBLE_HOST = "(i.86|x86_64|arm|aarch64).*-linux" - -PR="r2" +DEPENDS = "bison flex" +SRCREV = "780de9ee36e5a7b4acc29a2ccd43d6bdc5dd5219" +PV = "20130626+git${SRCPV}" +PR = "r3" -SRC_URI="git://git.linaro.org/people/ahs3/acpica-tools.git \ +SRC_URI = "git://git.linaro.org/people/ahs3/acpica-tools.git \ file://fix_ftbfs_debian-kfreebsd.patch \ file://debian-big_endian.patch \ file://debian-unaligned.patch \ @@ -27,8 +26,6 @@ SRC_URI="git://git.linaro.org/people/ahs3/acpica-tools.git \ file://no-werror.patch \ file://fix-parallel-build.patch" -SRCREV = "${AUTOREV}" - S = "${WORKDIR}/git" EXTRA_OEMAKE = "'OPT_CFLAGS=-Wall'" @@ -42,3 +39,6 @@ do_install() { install -D -p -m0755 generate/unix/bin*/acpisrc ${D}${bindir}/acpisrc install -D -p -m0755 generate/unix/bin*/acpixtract ${D}${bindir}/acpixtract } + +COMPATIBLE_HOST = "(i.86|x86_64|arm|aarch64).*-linux" + -- 1.7.10.4

11 years, 8 months

[PATCH v2] exynos5250-arndale: DSDT requires _CRS to be serialized

by al.stone＠linaro.org

From: Al Stone <ahs3(a)redhat.com> This patch applies to the acpi-asl.git tree. This corrects a minor error reported by iasl when compiling the DSDT for Arndale. The error is minor enough that iasl still produces a table but it could potentially affect operation. Changes for v2: -- added some sort of explanation for the patch Signed-off-by: Al Stone <al.stone(a)linaro.org> --- platforms/exynos5250-arndale.acpi/dsdt.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platforms/exynos5250-arndale.acpi/dsdt.asl b/platforms/exynos5250-arndale.acpi/dsdt.asl index 2cca765..7f05c6b 100644 --- a/platforms/exynos5250-arndale.acpi/dsdt.asl +++ b/platforms/exynos5250-arndale.acpi/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( Name (_HID, "LINA0001") Name (_UID, 0) - Method (_CRS, 0x0, NotSerialized) { + Method (_CRS, 0x0, Serialized) { Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x12C60000, 0x00000100) -- 1.8.3.1

11 years, 8 months

← Newer
1
...
71
72
73
74
75
76
77
...
82
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

Linaro-acpi