I would be quite careful about deriving either memory/cpu or powerdomain/cpu topology information from the MPIDR_EL1 register. Aside from the differences that exist when MPIDR_EL1[MT] is set, the AFF0 value is restricted to the range zero to 15 by the definition of the ICC_SGI0R_EL1 and ICC_SGI1R_EL1 registers which support a 16-bit mask for the aff0 level. This may result in a mapping such as the following for SoC's with more than 16-cores:
AFF0 = core-id % 16 AFF1 = core-id / 16 AFF2 = socket-id
Given that the PSCI specification uses affinity levels as power-domains, the following mapping may be more appropriate for certain SoC's:
AFF0 = core-within-power-domain % 16 AFF1 = core-within-power-domain / 16 AFF2 = power-domain-id-within-socket AFF3 = socket-id
Thus, I agree that ACPI tables (or potentially FDT) are the appropriate means of conveying both power-domain and memory/core topology from the platform firmware to the operating software as there is no ARM architectural definition for the affinity levels.
scott
________________________________________ From: linaro-acpi-bounces@lists.linaro.org linaro-acpi-bounces@lists.linaro.org on behalf of Hanjun Guo hanjun.guo@linaro.org Sent: Tuesday, July 30, 2013 3:08 AM To: linaro-acpi Subject: Re: [Linaro-acpi] [RFC][PATCH 1/2] ARM64: add cpu topology definition
Hi
It seems that the upstream will not accept my patch for cpu topology using MPIDR register, they raised another solution which get cpu topology from FDT.
I proposed another solution using ACPI to get the cpu topology, how do you think of this solution?
Thanks Hanjun
On 2013-7-30 1:23, Lorenzo Pieralisi wrote:
On Mon, Jul 29, 2013 at 02:36:30PM +0100, Dave Martin wrote:
On Mon, Jul 29, 2013 at 10:54:01AM +0100, Will Deacon wrote:
On Mon, Jul 29, 2013 at 10:46:06AM +0100, Vincent Guittot wrote:
On 27 July 2013 12:42, Hanjun Guo hanjun.guo@linaro.org wrote:
Power aware scheduling needs the cpu topology information to improve the cpu scheduler decision making.
It's not only power aware scheduling. The scheduler already uses topology and cache sharing when CONFIG_SCHED_MC and/or CONFIG_SCHED_SMT are enable. So you should also add these configs for arm64 so the scheduler can use it
... except that the architecture doesn't define what the AFF fields in MPIDR really represent. Using them to make key scheduling decisions relating to
In fact, the ARM Architecture doesn't place any requirements on MPIDRs to force the aff fields to exist _at all_. It's just a recommendation. Instead, you have a 24 or 32-bit number which is unique per CPU, and which is _probably_ assigned in a way resembling the aff fields.
cache proximity seems pretty risky to me, especially given the track record we've seen already on AArch32 silicon. It's a convenient register if it contains the data we want it to contain, but we need to force ourselves to come to terms with reality here and simply use it as an identifier for a CPU.
+1
Also, we should align arm and arm64. The problem is basically exactly the same, and the solution needs to be the same. struct cputopo_arm is already being abused -- for example, TC2 describes the A15 and A7 clusters on a single die as having different "socket_id" values, even though this is obviously nonsense. But there's no other way to describe that system today.
Can't we just use the device-tree to represent this topological data for arm64? Lorenzo has been working on bindings in this area.
This may become more important as we start to see things like asymmetric topologies appearing (different numbers of nodes and different interdependence characteristics in adjacent branches of the topology etc.)
Will and Dave summed up the existing issues with MPIDR definition related to the topology description.
FYI, a link to the current topology bindings posted on DT-discuss and LAKML:
https://lists.ozlabs.org/pipermail/devicetree-discuss/2013-April/031725.html
I am waiting for the dust to settle on the DT bindings review discussions to repost them and get them finalized.
Lorenzo
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