From: Al Stone ahs3@redhat.com
This builds on the prior Arndale GPIO patch by adding another controller to the ACPI configuration.
Signed-off-by: Al Stone al.stone@linaro.org --- platforms/exynos5250-arndale.acpi/ssdt0.asl | 156 +++++++++++++++++++++++++++- 1 file changed, 154 insertions(+), 2 deletions(-)
diff --git a/platforms/exynos5250-arndale.acpi/ssdt0.asl b/platforms/exynos5250-arndale.acpi/ssdt0.asl index 8b8efc7..48fa409 100644 --- a/platforms/exynos5250-arndale.acpi/ssdt0.asl +++ b/platforms/exynos5250-arndale.acpi/ssdt0.asl @@ -12,10 +12,162 @@ DefinitionBlock ( 2, // SSDT compliance revision "LINARO", // OEM ID "ARNDALE ", // table ID - 0x00000003) // OEM revision + 0x00000004) // OEM revision { Scope (_SB) { + // Base Address: 0x10d10000 + Device (SPC2) // Samsung pin controller + { + Name (_HID, "LINA0002") + Name (_UID, 0x2) + + Name (BNKS, 0x5) // number of pin banks + Name (NGRP, 0x2) // number of pin groups + + Method (_CRS, 0x0, Serialized) + { + // Base address for the pin controller + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x10d10000, + 0x20) + }) + Return (RBUF) + } + + Device (GPV0) // GPIO chip GPV0 -- first bank + { + Name (TAG, "gpv0") // human-readable name + Name (BASE, 0x0) // base pin number + Name (NPIN, 0x8) // number of pins + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x10d10000, + 0x20) + }) + Return (RBUF) + } + } + + Device (GPV1) // GPIO chip GPV1 + { + Name (TAG, "gpv1") // human-readable name + Name (BASE, 0x0) // base pin number + Name (NPIN, 0x8) // number of pins + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x10d10020, + 0x20) + }) + Return (RBUF) + } + } + + Device (GPV2) // GPIO chip GPV2 + { + Name (TAG, "gpv2") // human-readable name + Name (BASE, 0x0) // base pin number + Name (NPIN, 0x8) // number of pins + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x10d10060, + 0x20) + }) + Return (RBUF) + } + } + + Device (GPV3) // GPIO chip GPV3 + { + Name (TAG, "gpv3") // human-readable name + Name (BASE, 0x0) // base pin number + Name (NPIN, 0x8) // number of pins + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x10d10080, + 0x20) + }) + Return (RBUF) + } + } + + Device (GPV4) // GPIO chip GPV4 + { + Name (TAG, "gpv4") // human-readable name + Name (BASE, 0x0) // base pin number + Name (NPIN, 0x8) // number of pins + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x10d100c0, + 0x20) + }) + Return (RBUF) + } + } + + Device (C2RX) // First pin group + { + Name (NPIN, 0x10) // number of pins + Name (FUNC, 0x2) // function number + Name (PUD, 0x0) // direction + Name (DRV, 0x0) // drive + + Method (PINS, 0x0, NotSerialized) + { + Return (Package () { + "gpv0-0", "gpv0-1", "gpv0-2", + "gpv0-3", "gpv0-4", "gpv0-5", + "gpv0-6", "gpv0-7", + "gpv1-0", "gpv1-1", "gpv1-2", + "gpv1-3", "gpv1-4", "gpv1-5", + "gpv1-6", "gpv1-7", + }) + } + } + + Device (C2TX) // second pin group + { + Name (NPIN, 0x10) // number of pins + Name (FUNC, 0x2) // function number + Name (PUD, 0x0) // direction + Name (DRV, 0x0) // drive + + Method (PINS, 0x0, NotSerialized) + { + Return (Package () { + "gpv2-0", "gpv2-1", "gpv2-2", + "gpv2-3", "gpv2-4", "gpv2-5", + "gpv2-6", "gpv2-7", + "gpv3-0", "gpv3-1", "gpv3-2", + "gpv3-3", "gpv3-4", "gpv3-5", + "gpv3-6", "gpv3-7", + }) + } + } + } + // Base Address: 0x03860000 Device (SPC3) // Samsung pin controller { @@ -24,7 +176,6 @@ DefinitionBlock (
Name (BNKS, 0x1) // number of pin banks Name (NGRP, 0x1) // number of pin groups - Name (NFUN, 0x1) // number of pinmux functions
Method (_CRS, 0x0, Serialized) { @@ -65,6 +216,7 @@ DefinitionBlock ( Name (FUNC, 0x2) // function number Name (PUD, 0x0) // direction Name (DRV, 0x0) // drive + Method (PINS, 0x0, NotSerialized) { Return (Package () {