Hi Graeme,
Please have a look at the comments below.
On 2013-8-2 16:57, Graeme Gregory wrote:
Hi Hanjun,
I managed to apply this patch by hand, but foundation model does not boot with it.
[...]
CPU0: thread -1, cpu 0, socket 0, mpidr 0x80000000 hw perfevents: enabled with arm/armv8-pmuv3 PMU driver, 9 counters available CPU1: Booted secondary processor CPU1: thread -1, cpu 1, socket 0, mpidr 0x80000001 BUG: failure at kernel/smpboot.c:134/smpboot_thread_fn()! Kernel panic - not syncing: BUG! CPU: 0 PID: 11 Comm: ksoftirqd/1 Not tainted 3.11.0-rc3+ #234 Call trace: [<ffffffc000087064>] dump_backtrace+0x0/0x12c [<ffffffc0000871a4>] show_stack+0x14/0x1c [<ffffffc0003de54c>] dump_stack+0x70/0x8c [<ffffffc0003db7b4>] panic+0xe8/0x214 [<ffffffc0000ba96c>] smpboot_thread_fn+0x1b0/0x1c8 [<ffffffc0000b2f74>] kthread+0xb4/0xbc
[...]
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 5ec1723..36d09fe 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -39,6 +39,7 @@ #include <asm/atomic.h> #include <asm/cacheflush.h> #include <asm/cputype.h> +#include <asm/topology.h> #include <asm/mmu_context.h> #include <asm/pgtable.h> #include <asm/pgalloc.h> @@ -206,6 +207,8 @@ asmlinkage void __cpuinit secondary_start_kernel(void) local_irq_enable(); local_fiq_enable();
- store_cpu_topology(cpu);
I tested the patch on ARMv8 foundation model, it booted ok and work as expected if I add store_cpu_topology(cpu) in following two places (function [1]):
a) put it behind local_fiq_enable(); b) put it before set_cpu_online(cpu, true);
it will boot failed in you using "patch -p1 < 0001-xxx.patch", and the store_cpu_topology(cpu) will put just behind complete(&cpu_running);
I booted with the config you provided (config-armv8-3.11), and with MADT in the former acpi git tree.
It is weird, I haven't figure out why, that would be thankful if anybody gives me some hints.
Thanks Hanjun
[1]: asmlinkage void secondary_start_kernel(void) { struct mm_struct *mm = &init_mm; unsigned int cpu = smp_processor_id();
printk("CPU%u: Booted secondary processor\n", cpu);
/* * All kernel threads share the same mm context; grab a * reference and switch to it. */ atomic_inc(&mm->mm_count); current->active_mm = mm; cpumask_set_cpu(cpu, mm_cpumask(mm));
/* * TTBR0 is only used for the identity mapping at this stage. Make it * point to zero page to avoid speculatively fetching new entries. */ cpu_set_reserved_ttbr0(); flush_tlb_all();
preempt_disable(); trace_hardirqs_off();
/* * Let the primary processor know we're out of the * pen, then head off into the C entry point */ write_pen_release(INVALID_HWID);
/* * Synchronise with the boot thread. */ raw_spin_lock(&boot_lock); raw_spin_unlock(&boot_lock);
/* * OK, now it's safe to let the boot CPU continue. Wait for * the CPU migration code to notice that the CPU is online * before we continue. */ set_cpu_online(cpu, true); complete(&cpu_running);
/* * Enable GIC and timers. */ notify_cpu_starting(cpu);
local_irq_enable(); local_fiq_enable();
/* * OK, it's off to the idle thread for us */ cpu_startup_entry(CPUHP_ONLINE); }