On 2013-7-31 0:44, Lurndal, Scott wrote:
I would be quite careful about deriving either memory/cpu or powerdomain/cpu topology information from the MPIDR_EL1 register. Aside from the differences that exist when MPIDR_EL1[MT] is set, the AFF0 value is restricted to the range zero to 15 by the definition of the ICC_SGI0R_EL1 and ICC_SGI1R_EL1 registers which support a 16-bit mask for the aff0 level. This may result in a mapping such as the following for SoC's with more than 16-cores:
AFF0 = core-id % 16 AFF1 = core-id / 16 AFF2 = socket-id
Given that the PSCI specification uses affinity levels as power-domains, the following mapping may be more appropriate for certain SoC's:
AFF0 = core-within-power-domain % 16 AFF1 = core-within-power-domain / 16 AFF2 = power-domain-id-within-socket AFF3 = socket-id
This kind of mapping is different for different SoCs, I think this kind of code will be platform dependent which will not accepted by upstream.
Thus, I agree that ACPI tables (or potentially FDT) are the appropriate means of conveying both power-domain and memory/core topology from the platform firmware to the operating software as there is no ARM architectural definition for the affinity levels.
I can't agree with you more. :)
We already created a JIRA cards to do this in ACPI way: https://cards.linaro.org/browse/LEG-461
scott