Re: [Linaro-acpi] [PATCHv2] platforms: add rtsm_ve-aemv8a.acpi

On 08/26/2013 02:11 AM, Graeme Gregory wrote:

There are enough differences between this model and foundation model I think it is ok to be a different platform.

Signed-off-by: Graeme Gregory graeme.gregory@linaro.org

Minor whitespace issues:

Applying: platforms: add rtsm_ve-aemv8a.acpi .git/rebase-apply/patch:1156: new blank line at EOF. + .git/rebase-apply/patch:1895: new blank line at EOF. + warning: 2 lines add whitespace errors.

Otherwise...

Acked-by: Al Stone al.stone@linaro.org

platforms/rtsm_ve-aemv8a.acpi/.gitignore | 3 + platforms/rtsm_ve-aemv8a.acpi/apic.asl | 126 ++++++++++ platforms/rtsm_ve-aemv8a.acpi/bert.asl | 21 ++ platforms/rtsm_ve-aemv8a.acpi/cpep.asl | 26 ++ platforms/rtsm_ve-aemv8a.acpi/dsdt.asl | 234 +++++++++++++++++ platforms/rtsm_ve-aemv8a.acpi/ecdt.asl | 37 +++ platforms/rtsm_ve-aemv8a.acpi/einj.asl | 151 +++++++++++ platforms/rtsm_ve-aemv8a.acpi/erst.asl | 278 +++++++++++++++++++++ platforms/rtsm_ve-aemv8a.acpi/facp.asl | 167 +++++++++++++ platforms/rtsm_ve-aemv8a.acpi/facs.asl | 21 ++ platforms/rtsm_ve-aemv8a.acpi/fpdt.asl | 35 +++ platforms/rtsm_ve-aemv8a.acpi/gtdt.asl | 42 ++++ platforms/rtsm_ve-aemv8a.acpi/hest.asl | 193 ++++++++++++++ platforms/rtsm_ve-aemv8a.acpi/mcfg.asl | 26 ++ platforms/rtsm_ve-aemv8a.acpi/mchi.asl | 38 +++ platforms/rtsm_ve-aemv8a.acpi/mpst.asl | 87 +++++++ platforms/rtsm_ve-aemv8a.acpi/msct.asl | 51 ++++ platforms/rtsm_ve-aemv8a.acpi/oem0.asl | 18 ++ platforms/rtsm_ve-aemv8a.acpi/pmtt.asl | 105 ++++++++ platforms/rtsm_ve-aemv8a.acpi/rsdp.asl | 17 ++ .../rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest | 34 +++ platforms/rtsm_ve-aemv8a.acpi/slit.asl | 60 +++++ platforms/rtsm_ve-aemv8a.acpi/spmi.asl | 40 +++ platforms/rtsm_ve-aemv8a.acpi/srat.asl | 57 +++++ platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl | 17 ++ platforms/rtsm_ve-aemv8a.acpi/tpm2.asl | 22 ++ platforms/rtsm_ve-aemv8a.acpi/uefi.asl | 21 ++ platforms/rtsm_ve-aemv8a.acpi/xsdt.asl | 39 +++ 28 files changed, 1966 insertions(+) create mode 100644 platforms/rtsm_ve-aemv8a.acpi/.gitignore create mode 100644 platforms/rtsm_ve-aemv8a.acpi/apic.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/bert.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/cpep.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/dsdt.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/ecdt.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/einj.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/erst.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/facp.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/facs.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/fpdt.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/gtdt.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/hest.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/mcfg.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/mchi.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/mpst.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/msct.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/oem0.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/pmtt.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/rsdp.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest create mode 100644 platforms/rtsm_ve-aemv8a.acpi/slit.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/spmi.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/srat.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/tpm2.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/uefi.asl create mode 100644 platforms/rtsm_ve-aemv8a.acpi/xsdt.asl

diff --git a/platforms/rtsm_ve-aemv8a.acpi/.gitignore b/platforms/rtsm_ve-aemv8a.acpi/.gitignore new file mode 100644 index 0000000..9585b50 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/.gitignore @@ -0,0 +1,3 @@ +*.aml +*.lst +*.acpi diff --git a/platforms/rtsm_ve-aemv8a.acpi/apic.asl b/platforms/rtsm_ve-aemv8a.acpi/apic.asl new file mode 100644 index 0000000..6f1158e --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/apic.asl @@ -0,0 +1,126 @@ +/*

• • Copyright (c) 2013, Al Stone al.stone@linaro.org
• • [APIC] Multiple APIC Description Table (MADT)
• • Format: [ByteLength] FieldName : HexFieldValue
• • This source is released under the terms of the GPLv2.
• */

+[0004] Signature : "APIC" +[0004] Table Length : 000000F6 +[0001] Revision : 03 +[0001] Checksum : B0 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110623

+[0004] Local Apic Address : 2C002000 +[0004] Flags (decoded below) : 00000001

•                  PC-AT Compatibility : 0
  

+[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000000 /* Should be equal to FDT provided or CPU hardware ID */ +[0004] Processor UID : 00000000 +[0004] Flags (decoded below) : 00000001

•                    Processor Enabled : 1
  

+[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C002000 /* this is the foundation model's GIC address */

+[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000001 +[0004] Processor UID : 00000001 +[0004] Flags (decoded below) : 00000001

•                    Processor Enabled : 1
  

+[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C002000

+[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000002 +[0004] Processor UID : 00000002 +[0004] Flags (decoded below) : 00000001

•                    Processor Enabled : 1
  

+[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C002000

+[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000003 +[0004] Processor UID : 00000003 +[0004] Flags (decoded below) : 00000001

•                    Processor Enabled : 1
  

+[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C002000

+[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000004 +[0004] Processor UID : 00000004 +[0004] Flags (decoded below) : 00000000

•                    Processor Enabled : 0
  

+[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C002000

+[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000005 +[0004] Processor UID : 00000005 +[0004] Flags (decoded below) : 00000000

•                    Processor Enabled : 0
  

+[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C002000

+[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000006 +[0004] Processor UID : 00000006 +[0004] Flags (decoded below) : 00000000

•                    Processor Enabled : 0
  

+[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C002000

+[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000007 +[0004] Processor UID : 00000007 +[0004] Flags (decoded below) : 00000000

•                    Processor Enabled : 0
  

+[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C002000

+[0001] Subtable Type : 0C [Generic Interrupt Distributor] +[0001] Length : 18 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000000 +[0008] Base Address : 000000002C001000 /* armv8 foundation model's GIC distributor base addr */ +[0004] Interrupt Base : 00000000 +[0004] Reserved : 00000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/bert.asl b/platforms/rtsm_ve-aemv8a.acpi/bert.asl new file mode 100644 index 0000000..60a147f --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/bert.asl @@ -0,0 +1,21 @@ +/*

• • Copyright (c) 2013, Al Stone al.stone@linaro.org
• • [BERT] Boot Error Record Table
• • Format: [ByteLength] FieldName : HexFieldValue
• • This source is released under the terms of the GPLv2.
• */

+[0004] Signature : "BERT" +[0004] Table Length : 00000030 +[0001] Revision : 01 +[0001] Checksum : 15 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528

+[0004] Boot Error Region Length : 00000000 +[0008] Boot Error Region Address : 0000000000000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/cpep.asl b/platforms/rtsm_ve-aemv8a.acpi/cpep.asl new file mode 100644 index 0000000..332b6fd --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/cpep.asl @@ -0,0 +1,26 @@ +/*

• • Copyright (c) 2013, Al Stone al.stone@linaro.org
• • [CPEP] Corrected Platform Error Polling Table
• • Format: [ByteLength] FieldName : HexFieldValue
• • This source is released under the terms of the GPLv2.
• */

+[0004] Signature : "CPEP" +[0004] Table Length : 00000034 +[0001] Revision : 01 +[0001] Checksum : 0F +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528

+[0008] Reserved : 0000000000000000

+[0001] Subtable Type : 00 +[0001] Length : 08 +[0001] Processor ID : 00 +[0001] Processor EID : 00 +[0004] Polling Interval : 00000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/dsdt.asl b/platforms/rtsm_ve-aemv8a.acpi/dsdt.asl new file mode 100644 index 0000000..ed13b1f --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/dsdt.asl @@ -0,0 +1,234 @@ +/*

• • Copyright (c) 2013, Al Stone al.stone@linaro.org
• • [DSDT] Description of the armv8 VE Model
• • This source is released under the terms of the GPLv2.
• */

+DefinitionBlock (

• "dsdt.aml", // output filename
• "DSDT", // table signature
• 2, // DSDT compliance revision
• "LINARO", // OEM ID
• "RTSMVEV8", // table ID
• 0x00000002) // OEM revision

+{

• Scope (_SB)
• {

• Device (SCK0)
  

• {
  

• 	Name (_HID, "ACPI0004")
  

• 	Name (_UID, 0x00)
  

• 	Method (_STA, 0, NotSerialized)
  

• 	{
  

• 		Return (0x0F)
  

• 	}
  

• 	Device (PRC0)
  

• 	{
  

• 		Name (_HID, "ACPI0007")
  

• 		Name (_UID, 0x00)
  

• 		/* CPU0 will be always present */
  

• 		Method (_STA, 0, NotSerialized)
  

• 		{
  

• 			Return (0x0F)
  

• 		}
  

• 		Name (MAT0, Buffer (0x28)
  

• 		{
  

• 		/* 0000 */    0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* type, len, reserved, gic_id */
  

• 		/* 0008 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, /* uid, flags */
  

• 		/* 0010 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* parking_version, performance_interrupt */
  

• 		/* 0018 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* parked_address */
  

• 		/* 0020 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00  /* base_address */
  

• 		})
  

• 		Name (MAT1, Buffer (0x28)
  

• 		{
  

• 		/* 0000 */    0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  

• 		/* 0008 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  

• 		/* 0010 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  

• 		/* 0018 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  

• 		/* 0020 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  

• 		})
  

• 		Method (_MAT, 0, NotSerialized)
  

• 		{
  

• 			If (_STA())
  

• 			{
  

• 				Return (MAT0)
  

• 			}
  

• 			Else
  

• 			{
  

• 				Return (MAT1)
  

• 			}
  

• 		}
  

• 	}
  

• 	Device (PRC1)
  

• 	{
  

• 		Name (_HID, "ACPI0007")
  

• 		Name (_UID, 0x01)
  

• 		Name (STA1, 0x0F)
  

• 		Method (_STA, 0, NotSerialized)
  

• 		{
  

• 			Return (STA1)
  

• 		}
  

• 		Method (_EJ0, 1, NotSerialized)
  

• 		{
  

• 			If (LEqual (STA1, 0x0F))
  

• 			{
  

• 				Store (0x00, STA1)
  

• 			}
  

• 		}
  

• 		Name (MAT0, Buffer (0x28)
  

• 		{
  

• 		/* 0000 */    0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
  

• 		/* 0008 */    0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01,
  

• 		/* 0010 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  

• 		/* 0018 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  

• 		/* 0020 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  

• 		})
  

• 		Name (MAT1, Buffer (0x28)
  

• 		{
  

• 		/* 0000 */    0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
  

• 		/* 0008 */    0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
  

• 		/* 0010 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  

• 		/* 0018 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  

• 		/* 0020 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  

• 		})
  

• 		Method (_MAT, 0, NotSerialized)
  

• 		{
  

• 			If (_STA())
  

• 			{
  

• 				Return (MAT0)
  

• 			}
  

• 			Else
  

• 			{
  

• 				Return (MAT1)
  

• 			}
  

• 		}
  

• 	}
  

• 	Device (PRC2)
  

• 	{
  

• 		Name (_HID, "ACPI0007")
  

• 		Name (_UID, 0x02)
  

• 		Name (STA2, 0x0F)
  

• 		Method (_STA, 0, NotSerialized)
  

• 		{
  

• 			Return (STA2)
  

• 		}
  

• 		Method (_EJ0, 1, NotSerialized)
  

• 		{
  

• 			If (LEqual (STA2, 0x0F))
  

• 			{
  

• 				Store (0x00, STA2)
  

• 			}
  

• 		}
  

• 		Name (MAT0, Buffer (0x28)
  

• 		{
  

• 		/* 0000 */    0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
  

• 		/* 0008 */    0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,
  

• 		/* 0010 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  

• 		/* 0018 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  

• 		/* 0020 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  

• 		})
  

• 		Name (MAT1, Buffer (0x28)
  

• 		{
  

• 		/* 0000 */    0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
  

• 		/* 0008 */    0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
  

• 		/* 0010 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  

• 		/* 0018 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  

• 		/* 0020 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  

• 		})
  

• 		Method (_MAT, 0, NotSerialized)
  

• 		{
  

• 			If (_STA())
  

• 			{
  

• 				Return (MAT0)
  

• 			}
  

• 			Else
  

• 			{
  

• 				Return (MAT1)
  

• 			}
  

• 		}
  

• 	}
  

• 	Device (PRC3)
  

• 	{
  

• 		Name (_HID, "ACPI0007")
  

• 		Name (_UID, 0x03)
  

• 		Name (STA3, 0x0F)
  

• 		Method (_STA, 0, NotSerialized)
  

• 		{
  

• 			Return (STA3)
  

• 		}
  

• 		Method (_EJ0, 1, NotSerialized)
  

• 		{
  

• 			If (LEqual (STA3, 0x0F))
  

• 			{
  

• 				Store (0x00, STA3)
  

• 			}
  

• 		}
  

• 		Name (MAT0, Buffer (0x28)
  

• 		{
  

• 		/* 0000 */    0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
  

• 		/* 0008 */    0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01,
  

• 		/* 0010 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  

• 		/* 0018 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  

• 		/* 0020 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  

• 		})
  

• 		Name (MAT1, Buffer (0x28)
  

• 		{
  

• 		/* 0000 */    0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
  

• 		/* 0008 */    0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00,
  

• 		/* 0010 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  

• 		/* 0018 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  

• 		/* 0020 */    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  

• 		})
  

• 		Method (_MAT, 0, NotSerialized)
  

• 		{
  

• 			If (_STA())
  

• 			{
  

• 				Return (MAT0)
  

• 			}
  

• 			Else
  

• 			{
  

• 				Return (MAT1)
  

• 			}
  

• 		}
  

• 	}
  

• }
  

• Device (NET0) {
  

• 	Name (_HID, "LINA0003")
  

• 	Name (_UID, 0)
  

• 	Method (_CRS, 0x0, Serialized) {
  

• 		Name (RBUF, ResourceTemplate () {
  

• 			Memory32Fixed (ReadWrite, 0x1a000000, 0x00010000)
  

• 			Interrupt (ResourceConsumer, Edge, ActiveBoth, Exclusive, , , ) {0x2F}
  

• 		})
  

• 		Return (RBUF)
  

• 	}
  

• }
  

• }

+} diff --git a/platforms/rtsm_ve-aemv8a.acpi/ecdt.asl b/platforms/rtsm_ve-aemv8a.acpi/ecdt.asl new file mode 100644 index 0000000..a7e1442 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/ecdt.asl @@ -0,0 +1,37 @@ +/*

• • Copyright (c) 2013, Al Stone al.stone@linaro.org
• • [ECDT] Embedded Controller Boot Resources Table
• • Format: [ByteLength] FieldName : HexFieldValue
• • This source is released under the terms of the GPLv2.
• */

+[0004] Signature : "ECDT" +[0004] Table Length : 00000042 +[0001] Revision : 01 +[0001] Checksum : 2D +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528

+[0012] Command/Status Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000066

+[0012] Data Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000062

+[0004] UID : 00000000 +[0001] GPE Number : 09 +[0001] Namepath : "" diff --git a/platforms/rtsm_ve-aemv8a.acpi/einj.asl b/platforms/rtsm_ve-aemv8a.acpi/einj.asl new file mode 100644 index 0000000..e12c75b --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/einj.asl @@ -0,0 +1,151 @@ +/*

• • Copyright (c) 2013, Al Stone al.stone@linaro.org
• • [EINJ] Error Injection Table
• • Format: [ByteLength] FieldName : HexFieldValue
• • This source released under the terms of the GPLv2.
• */

+[0004] Signature : "EINJ" +[0004] Table Length : 00000130 +[0001] Revision : 01 +[0001] Checksum : 09 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528

+[0004] Injection Header Length : 00000030 +[0001] Flags : 00 +[0003] Reserved : 000000 +[0004] Injection Entry Count : 0000000A

+[0001] Action : 00 [Begin Operation] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00

•               Preserve Register Bits : 0
  

+[0001] Reserved : 00

+[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000

+[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF

+[0001] Action : 01 [Get Trigger Table] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00

•               Preserve Register Bits : 0
  

+[0001] Reserved : 00

+[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000

+[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF

+[0001] Action : 02 [Set Error Type] +[0001] Instruction : 02 [Write Register] +[0001] Flags (decoded below) : 01

•               Preserve Register Bits : 1
  

+[0001] Reserved : 00

+[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000

+[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF

+[0001] Action : 03 [Get Error Type] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00

•               Preserve Register Bits : 0
  

+[0001] Reserved : 00

+[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000

+[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF

+[0001] Action : 04 [End Operation] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 01

•               Preserve Register Bits : 1
  

+[0001] Reserved : 00

+[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000

+[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF

+[0001] Action : 05 [Execute Operation] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 01

•               Preserve Register Bits : 1
  

+[0001] Reserved : 00

+[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 10 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 02 [Word Access:16] +[0008] Address : 0000000000000000

+[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF

+[0001] Action : 06 [Check Busy Status] +[0001] Instruction : 01 [Read Register Value] +[0001] Flags (decoded below) : 00

•               Preserve Register Bits : 0
  

+[0001] Reserved : 00

+[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000

+[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF

+[0001] Action : 07 [Get Command Status] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 01

•               Preserve Register Bits : 1
  

+[0001] Reserved : 00

+[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000

+[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF diff --git a/platforms/rtsm_ve-aemv8a.acpi/erst.asl b/platforms/rtsm_ve-aemv8a.acpi/erst.asl new file mode 100644 index 0000000..817845f --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/erst.asl @@ -0,0 +1,278 @@ +/*

• • Copyright (c) 2013, Al Stone al.stone@linaro.org
• • [ERST] Error Record Serialization Table
• • Format: [ByteLength] FieldName : HexFieldValue
• • This source released under the terms of the GPLv2.
• */

+[0004] Signature : "ERST" +[0004] Table Length : 00000230 +[0001] Revision : 01 +[0001] Checksum : AB +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528

+[0004] Serialization Header Length : 00000030 +[0004] Reserved : 00000000 +[0004] Instruction Entry Count : 00000010

+[0001] Action : 00 [Begin Write Operation] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 00

•               Preserve Register Bits : 0
  

+[0001] Reserved : 00

+[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000

+[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF

+[0001] Action : 01 [Begin Read Operation] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 00

•               Preserve Register Bits : 0
  

+[0001] Reserved : 00

+[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000

+[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF

+[0001] Action : 02 [Begin Clear Operation] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 00

•               Preserve Register Bits : 0
  

+[0001] Reserved : 00

+[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000

+[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF

+[0001] Action : 03 [End Operation] +[0001] Instruction : 04 [Noop] +[0001] Flags (decoded below) : 01

•               Preserve Register Bits : 1
  

+[0001] Reserved : 00

+[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000

+[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF

+[0001] Action : 04 [Set Record Offset] +[0001] Instruction : 02 [Write Register] +[0001] Flags (decoded below) : 00

•               Preserve Register Bits : 0
  

+[0001] Reserved : 00

+[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000

+[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF

+[0001] Action : 05 [Execute Operation] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 00

•               Preserve Register Bits : 0
  

+[0001] Reserved : 00

+[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000000

+[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF

+[0001] Action : 06 [Check Busy Status] +[0001] Instruction : 01 [Read Register Value] +[0001] Flags (decoded below) : 00

•               Preserve Register Bits : 0
  

+[0001] Reserved : 00

+[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000

+[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF

+[0001] Action : 07 [Get Command Status] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00

•               Preserve Register Bits : 0
  

+[0001] Reserved : 00

+[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000

+[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF

+[0001] Action : 08 [Get Record Identifier] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00

•               Preserve Register Bits : 0
  

+[0001] Reserved : 00

+[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000

+[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF

+[0001] Action : 09 [Set Record Identifier] +[0001] Instruction : 02 [Write Register] +[0001] Flags (decoded below) : 00

•               Preserve Register Bits : 0
  

+[0001] Reserved : 00

+[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000

+[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF

+[0001] Action : 0A [Get Record Count] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00

•               Preserve Register Bits : 0
  

+[0001] Reserved : 00

+[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000

+[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF

+[0001] Action : 0B [Begin Dummy Write] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 00

•               Preserve Register Bits : 0
  

+[0001] Reserved : 00

+[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000

+[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF

+[0001] Action : 0C [Unused/Unknown Action] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00

•               Preserve Register Bits : 0
  

+[0001] Reserved : 00

+[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000

+[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF

+[0001] Action : 0D [Get Error Address Range] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00

•               Preserve Register Bits : 0
  

+[0001] Reserved : 00

+[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000

+[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF

+[0001] Action : 0E [Get Error Address Length] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00

•               Preserve Register Bits : 0
  

+[0001] Reserved : 00

+[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000

+[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF

+[0001] Action : 0F [Get Error Attributes] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00

•               Preserve Register Bits : 0
  

+[0001] Reserved : 00

+[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000

+[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF diff --git a/platforms/rtsm_ve-aemv8a.acpi/facp.asl b/platforms/rtsm_ve-aemv8a.acpi/facp.asl new file mode 100644 index 0000000..14ed9f2 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/facp.asl @@ -0,0 +1,167 @@ +/*

• • Copyright (c) 2013, Al Stone al.stone@linaro.org
• • [FACP] ACPI Table
• • This source is released under the terms of the GPLv2.
• */

+[0004] Signature : "FACP" +[0004] Table Length : 0000010C +[0001] Revision : 05 +[0001] Checksum : 18 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20111123

+[0004] FACS Address : 00000000 +[0004] DSDT Address : 00000010 +[0001] Model : 00 +[0001] PM Profile : 04 /* Enterprise Server */ +[0002] SCI Interrupt : 0000 +[0004] SMI Command Port : 00000000 +[0001] ACPI Enable Value : 00 +[0001] ACPI Disable Value : 00 +[0001] S4BIOS Command : 00 +[0001] P-State Control : 00 +[0004] PM1A Event Block Address : 00000001 +[0004] PM1B Event Block Address : 00000000 +[0004] PM1A Control Block Address : 00000001 +[0004] PM1B Control Block Address : 00000000 +[0004] PM2 Control Block Address : 00000001 +[0004] PM Timer Block Address : 00000001 +[0004] GPE0 Block Address : 00000001 +[0004] GPE1 Block Address : 00000000 +[0001] PM1 Event Block Length : 04 +[0001] PM1 Control Block Length : 02 +[0001] PM2 Control Block Length : 01 +[0001] PM Timer Block Length : 04 +[0001] GPE0 Block Length : 08 +[0001] GPE1 Block Length : 00 +[0001] GPE1 Base Offset : 00 +[0001] _CST Support : 00 +[0002] C2 Latency : 0000 +[0002] C3 Latency : 0000 +[0002] CPU Cache Size : 0000 +[0002] Cache Flush Stride : 0000 +[0001] Duty Cycle Offset : 00 +[0001] Duty Cycle Width : 00 +[0001] RTC Day Alarm Index : 00 +[0001] RTC Month Alarm Index : 00 +[0001] RTC Century Index : 00 +[0002] Boot Flags (decoded below) : 0000

•        Legacy Devices Supported (V2) : 0
  

•     8042 Present on ports 60/64 (V2) : 0
  

•                 VGA Not Present (V4) : 0
  

•               MSI Not Supported (V4) : 0
  

•         PCIe ASPM Not Supported (V4) : 0
  

•            CMOS RTC Not Present (V5) : 0
  

+[0001] Reserved : 00 +[0004] Flags (decoded below) : 00000000

• WBINVD instruction is operational (V1) : 1

•       WBINVD flushes all caches (V1) : 1
  

•             All CPUs support C1 (V1) : 0
  

•           C2 works on MP system (V1) : 0
  

•     Control Method Power Button (V1) : 1
  

•     Control Method Sleep Button (V1) : 1
  

• RTC wake not in fixed reg space (V1) : 0
  

•     RTC can wake system from S4 (V1) : 0
  

•                 32-bit PM Timer (V1) : 0
  

•               Docking Supported (V1) : 0
  

•        Reset Register Supported (V2) : 0
  

•                     Sealed Case (V3) : 0
  

•             Headless - No Video (V3) : 1
  

• Use native instr after SLP_TYPx (V3) : 0
  

•       PCIEXP_WAK Bits Supported (V4) : 0
  

•              Use Platform Timer (V4) : 0
  

•        RTC_STS valid on S4 wake (V4) : 0
  

•         Remote Power-on capable (V4) : 1
  

•          Use APIC Cluster Model (V4) : 0
  

• Use APIC Physical Destination Mode (V4) : 0

•                Hardware Reduced (V5) : 1
  

•               Low Power S0 Idle (V5) : 1
  

+[0012] Reset Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000001

+[0001] Value to cause reset : 00 +[0003] Reserved : 000000 +[0008] FACS Address : 0000000000000000 +[0008] DSDT Address : 0000000000000010 +[0012] PM1A Event Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 20 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 02 [Word Access:16] +[0008] Address : 0000000000000001

+[0012] PM1B Event Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000

+[0012] PM1A Control Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 10 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 02 [Word Access:16] +[0008] Address : 0000000000000001

+[0012] PM1B Control Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000

+[0012] PM2 Control Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000001

+[0012] PM Timer Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 20 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 03 [DWord Access:32] +[0008] Address : 0000000000000001

+[0012] GPE0 Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 80 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000001

+[0012] GPE1 Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000

+[0012] Sleep Control Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000000

+[0012] Sleep Status Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000000

diff --git a/platforms/rtsm_ve-aemv8a.acpi/facs.asl b/platforms/rtsm_ve-aemv8a.acpi/facs.asl new file mode 100644 index 0000000..9695e05 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/facs.asl @@ -0,0 +1,21 @@ +/*

• • Copyright (c) 2013, Al Stone al.stone@linaro.org
• • [FACS] ACPI Table
• • This source is released under the terms of the GPLv2.
• */

+[0004] Signature : "FACS" +[0004] Length : 00000040 +[0004] Hardware Signature : 00000000 +[0004] 32 Firmware Waking Vector : 00000000 +[0004] Global Lock : 00000000 +[0004] Flags (decoded below) : 00000000

•               S4BIOS Support Present : 0
  

•           64-bit Wake Supported (V2) : 0
  

+[0008] 64 Firmware Waking Vector : 0000000000000000 +[0001] Version : 02 +[0003] Reserved : 000000 +[0004] OspmFlags (decoded below) : 00000000

•        64-bit Wake Env Required (V2) : 0
  

diff --git a/platforms/rtsm_ve-aemv8a.acpi/fpdt.asl b/platforms/rtsm_ve-aemv8a.acpi/fpdt.asl new file mode 100644 index 0000000..bb03f47 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/fpdt.asl @@ -0,0 +1,35 @@ +/*

• • Copyright (c) 2013, Al Stone al.stone@linaro.org
• • [FPDT] Firmware Performance Data Table
• • Format: [ByteLength] FieldName : HexFieldValue
• • This source released under the terms of the GPLv2.
• */

+[0004] Signature : "FPDT" +[0004] Table Length : 00000064 +[0001] Revision : 01 +[0001] Checksum : BD +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110804

+[0002] Subtable Type : 0000 +[0001] Length : 30 +[0001] Revision : 01 +[0004] Reserved : 00000000 +[0008] Reset End : 0000000000000000 +[0008] Load Image Start : 0000000000000000 +[0008] Start Image Start : 0000000000000000 +[0008] Exit Services Entry : 0000000000000000 +[0008] Exit Services Exit : 0000000000000000

+[0002] Subtable Type : 0001 +[0001] Length : 10 +[0001] Revision : 01 +[0004] Reserved : 00000000 +[0008] S3PT Address : 0000000000000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl b/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl new file mode 100644 index 0000000..068ad4a --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl @@ -0,0 +1,42 @@ +/*

• • Copyright (c) 2013, Al Stone al.stone@linaro.org
• • [GTDT] Generic Timer Description Table
• • Format: [ByteLength] FieldName : HexFieldValue
• • This source is released under the terms of the GPLv2.
• */

+[0004] Signature : "GTDT" +[0004] Table Length : 00000050 +[0001] Revision : 01 +[0001] Checksum : F1 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110623

+[0008] Timer Address : 0000000000000000 +[0004] Flags (decoded below) : 00000001

•                       Memory Present : 1
  

+[0004] Secure PL1 Interrupt : 00000000 +[0004] SPL1 Flags (decoded below) : 00000000

•                         Trigger Mode : 0
  

•                             Polarity : 0
  

+[0004] Non-Secure PL1 Interrupt : 00000000 +[0004] NSPL1 Flags (decoded below) : 00000000

•                         Trigger Mode : 0
  

•                             Polarity : 0
  

+[0004] Virtual Timer Interrupt : 00000000 +[0004] VT Flags (decoded below) : 00000000

•                         Trigger Mode : 0
  

•                             Polarity : 0
  

+[0004] Non-Secure PL2 Interrupt : 00000000 +[0004] NSPL2 Flags (decoded below) : 00000000

•                         Trigger Mode : 0
  

•                             Polarity : 0
  

diff --git a/platforms/rtsm_ve-aemv8a.acpi/hest.asl b/platforms/rtsm_ve-aemv8a.acpi/hest.asl new file mode 100644 index 0000000..b143bbb --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/hest.asl @@ -0,0 +1,193 @@ +/*

• • Copyright (c) 2013, Al Stone <al.stone@linaro.org
• • [HEST] Hardware Error Source Table
• • Format: [ByteLength] FieldName : HexFieldValue
• • This source is released under the terms of the GPLv2.
• */

+[0004] Signature : "HEST" +[0004] Table Length : 000001D4 +[0001] Revision : 01 +[0001] Checksum : 20 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528

+[0004] Error Source Count : 00000004

+[0002] Subtable Type : 0000 [IA-32 Machine Check Exception] +[0002] Source Id : 0000 +[0002] Reserved1 : 0000 +[0001] Flags (decoded below) : 00

•                       Firmware First : 0
  

+[0001] Enabled : 01 +[0004] Records To Preallocate : 00000001 +[0004] Max Sections Per Record : 00000001 +[0008] Global Capability Data : 0000000000000000 +[0008] Global Control Data : 0000000000000000 +[0001] Num Hardware Banks : 02 +[0007] Reserved2 : 00000000000000

+[0001] Bank Number : 00 +[0001] Clear Status On Init : 00 +[0001] Status Format : 00 +[0001] Reserved : 00 +[0004] Control Register : 00000000 +[0008] Control Data : 0000000000000000 +[0004] Status Register : 00000000 +[0004] Address Register : 00000000 +[0004] Misc Register : 00000000

+[0001] Bank Number : 01 +[0001] Clear Status On Init : 00 +[0001] Status Format : 00 +[0001] Reserved : 00 +[0004] Control Register : 00000000 +[0008] Control Data : 0000000000000000 +[0004] Status Register : 00000000 +[0004] Address Register : 00000000 +[0004] Misc Register : 00000000

+[0002] Subtable Type : 0001 [IA-32 Corrected Machine Check] +[0002] Source Id : 0001 +[0002] Reserved1 : 0000 +[0001] Flags (decoded below) : 00

•                       Firmware First : 0
  

+[0001] Enabled : 01 +[0004] Records To Preallocate : 00000001 +[0004] Max Sections Per Record : 00000001

+[0028] Notify : [Hardware Error Notification Structure] +[0001] Notify Type : 00 [Polled] +[0001] Notify Length : 00 +[0002] Configuration Write Enable : 0000 +[0004] PollInterval : 00000000 +[0004] Vector : 00000000 +[0004] Polling Threshold Value : 00000000 +[0004] Polling Threshold Window : 00000000 +[0004] Error Threshold Value : 00000000 +[0004] Error Threshold Window : 00000000

+[0001] Num Hardware Banks : 02 +[0003] Reserved2 : 000000

+[0001] Bank Number : 00 +[0001] Clear Status On Init : 00 +[0001] Status Format : 00 +[0001] Reserved : 00 +[0004] Control Register : 00000000 +[0008] Control Data : 0000000000000000 +[0004] Status Register : 00000000 +[0004] Address Register : 00000000 +[0004] Misc Register : 00000000

+[0001] Bank Number : 01 +[0001] Clear Status On Init : 00 +[0001] Status Format : 00 +[0001] Reserved : 00 +[0004] Control Register : 00000000 +[0008] Control Data : 0000000000000000 +[0004] Status Register : 00000000 +[0004] Address Register : 00000000 +[0004] Misc Register : 00000000

+[0002] Subtable Type : 0007 [PCI Express AER (AER Endpoint)] +[0002] Source Id : 0000 +[0002] Reserved : 0000 +[0001] Flags (decoded below) : 00

•                       Firmware First : 0
  

+[0001] Enabled : 01 +[0004] Records To Preallocate : 00000001 +[0004] Max Sections Per Record : 00000001 +[0004] Bus : 00000000 +[0002] Device : 0000 +[0002] Function : 0000 +[0002] DeviceControl : 0000 +[0002] Reserved : 0000 +[0004] Uncorrectable Mask : 00000000 +[0004] Uncorrectable Severity : 00000000 +[0004] Correctable Mask : 00000000 +[0004] Advanced Capabilities : 00000000

+[0002] Subtable Type : 0008 [PCI Express/PCI-X Bridge AER] +[0002] Source Id : 0000 +[0002] Reserved : 0000 +[0001] Flags (decoded below) : 00

•                       Firmware First : 0
  

+[0001] Enabled : 01 +[0004] Records To Preallocate : 00000001 +[0004] Max Sections Per Record : 00000001 +[0004] Bus : 00000000 +[0002] Device : 0000 +[0002] Function : 0000 +[0002] DeviceControl : 0000 +[0002] Reserved : 0000 +[0004] Uncorrectable Mask : 00000000 +[0004] Uncorrectable Severity : 00000000 +[0004] Correctable Mask : 00000000 +[0004] Advanced Capabilities : 00000000 +[0004] 2nd Uncorrectable Mask : 00000000 +[0004] 2nd Uncorrectable Severity : 00000000 +[0004] 2nd Advanced Capabilities : 00000000

+[0002] Subtable Type : 0009 [Generic Hardware Error Source] +[0002] Source Id : 0002 +[0002] Related Source Id : FFFF +[0001] Reserved : 00 +[0001] Enabled : 01 +[0004] Records To Preallocate : 00000001 +[0004] Max Sections Per Record : 00000001 +[0004] Max Raw Data Length : 00001000

+[0012] Error Status Address : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000

+[0028] Notify : [Hardware Error Notification Structure] +[0001] Notify Type : 03 [SCI] +[0001] Notify Length : 1C +[0002] Configuration Write Enable : 0000 +[0004] PollInterval : 00000000 +[0004] Vector : 00000000 +[0004] Polling Threshold Value : 00000000 +[0004] Polling Threshold Window : 00000000 +[0004] Error Threshold Value : 00000000 +[0004] Error Threshold Window : 00000000

+[0004] Error Status Block Length : 00001000

+[0002] Subtable Type : 0009 [Generic Hardware Error Source] +[0002] Source Id : 0003 +[0002] Related Source Id : 0000 +[0001] Reserved : 00 +[0001] Enabled : 01 +[0004] Records To Preallocate : 00000001 +[0004] Max Sections Per Record : 00000001 +[0004] Max Raw Data Length : 00001000

+[0012] Error Status Address : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000

+[0028] Notify : [Hardware Error Notification Structure] +[0001] Notify Type : 04 [NMI] +[0001] Notify Length : 1C +[0002] Configuration Write Enable : 0000 +[0004] PollInterval : 00000000 +[0004] Vector : 00000000 +[0004] Polling Threshold Value : 00000000 +[0004] Polling Threshold Window : 00000000 +[0004] Error Threshold Value : 00000000 +[0004] Error Threshold Window : 00000000

+[0004] Error Status Block Length : 00001000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/mcfg.asl b/platforms/rtsm_ve-aemv8a.acpi/mcfg.asl new file mode 100644 index 0000000..aa56900 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/mcfg.asl @@ -0,0 +1,26 @@ +/*

• • Copyright (c) 2013, Al Stone al.stone@linaro.org
• • [MCFG] PCIe Memory Mapped Configuration Table
• • Format: [ByteLength] FieldName : HexFieldValue
• • This source is released under the terms of the GPLv2.
• */

+[0004] Signature : "MCFG" +[0004] Table Length : 0000003C +[0001] Revision : 01 +[0001] Checksum : 19 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528

+[0008] Reserved : 0000000000000000

+[0008] Base Address : 0000000000000000 +[0002] Segment Group Number : 0000 +[0001] Start Bus Number : 00 +[0001] End Bus Number : 00 +[0004] Reserved : 00000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/mchi.asl b/platforms/rtsm_ve-aemv8a.acpi/mchi.asl new file mode 100644 index 0000000..33b5ea2 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/mchi.asl @@ -0,0 +1,38 @@ +/*

• • Copyright (c) 2013, Al Stone al.stone@linaro.org
• • [MCHI] Management Controller Host Interface Table
• • Format: [ByteLength] FieldName : HexFieldValue
• • This source released under the terms of the GPLv2.
• */

+[0004] Signature : "MCHI" +[0004] Table Length : 00000045 +[0001] Revision : 01 +[0001] Checksum : E4 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 02000715 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528

+[0001] Interface Type : 01 +[0001] Protocol : 00 +[0008] Protocol Data : 0000000000000000 +[0001] Interrupt Type : 00 +[0001] Gpe : 00 +[0001] Pci Device Flag : 00 +[0004] Global Interrupt : 00000000

+[0012] Control Register : [Generic Address Structure] +[0001] Space ID : 02 [PCI_Config] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000

+[0001] Pci Segment : 00 +[0001] Pci Bus : 00 +[0001] Pci Device : 00 +[0001] Pci Function : 00 diff --git a/platforms/rtsm_ve-aemv8a.acpi/mpst.asl b/platforms/rtsm_ve-aemv8a.acpi/mpst.asl new file mode 100644 index 0000000..8fe524f --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/mpst.asl @@ -0,0 +1,87 @@ +/*

• • Copyright (c) 2013, Al Stone al.stone@linaro.org
• • [MPST] Memory Power State Table
• • Format: [ByteLength] FieldName : HexFieldValue
• • This source is released under the terms of the GPLv2.
• */

+[0004] Signature : "MPST" +[0004] Table Length : 000000B6 +[0001] Revision : 01 +[0001] Checksum : 77 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20120913

+[0001] Channel ID : 00 +[0003] Reserved : 000000 +[0002] Power Node Count : 0002 +[0002] Reserved : 0000

+[0001] Flags (decoded below) : 00

•                         Node Enabled : 0
  

•                        Power Managed : 0
  

•                     Hot Plug Capable : 0
  

+[0001] Reserved : 00 +[0002] Node ID : 0000 +[0004] Length : 00000000 +[0008] Range Address : 0000000000000000 +[0008] Range Length : 0000000000000000 +[0004] Num Power States : 00000002 +[0004] Num Physical Components : 00000003

+[0001] Power State : 00 +[0001] InfoIndex : 00

+[0001] Power State : 00 +[0001] InfoIndex : 00

+[0002] Component Id : 0000 +[0002] Component Id : 0001 +[0002] Component Id : 0002

+[0001] Flags (decoded below) : 00

•                         Node Enabled : 0
  

•                        Power Managed : 0
  

•                     Hot Plug Capable : 0
  

+[0001] Reserved : 00 +[0002] Node ID : 0000 +[0004] Length : 00000000 +[0008] Range Address : 0000000000000000 +[0008] Range Length : 0000000000000000 +[0004] Num Power States : 00000001 +[0004] Num Physical Components : 00000001

+[0001] Power State : 00 +[0001] InfoIndex : 00

+[0002] Component Id : 0000

+[0002] Characteristics Count : 0002 +[0002] Reserved : 0000

+[0001] Structure ID : 01 +[0001] Flags (decoded below) : 00

•                     Memory Preserved : 0
  

•                           Auto Entry : 0
  

•                            Auto Exit : 0
  

+[0002] Reserved : 0000 +[0004] Average Power : 00000000 +[0004] Power Saving : 00000000 +[0008] Exit Latency : 0000000000000000 +[0008] Reserved : 0000000000000000

+[0001] Structure ID : 01 +[0001] Flags (decoded below) : 00

•                     Memory Preserved : 0
  

•                           Auto Entry : 0
  

•                            Auto Exit : 0
  

+[0002] Reserved : 0000 +[0004] Average Power : 00000000 +[0004] Power Saving : 00000000 +[0008] Exit Latency : 0000000000000000 +[0008] Reserved : 0000000000000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/msct.asl b/platforms/rtsm_ve-aemv8a.acpi/msct.asl new file mode 100644 index 0000000..39dd49a --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/msct.asl @@ -0,0 +1,51 @@ +/*

• • Copyright (c) 2013, Al Stone al.stone@linaro.org
• • [MSCT] Maximum System Characteristics Table
• • Format: [ByteLength] FieldName : HexFieldValue
• • This source released under the terms of the GPLv2.
• */

+[0004] Signature : "MSCT" +[0004] Table Length : 00000090 +[0001] Revision : 01 +[0001] Checksum : B7 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528

+[0004] Proximity Offset : 00000038 +[0004] Max Proximity Domains : 00000003 +[0004] Max Clock Domains : 00000000 +[0008] Max Physical Address : 00000FFFFFFFFFFF

+[0001] Revision : 01 +[0001] Length : 16 +[0004] Domain Range Start : 00000000 +[0004] Domain Range End : 00000003 +[0004] Processor Capacity : 00000010 +[0008] Memory Capacity : 0000004000000000

+[0001] Revision : 01 +[0001] Length : 16 +[0004] Domain Range Start : 00000000 +[0004] Domain Range End : 00000000 +[0004] Processor Capacity : 00000000 +[0008] Memory Capacity : 0000000000000000

+[0001] Revision : 01 +[0001] Length : 16 +[0004] Domain Range Start : 00000000 +[0004] Domain Range End : 00000000 +[0004] Processor Capacity : 00000000 +[0008] Memory Capacity : 0000000000000000

+[0001] Revision : 01 +[0001] Length : 16 +[0004] Domain Range Start : 00000000 +[0004] Domain Range End : 00000000 +[0004] Processor Capacity : 00000000 +[0008] Memory Capacity : 0000000000000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/oem0.asl b/platforms/rtsm_ve-aemv8a.acpi/oem0.asl new file mode 100644 index 0000000..570ea27 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/oem0.asl @@ -0,0 +1,18 @@ +/*

• • Copyright (c) 2013, Al Stone al.stone@linaro.org
• • [OEMx] OEM Specific Table
• • Format: [ByteLength] FieldName : HexFieldValue
• • This source is released under the terms of the GPLv2.
• */

+[0004] Signature : "OEM0" +[0004] Table Length : 00000024 +[0001] Revision : 01 +[0001] Checksum : 8B +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 0000000A +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 diff --git a/platforms/rtsm_ve-aemv8a.acpi/pmtt.asl b/platforms/rtsm_ve-aemv8a.acpi/pmtt.asl new file mode 100644 index 0000000..ce4fcba --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/pmtt.asl @@ -0,0 +1,105 @@ +/*

• • Copyright (c) 2013, Al Stone al.stone@linaro.org
• • [PMTT] Platform Memory Topology Table
• • Format: [ByteLength] FieldName : HexFieldValue
• • This source is released under the terms of the GPLv2.
• */

+[0004] Signature : "PMTT" +[0004] Table Length : 000000B4 +[0001] Revision : 01 +[0001] Checksum : 3A +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110826

+[0004] Reserved : 00000000

+[0001] Subtable Type : 00 [Socket] +[0001] Reserved : 00 +[0002] Length : 0080 +[0002] Flags (decoded below) : 0001

•                     Top-level Device : 1
  

•                     Physical Element : 0
  

•                          Memory Type : 0
  

+[0002] Reserved : 0000 +[0002] Socket ID : 0000 +[0002] Reserved : 0000

+[0001] Subtable Type : 01 [Memory Controller] +[0001] Reserved : 00 +[0002] Length : 0054 +[0002] Flags (decoded below) : 0005

•                     Top-level Device : 1
  

•                     Physical Element : 0
  

•                          Memory Type : 1
  

+[0002] Reserved : 0000 +[0004] Read Latency : 00000000 +[0004] Write Latency : 00000000 +[0004] Read Bandwidth : 00000000 +[0004] Write Bandwidth : 00000000 +[0002] Access Width : 0000 +[0002] Alignment : 0000 +[0002] Reserved : 0000 +[0002] Domain Count : 0003 +[0004] Proximity Domain : 00000000 +[0004] Proximity Domain : 00000000 +[0004] Proximity Domain : 00000000

+[0001] Subtable Type : 02 [Physical Component (DIMM)] +[0001] Reserved : 00 +[0002] Length : 0014 +[0002] Flags (decoded below) : 0002

•                     Top-level Device : 0
  

•                     Physical Element : 1
  

•                          Memory Type : 0
  

+[0002] Reserved : 0000 +[0002] Component ID : 0000 +[0002] Reserved : 0000 +[0004] Memory Size : 00000000 +[0004] Bios Handle : 00000000

+[0001] Subtable Type : 02 [Physical Component (DIMM)] +[0001] Reserved : 00 +[0002] Length : 0014 +[0002] Flags (decoded below) : 0002

•                     Top-level Device : 0
  

•                     Physical Element : 1
  

•                          Memory Type : 0
  

+[0002] Reserved : 0000 +[0002] Component ID : 0000 +[0002] Reserved : 0000 +[0004] Memory Size : 00000000 +[0004] Bios Handle : 00000000

+[0001] Subtable Type : 01 [Memory Controller] +[0001] Reserved : 00 +[0002] Length : 0020 +[0002] Flags (decoded below) : 0001

•                     Top-level Device : 1
  

•                     Physical Element : 0
  

•                          Memory Type : 0
  

+[0002] Reserved : 0000 +[0004] Read Latency : 00000000 +[0004] Write Latency : 00000000 +[0004] Read Bandwidth : 00000000 +[0004] Write Bandwidth : 00000000 +[0002] Access Width : 0000 +[0002] Alignment : 0000 +[0002] Reserved : 0000 +[0002] Domain Count : 0000

+[0001] Subtable Type : 00 [Socket] +[0001] Reserved : 00 +[0002] Length : 000C +[0002] Flags (decoded below) : 0001

•                     Top-level Device : 1
  

•                     Physical Element : 0
  

•                          Memory Type : 0
  

+[0002] Reserved : 0000 +[0002] Socket ID : 0000 +[0002] Reserved : 0000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/rsdp.asl b/platforms/rtsm_ve-aemv8a.acpi/rsdp.asl new file mode 100644 index 0000000..329ffe5 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/rsdp.asl @@ -0,0 +1,17 @@ +/*

• • Copyright (c) 2013, Al Stone al.stone@linaro.org
• • [RSDP] ACPI Table
• • This source is released under the terms of the GPLv2.
• */

+[0008] Signature : "RSD PTR " +[0001] Checksum : 43 +[0006] Oem ID : "LINARO" +[0001] Revision : 02 +[0004] RSDT Address : 00000000 +[0004] Length : 00000024 +[0008] XSDT Address : 0000000000000000 +[0001] Extended Checksum : DC +[0003] Reserved : 000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest b/platforms/rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest new file mode 100644 index 0000000..6b3a743 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest @@ -0,0 +1,34 @@ +# +# Each line is either a comment, white space, or two fields: +# +# <signature> : <ASL file name> +# +# NB: for each file x.asl, an AML file called x.aml will be created +#

+rsdp: rsdp.asl +xsdt: xsdt.asl +facp: facp.asl +dsdt: dsdt.asl +ssdt: ssdt0.asl +bert: bert.asl +ecdt: ecdt.asl +facs: facs.asl +gtdt: gtdt.asl +hest: hest.asl +apic: apic.asl +mcfg: mcfg.asl +mpst: mpst.asl +oem: oem0.asl +pmmt: pmmt.asl +slit: slit.asl +spmi: spmi.asl +srat: srat.asl +uefi: uefi.asl +cpep: cpep.asl +einj: einj.asl +erst: erst.asl +fpdt: fpdt.asl +mchi: mchi.asl +msct: msct.asl

diff --git a/platforms/rtsm_ve-aemv8a.acpi/slit.asl b/platforms/rtsm_ve-aemv8a.acpi/slit.asl new file mode 100644 index 0000000..96305c8 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/slit.asl @@ -0,0 +1,60 @@ +/*

• • Copyright (c) 2013, Al Stone al.stone@linaro.org
• • [SLIT] System Locality Information Table
• • Format: [ByteLength] FieldName : HexFieldValue
• • This source is released under the terms of the GPLv2.
• */

+[0004] Signature : "SLIT" +[0004] Table Length : 000001BC +[0001] Revision : 01 +[0001] Checksum : 00 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110316

+[0008] Localities : 0000000000000014 +[0020] Locality 0 : 0A 10 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 \

•                                        24 25 26 27
  

+[0020] Locality 1 : 10 0A 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 \

•                                        23 24 25 26
  

+[0020] Locality 2 : 16 15 0A 10 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 \

•                                        22 23 24 25
  

+[0020] Locality 3 : 17 16 10 0A 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 \

•                                        21 22 23 24
  

+[0020] Locality 4 : 18 17 16 15 0A 10 16 17 18 19 1A 1B 1C 1D 1E 1F \

•                                        20 21 22 23
  

+[0020] Locality 5 : 19 18 17 16 10 0A 15 16 17 18 19 1A 1B 1C 1D 1E \

•                                        1F 20 21 22
  

+[0020] Locality 6 : 1A 19 18 17 16 15 0A 10 16 17 18 19 1A 1B 1C 1D \

•                                        1E 1F 20 21
  

+[0020] Locality 7 : 1B 1A 19 18 17 16 10 0A 15 16 17 18 19 1A 1B 1C \

•                                        1D 1E 1F 20
  

+[0020] Locality 8 : 1C 1B 1A 19 18 17 16 15 0A 10 16 17 18 19 1A 1B \

•                                        1C 1D 1E 1F
  

+[0020] Locality 9 : 1D 1C 1B 1A 19 18 17 16 10 0A 15 16 17 18 19 1A \

•                                        1B 1C 1D 1E
  

+[0020] Locality 10 : 1E 1D 1C 1B 1A 19 18 17 16 15 0A 10 16 17 18 19 \

•                                        1A 1B 1C 1D
  

+[0020] Locality 11 : 1F 1E 1D 1C 1B 1A 19 18 17 16 10 0A 15 16 17 18 \

•                                        19 1A 1B 1C
  

+[0020] Locality 12 : 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 0A 10 16 17 \

•                                        18 19 1A 1B
  

+[0020] Locality 13 : 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 10 0A 15 16 \

•                                        17 18 19 1A
  

+[0020] Locality 14 : 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 0A 10 \

•                                        16 17 18 19
  

+[0020] Locality 15 : 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 10 0A \

•                                        15 16 17 18
  

+[0020] Locality 16 : 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 \

•                                        0A 10 16 17
  

+[0020] Locality 17 : 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 \

•                                        10 0A 15 16
  

+[0020] Locality 18 : 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 \

•                                        16 15 0A 10
  

+[0020] Locality 19 : 27 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 \

•                                        17 16 10 0A
  

diff --git a/platforms/rtsm_ve-aemv8a.acpi/spmi.asl b/platforms/rtsm_ve-aemv8a.acpi/spmi.asl new file mode 100644 index 0000000..8793979 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/spmi.asl @@ -0,0 +1,40 @@ +/*

• • Copyright (c) 2013, Al Stone <al.stone@linaro.org
• • [SPMI] Server Platform Management Interface Table
• • Format: [ByteLength] FieldName : HexFieldValue
• • This source is released under the terms of the GPLv2.
• */

+[0004] Signature : "SPMI" +[0004] Table Length : 00000041 +[0001] Revision : 04 +[0001] Checksum : ED +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528

+[0001] Interface Type : 00 +[0001] Reserved : 00 +[0002] IPMI Spec Version : 0000 +[0001] Interrupt Type : 00 +[0001] GPE Number : 00 +[0001] Reserved : 00 +[0001] PCI Device Flag : 00 +[0004] Interrupt : 00000000

+[0012] IPMI Register : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000000

+[0001] PCI Segment : 00 +[0001] PCI Bus : 00 +[0001] PCI Device : 00 +[0001] PCI Function : 00 +[0001] Reserved : 00 diff --git a/platforms/rtsm_ve-aemv8a.acpi/srat.asl b/platforms/rtsm_ve-aemv8a.acpi/srat.asl new file mode 100644 index 0000000..c525c89 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/srat.asl @@ -0,0 +1,57 @@ +/*

• • Copyright (c) 2013, Al Stone al.stone@linaro.org
• • [SRAT] System Resource Affinity Table
• • Format: [ByteLength] FieldName : HexFieldValue
• • This source is released under the terms of the GPLv2.
• */

+[0004] Signature : "SRAT" +[0004] Table Length : 00000080 +[0001] Revision : 03 +[0001] Checksum : 5A +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528

+[0004] Table Revision : 00000001 +[0008] Reserved : 0000000000000000

+[0001] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[0001] Length : 10

+[0001] Proximity Domain Low(8) : 00 +[0001] Apic ID : 00 +[0004] Flags (decoded below) : 00000001

•                              Enabled : 1
  

+[0001] Local Sapic EID : 00 +[0003] Proximity Domain High(24) : 000000 +[0004] Reserved : 00000000

+[0001] Subtable Type : 01 [Memory Affinity] +[0001] Length : 28

+[0004] Proximity Domain : 00000000 +[0002] Reserved1 : 0000 +[0008] Base Address : 0000000000000000 +[0008] Address Length : 000000000009FC00 +[0004] Reserved2 : 00000000 +[0004] Flags (decoded below) : 00000001

•                              Enabled : 1
  

•                        Hot Pluggable : 0
  

•                         Non-Volatile : 0
  

+[0008] Reserved3 : 0000000000000000

+[0001] Subtable Type : 02 [Processor Local x2APIC Affinity] +[0001] Length : 18

+[0002] Reserved1 : 0000 +[0004] Proximity Domain : 00000000 +[0004] Apic ID : 00000000 +[0004] Flags (decoded below) : 00000001

•                              Enabled : 1
  

+[0004] Clock Domain : 00000000 +[0004] Reserved2 : 00000000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl b/platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl new file mode 100644 index 0000000..c13ceef --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl @@ -0,0 +1,17 @@ +/*

• • Copyright (c) 2013, Al Stone al.stone@linaro.org
• • [SSDT] Description of the armv8 VE Model
• • This source is released under the terms of the GPLv2.
• */

+DefinitionBlock (

• "ssdt0.aml", // output filename
• "SSDT", // table signature
• 2, // SSDT compliance revision
• "LINARO", // OEM ID
• "RTSMVEV8", // table ID
• 0x00000001) // OEM revision

+{ +} diff --git a/platforms/rtsm_ve-aemv8a.acpi/tpm2.asl b/platforms/rtsm_ve-aemv8a.acpi/tpm2.asl new file mode 100644 index 0000000..c88eb2c --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/tpm2.asl @@ -0,0 +1,22 @@ +/*

• • Intel ACPI Component Architecture
• • iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
• • Copyright (c) 2000 - 2013 Intel Corporation
• • Template for [TPM2] ACPI Table
• • Format: [ByteLength] FieldName : HexFieldValue
• */

+[0004] Signature : "TPM2" [Trusted Platform Module hardware interface table] +[0004] Table Length : 00000034 +[0001] Revision : 03 +[0001] Checksum : 42 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20121114

+[0004] Flags : 00000000 +[0008] Control Address : 0011223344556677 +[0004] Start Method : 00000001 diff --git a/platforms/rtsm_ve-aemv8a.acpi/uefi.asl b/platforms/rtsm_ve-aemv8a.acpi/uefi.asl new file mode 100644 index 0000000..2b927d7 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/uefi.asl @@ -0,0 +1,21 @@ +/*

• • Copyright (c) 2013, Al Stone al.stone@linaro.org
• • [UEFI] UEFI Boot Optimization Table
• • Format: [ByteLength] FieldName : HexFieldValue
• • This source is released under the terms of the GPLv2.
• */

+[0004] Signature : "UEFI" +[0004] Table Length : 00000036 +[0001] Revision : 01 +[0001] Checksum : 9B +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528

+[0016] UUID Identifier : 03020100-0504-0706-0809-0A0B0C0D0E0F +[0002] Data Offset : 0000 diff --git a/platforms/rtsm_ve-aemv8a.acpi/xsdt.asl b/platforms/rtsm_ve-aemv8a.acpi/xsdt.asl new file mode 100644 index 0000000..d935006 --- /dev/null +++ b/platforms/rtsm_ve-aemv8a.acpi/xsdt.asl @@ -0,0 +1,39 @@ +/*

• • Copyright (c) 2013, Al Stone al.stone@linaro.org
• • [XSDT] Extended System Description Table
• • Format: [ByteLength] FieldName : HexFieldValue
• • This source is released under the terms of the GPLv2.
• */

+[0004] Signature : "XSDT" +[0004] Table Length : 00000064 +[0001] Revision : 01 +[0001] Checksum : 8B +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000014 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528

+[0008] ACPI Table Address 0 : 0000000000000010 +[0008] ACPI Table Address 0 : 0000000000000020 +[0008] ACPI Table Address 0 : 0000000000000030 +[0008] ACPI Table Address 0 : 0000000000000040 +[0008] ACPI Table Address 0 : 0000000000000050 +[0008] ACPI Table Address 0 : 0000000000000060 +[0008] ACPI Table Address 0 : 0000000000000070 +[0008] ACPI Table Address 0 : 0000000000000080 +[0008] ACPI Table Address 0 : 0000000000000090 +[0008] ACPI Table Address 0 : 00000000000000A0 +[0008] ACPI Table Address 0 : 00000000000000B0 +[0008] ACPI Table Address 0 : 00000000000000C0 +[0008] ACPI Table Address 0 : 00000000000000D0 +[0008] ACPI Table Address 0 : 00000000000000E0 +[0008] ACPI Table Address 0 : 00000000000000F0 +[0008] ACPI Table Address 0 : 0000000000000100 +[0008] ACPI Table Address 0 : 0000000000000110 +[0008] ACPI Table Address 0 : 0000000000000120 +[0008] ACPI Table Address 0 : 0000000000000130 +[0008] ACPI Table Address 0 : 0000000000000140