CPPC: ====
CPPC (Collaborative Processor Performance Control) is a new way to control CPU performance using an abstract continous scale as against a discretized P-state scale which is tied to CPU frequency only. It is defined in the ACPI 5.0+ spec. In brief, the basic operation involves: - OS makes a CPU performance request. (Can provide min and max tolerable bounds)
- Platform (such as BMC) is free to optimize request within requested bounds depending on power/thermal budgets etc.
- Platform conveys its decision back to OS
The communication between OS and platform occurs through another medium called (PCC) Platform communication Channel. This is a generic mailbox like mechanism which includes doorbell semantics to indicate register updates. See drivers/mailbox/pcc.c
This patchset introduces a CPPC based CPUFreq driver that works with existing governors such as ondemand. The CPPC table parsing and the CPPC communication semantics are abstracted into separate files to allow future CPPC based drivers to implement their own governors if required.
Initial patchsets included an adaptation of the PID governor from intel_pstate.c. However recent experiments led to extensive modifications of the algorithm to calculate CPU busyness. Until it is verified that these changes are worthwhile, the existing governors should provide for a good enough starting point for ARM64 servers.
Finer details about the PCC and CPPC spec are available in the latest ACPI 5.1 specification.[2]
Testing: =======
This was tested on an SBSA compatible ARMv8 server with CPPCv2 firmware running on a remote processor. I verified that each CPUs performance limits were detected and that new performance requests were made by the on-demand governor proportional to the load on each CPU. I also verified that using the acpi_processor driver correctly maps the physical CPU ids to logical CPU ids, which helps in picking up the proper _CPC details from a processor object, in the case where CPU physical ids may not be contiguous.
Changes since V8: - Fixed up several debug prints, return types and comments. - Simplified read/write ops using existing ACPI core API. - Removed ->get() from cpufreq driver for now. - Fixed bug introduced by copy-paste err in set_perf.
Changes since V7: - Simplied new kconfig options for PSS and idle. - Separated patch to enable acpi processor on ARM64. - Removed redundant kconfig cross deps on PCC. - Decoupled processor_perflib from new PSS kconfig option.
Changes since V6: - Separated PSS and CST from ACPI processor driver in two patches. - Made new Kconfig symbols auto selectable from Arch Kconfigs.
Changes since V5: - Checkpatch cleanups. - Change pss_init to pss_perf_init. Rec by Srinivas Pandruvada. - Explicit comment explaining why postcore_initcall to pcc mailbox. - Fold acpi_processor_syscore_init/exit into CONFIG_ACPI_CST. - Added patch with dummy functions used by ACPI_HOTPLUG_CPU.
Changes since V4: - Misc cleanups. Addressed feedback from Rafael. - Made acpi_processor.c independent of C-states, P-states and others. - Per CPU scanning for _CPC is now made from acpi_processor.c - Added new Kconfig options for legacy C states and P states to enable future support for newer alternatives as defined in the ACPI spec 6.0.
Changes since V3: - Split CPPC backend methods into separate files. - Add frontend driver which plugs into existing CPUfreq governors. - Simplify PCC driver by moving communication space mapping and read/write into client drivers.
Changes since V2: - Select driver if !X86, since intel_pstate will use HWP extensions instead. - Added more comments. - Added Freq domain awareness and PSD parsing.
Changes since V1: - Create a new driver based on Dirks suggestion. - Fold in CPPC backend hooks into main driver.
Changes since V0: [1] - Split intel_pstate.c into a generic PID governor and platform specific backend. - Add CPPC accessors as PID backend.
[1] - http://lwn.net/Articles/608715/ [2] - http://www.uefi.org/sites/default/files/resources/ACPI_5_1release.pdf [3] - https://patches.linaro.org/40705/
Ashwin Chaugule (5): ACPI: Introduce CPU performance controls using CPPC CPPC: Add a CPUFreq driver for use with CPPC ACPI: Add weak routines for ACPI CPU Hotplug CPPC: Probe for CPPC tables for each ACPI Processor object ACPI: Allow selection of the ACPI processor driver for ARM64
drivers/acpi/Kconfig | 20 +- drivers/acpi/Makefile | 1 + drivers/acpi/acpi_processor.c | 18 + drivers/acpi/cppc_acpi.c | 755 ++++++++++++++++++++++++++++++++++++++++ drivers/acpi/processor_driver.c | 6 + drivers/cpufreq/Kconfig.arm | 17 + drivers/cpufreq/Makefile | 2 + drivers/cpufreq/cppc_cpufreq.c | 169 +++++++++ include/acpi/cppc_acpi.h | 138 ++++++++ include/acpi/processor.h | 14 + 10 files changed, 1137 insertions(+), 3 deletions(-) create mode 100644 drivers/acpi/cppc_acpi.c create mode 100644 drivers/cpufreq/cppc_cpufreq.c create mode 100644 include/acpi/cppc_acpi.h
CPPC stands for Collaborative Processor Performance Controls and is defined in the ACPI v5.0+ spec. It describes CPU performance controls on an abstract and continuous scale allowing the platform (e.g. remote power processor) to flexibly optimize CPU performance with its knowledge of power budgets and other architecture specific knowledge.
This patch adds a shim which exports commonly used functions to get and set CPPC specific controls for each CPU. This enables CPUFreq drivers to gather per CPU performance data and use with exisiting governors or even allows for customized governors which are implemented inside CPUFreq drivers.
Signed-off-by: Ashwin Chaugule ashwin.chaugule@linaro.org Reviewed-by: Al Stone al.stone@linaro.org --- drivers/acpi/Kconfig | 14 + drivers/acpi/Makefile | 1 + drivers/acpi/cppc_acpi.c | 755 +++++++++++++++++++++++++++++++++++++++++++++++ include/acpi/cppc_acpi.h | 138 +++++++++ 4 files changed, 908 insertions(+) create mode 100644 drivers/acpi/cppc_acpi.c create mode 100644 include/acpi/cppc_acpi.h
diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index 54e9729..eef74b7 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -197,6 +197,20 @@ config ACPI_PROCESSOR_IDLE bool select CPU_IDLE
+config ACPI_CPPC_LIB + bool + depends on ACPI_PROCESSOR + depends on !ACPI_CPU_FREQ_PSS + select MAILBOX + select PCC + help + If this option is enabled, this file implements common functionality + to parse CPPC tables as described in the ACPI 5.1+ spec. The + routines implemented are meant to be used by other + drivers to control CPU performance using CPPC semantics. + If your platform does not support CPPC in firmware, + leave this option disabled. + config ACPI_PROCESSOR tristate "Processor" depends on X86 || IA64 diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile index 3ea59ae..4c393a69 100644 --- a/drivers/acpi/Makefile +++ b/drivers/acpi/Makefile @@ -78,6 +78,7 @@ obj-$(CONFIG_ACPI_HED) += hed.o obj-$(CONFIG_ACPI_EC_DEBUGFS) += ec_sys.o obj-$(CONFIG_ACPI_CUSTOM_METHOD)+= custom_method.o obj-$(CONFIG_ACPI_BGRT) += bgrt.o +obj-$(CONFIG_ACPI_CPPC_LIB) += cppc_acpi.o
# processor has its own "processor." module_param namespace processor-y := processor_driver.o diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c new file mode 100644 index 0000000..bcbfaf5 --- /dev/null +++ b/drivers/acpi/cppc_acpi.c @@ -0,0 +1,755 @@ +/* + * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers. + * + * (C) Copyright 2014, 2015 Linaro Ltd. + * Author: Ashwin Chaugule ashwin.chaugule@linaro.org + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; version 2 + * of the License. + * + * CPPC describes a few methods for controlling CPU performance using + * information from a per CPU table called CPC. This table is described in + * the ACPI v5.0+ specification. The table consists of a list of + * registers which may be memory mapped or hardware registers and also may + * include some static integer values. + * + * CPU performance is on an abstract continuous scale as against a discretized + * P-state scale which is tied to CPU frequency only. In brief, the basic + * operation involves: + * + * - OS makes a CPU performance request. (Can provide min and max bounds) + * + * - Platform (such as BMC) is free to optimize request within requested bounds + * depending on power/thermal budgets etc. + * + * - Platform conveys its decision back to OS + * + * The communication between OS and platform occurs through another medium + * called (PCC) Platform Communication Channel. This is a generic mailbox like + * mechanism which includes doorbell semantics to indicate register updates. + * See drivers/mailbox/pcc.c for details on PCC. + * + * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and + * above specifications. + */ + +#define pr_fmt(fmt) "ACPI CPPC: " fmt + +#include <linux/cpufreq.h> +#include <linux/delay.h> + +#include <acpi/cppc_acpi.h> +/* + * Lock to provide mutually exclusive access to the PCC + * channel. e.g. When the remote updates the shared region + * with new data, the reader needs to be protected from + * other CPUs activity on the same channel. + */ +static DEFINE_SPINLOCK(pcc_lock); + +/* + * The cpc_desc structure contains the ACPI register details + * as described in the per CPU _CPC tables. The details + * include the type of register (e.g. PCC, System IO, FFH etc.) + * and destination addresses which lets us READ/WRITE CPU performance + * information using the appropriate I/O methods. + */ +static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr); + +/* This layer handles all the PCC specifics for CPPC. */ +static struct mbox_chan *pcc_channel; +static void __iomem *pcc_comm_addr; +static u64 comm_base_addr; +static int pcc_subspace_idx = -1; +static u16 pcc_cmd_delay; +static bool pcc_channel_acquired; + +/* + * Arbitrary Retries in case the remote processor is slow to respond + * to PCC commands. + */ +#define NUM_RETRIES 500 + +static int send_pcc_cmd(u16 cmd) +{ + int retries, result = -EIO; + struct acpi_pcct_hw_reduced *pcct_ss = pcc_channel->con_priv; + struct acpi_pcct_shared_memory *generic_comm_base = + (struct acpi_pcct_shared_memory *) pcc_comm_addr; + u32 cmd_latency = pcct_ss->latency; + + /* Min time OS should wait before sending next command. */ + udelay(pcc_cmd_delay); + + /* Write to the shared comm region. */ + writew(cmd, &generic_comm_base->command); + + /* Flip CMD COMPLETE bit */ + writew(0, &generic_comm_base->status); + + /* Ring doorbell */ + result = mbox_send_message(pcc_channel, &cmd); + if (result < 0) { + pr_err("Err sending PCC mbox message. cmd:%d, ret:%d\n", + cmd, result); + return result; + } + + /* Wait for a nominal time to let platform process command. */ + udelay(cmd_latency); + + /* Retry in case the remote processor was too slow to catch up. */ + for (retries = NUM_RETRIES; retries > 0; retries--) { + if (readw_relaxed(&generic_comm_base->status) & PCC_CMD_COMPLETE) { + result = 0; + break; + } + } + + mbox_client_txdone(pcc_channel, result); + return result; +} + +static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret) +{ + if (ret) + pr_debug("TX did not complete: CMD sent:%x, ret:%d\n", + *(u16 *)msg, ret); + else + pr_debug("TX completed. CMD sent:%x, ret:%d\n", + *(u16 *)msg, ret); +} + +struct mbox_client cppc_mbox_cl = { + .tx_done = cppc_chan_tx_done, + .knows_txdone = true, +}; + +static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle) +{ + int result = -EFAULT; + acpi_status status = AE_OK; + struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL}; + struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"}; + struct acpi_buffer state = {0, NULL}; + union acpi_object *psd = NULL; + struct acpi_psd_package *pdomain; + + status = acpi_evaluate_object_typed(handle, "_PSD", NULL, &buffer, + ACPI_TYPE_PACKAGE); + if (ACPI_FAILURE(status)) + return -ENODEV; + + psd = buffer.pointer; + if (!psd || psd->package.count != 1) { + pr_debug("Invalid _PSD data\n"); + goto end; + } + + pdomain = &(cpc_ptr->domain_info); + + state.length = sizeof(struct acpi_psd_package); + state.pointer = pdomain; + + status = acpi_extract_package(&(psd->package.elements[0]), + &format, &state); + if (ACPI_FAILURE(status)) { + pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id); + goto end; + } + + if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) { + pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id); + goto end; + } + + if (pdomain->revision != ACPI_PSD_REV0_REVISION) { + pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id); + goto end; + } + + if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL && + pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY && + pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) { + pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id); + goto end; + } + + result = 0; +end: + kfree(buffer.pointer); + return result; +} + +/** + * acpi_get_psd_map - Map the CPUs in a common freq domain as indicated + * in the respective _PSD entries. + * @all_cpu_data: This array of pointers contains all the CPU specific + * details to access CPPC registers and freq domain information for each + * CPU. + * + * Return: 0 for success or negative value for err. + */ +int acpi_get_psd_map(struct cpudata **all_cpu_data) +{ + int count_target; + int retval = 0; + unsigned int i, j; + cpumask_var_t covered_cpus; + struct cpudata *pr, *match_pr; + struct acpi_psd_package *pdomain; + struct acpi_psd_package *match_pdomain; + struct cpc_desc *cpc_ptr, *match_cpc_ptr; + + if (!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL)) + return -ENOMEM; + + /* + * Now that we have _PSD data from all CPUs, lets setup P-state + * domain info. + */ + for_each_possible_cpu(i) { + pr = all_cpu_data[i]; + if (!pr) + continue; + + if (cpumask_test_cpu(i, covered_cpus)) + continue; + + cpc_ptr = per_cpu(cpc_desc_ptr, i); + if (!cpc_ptr) + continue; + + pdomain = &(cpc_ptr->domain_info); + cpumask_set_cpu(i, pr->shared_cpu_map); + cpumask_set_cpu(i, covered_cpus); + if (pdomain->num_processors <= 1) + continue; + + /* Validate the Domain info */ + count_target = pdomain->num_processors; + if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL) + pr->shared_type = CPUFREQ_SHARED_TYPE_ALL; + else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL) + pr->shared_type = CPUFREQ_SHARED_TYPE_HW; + else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY) + pr->shared_type = CPUFREQ_SHARED_TYPE_ANY; + + for_each_possible_cpu(j) { + if (i == j) + continue; + + match_cpc_ptr = per_cpu(cpc_desc_ptr, j); + if (!match_cpc_ptr) + continue; + + match_pdomain = &(match_cpc_ptr->domain_info); + if (match_pdomain->domain != pdomain->domain) + continue; + + /* Here i and j are in the same domain */ + if (match_pdomain->num_processors != count_target) { + retval = -EFAULT; + goto err_ret; + } + + if (pdomain->coord_type != match_pdomain->coord_type) { + retval = -EFAULT; + goto err_ret; + } + + cpumask_set_cpu(j, covered_cpus); + cpumask_set_cpu(j, pr->shared_cpu_map); + } + + for_each_possible_cpu(j) { + if (i == j) + continue; + + match_pr = all_cpu_data[j]; + if (!match_pr) + continue; + + match_cpc_ptr = per_cpu(cpc_desc_ptr, j); + if (!match_cpc_ptr) + continue; + + match_pdomain = &(match_cpc_ptr->domain_info); + if (match_pdomain->domain != pdomain->domain) + continue; + + match_pr->shared_type = pr->shared_type; + cpumask_copy(match_pr->shared_cpu_map, + pr->shared_cpu_map); + } + } + +err_ret: + for_each_possible_cpu(i) { + pr = all_cpu_data[i]; + if (!pr) + continue; + + /* Assume no coordination on any error parsing domain info */ + if (retval) { + cpumask_clear(pr->shared_cpu_map); + cpumask_set_cpu(i, pr->shared_cpu_map); + pr->shared_type = CPUFREQ_SHARED_TYPE_ALL; + } + } + + free_cpumask_var(covered_cpus); + return retval; +} +EXPORT_SYMBOL_GPL(acpi_get_psd_map); + +static int register_pcc_channel(unsigned pcc_subspace_idx) +{ + struct acpi_pcct_subspace *cppc_ss; + unsigned int len; + + if (pcc_subspace_idx >= 0) { + pcc_channel = pcc_mbox_request_channel(&cppc_mbox_cl, + pcc_subspace_idx); + + if (IS_ERR(pcc_channel)) { + pr_err("Failed to find PCC communication channel\n"); + return -ENODEV; + } + + /* + * The PCC mailbox controller driver should + * have parsed the PCCT (global table of all + * PCC channels) and stored pointers to the + * subspace communication region in con_priv. + */ + cppc_ss = pcc_channel->con_priv; + + if (!cppc_ss) { + pr_err("No PCC subspace found for CPPC\n"); + return -ENODEV; + } + + /* + * This is the shared communication region + * for the OS and Platform to communicate over. + */ + comm_base_addr = cppc_ss->base_address; + len = cppc_ss->length; + pcc_cmd_delay = cppc_ss->min_turnaround_time; + + pcc_comm_addr = acpi_os_ioremap(comm_base_addr, len); + if (!pcc_comm_addr) { + pr_err("Failed to ioremap PCC comm region mem\n"); + return -ENOMEM; + } + + /* Set flag so that we dont come here for each CPU. */ + pcc_channel_acquired = true; + + } + + /* + * If there are no PCC registers, then assume all regs + * are FFH, SystemIO or System mem. + */ + + return 0; +} + +/* + * An example CPC table looks like the following. + * + * Name(_CPC, Package() + * { + * 17, + * NumEntries + * 1, + * // Revision + * ResourceTemplate(){Register(PCC, 32, 0, 0x120, 2)}, + * // Highest Performance + * ResourceTemplate(){Register(PCC, 32, 0, 0x124, 2)}, + * // Nominal Performance + * ResourceTemplate(){Register(PCC, 32, 0, 0x128, 2)}, + * // Lowest Nonlinear Performance + * ResourceTemplate(){Register(PCC, 32, 0, 0x12C, 2)}, + * // Lowest Performance + * ResourceTemplate(){Register(PCC, 32, 0, 0x130, 2)}, + * // Guaranteed Performance Register + * ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)}, + * // Desired Performance Register + * ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, + * .. + * .. + * .. + * + * } + * Each Register() encodes how to access that specific register. + * e.g. a sample PCC entry has the following encoding: + * + * Register ( + * PCC, + * AddressSpaceKeyword + * 8, + * //RegisterBitWidth + * 8, + * //RegisterBitOffset + * 0x30, + * //RegisterAddress + * 9 + * //AccessSize (subspace ID) + * 0 + * ) + * } + */ + +/** + * acpi_cppc_processor_probe - Search for per CPU _CPC objects. + * @pr: This structure ptr comes from processor_driver.c for each ACPI + * Processor object detected. It also contains the physical + * to logical CPU id mapping. + * + * Return: 0 for success or negative value for err. + */ +int acpi_cppc_processor_probe(struct acpi_processor *pr) +{ + struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL}; + union acpi_object *out_obj, *cpc_obj; + struct cpc_desc *cpc_ptr; + struct cpc_reg *gas_t; + acpi_handle handle = pr->handle; + unsigned int num_ent, i, cpc_rev; + acpi_status status; + int ret = -EFAULT; + + /* Parse the ACPI _CPC table for this cpu. */ + status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output, + ACPI_TYPE_PACKAGE); + if (ACPI_FAILURE(status)) { + ret = -ENODEV; + goto out_buf_free; + } + + out_obj = (union acpi_object *) output.pointer; + + cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL); + if (!cpc_ptr) { + ret = -ENOMEM; + goto out_buf_free; + } + + /* First entry is NumEntries. */ + cpc_obj = &out_obj->package.elements[0]; + if (cpc_obj->type == ACPI_TYPE_INTEGER) { + num_ent = cpc_obj->integer.value; + } else { + pr_debug("Unexpected entry type(%d) for NumEntries\n", + cpc_obj->type); + goto out_free; + } + + /* Only support CPPCv2. Bail otherwise. */ + if (num_ent != CPPC_NUM_ENT) { + pr_debug("Firmware exports %d entries. Expected: %d\n", + num_ent, CPPC_NUM_ENT); + goto out_free; + } + + /* Second entry should be revision. */ + cpc_obj = &out_obj->package.elements[1]; + if (cpc_obj->type == ACPI_TYPE_INTEGER) { + cpc_rev = cpc_obj->integer.value; + } else { + pr_debug("Unexpected entry type(%d) for Revision\n", + cpc_obj->type); + goto out_free; + } + + if (cpc_rev != CPPC_REV) { + pr_debug("Firmware exports revision:%d. Expected:%d\n", + cpc_rev, CPPC_REV); + goto out_free; + } + + /* Iterate through remaining entries in _CPC */ + for (i = 2; i < num_ent; i++) { + cpc_obj = &out_obj->package.elements[i]; + + if (cpc_obj->type == ACPI_TYPE_INTEGER) { + cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER; + cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value; + } else if (cpc_obj->type == ACPI_TYPE_BUFFER) { + gas_t = (struct cpc_reg *) + cpc_obj->buffer.pointer; + + /* + * The PCC Subspace index is encoded inside + * the CPC table entries. The same PCC index + * will be used for all the PCC entries, + * so extract it only once. + */ + if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) { + if (pcc_subspace_idx < 0) + pcc_subspace_idx = gas_t->access_width; + else if (pcc_subspace_idx != gas_t->access_width) { + /* + * Mismatched PCC id detected. + * Firmware bug. + */ + pr_debug("Mismatched PCC ids\n"); + goto out_free; + } + } + + cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER; + memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t)); + } else { + pr_debug("Error in entry:%d in CPC table.\n", i); + goto out_free; + } + } + /* Store CPU Logical ID */ + cpc_ptr->cpu_id = pr->id; + + /* Plug it into this CPUs CPC descriptor. */ + per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr; + + /* Parse PSD data for this CPU */ + ret = acpi_get_psd(cpc_ptr, handle); + if (ret) + goto out_free; + + /* Register PCC channel once for all CPUs. */ + if (!pcc_channel_acquired) { + ret = register_pcc_channel(pcc_subspace_idx); + if (ret) + goto out_free; + } + + /* Everything looks okay */ + pr_debug("Successfully parsed CPC struct for CPU: %d\n", pr->id); + + kfree(output.pointer); + return 0; + +out_free: + cpc_ptr = per_cpu(cpc_desc_ptr, pr->id); + kfree(cpc_ptr); + +out_buf_free: + kfree(output.pointer); + return ret; +} +EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe); + +/** + * acpi_cppc_processor_exit - Cleanup CPC structs. + * @pr: This structure ptr comes from processor_driver.c for each ACPI + * Processor object detected. It also contains the physical + * to logical CPU id mapping. + * Return - Void + */ +void acpi_cppc_processor_exit(struct acpi_processor *pr) +{ + struct cpc_desc *cpc_ptr; + cpc_ptr = per_cpu(cpc_desc_ptr, pr->id); + kfree(cpc_ptr); +} +EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit); + +static u64 get_phys_pcc_addr(struct cpc_reg *reg) +{ + /* PCC communication addr space begins at byte offset 0x8. */ + return (u64)comm_base_addr + 0x8 + reg->address; +} + +static void cpc_read(struct cpc_reg *reg, u64 *val) +{ + u64 addr; + + if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) + addr = get_phys_pcc_addr(reg); + + acpi_os_read_memory((acpi_physical_address)addr, + val, reg->bit_width); + + /* TODO:Add FFH, SYSTEM_IO support later. */ +} + +static void cpc_write(struct cpc_reg *reg, u64 val) +{ + u64 addr; + + if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) + addr = get_phys_pcc_addr(reg); + + acpi_os_write_memory((acpi_physical_address)addr, + val, reg->bit_width); + + /* TODO:Add FFH, SYSTEM_IO support later. */ +} + +/** + * cppc_get_perf_caps - Get a CPUs performance capabilities. + * @cpunum: CPU from which to get capabilities info. + * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h + * + * Return - 0 for success with perf_caps populated else + * -ERRNO. + */ +int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps) +{ + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); + struct cpc_register_resource *highest_reg, *lowest_reg, *ref_perf, + *nom_perf; + u64 high, low, ref, nom; + int ret = 0; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU:%d\n", cpunum); + return -ENODEV; + } + + highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF]; + lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF]; + ref_perf = &cpc_desc->cpc_regs[REFERENCE_PERF]; + nom_perf = &cpc_desc->cpc_regs[NOMINAL_PERF]; + + spin_lock(&pcc_lock); + + /* Are any of the regs PCC ?*/ + if ((highest_reg->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) || + (lowest_reg->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) || + (ref_perf->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) || + (nom_perf->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM)) { + /* Ring doorbell once to update PCC subspace */ + if (send_pcc_cmd(CMD_READ)) { + ret = -EIO; + goto out_err; + } + } + + cpc_read(&highest_reg->cpc_entry.reg, &high); + perf_caps->highest_perf = high; + + cpc_read(&lowest_reg->cpc_entry.reg, &low); + perf_caps->lowest_perf = low; + + cpc_read(&ref_perf->cpc_entry.reg, &ref); + perf_caps->reference_perf = ref; + + cpc_read(&nom_perf->cpc_entry.reg, &nom); + perf_caps->nominal_perf = nom; + + if (!ref) + perf_caps->reference_perf = perf_caps->nominal_perf; + + if (!high || !low || !nom) + ret = -EFAULT; + +out_err: + spin_unlock(&pcc_lock); + return ret; +} +EXPORT_SYMBOL_GPL(cppc_get_perf_caps); + +/** + * cppc_get_perf_ctrs - Read a CPUs performance feedback counters. + * @cpunum: CPU from which to read counters. + * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h + * + * Return - 0 for success with perf_fb_ctrs populated else + * -ERRNO. + */ +int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) +{ + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); + struct cpc_register_resource *delivered_reg, *reference_reg; + u64 delivered, reference; + int ret = 0; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU:%d\n", cpunum); + return -ENODEV; + } + + delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR]; + reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR]; + + spin_lock(&pcc_lock); + + /* Are any of the regs PCC ?*/ + if ((delivered_reg->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) || + (reference_reg->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM)) { + /* Ring doorbell once to update PCC subspace */ + if (send_pcc_cmd(CMD_READ)) { + ret = -EIO; + goto out_err; + } + } + + cpc_read(&delivered_reg->cpc_entry.reg, &delivered); + cpc_read(&reference_reg->cpc_entry.reg, &reference); + + if (!delivered || !reference) { + ret = -EFAULT; + goto out_err; + } + + perf_fb_ctrs->delivered = delivered; + perf_fb_ctrs->reference = reference; + + perf_fb_ctrs->delivered -= perf_fb_ctrs->prev_delivered; + perf_fb_ctrs->reference -= perf_fb_ctrs->prev_reference; + + perf_fb_ctrs->prev_delivered = delivered; + perf_fb_ctrs->prev_reference = reference; + +out_err: + spin_unlock(&pcc_lock); + return ret; +} +EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); + +/** + * cppc_set_perf - Set a CPUs performance controls. + * @cpu: CPU for which to set performance controls. + * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h + * + * Return: 0 for success, -ERRNO otherwise. + */ +int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) +{ + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); + struct cpc_register_resource *desired_reg; + int ret = 0; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU:%d\n", cpu); + return -ENODEV; + } + + desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; + + spin_lock(&pcc_lock); + + /* + * Skip writing MIN/MAX until Linux knows how to come up with + * useful values. + */ + cpc_write(&desired_reg->cpc_entry.reg, perf_ctrls->desired_perf); + + /* Is this a PCC reg ?*/ + if (desired_reg->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) { + /* Ring doorbell so Remote can get our perf request. */ + if (send_pcc_cmd(CMD_WRITE)) + ret = -EIO; + } + + spin_unlock(&pcc_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(cppc_set_perf); diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h new file mode 100644 index 0000000..717a298 --- /dev/null +++ b/include/acpi/cppc_acpi.h @@ -0,0 +1,138 @@ +/* + * CPPC (Collaborative Processor Performance Control) methods used + * by CPUfreq drivers. + * + * (C) Copyright 2014, 2015 Linaro Ltd. + * Author: Ashwin Chaugule ashwin.chaugule@linaro.org + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; version 2 + * of the License. + */ + +#ifndef _CPPC_ACPI_H +#define _CPPC_ACPI_H + +#include <linux/acpi.h> +#include <linux/mailbox_controller.h> +#include <linux/mailbox_client.h> +#include <linux/types.h> + +#include <acpi/processor.h> + +/* Only support CPPCv2 for now. */ +#define CPPC_NUM_ENT 21 +#define CPPC_REV 2 + +#define PCC_CMD_COMPLETE 1 +#define MAX_CPC_REG_ENT 19 + +/* CPPC specific PCC commands. */ +#define CMD_READ 0 +#define CMD_WRITE 1 + +/* Each register has the folowing format. */ +struct cpc_reg { + u8 descriptor; + u16 length; + u8 space_id; + u8 bit_width; + u8 bit_offset; + u8 access_width; + u64 __iomem address; +} __packed; + +/* + * Each entry in the CPC table is either + * of type ACPI_TYPE_BUFFER or + * ACPI_TYPE_INTEGER. + */ +struct cpc_register_resource { + acpi_object_type type; + union { + struct cpc_reg reg; + u64 int_value; + } cpc_entry; +}; + +/* Container to hold the CPC details for each CPU */ +struct cpc_desc { + int num_entries; + int version; + int cpu_id; + struct cpc_register_resource cpc_regs[MAX_CPC_REG_ENT]; + struct acpi_psd_package domain_info; +}; + +/* These are indexes into the per-cpu cpc_regs[]. Order is important. */ +enum cppc_regs { + HIGHEST_PERF, + NOMINAL_PERF, + LOW_NON_LINEAR_PERF, + LOWEST_PERF, + GUARANTEED_PERF, + DESIRED_PERF, + MIN_PERF, + MAX_PERF, + PERF_REDUC_TOLERANCE, + TIME_WINDOW, + CTR_WRAP_TIME, + REFERENCE_CTR, + DELIVERED_CTR, + PERF_LIMITED, + ENABLE, + AUTO_SEL_ENABLE, + AUTO_ACT_WINDOW, + ENERGY_PERF, + REFERENCE_PERF, +}; + +/* + * Categorization of registers as described + * in the ACPI v.5.1 spec. + * XXX: Only filling up ones which are used by governors + * today. + */ +struct cppc_perf_caps { + u32 highest_perf; + u32 nominal_perf; + u32 reference_perf; + u32 lowest_perf; +}; + +struct cppc_perf_ctrls { + u32 max_perf; + u32 min_perf; + u32 desired_perf; +}; + +struct cppc_perf_fb_ctrs { + u64 reference; + u64 prev_reference; + u64 delivered; + u64 prev_delivered; +}; + +/* Per CPU container for runtime CPPC management. */ +struct cpudata { + int cpu; + struct cppc_perf_caps perf_caps; + struct cppc_perf_ctrls perf_ctrls; + struct cppc_perf_fb_ctrs perf_fb_ctrs; + struct cpufreq_policy *cur_policy; + unsigned int shared_type; + cpumask_var_t shared_cpu_map; +}; + +extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); +extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); +extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps); +extern int acpi_get_psd_map(struct cpudata **); + +/* Methods to interact with the PCC mailbox controller. */ +extern struct mbox_chan * + pcc_mbox_request_channel(struct mbox_client *, unsigned int); +extern int mbox_send_message(struct mbox_chan *chan, void *mssg); + +#endif /* _CPPC_ACPI_H*/
Hi Rafael,
Are there any more suggestions for this patch series? I noticed a compiler warning, which was strangely hidden before I sent v9. Will fix and resend if there isnt anything else.
On 9 September 2015 at 16:27, Ashwin Chaugule ashwin.chaugule@linaro.org wrote:
CPPC stands for Collaborative Processor Performance Controls and is defined in the ACPI v5.0+ spec. It describes CPU performance controls on an abstract and continuous scale allowing the platform (e.g. remote power processor) to flexibly optimize CPU performance with its knowledge of power budgets and other architecture specific knowledge.
This patch adds a shim which exports commonly used functions to get and set CPPC specific controls for each CPU. This enables CPUFreq drivers to gather per CPU performance data and use with exisiting governors or even allows for customized governors which are implemented inside CPUFreq drivers.
Signed-off-by: Ashwin Chaugule ashwin.chaugule@linaro.org Reviewed-by: Al Stone al.stone@linaro.org
drivers/acpi/Kconfig | 14 + drivers/acpi/Makefile | 1 + drivers/acpi/cppc_acpi.c | 755 +++++++++++++++++++++++++++++++++++++++++++++++ include/acpi/cppc_acpi.h | 138 +++++++++ 4 files changed, 908 insertions(+) create mode 100644 drivers/acpi/cppc_acpi.c create mode 100644 include/acpi/cppc_acpi.h
[..]
+static u64 get_phys_pcc_addr(struct cpc_reg *reg) +{
/* PCC communication addr space begins at byte offset 0x8. */
return (u64)comm_base_addr + 0x8 + reg->address;
+}
+static void cpc_read(struct cpc_reg *reg, u64 *val) +{
u64 addr;
Default addr = reg->address; That'll enable sys mem type read/write ops.
if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM)
addr = get_phys_pcc_addr(reg);
Or alternately, fold this into a function get_phys_addr() which parses for type PCC, sys mem. etc. and returns address.
acpi_os_read_memory((acpi_physical_address)addr,
val, reg->bit_width);
/* TODO:Add FFH, SYSTEM_IO support later. */
Will add a pr_err() if type is FFH/Sys IO. Likewise below.
+}
+static void cpc_write(struct cpc_reg *reg, u64 val) +{
u64 addr;
if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM)
addr = get_phys_pcc_addr(reg);
acpi_os_write_memory((acpi_physical_address)addr,
val, reg->bit_width);
/* TODO:Add FFH, SYSTEM_IO support later. */
+}
Regards, Ashwin.
On Wednesday, September 23, 2015 07:09:49 AM Ashwin Chaugule wrote:
Hi Rafael,
Are there any more suggestions for this patch series?
Not at the moment. I'll get to it tomorrow or failing that early next week.
Thanks, Rafael
On Wednesday, September 09, 2015 04:27:04 PM Ashwin Chaugule wrote:
CPPC stands for Collaborative Processor Performance Controls and is defined in the ACPI v5.0+ spec. It describes CPU performance controls on an abstract and continuous scale allowing the platform (e.g. remote power processor) to flexibly optimize CPU performance with its knowledge of power budgets and other architecture specific knowledge.
This patch adds a shim which exports commonly used functions to get and set CPPC specific controls for each CPU. This enables CPUFreq drivers to gather per CPU performance data and use with exisiting governors or even allows for customized governors which are implemented inside CPUFreq drivers.
Signed-off-by: Ashwin Chaugule ashwin.chaugule@linaro.org Reviewed-by: Al Stone al.stone@linaro.org
[cut]
+/**
- acpi_get_psd_map - Map the CPUs in a common freq domain as indicated
- in the respective _PSD entries.
One minor nit: this needs to be one-line in a proper kerneldoc.
- @all_cpu_data: This array of pointers contains all the CPU specific
- details to access CPPC registers and freq domain information for each
- CPU.
Ditto.
You can add more description below.
[cut]
+int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) +{
- struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
- struct cpc_register_resource *delivered_reg, *reference_reg;
- u64 delivered, reference;
- int ret = 0;
- if (!cpc_desc) {
pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
return -ENODEV;
- }
- delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
- reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
- spin_lock(&pcc_lock);
I still have the question about this lock.
Why does it have to be a spinlock?
Rafael
Hi Rafael,
On 25 September 2015 at 20:05, Rafael J. Wysocki rjw@rjwysocki.net wrote:
On Wednesday, September 09, 2015 04:27:04 PM Ashwin Chaugule wrote:
CPPC stands for Collaborative Processor Performance Controls and is defined in the ACPI v5.0+ spec. It describes CPU performance controls on an abstract and continuous scale allowing the platform (e.g. remote power processor) to flexibly optimize CPU performance with its knowledge of power budgets and other architecture specific knowledge.
This patch adds a shim which exports commonly used functions to get and set CPPC specific controls for each CPU. This enables CPUFreq drivers to gather per CPU performance data and use with exisiting governors or even allows for customized governors which are implemented inside CPUFreq drivers.
Signed-off-by: Ashwin Chaugule ashwin.chaugule@linaro.org Reviewed-by: Al Stone al.stone@linaro.org
[cut]
+/**
- acpi_get_psd_map - Map the CPUs in a common freq domain as indicated
- in the respective _PSD entries.
One minor nit: this needs to be one-line in a proper kerneldoc.
- @all_cpu_data: This array of pointers contains all the CPU specific
- details to access CPPC registers and freq domain information for each
- CPU.
Ditto.
You can add more description below.
Ok. Will do.
[cut]
+int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) +{
struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
struct cpc_register_resource *delivered_reg, *reference_reg;
u64 delivered, reference;
int ret = 0;
if (!cpc_desc) {
pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
return -ENODEV;
}
delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
spin_lock(&pcc_lock);
I still have the question about this lock.
Why does it have to be a spinlock?
The idea is to let CPUs send in their requests as quickly as possible. The PCC transaction only relays the request. So the CPUs don't really wait for all the clk + voltage toggling etc. I think any other primitive, might cause unnecessary delays in sending requests. Also FWIW, this is another thing I was influenced by from the pcc-cpufreq.c driver. :)
Regards, Ashwin.
On Sunday, September 27, 2015 01:15:20 PM Ashwin Chaugule wrote:
Hi Rafael,
On 25 September 2015 at 20:05, Rafael J. Wysocki rjw@rjwysocki.net wrote:
On Wednesday, September 09, 2015 04:27:04 PM Ashwin Chaugule wrote:
CPPC stands for Collaborative Processor Performance Controls and is defined in the ACPI v5.0+ spec. It describes CPU performance controls on an abstract and continuous scale allowing the platform (e.g. remote power processor) to flexibly optimize CPU performance with its knowledge of power budgets and other architecture specific knowledge.
This patch adds a shim which exports commonly used functions to get and set CPPC specific controls for each CPU. This enables CPUFreq drivers to gather per CPU performance data and use with exisiting governors or even allows for customized governors which are implemented inside CPUFreq drivers.
Signed-off-by: Ashwin Chaugule ashwin.chaugule@linaro.org Reviewed-by: Al Stone al.stone@linaro.org
[cut]
+/**
- acpi_get_psd_map - Map the CPUs in a common freq domain as indicated
- in the respective _PSD entries.
One minor nit: this needs to be one-line in a proper kerneldoc.
- @all_cpu_data: This array of pointers contains all the CPU specific
- details to access CPPC registers and freq domain information for each
- CPU.
Ditto.
You can add more description below.
Ok. Will do.
[cut]
+int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) +{
struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
struct cpc_register_resource *delivered_reg, *reference_reg;
u64 delivered, reference;
int ret = 0;
if (!cpc_desc) {
pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
return -ENODEV;
}
delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
spin_lock(&pcc_lock);
I still have the question about this lock.
Why does it have to be a spinlock?
The idea is to let CPUs send in their requests as quickly as possible. The PCC transaction only relays the request. So the CPUs don't really wait for all the clk + voltage toggling etc. I think any other primitive, might cause unnecessary delays in sending requests.
It might if there was contention.
Also FWIW, this is another thing I was influenced by from the pcc-cpufreq.c driver. :)
OK, so this sounds like an optimization, which is fine.
Thanks, Rafael
Hi Rafael,
On 28 September 2015 at 09:36, Rafael J. Wysocki rjw@rjwysocki.net wrote:
On Sunday, September 27, 2015 01:15:20 PM Ashwin Chaugule wrote:
On 25 September 2015 at 20:05, Rafael J. Wysocki rjw@rjwysocki.net wrote:
On Wednesday, September 09, 2015 04:27:04 PM Ashwin Chaugule wrote:
+int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) +{
struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
struct cpc_register_resource *delivered_reg, *reference_reg;
u64 delivered, reference;
int ret = 0;
if (!cpc_desc) {
pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
return -ENODEV;
}
delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
spin_lock(&pcc_lock);
I still have the question about this lock.
Why does it have to be a spinlock?
The idea is to let CPUs send in their requests as quickly as possible. The PCC transaction only relays the request. So the CPUs don't really wait for all the clk + voltage toggling etc. I think any other primitive, might cause unnecessary delays in sending requests.
It might if there was contention.
Also FWIW, this is another thing I was influenced by from the pcc-cpufreq.c driver. :)
OK, so this sounds like an optimization, which is fine.
Great. Would you prefer a git pull request with the kernel doc + compiler warning fix, or should I send V10 ?
Regards, Ashwin.
On Thursday, October 01, 2015 06:20:50 AM Ashwin Chaugule wrote:
Hi Rafael,
On 28 September 2015 at 09:36, Rafael J. Wysocki rjw@rjwysocki.net wrote:
On Sunday, September 27, 2015 01:15:20 PM Ashwin Chaugule wrote:
On 25 September 2015 at 20:05, Rafael J. Wysocki rjw@rjwysocki.net wrote:
On Wednesday, September 09, 2015 04:27:04 PM Ashwin Chaugule wrote:
+int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) +{
struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
struct cpc_register_resource *delivered_reg, *reference_reg;
u64 delivered, reference;
int ret = 0;
if (!cpc_desc) {
pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
return -ENODEV;
}
delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
spin_lock(&pcc_lock);
I still have the question about this lock.
Why does it have to be a spinlock?
The idea is to let CPUs send in their requests as quickly as possible. The PCC transaction only relays the request. So the CPUs don't really wait for all the clk + voltage toggling etc. I think any other primitive, might cause unnecessary delays in sending requests.
It might if there was contention.
Also FWIW, this is another thing I was influenced by from the pcc-cpufreq.c driver. :)
OK, so this sounds like an optimization, which is fine.
Great. Would you prefer a git pull request
No pull requests, please.
with the kernel doc + compiler warning fix, or should I send V10 ?
You can simply update the patches that need to be updated.
Thanks, Rafael
CPPC stands for Collaborative Processor Performance Controls and is defined in the ACPI v5.0+ spec. It describes CPU performance controls on an abstract and continuous scale allowing the platform (e.g. remote power processor) to flexibly optimize CPU performance with its knowledge of power budgets and other architecture specific knowledge.
This patch adds a shim which exports commonly used functions to get and set CPPC specific controls for each CPU. This enables CPUFreq drivers to gather per CPU performance data and use with exisiting governors or even allows for customized governors which are implemented inside CPUFreq drivers.
Signed-off-by: Ashwin Chaugule ashwin.chaugule@linaro.org Reviewed-by: Al Stone al.stone@linaro.org --- drivers/acpi/Kconfig | 14 + drivers/acpi/Makefile | 1 + drivers/acpi/cppc_acpi.c | 734 +++++++++++++++++++++++++++++++++++++++++++++++ include/acpi/cppc_acpi.h | 138 +++++++++ 4 files changed, 887 insertions(+) create mode 100644 drivers/acpi/cppc_acpi.c create mode 100644 include/acpi/cppc_acpi.h
diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index 54e9729..eef74b7 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -197,6 +197,20 @@ config ACPI_PROCESSOR_IDLE bool select CPU_IDLE
+config ACPI_CPPC_LIB + bool + depends on ACPI_PROCESSOR + depends on !ACPI_CPU_FREQ_PSS + select MAILBOX + select PCC + help + If this option is enabled, this file implements common functionality + to parse CPPC tables as described in the ACPI 5.1+ spec. The + routines implemented are meant to be used by other + drivers to control CPU performance using CPPC semantics. + If your platform does not support CPPC in firmware, + leave this option disabled. + config ACPI_PROCESSOR tristate "Processor" depends on X86 || IA64 diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile index 3ea59ae..4c393a69 100644 --- a/drivers/acpi/Makefile +++ b/drivers/acpi/Makefile @@ -78,6 +78,7 @@ obj-$(CONFIG_ACPI_HED) += hed.o obj-$(CONFIG_ACPI_EC_DEBUGFS) += ec_sys.o obj-$(CONFIG_ACPI_CUSTOM_METHOD)+= custom_method.o obj-$(CONFIG_ACPI_BGRT) += bgrt.o +obj-$(CONFIG_ACPI_CPPC_LIB) += cppc_acpi.o
# processor has its own "processor." module_param namespace processor-y := processor_driver.o diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c new file mode 100644 index 0000000..0bbf84b --- /dev/null +++ b/drivers/acpi/cppc_acpi.c @@ -0,0 +1,734 @@ +/* + * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers. + * + * (C) Copyright 2014, 2015 Linaro Ltd. + * Author: Ashwin Chaugule ashwin.chaugule@linaro.org + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; version 2 + * of the License. + * + * CPPC describes a few methods for controlling CPU performance using + * information from a per CPU table called CPC. This table is described in + * the ACPI v5.0+ specification. The table consists of a list of + * registers which may be memory mapped or hardware registers and also may + * include some static integer values. + * + * CPU performance is on an abstract continuous scale as against a discretized + * P-state scale which is tied to CPU frequency only. In brief, the basic + * operation involves: + * + * - OS makes a CPU performance request. (Can provide min and max bounds) + * + * - Platform (such as BMC) is free to optimize request within requested bounds + * depending on power/thermal budgets etc. + * + * - Platform conveys its decision back to OS + * + * The communication between OS and platform occurs through another medium + * called (PCC) Platform Communication Channel. This is a generic mailbox like + * mechanism which includes doorbell semantics to indicate register updates. + * See drivers/mailbox/pcc.c for details on PCC. + * + * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and + * above specifications. + */ + +#define pr_fmt(fmt) "ACPI CPPC: " fmt + +#include <linux/cpufreq.h> +#include <linux/delay.h> + +#include <acpi/cppc_acpi.h> +/* + * Lock to provide mutually exclusive access to the PCC + * channel. e.g. When the remote updates the shared region + * with new data, the reader needs to be protected from + * other CPUs activity on the same channel. + */ +static DEFINE_SPINLOCK(pcc_lock); + +/* + * The cpc_desc structure contains the ACPI register details + * as described in the per CPU _CPC tables. The details + * include the type of register (e.g. PCC, System IO, FFH etc.) + * and destination addresses which lets us READ/WRITE CPU performance + * information using the appropriate I/O methods. + */ +static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr); + +/* This layer handles all the PCC specifics for CPPC. */ +static struct mbox_chan *pcc_channel; +static void __iomem *pcc_comm_addr; +static u64 comm_base_addr; +static int pcc_subspace_idx = -1; +static u16 pcc_cmd_delay; +static bool pcc_channel_acquired; + +/* + * Arbitrary Retries in case the remote processor is slow to respond + * to PCC commands. + */ +#define NUM_RETRIES 500 + +static int send_pcc_cmd(u16 cmd) +{ + int retries, result = -EIO; + struct acpi_pcct_hw_reduced *pcct_ss = pcc_channel->con_priv; + struct acpi_pcct_shared_memory *generic_comm_base = + (struct acpi_pcct_shared_memory *) pcc_comm_addr; + u32 cmd_latency = pcct_ss->latency; + + /* Min time OS should wait before sending next command. */ + udelay(pcc_cmd_delay); + + /* Write to the shared comm region. */ + writew(cmd, &generic_comm_base->command); + + /* Flip CMD COMPLETE bit */ + writew(0, &generic_comm_base->status); + + /* Ring doorbell */ + result = mbox_send_message(pcc_channel, &cmd); + if (result < 0) { + pr_err("Err sending PCC mbox message. cmd:%d, ret:%d\n", + cmd, result); + return result; + } + + /* Wait for a nominal time to let platform process command. */ + udelay(cmd_latency); + + /* Retry in case the remote processor was too slow to catch up. */ + for (retries = NUM_RETRIES; retries > 0; retries--) { + if (readw_relaxed(&generic_comm_base->status) & PCC_CMD_COMPLETE) { + result = 0; + break; + } + } + + mbox_client_txdone(pcc_channel, result); + return result; +} + +static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret) +{ + if (ret) + pr_debug("TX did not complete: CMD sent:%x, ret:%d\n", + *(u16 *)msg, ret); + else + pr_debug("TX completed. CMD sent:%x, ret:%d\n", + *(u16 *)msg, ret); +} + +struct mbox_client cppc_mbox_cl = { + .tx_done = cppc_chan_tx_done, + .knows_txdone = true, +}; + +static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle) +{ + int result = -EFAULT; + acpi_status status = AE_OK; + struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL}; + struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"}; + struct acpi_buffer state = {0, NULL}; + union acpi_object *psd = NULL; + struct acpi_psd_package *pdomain; + + status = acpi_evaluate_object_typed(handle, "_PSD", NULL, &buffer, + ACPI_TYPE_PACKAGE); + if (ACPI_FAILURE(status)) + return -ENODEV; + + psd = buffer.pointer; + if (!psd || psd->package.count != 1) { + pr_debug("Invalid _PSD data\n"); + goto end; + } + + pdomain = &(cpc_ptr->domain_info); + + state.length = sizeof(struct acpi_psd_package); + state.pointer = pdomain; + + status = acpi_extract_package(&(psd->package.elements[0]), + &format, &state); + if (ACPI_FAILURE(status)) { + pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id); + goto end; + } + + if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) { + pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id); + goto end; + } + + if (pdomain->revision != ACPI_PSD_REV0_REVISION) { + pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id); + goto end; + } + + if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL && + pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY && + pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) { + pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id); + goto end; + } + + result = 0; +end: + kfree(buffer.pointer); + return result; +} + +/** + * acpi_get_psd_map - Map the CPUs in a common freq domain. + * @all_cpu_data: Ptrs to CPU specific CPPC data including PSD info. + * + * Return: 0 for success or negative value for err. + */ +int acpi_get_psd_map(struct cpudata **all_cpu_data) +{ + int count_target; + int retval = 0; + unsigned int i, j; + cpumask_var_t covered_cpus; + struct cpudata *pr, *match_pr; + struct acpi_psd_package *pdomain; + struct acpi_psd_package *match_pdomain; + struct cpc_desc *cpc_ptr, *match_cpc_ptr; + + if (!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL)) + return -ENOMEM; + + /* + * Now that we have _PSD data from all CPUs, lets setup P-state + * domain info. + */ + for_each_possible_cpu(i) { + pr = all_cpu_data[i]; + if (!pr) + continue; + + if (cpumask_test_cpu(i, covered_cpus)) + continue; + + cpc_ptr = per_cpu(cpc_desc_ptr, i); + if (!cpc_ptr) + continue; + + pdomain = &(cpc_ptr->domain_info); + cpumask_set_cpu(i, pr->shared_cpu_map); + cpumask_set_cpu(i, covered_cpus); + if (pdomain->num_processors <= 1) + continue; + + /* Validate the Domain info */ + count_target = pdomain->num_processors; + if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL) + pr->shared_type = CPUFREQ_SHARED_TYPE_ALL; + else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL) + pr->shared_type = CPUFREQ_SHARED_TYPE_HW; + else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY) + pr->shared_type = CPUFREQ_SHARED_TYPE_ANY; + + for_each_possible_cpu(j) { + if (i == j) + continue; + + match_cpc_ptr = per_cpu(cpc_desc_ptr, j); + if (!match_cpc_ptr) + continue; + + match_pdomain = &(match_cpc_ptr->domain_info); + if (match_pdomain->domain != pdomain->domain) + continue; + + /* Here i and j are in the same domain */ + if (match_pdomain->num_processors != count_target) { + retval = -EFAULT; + goto err_ret; + } + + if (pdomain->coord_type != match_pdomain->coord_type) { + retval = -EFAULT; + goto err_ret; + } + + cpumask_set_cpu(j, covered_cpus); + cpumask_set_cpu(j, pr->shared_cpu_map); + } + + for_each_possible_cpu(j) { + if (i == j) + continue; + + match_pr = all_cpu_data[j]; + if (!match_pr) + continue; + + match_cpc_ptr = per_cpu(cpc_desc_ptr, j); + if (!match_cpc_ptr) + continue; + + match_pdomain = &(match_cpc_ptr->domain_info); + if (match_pdomain->domain != pdomain->domain) + continue; + + match_pr->shared_type = pr->shared_type; + cpumask_copy(match_pr->shared_cpu_map, + pr->shared_cpu_map); + } + } + +err_ret: + for_each_possible_cpu(i) { + pr = all_cpu_data[i]; + if (!pr) + continue; + + /* Assume no coordination on any error parsing domain info */ + if (retval) { + cpumask_clear(pr->shared_cpu_map); + cpumask_set_cpu(i, pr->shared_cpu_map); + pr->shared_type = CPUFREQ_SHARED_TYPE_ALL; + } + } + + free_cpumask_var(covered_cpus); + return retval; +} +EXPORT_SYMBOL_GPL(acpi_get_psd_map); + +static int register_pcc_channel(unsigned pcc_subspace_idx) +{ + struct acpi_pcct_subspace *cppc_ss; + unsigned int len; + + if (pcc_subspace_idx >= 0) { + pcc_channel = pcc_mbox_request_channel(&cppc_mbox_cl, + pcc_subspace_idx); + + if (IS_ERR(pcc_channel)) { + pr_err("Failed to find PCC communication channel\n"); + return -ENODEV; + } + + /* + * The PCC mailbox controller driver should + * have parsed the PCCT (global table of all + * PCC channels) and stored pointers to the + * subspace communication region in con_priv. + */ + cppc_ss = pcc_channel->con_priv; + + if (!cppc_ss) { + pr_err("No PCC subspace found for CPPC\n"); + return -ENODEV; + } + + /* + * This is the shared communication region + * for the OS and Platform to communicate over. + */ + comm_base_addr = cppc_ss->base_address; + len = cppc_ss->length; + pcc_cmd_delay = cppc_ss->min_turnaround_time; + + pcc_comm_addr = acpi_os_ioremap(comm_base_addr, len); + if (!pcc_comm_addr) { + pr_err("Failed to ioremap PCC comm region mem\n"); + return -ENOMEM; + } + + /* Set flag so that we dont come here for each CPU. */ + pcc_channel_acquired = true; + } + + return 0; +} + +/* + * An example CPC table looks like the following. + * + * Name(_CPC, Package() + * { + * 17, + * NumEntries + * 1, + * // Revision + * ResourceTemplate(){Register(PCC, 32, 0, 0x120, 2)}, + * // Highest Performance + * ResourceTemplate(){Register(PCC, 32, 0, 0x124, 2)}, + * // Nominal Performance + * ResourceTemplate(){Register(PCC, 32, 0, 0x128, 2)}, + * // Lowest Nonlinear Performance + * ResourceTemplate(){Register(PCC, 32, 0, 0x12C, 2)}, + * // Lowest Performance + * ResourceTemplate(){Register(PCC, 32, 0, 0x130, 2)}, + * // Guaranteed Performance Register + * ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)}, + * // Desired Performance Register + * ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, + * .. + * .. + * .. + * + * } + * Each Register() encodes how to access that specific register. + * e.g. a sample PCC entry has the following encoding: + * + * Register ( + * PCC, + * AddressSpaceKeyword + * 8, + * //RegisterBitWidth + * 8, + * //RegisterBitOffset + * 0x30, + * //RegisterAddress + * 9 + * //AccessSize (subspace ID) + * 0 + * ) + * } + */ + +/** + * acpi_cppc_processor_probe - Search for per CPU _CPC objects. + * @pr: Ptr to acpi_processor containing this CPUs logical Id. + * + * Return: 0 for success or negative value for err. + */ +int acpi_cppc_processor_probe(struct acpi_processor *pr) +{ + struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL}; + union acpi_object *out_obj, *cpc_obj; + struct cpc_desc *cpc_ptr; + struct cpc_reg *gas_t; + acpi_handle handle = pr->handle; + unsigned int num_ent, i, cpc_rev; + acpi_status status; + int ret = -EFAULT; + + /* Parse the ACPI _CPC table for this cpu. */ + status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output, + ACPI_TYPE_PACKAGE); + if (ACPI_FAILURE(status)) { + ret = -ENODEV; + goto out_buf_free; + } + + out_obj = (union acpi_object *) output.pointer; + + cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL); + if (!cpc_ptr) { + ret = -ENOMEM; + goto out_buf_free; + } + + /* First entry is NumEntries. */ + cpc_obj = &out_obj->package.elements[0]; + if (cpc_obj->type == ACPI_TYPE_INTEGER) { + num_ent = cpc_obj->integer.value; + } else { + pr_debug("Unexpected entry type(%d) for NumEntries\n", + cpc_obj->type); + goto out_free; + } + + /* Only support CPPCv2. Bail otherwise. */ + if (num_ent != CPPC_NUM_ENT) { + pr_debug("Firmware exports %d entries. Expected: %d\n", + num_ent, CPPC_NUM_ENT); + goto out_free; + } + + /* Second entry should be revision. */ + cpc_obj = &out_obj->package.elements[1]; + if (cpc_obj->type == ACPI_TYPE_INTEGER) { + cpc_rev = cpc_obj->integer.value; + } else { + pr_debug("Unexpected entry type(%d) for Revision\n", + cpc_obj->type); + goto out_free; + } + + if (cpc_rev != CPPC_REV) { + pr_debug("Firmware exports revision:%d. Expected:%d\n", + cpc_rev, CPPC_REV); + goto out_free; + } + + /* Iterate through remaining entries in _CPC */ + for (i = 2; i < num_ent; i++) { + cpc_obj = &out_obj->package.elements[i]; + + if (cpc_obj->type == ACPI_TYPE_INTEGER) { + cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER; + cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value; + } else if (cpc_obj->type == ACPI_TYPE_BUFFER) { + gas_t = (struct cpc_reg *) + cpc_obj->buffer.pointer; + + /* + * The PCC Subspace index is encoded inside + * the CPC table entries. The same PCC index + * will be used for all the PCC entries, + * so extract it only once. + */ + if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) { + if (pcc_subspace_idx < 0) + pcc_subspace_idx = gas_t->access_width; + else if (pcc_subspace_idx != gas_t->access_width) { + pr_debug("Mismatched PCC ids.\n"); + goto out_free; + } + } else if (gas_t->space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) { + /* Support only PCC and SYS MEM type regs */ + pr_debug("Unsupported register type: %d\n", gas_t->space_id); + goto out_free; + } + + cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER; + memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t)); + } else { + pr_debug("Err in entry:%d in CPC table of CPU:%d \n", i, pr->id); + goto out_free; + } + } + /* Store CPU Logical ID */ + cpc_ptr->cpu_id = pr->id; + + /* Plug it into this CPUs CPC descriptor. */ + per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr; + + /* Parse PSD data for this CPU */ + ret = acpi_get_psd(cpc_ptr, handle); + if (ret) + goto out_free; + + /* Register PCC channel once for all CPUs. */ + if (!pcc_channel_acquired) { + ret = register_pcc_channel(pcc_subspace_idx); + if (ret) + goto out_free; + } + + /* Everything looks okay */ + pr_debug("Parsed CPC struct for CPU: %d\n", pr->id); + + kfree(output.pointer); + return 0; + +out_free: + cpc_ptr = per_cpu(cpc_desc_ptr, pr->id); + kfree(cpc_ptr); + +out_buf_free: + kfree(output.pointer); + return ret; +} +EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe); + +/** + * acpi_cppc_processor_exit - Cleanup CPC structs. + * @pr: Ptr to acpi_processor containing this CPUs logical Id. + * + * Return: Void + */ +void acpi_cppc_processor_exit(struct acpi_processor *pr) +{ + struct cpc_desc *cpc_ptr; + cpc_ptr = per_cpu(cpc_desc_ptr, pr->id); + kfree(cpc_ptr); +} +EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit); + +static u64 get_phys_addr(struct cpc_reg *reg) +{ + /* PCC communication addr space begins at byte offset 0x8. */ + if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) + return (u64)comm_base_addr + 0x8 + reg->address; + else + return reg->address; +} + +static void cpc_read(struct cpc_reg *reg, u64 *val) +{ + u64 addr = get_phys_addr(reg); + + acpi_os_read_memory((acpi_physical_address)addr, + val, reg->bit_width); +} + +static void cpc_write(struct cpc_reg *reg, u64 val) +{ + u64 addr = get_phys_addr(reg); + + acpi_os_write_memory((acpi_physical_address)addr, + val, reg->bit_width); +} + +/** + * cppc_get_perf_caps - Get a CPUs performance capabilities. + * @cpunum: CPU from which to get capabilities info. + * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h + * + * Return: 0 for success with perf_caps populated else -ERRNO. + */ +int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps) +{ + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); + struct cpc_register_resource *highest_reg, *lowest_reg, *ref_perf, + *nom_perf; + u64 high, low, ref, nom; + int ret = 0; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU:%d\n", cpunum); + return -ENODEV; + } + + highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF]; + lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF]; + ref_perf = &cpc_desc->cpc_regs[REFERENCE_PERF]; + nom_perf = &cpc_desc->cpc_regs[NOMINAL_PERF]; + + spin_lock(&pcc_lock); + + /* Are any of the regs PCC ?*/ + if ((highest_reg->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) || + (lowest_reg->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) || + (ref_perf->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) || + (nom_perf->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM)) { + /* Ring doorbell once to update PCC subspace */ + if (send_pcc_cmd(CMD_READ)) { + ret = -EIO; + goto out_err; + } + } + + cpc_read(&highest_reg->cpc_entry.reg, &high); + perf_caps->highest_perf = high; + + cpc_read(&lowest_reg->cpc_entry.reg, &low); + perf_caps->lowest_perf = low; + + cpc_read(&ref_perf->cpc_entry.reg, &ref); + perf_caps->reference_perf = ref; + + cpc_read(&nom_perf->cpc_entry.reg, &nom); + perf_caps->nominal_perf = nom; + + if (!ref) + perf_caps->reference_perf = perf_caps->nominal_perf; + + if (!high || !low || !nom) + ret = -EFAULT; + +out_err: + spin_unlock(&pcc_lock); + return ret; +} +EXPORT_SYMBOL_GPL(cppc_get_perf_caps); + +/** + * cppc_get_perf_ctrs - Read a CPUs performance feedback counters. + * @cpunum: CPU from which to read counters. + * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h + * + * Return: 0 for success with perf_fb_ctrs populated else -ERRNO. + */ +int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) +{ + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); + struct cpc_register_resource *delivered_reg, *reference_reg; + u64 delivered, reference; + int ret = 0; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU:%d\n", cpunum); + return -ENODEV; + } + + delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR]; + reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR]; + + spin_lock(&pcc_lock); + + /* Are any of the regs PCC ?*/ + if ((delivered_reg->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) || + (reference_reg->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM)) { + /* Ring doorbell once to update PCC subspace */ + if (send_pcc_cmd(CMD_READ)) { + ret = -EIO; + goto out_err; + } + } + + cpc_read(&delivered_reg->cpc_entry.reg, &delivered); + cpc_read(&reference_reg->cpc_entry.reg, &reference); + + if (!delivered || !reference) { + ret = -EFAULT; + goto out_err; + } + + perf_fb_ctrs->delivered = delivered; + perf_fb_ctrs->reference = reference; + + perf_fb_ctrs->delivered -= perf_fb_ctrs->prev_delivered; + perf_fb_ctrs->reference -= perf_fb_ctrs->prev_reference; + + perf_fb_ctrs->prev_delivered = delivered; + perf_fb_ctrs->prev_reference = reference; + +out_err: + spin_unlock(&pcc_lock); + return ret; +} +EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); + +/** + * cppc_set_perf - Set a CPUs performance controls. + * @cpu: CPU for which to set performance controls. + * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h + * + * Return: 0 for success, -ERRNO otherwise. + */ +int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) +{ + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); + struct cpc_register_resource *desired_reg; + int ret = 0; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU:%d\n", cpu); + return -ENODEV; + } + + desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; + + spin_lock(&pcc_lock); + + /* + * Skip writing MIN/MAX until Linux knows how to come up with + * useful values. + */ + cpc_write(&desired_reg->cpc_entry.reg, perf_ctrls->desired_perf); + + /* Is this a PCC reg ?*/ + if (desired_reg->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) { + /* Ring doorbell so Remote can get our perf request. */ + if (send_pcc_cmd(CMD_WRITE)) + ret = -EIO; + } + + spin_unlock(&pcc_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(cppc_set_perf); diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h new file mode 100644 index 0000000..717a298 --- /dev/null +++ b/include/acpi/cppc_acpi.h @@ -0,0 +1,138 @@ +/* + * CPPC (Collaborative Processor Performance Control) methods used + * by CPUfreq drivers. + * + * (C) Copyright 2014, 2015 Linaro Ltd. + * Author: Ashwin Chaugule ashwin.chaugule@linaro.org + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; version 2 + * of the License. + */ + +#ifndef _CPPC_ACPI_H +#define _CPPC_ACPI_H + +#include <linux/acpi.h> +#include <linux/mailbox_controller.h> +#include <linux/mailbox_client.h> +#include <linux/types.h> + +#include <acpi/processor.h> + +/* Only support CPPCv2 for now. */ +#define CPPC_NUM_ENT 21 +#define CPPC_REV 2 + +#define PCC_CMD_COMPLETE 1 +#define MAX_CPC_REG_ENT 19 + +/* CPPC specific PCC commands. */ +#define CMD_READ 0 +#define CMD_WRITE 1 + +/* Each register has the folowing format. */ +struct cpc_reg { + u8 descriptor; + u16 length; + u8 space_id; + u8 bit_width; + u8 bit_offset; + u8 access_width; + u64 __iomem address; +} __packed; + +/* + * Each entry in the CPC table is either + * of type ACPI_TYPE_BUFFER or + * ACPI_TYPE_INTEGER. + */ +struct cpc_register_resource { + acpi_object_type type; + union { + struct cpc_reg reg; + u64 int_value; + } cpc_entry; +}; + +/* Container to hold the CPC details for each CPU */ +struct cpc_desc { + int num_entries; + int version; + int cpu_id; + struct cpc_register_resource cpc_regs[MAX_CPC_REG_ENT]; + struct acpi_psd_package domain_info; +}; + +/* These are indexes into the per-cpu cpc_regs[]. Order is important. */ +enum cppc_regs { + HIGHEST_PERF, + NOMINAL_PERF, + LOW_NON_LINEAR_PERF, + LOWEST_PERF, + GUARANTEED_PERF, + DESIRED_PERF, + MIN_PERF, + MAX_PERF, + PERF_REDUC_TOLERANCE, + TIME_WINDOW, + CTR_WRAP_TIME, + REFERENCE_CTR, + DELIVERED_CTR, + PERF_LIMITED, + ENABLE, + AUTO_SEL_ENABLE, + AUTO_ACT_WINDOW, + ENERGY_PERF, + REFERENCE_PERF, +}; + +/* + * Categorization of registers as described + * in the ACPI v.5.1 spec. + * XXX: Only filling up ones which are used by governors + * today. + */ +struct cppc_perf_caps { + u32 highest_perf; + u32 nominal_perf; + u32 reference_perf; + u32 lowest_perf; +}; + +struct cppc_perf_ctrls { + u32 max_perf; + u32 min_perf; + u32 desired_perf; +}; + +struct cppc_perf_fb_ctrs { + u64 reference; + u64 prev_reference; + u64 delivered; + u64 prev_delivered; +}; + +/* Per CPU container for runtime CPPC management. */ +struct cpudata { + int cpu; + struct cppc_perf_caps perf_caps; + struct cppc_perf_ctrls perf_ctrls; + struct cppc_perf_fb_ctrs perf_fb_ctrs; + struct cpufreq_policy *cur_policy; + unsigned int shared_type; + cpumask_var_t shared_cpu_map; +}; + +extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); +extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); +extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps); +extern int acpi_get_psd_map(struct cpudata **); + +/* Methods to interact with the PCC mailbox controller. */ +extern struct mbox_chan * + pcc_mbox_request_channel(struct mbox_client *, unsigned int); +extern int mbox_send_message(struct mbox_chan *chan, void *mssg); + +#endif /* _CPPC_ACPI_H*/
This driver utilizes the methods introduced in the previous patch - "ACPI: Introduce CPU performance controls using CPPC" and enables usage with existing CPUFreq governors.
Signed-off-by: Ashwin Chaugule ashwin.chaugule@linaro.org Reviewed-by: Al Stone al.stone@linaro.org --- drivers/cpufreq/Kconfig.arm | 17 +++++ drivers/cpufreq/Makefile | 2 + drivers/cpufreq/cppc_cpufreq.c | 169 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 188 insertions(+) create mode 100644 drivers/cpufreq/cppc_cpufreq.c
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index cc8a71c..e8bb41b 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -261,3 +261,20 @@ config ARM_PXA2xx_CPUFREQ This add the CPUFreq driver support for Intel PXA2xx SOCs.
If in doubt, say N. + +config ACPI_CPPC_CPUFREQ + tristate "CPUFreq driver based on the ACPI CPPC spec" + depends on ACPI + select ACPI_CPPC_LIB + default n + help + This adds a CPUFreq driver which uses CPPC methods + as described in the ACPIv5.1 spec. CPPC stands for + Collaborative Processor Performance Controls. It + is based on an abstract continuous scale of CPU + performance values which allows the remote power + processor to flexibly optimize for power and + performance. CPPC relies on power management firmware + support for its operation. + + If in doubt, say N. diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index 2169bf7..676660e 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -78,6 +78,8 @@ obj-$(CONFIG_ARM_SA1110_CPUFREQ) += sa1110-cpufreq.o obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o obj-$(CONFIG_ARM_TEGRA_CPUFREQ) += tegra-cpufreq.o obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ) += vexpress-spc-cpufreq.o +obj-$(CONFIG_ACPI_CPPC_CPUFREQ) += cppc_cpufreq.o +
################################################################################## # PowerPC platform drivers diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c new file mode 100644 index 0000000..2f6ed0b --- /dev/null +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -0,0 +1,169 @@ +/* + * CPPC (Collaborative Processor Performance Control) driver for + * interfacing with the CPUfreq layer and governors. See + * cppc_acpi.c for CPPC specific methods. + * + * (C) Copyright 2014, 2015 Linaro Ltd. + * Author: Ashwin Chaugule ashwin.chaugule@linaro.org + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; version 2 + * of the License. + */ + +#define pr_fmt(fmt) "CPPC Cpufreq:" fmt + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/delay.h> +#include <linux/cpu.h> +#include <linux/cpufreq.h> +#include <linux/vmalloc.h> + +#include <acpi/cppc_acpi.h> + +/* + * These structs contain information parsed from per CPU + * ACPI _CPC structures. + * e.g. For each CPU the highest, lowest supported + * performance capabilities, desired performance level + * requested etc. + */ +static struct cpudata **all_cpu_data; + +static int cppc_cpufreq_set_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + struct cpudata *cpu; + struct cpufreq_freqs freqs; + int ret = 0; + + cpu = all_cpu_data[policy->cpu]; + + cpu->perf_ctrls.desired_perf = target_freq; + freqs.old = policy->cur; + freqs.new = target_freq; + + cpufreq_freq_transition_begin(policy, &freqs); + ret = cppc_set_perf(cpu->cpu, &cpu->perf_ctrls); + cpufreq_freq_transition_end(policy, &freqs, ret != 0); + + if (ret) { + pr_debug("Failed to set target on CPU:%d. ret:%d\n", + cpu->cpu, ret); + return -EFAULT; + } + + return ret; +} + +static int cppc_verify_policy(struct cpufreq_policy *policy) +{ + cpufreq_verify_within_cpu_limits(policy); + return 0; +} + +static void cppc_cpufreq_stop_cpu(struct cpufreq_policy *policy) +{ + int cpu_num = policy->cpu; + struct cpudata *cpu = all_cpu_data[cpu_num]; + int ret; + + pr_info("CPU %d exiting\n", cpu_num); + + cpu->perf_ctrls.desired_perf = cpu->perf_caps.lowest_perf; + + ret = cppc_set_perf(cpu_num, &cpu->perf_ctrls); + if (ret) + pr_err("Err setting perf value:%d on CPU:%d. ret:%d\n", + cpu->perf_caps.lowest_perf, cpu_num, ret); +} + +static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) +{ + struct cpudata *cpu; + int ret = 0; + + cpu = all_cpu_data[policy->cpu]; + + cpu->cpu = policy->cpu; + ret = cppc_get_perf_caps(policy->cpu, &cpu->perf_caps); + + if (ret) { + pr_err("Err reading CPU%d perf capabilities. ret:%d\n", + cpu->cpu, ret); + return -FAULT; + } + + policy->min = cpu->perf_caps.lowest_perf; + policy->max = cpu->perf_caps.highest_perf; + policy->cpuinfo.min_freq = policy->min; + policy->cpuinfo.max_freq = policy->max; + + if (policy->shared_type == CPUFREQ_SHARED_TYPE_ALL || + policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) + cpumask_copy(policy->cpus, cpu->shared_cpu_map); + + cpumask_set_cpu(policy->cpu, policy->cpus); + cpu->cur_policy = policy; + + pr_debug("Initialized on cpu:%d\n", cpu->cpu); + return ret; +} + +static struct cpufreq_driver cppc_cpufreq_driver = { + .flags = CPUFREQ_CONST_LOOPS, + .verify = cppc_verify_policy, + .target = cppc_cpufreq_set_target, + .init = cppc_cpufreq_cpu_init, + .stop_cpu = cppc_cpufreq_stop_cpu, + .name = "cppc_cpufreq", +}; + +static int __init cppc_cpufreq_init(void) +{ + int i, ret = 0; + struct cpudata *cpu; + + if (acpi_disabled) + return -ENODEV; + + all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); + if (!all_cpu_data) + return -ENOMEM; + + for_each_possible_cpu(i) { + all_cpu_data[i] = kzalloc(sizeof(struct cpudata), GFP_KERNEL); + if (!all_cpu_data[i]) + goto out; + + cpu = all_cpu_data[i]; + if (!zalloc_cpumask_var(&cpu->shared_cpu_map, GFP_KERNEL)) + goto out; + } + + ret = acpi_get_psd_map(all_cpu_data); + if (ret) { + pr_debug("Error parsing PSD data. Aborting cpufreq registration.\n"); + goto out; + } + + ret = cpufreq_register_driver(&cppc_cpufreq_driver); + if (ret) + goto out; + + pr_info("Registration completed.\n"); + return ret; + +out: + for_each_possible_cpu(i) + if (all_cpu_data[i]) + kfree(all_cpu_data[i]); + + vfree(all_cpu_data); + return -ENODEV; +} + +late_initcall(cppc_cpufreq_init);
This driver utilizes the methods introduced in a previous patch titled - "ACPI: Introduce CPU performance controls using CPPC" and enables usage with existing CPUFreq governors.
Signed-off-by: Ashwin Chaugule ashwin.chaugule@linaro.org Reviewed-by: Al Stone al.stone@linaro.org --- drivers/cpufreq/Kconfig.arm | 17 ++++ drivers/cpufreq/Makefile | 2 + drivers/cpufreq/cppc_cpufreq.c | 176 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 195 insertions(+) create mode 100644 drivers/cpufreq/cppc_cpufreq.c
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index cc8a71c..e8bb41b 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -261,3 +261,20 @@ config ARM_PXA2xx_CPUFREQ This add the CPUFreq driver support for Intel PXA2xx SOCs.
If in doubt, say N. + +config ACPI_CPPC_CPUFREQ + tristate "CPUFreq driver based on the ACPI CPPC spec" + depends on ACPI + select ACPI_CPPC_LIB + default n + help + This adds a CPUFreq driver which uses CPPC methods + as described in the ACPIv5.1 spec. CPPC stands for + Collaborative Processor Performance Controls. It + is based on an abstract continuous scale of CPU + performance values which allows the remote power + processor to flexibly optimize for power and + performance. CPPC relies on power management firmware + support for its operation. + + If in doubt, say N. diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index 2169bf7..676660e 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -78,6 +78,8 @@ obj-$(CONFIG_ARM_SA1110_CPUFREQ) += sa1110-cpufreq.o obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o obj-$(CONFIG_ARM_TEGRA_CPUFREQ) += tegra-cpufreq.o obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ) += vexpress-spc-cpufreq.o +obj-$(CONFIG_ACPI_CPPC_CPUFREQ) += cppc_cpufreq.o +
################################################################################## # PowerPC platform drivers diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c new file mode 100644 index 0000000..93c219f --- /dev/null +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -0,0 +1,176 @@ +/* + * CPPC (Collaborative Processor Performance Control) driver for + * interfacing with the CPUfreq layer and governors. See + * cppc_acpi.c for CPPC specific methods. + * + * (C) Copyright 2014, 2015 Linaro Ltd. + * Author: Ashwin Chaugule ashwin.chaugule@linaro.org + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; version 2 + * of the License. + */ + +#define pr_fmt(fmt) "CPPC Cpufreq:" fmt + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/delay.h> +#include <linux/cpu.h> +#include <linux/cpufreq.h> +#include <linux/vmalloc.h> + +#include <acpi/cppc_acpi.h> + +/* + * These structs contain information parsed from per CPU + * ACPI _CPC structures. + * e.g. For each CPU the highest, lowest supported + * performance capabilities, desired performance level + * requested etc. + */ +static struct cpudata **all_cpu_data; + +static int cppc_cpufreq_set_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + struct cpudata *cpu; + struct cpufreq_freqs freqs; + int ret = 0; + + cpu = all_cpu_data[policy->cpu]; + + cpu->perf_ctrls.desired_perf = target_freq; + freqs.old = policy->cur; + freqs.new = target_freq; + + cpufreq_freq_transition_begin(policy, &freqs); + ret = cppc_set_perf(cpu->cpu, &cpu->perf_ctrls); + cpufreq_freq_transition_end(policy, &freqs, ret != 0); + + if (ret) + pr_debug("Failed to set target on CPU:%d. ret:%d\n", + cpu->cpu, ret); + + return ret; +} + +static int cppc_verify_policy(struct cpufreq_policy *policy) +{ + cpufreq_verify_within_cpu_limits(policy); + return 0; +} + +static void cppc_cpufreq_stop_cpu(struct cpufreq_policy *policy) +{ + int cpu_num = policy->cpu; + struct cpudata *cpu = all_cpu_data[cpu_num]; + int ret; + + cpu->perf_ctrls.desired_perf = cpu->perf_caps.lowest_perf; + + ret = cppc_set_perf(cpu_num, &cpu->perf_ctrls); + if (ret) + pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n", + cpu->perf_caps.lowest_perf, cpu_num, ret); +} + +static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) +{ + struct cpudata *cpu; + unsigned int cpu_num = policy->cpu; + int ret = 0; + + cpu = all_cpu_data[policy->cpu]; + + cpu->cpu = cpu_num; + ret = cppc_get_perf_caps(policy->cpu, &cpu->perf_caps); + + if (ret) { + pr_debug("Err reading CPU%d perf capabilities. ret:%d\n", + cpu_num, ret); + return ret; + } + + policy->min = cpu->perf_caps.lowest_perf; + policy->max = cpu->perf_caps.highest_perf; + policy->cpuinfo.min_freq = policy->min; + policy->cpuinfo.max_freq = policy->max; + + if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) + cpumask_copy(policy->cpus, cpu->shared_cpu_map); + else { + /* Support only SW_ANY for now. */ + pr_debug("Unsupported CPU co-ord type\n"); + return -EFAULT; + } + + cpumask_set_cpu(policy->cpu, policy->cpus); + cpu->cur_policy = policy; + + /* Set policy->cur to max now. The governors will adjust later. */ + policy->cur = cpu->perf_ctrls.desired_perf = cpu->perf_caps.highest_perf; + + ret = cppc_set_perf(cpu_num, &cpu->perf_ctrls); + if (ret) + pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n", + cpu->perf_caps.highest_perf, cpu_num, ret); + + return ret; +} + +static struct cpufreq_driver cppc_cpufreq_driver = { + .flags = CPUFREQ_CONST_LOOPS, + .verify = cppc_verify_policy, + .target = cppc_cpufreq_set_target, + .init = cppc_cpufreq_cpu_init, + .stop_cpu = cppc_cpufreq_stop_cpu, + .name = "cppc_cpufreq", +}; + +static int __init cppc_cpufreq_init(void) +{ + int i, ret = 0; + struct cpudata *cpu; + + if (acpi_disabled) + return -ENODEV; + + all_cpu_data = kzalloc(sizeof(void *) * num_possible_cpus(), GFP_KERNEL); + if (!all_cpu_data) + return -ENOMEM; + + for_each_possible_cpu(i) { + all_cpu_data[i] = kzalloc(sizeof(struct cpudata), GFP_KERNEL); + if (!all_cpu_data[i]) + goto out; + + cpu = all_cpu_data[i]; + if (!zalloc_cpumask_var(&cpu->shared_cpu_map, GFP_KERNEL)) + goto out; + } + + ret = acpi_get_psd_map(all_cpu_data); + if (ret) { + pr_debug("Error parsing PSD data. Aborting cpufreq registration.\n"); + goto out; + } + + ret = cpufreq_register_driver(&cppc_cpufreq_driver); + if (ret) + goto out; + + return ret; + +out: + for_each_possible_cpu(i) + if (all_cpu_data[i]) + kfree(all_cpu_data[i]); + + kfree(all_cpu_data); + return -ENODEV; +} + +late_initcall(cppc_cpufreq_init);
On Friday, October 02, 2015 10:04:01 AM Ashwin Chaugule wrote:
This driver utilizes the methods introduced in a previous patch titled - "ACPI: Introduce CPU performance controls using CPPC" and enables usage with existing CPUFreq governors.
Signed-off-by: Ashwin Chaugule ashwin.chaugule@linaro.org Reviewed-by: Al Stone al.stone@linaro.org
This doesn't seem to apply for me, care to refresh (on top of my bleeding-edge branch)?
Thanks, Rafael
On Monday, October 12, 2015 11:23:01 PM Rafael J. Wysocki wrote:
On Friday, October 02, 2015 10:04:01 AM Ashwin Chaugule wrote:
This driver utilizes the methods introduced in a previous patch titled - "ACPI: Introduce CPU performance controls using CPPC" and enables usage with existing CPUFreq governors.
Signed-off-by: Ashwin Chaugule ashwin.chaugule@linaro.org Reviewed-by: Al Stone al.stone@linaro.org
This doesn't seem to apply for me, care to refresh (on top of my bleeding-edge branch)?
Never mind, I've resolved this already.
Thanks, Rafael
On 12 October 2015 at 17:34, Rafael J. Wysocki rjw@rjwysocki.net wrote:
On Monday, October 12, 2015 11:23:01 PM Rafael J. Wysocki wrote:
On Friday, October 02, 2015 10:04:01 AM Ashwin Chaugule wrote:
This driver utilizes the methods introduced in a previous patch titled - "ACPI: Introduce CPU performance controls using CPPC" and enables usage with existing CPUFreq governors.
Signed-off-by: Ashwin Chaugule ashwin.chaugule@linaro.org Reviewed-by: Al Stone al.stone@linaro.org
This doesn't seem to apply for me, care to refresh (on top of my bleeding-edge branch)?
Never mind, I've resolved this already.
Guessing some Makefile conflict. Thanks though!
Regards, Ashwin.
Add weak functions for architectures which do not support hot-adding and removing CPUs which aren't detected at bootup. (e.g. via MADT).
This helps preserve the Kconfig dependency from:
commit cbfc1bae55bb ("[ACPI] ACPI_HOTPLUG_CPU Kconfig dependency update")
prevent:
HOTPLUG_CPU=y ACPI_PROCESSOR=y ACPI_HOTPLUG_CPU=n
Signed-off-by: Ashwin Chaugule ashwin.chaugule@linaro.org --- drivers/acpi/acpi_processor.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
diff --git a/drivers/acpi/acpi_processor.c b/drivers/acpi/acpi_processor.c index 92a5f73..e1e0285 100644 --- a/drivers/acpi/acpi_processor.c +++ b/drivers/acpi/acpi_processor.c @@ -164,6 +164,24 @@ static int acpi_processor_errata(void) -------------------------------------------------------------------------- */
#ifdef CONFIG_ACPI_HOTPLUG_CPU +int __weak acpi_map_cpu(acpi_handle handle, + phys_cpuid_t physid, int *pcpu) +{ + return -ENODEV; +} + +int __weak acpi_unmap_cpu(int cpu) +{ + return -ENODEV; +} + +int __weak arch_register_cpu(int cpu) +{ + return -ENODEV; +} + +void __weak arch_unregister_cpu(int cpu) {} + static int acpi_processor_hotadd_init(struct acpi_processor *pr) { unsigned long long sta;
For each detected ACPI Processor object (ACPI0007), search its device handle for CPPC specific tables (i.e. _CPC) and extract CPU specific performance capabilities.
Signed-off-by: Ashwin Chaugule ashwin.chaugule@linaro.org Reviewed-by: Al Stone al.stone@linaro.org --- drivers/acpi/processor_driver.c | 6 ++++++ include/acpi/processor.h | 14 ++++++++++++++ 2 files changed, 20 insertions(+)
diff --git a/drivers/acpi/processor_driver.c b/drivers/acpi/processor_driver.c index 16d44ad..6519c22 100644 --- a/drivers/acpi/processor_driver.c +++ b/drivers/acpi/processor_driver.c @@ -246,6 +246,10 @@ static int __acpi_processor_start(struct acpi_device *device) if (pr->flags.need_hotplug_init) return 0;
+ result = acpi_cppc_processor_probe(pr); + if (result) + return -ENODEV; + if (!cpuidle_get_driver() || cpuidle_get_driver() == &acpi_idle_driver) acpi_processor_power_init(pr);
@@ -291,6 +295,8 @@ static int acpi_processor_stop(struct device *dev)
acpi_pss_perf_exit(pr, device);
+ acpi_cppc_processor_exit(pr); + return 0; }
diff --git a/include/acpi/processor.h b/include/acpi/processor.h index 2c4e7a9..43ee1bf 100644 --- a/include/acpi/processor.h +++ b/include/acpi/processor.h @@ -314,6 +314,20 @@ phys_cpuid_t acpi_get_phys_id(acpi_handle, int type, u32 acpi_id); int acpi_map_cpuid(phys_cpuid_t phys_id, u32 acpi_id); int acpi_get_cpuid(acpi_handle, int type, u32 acpi_id);
+#ifdef CONFIG_ACPI_CPPC_LIB +extern int acpi_cppc_processor_probe(struct acpi_processor *pr); +extern void acpi_cppc_processor_exit(struct acpi_processor *pr); +#else +static inline int acpi_cppc_processor_probe(struct acpi_processor *pr) +{ + return 0; +} +static inline void acpi_cppc_processor_exit(struct acpi_processor *pr) +{ + return; +} +#endif /* CONFIG_ACPI_CPPC_LIB */ + /* in processor_pdc.c */ void acpi_processor_set_pdc(acpi_handle handle);
Now that the ACPI processor driver has been decoupled from the C states and P states functionality, make it selectable on ARM64 so that it can be used by others e.g. CPPC.
The C states and P states code is selected only on X86 or IA64 until the relevant support is added on ARM64.
Signed-off-by: Ashwin Chaugule ashwin.chaugule@linaro.org --- drivers/acpi/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index eef74b7..97788bf 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -213,9 +213,9 @@ config ACPI_CPPC_LIB
config ACPI_PROCESSOR tristate "Processor" - depends on X86 || IA64 - select ACPI_PROCESSOR_IDLE - select ACPI_CPU_FREQ_PSS + depends on X86 || IA64 || ARM64 + select ACPI_PROCESSOR_IDLE if X86 || IA64 + select ACPI_CPU_FREQ_PSS if X86 || IA64 default y help This driver adds support for the ACPI Processor package. It is required
On Wednesday, September 09, 2015 04:27:03 PM Ashwin Chaugule wrote:
CPPC:
CPPC (Collaborative Processor Performance Control) is a new way to control CPU performance using an abstract continous scale as against a discretized P-state scale which is tied to CPU frequency only. It is defined in the ACPI 5.0+ spec. In brief, the basic operation involves:
OS makes a CPU performance request. (Can provide min and max tolerable bounds)
Platform (such as BMC) is free to optimize request within requested bounds depending
on power/thermal budgets etc.
- Platform conveys its decision back to OS
The communication between OS and platform occurs through another medium called (PCC) Platform communication Channel. This is a generic mailbox like mechanism which includes doorbell semantics to indicate register updates. See drivers/mailbox/pcc.c
This patchset introduces a CPPC based CPUFreq driver that works with existing governors such as ondemand. The CPPC table parsing and the CPPC communication semantics are abstracted into separate files to allow future CPPC based drivers to implement their own governors if required.
Initial patchsets included an adaptation of the PID governor from intel_pstate.c. However recent experiments led to extensive modifications of the algorithm to calculate CPU busyness. Until it is verified that these changes are worthwhile, the existing governors should provide for a good enough starting point for ARM64 servers.
Finer details about the PCC and CPPC spec are available in the latest ACPI 5.1 specification.[2]
Testing:
This was tested on an SBSA compatible ARMv8 server with CPPCv2 firmware running on a remote processor. I verified that each CPUs performance limits were detected and that new performance requests were made by the on-demand governor proportional to the load on each CPU. I also verified that using the acpi_processor driver correctly maps the physical CPU ids to logical CPU ids, which helps in picking up the proper _CPC details from a processor object, in the case where CPU physical ids may not be contiguous.
Changes since V8:
- Fixed up several debug prints, return types and comments.
- Simplified read/write ops using existing ACPI core API.
- Removed ->get() from cpufreq driver for now.
- Fixed bug introduced by copy-paste err in set_perf.
Changes since V7:
- Simplied new kconfig options for PSS and idle.
- Separated patch to enable acpi processor on ARM64.
- Removed redundant kconfig cross deps on PCC.
- Decoupled processor_perflib from new PSS kconfig option.
Changes since V6:
- Separated PSS and CST from ACPI processor driver in two patches.
- Made new Kconfig symbols auto selectable from Arch Kconfigs.
Changes since V5:
- Checkpatch cleanups.
- Change pss_init to pss_perf_init. Rec by Srinivas Pandruvada.
- Explicit comment explaining why postcore_initcall to pcc mailbox.
- Fold acpi_processor_syscore_init/exit into CONFIG_ACPI_CST.
- Added patch with dummy functions used by ACPI_HOTPLUG_CPU.
Changes since V4:
- Misc cleanups. Addressed feedback from Rafael.
- Made acpi_processor.c independent of C-states, P-states and others.
- Per CPU scanning for _CPC is now made from acpi_processor.c
- Added new Kconfig options for legacy C states and P states to enable future
support for newer alternatives as defined in the ACPI spec 6.0.
Changes since V3:
- Split CPPC backend methods into separate files.
- Add frontend driver which plugs into existing CPUfreq governors.
- Simplify PCC driver by moving communication space mapping and read/write into client drivers.
Changes since V2:
- Select driver if !X86, since intel_pstate will use HWP extensions instead.
- Added more comments.
- Added Freq domain awareness and PSD parsing.
Changes since V1:
- Create a new driver based on Dirks suggestion.
- Fold in CPPC backend hooks into main driver.
Changes since V0: [1]
- Split intel_pstate.c into a generic PID governor and platform specific backend.
- Add CPPC accessors as PID backend.
[1] - http://lwn.net/Articles/608715/ [2] - http://www.uefi.org/sites/default/files/resources/ACPI_5_1release.pdf [3] - https://patches.linaro.org/40705/
Ashwin Chaugule (5): ACPI: Introduce CPU performance controls using CPPC CPPC: Add a CPUFreq driver for use with CPPC ACPI: Add weak routines for ACPI CPU Hotplug CPPC: Probe for CPPC tables for each ACPI Processor object ACPI: Allow selection of the ACPI processor driver for ARM64
drivers/acpi/Kconfig | 20 +- drivers/acpi/Makefile | 1 + drivers/acpi/acpi_processor.c | 18 + drivers/acpi/cppc_acpi.c | 755 ++++++++++++++++++++++++++++++++++++++++ drivers/acpi/processor_driver.c | 6 + drivers/cpufreq/Kconfig.arm | 17 + drivers/cpufreq/Makefile | 2 + drivers/cpufreq/cppc_cpufreq.c | 169 +++++++++ include/acpi/cppc_acpi.h | 138 ++++++++ include/acpi/processor.h | 14 + 10 files changed, 1137 insertions(+), 3 deletions(-) create mode 100644 drivers/acpi/cppc_acpi.c create mode 100644 drivers/cpufreq/cppc_cpufreq.c create mode 100644 include/acpi/cppc_acpi.h
Series queued up for v4.4 (with the updates).
Thanks, Rafael
On 12 October 2015 at 17:37, Rafael J. Wysocki rjw@rjwysocki.net wrote:
On Wednesday, September 09, 2015 04:27:03 PM Ashwin Chaugule wrote:
CPPC:
CPPC (Collaborative Processor Performance Control) is a new way to control CPU performance using an abstract continous scale as against a discretized P-state scale which is tied to CPU frequency only. It is defined in the ACPI 5.0+ spec. In brief, the basic operation involves:
OS makes a CPU performance request. (Can provide min and max tolerable bounds)
Platform (such as BMC) is free to optimize request within requested bounds depending
on power/thermal budgets etc.
- Platform conveys its decision back to OS
The communication between OS and platform occurs through another medium called (PCC) Platform communication Channel. This is a generic mailbox like mechanism which includes doorbell semantics to indicate register updates. See drivers/mailbox/pcc.c
This patchset introduces a CPPC based CPUFreq driver that works with existing governors such as ondemand. The CPPC table parsing and the CPPC communication semantics are abstracted into separate files to allow future CPPC based drivers to implement their own governors if required.
Initial patchsets included an adaptation of the PID governor from intel_pstate.c. However recent experiments led to extensive modifications of the algorithm to calculate CPU busyness. Until it is verified that these changes are worthwhile, the existing governors should provide for a good enough starting point for ARM64 servers.
Finer details about the PCC and CPPC spec are available in the latest ACPI 5.1 specification.[2]
Testing:
This was tested on an SBSA compatible ARMv8 server with CPPCv2 firmware running on a remote processor. I verified that each CPUs performance limits were detected and that new performance requests were made by the on-demand governor proportional to the load on each CPU. I also verified that using the acpi_processor driver correctly maps the physical CPU ids to logical CPU ids, which helps in picking up the proper _CPC details from a processor object, in the case where CPU physical ids may not be contiguous.
Changes since V8:
- Fixed up several debug prints, return types and comments.
- Simplified read/write ops using existing ACPI core API.
- Removed ->get() from cpufreq driver for now.
- Fixed bug introduced by copy-paste err in set_perf.
Changes since V7:
- Simplied new kconfig options for PSS and idle.
- Separated patch to enable acpi processor on ARM64.
- Removed redundant kconfig cross deps on PCC.
- Decoupled processor_perflib from new PSS kconfig option.
Changes since V6:
- Separated PSS and CST from ACPI processor driver in two patches.
- Made new Kconfig symbols auto selectable from Arch Kconfigs.
Changes since V5:
- Checkpatch cleanups.
- Change pss_init to pss_perf_init. Rec by Srinivas Pandruvada.
- Explicit comment explaining why postcore_initcall to pcc mailbox.
- Fold acpi_processor_syscore_init/exit into CONFIG_ACPI_CST.
- Added patch with dummy functions used by ACPI_HOTPLUG_CPU.
Changes since V4:
- Misc cleanups. Addressed feedback from Rafael.
- Made acpi_processor.c independent of C-states, P-states and others.
- Per CPU scanning for _CPC is now made from acpi_processor.c
- Added new Kconfig options for legacy C states and P states to enable future
support for newer alternatives as defined in the ACPI spec 6.0.
Changes since V3:
- Split CPPC backend methods into separate files.
- Add frontend driver which plugs into existing CPUfreq governors.
- Simplify PCC driver by moving communication space mapping and read/write into client drivers.
Changes since V2:
- Select driver if !X86, since intel_pstate will use HWP extensions instead.
- Added more comments.
- Added Freq domain awareness and PSD parsing.
Changes since V1:
- Create a new driver based on Dirks suggestion.
- Fold in CPPC backend hooks into main driver.
Changes since V0: [1]
- Split intel_pstate.c into a generic PID governor and platform specific backend.
- Add CPPC accessors as PID backend.
[1] - http://lwn.net/Articles/608715/ [2] - http://www.uefi.org/sites/default/files/resources/ACPI_5_1release.pdf [3] - https://patches.linaro.org/40705/
Ashwin Chaugule (5): ACPI: Introduce CPU performance controls using CPPC CPPC: Add a CPUFreq driver for use with CPPC ACPI: Add weak routines for ACPI CPU Hotplug CPPC: Probe for CPPC tables for each ACPI Processor object ACPI: Allow selection of the ACPI processor driver for ARM64
drivers/acpi/Kconfig | 20 +- drivers/acpi/Makefile | 1 + drivers/acpi/acpi_processor.c | 18 + drivers/acpi/cppc_acpi.c | 755 ++++++++++++++++++++++++++++++++++++++++ drivers/acpi/processor_driver.c | 6 + drivers/cpufreq/Kconfig.arm | 17 + drivers/cpufreq/Makefile | 2 + drivers/cpufreq/cppc_cpufreq.c | 169 +++++++++ include/acpi/cppc_acpi.h | 138 ++++++++ include/acpi/processor.h | 14 + 10 files changed, 1137 insertions(+), 3 deletions(-) create mode 100644 drivers/acpi/cppc_acpi.c create mode 100644 drivers/cpufreq/cppc_cpufreq.c create mode 100644 include/acpi/cppc_acpi.h
Series queued up for v4.4 (with the updates).
Great! Thanks Rafael!