We can define the cpu topology of ARM64 platform from the affinity of processors which is defined in the MPIDR register. After we get the cpu topology, we can use it for sched_mc and sched_smt.
Signed-off-by: Hanjun Guo hanjun.guo@linaro.org --- arch/arm64/Kconfig | 25 ++++++++ arch/arm64/include/asm/cputype.h | 13 ++++ arch/arm64/include/asm/topology.h | 35 +++++++++++ arch/arm64/kernel/Makefile | 5 +- arch/arm64/kernel/smp.c | 6 ++ arch/arm64/kernel/topology.c | 120 +++++++++++++++++++++++++++++++++++++ 6 files changed, 200 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index c967b11..67c1c53 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -144,6 +144,31 @@ config SMP
If you don't know what to do here, say N.
+config ARM64_CPU_TOPOLOGY + bool "Support cpu topology definition" + depends on SMP && ARM64 + default y + help + Support ARM64 cpu topology definition. The MPIDR register defines + affinity between processors which is then used to describe the cpu + topology of an ARM64 System. + +config SCHED_MC + bool "Multi-core scheduler support" + depends on ARM64_CPU_TOPOLOGY + help + Multi-core scheduler support improves the CPU scheduler's decision + making when dealing with multi-core CPU chips at a cost of slightly + increased overhead in some places. If unsure say N here. + +config SCHED_SMT + bool "SMT scheduler support" + depends on ARM64_CPU_TOPOLOGY + help + Improves the CPU scheduler's decision making when dealing with + MultiThreading at a cost of slightly increased overhead in some + places. If unsure say N here. + config NR_CPUS int "Maximum number of CPUs (2-32)" range 2 32 diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index cf27494..75ac91c 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -30,6 +30,19 @@
#define MPIDR_HWID_BITMASK 0xff00ffffff
+#define MPIDR_SMP_BITMASK (0x3 << 30) +#define MPIDR_SMP_VALUE (0x2 << 30) + +#define MPIDR_MT_BITMASK (0x1 << 24) + +#define MPIDR_LEVEL_BITS 8 +#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) + +#define MPIDR_AFFINITY_LEVEL_0(mpidr) ((mpidr) & MPIDR_LEVEL_MASK) +#define MPIDR_AFFINITY_LEVEL_1(mpidr) ((mpidr >> 8) & MPIDR_LEVEL_MASK) +#define MPIDR_AFFINITY_LEVEL_2(mpidr) ((mpidr >> 16) & MPIDR_LEVEL_MASK) +#define MPIDR_AFFINITY_LEVEL_3(mpidr) ((mpidr >> 32) & MPIDR_LEVEL_MASK) + #define read_cpuid(reg) ({ \ u64 __val; \ asm("mrs %0, " reg : "=r" (__val)); \ diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h index 22c9421..6436e73 100644 --- a/arch/arm64/include/asm/topology.h +++ b/arch/arm64/include/asm/topology.h @@ -1,8 +1,43 @@ #ifndef _ASM_ARM64_TOPOLOGY_H #define _ASM_ARM64_TOPOLOGY_H
+#ifdef CONFIG_ARM64_CPU_TOPOLOGY + +#include <linux/cpumask.h> + +struct cputopo_arm64 { + int thread_id; + int core_id; + int socket_id; + cpumask_t thread_sibling; + cpumask_t core_sibling; +}; + +DECLARE_PER_CPU(struct cputopo_arm64, cpu_topology); + +#define cpu_topo(cpu) per_cpu(cpu_topology, cpu) + +#define topology_physical_package_id(cpu) (cpu_topo(cpu).socket_id) +#define topology_core_id(cpu) (cpu_topo(cpu).core_id) +#define topology_core_cpumask(cpu) (&cpu_topo(cpu).core_sibling) +#define topology_thread_cpumask(cpu) (&cpu_topo(cpu).thread_sibling) + +#define mc_capable() (cpu_topology[0].socket_id != -1) +#define smt_capable() (cpu_topology[0].thread_id != -1) + +void init_cpu_topology(void); +void store_cpu_topology(unsigned int cpuid); +const struct cpumask *cpu_coregroup_mask(int cpu); void arch_fix_phys_package_id(int num, u32 slot);
+#else + +static inline void arch_fix_phys_package_id(int num, u32 slot) {} +static inline void init_cpu_topology(void) { } +static inline void store_cpu_topology(unsigned int cpuid) { } + +#endif + #include <asm-generic/topology.h>
#endif /* _ASM_ARM64_TOPOLOGY_H */ diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index c5e29d5..a47c359 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -18,6 +18,7 @@ arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o smp_psci.o arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)+= hw_breakpoint.o arm64-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o +arm64-obj-$(CONFIG_ARM64_CPU_TOPOLOGY) += topology.o
obj-y += $(arm64-obj-y) vdso/ obj-m += $(arm64-obj-m) @@ -27,7 +28,3 @@ extra-y := $(head-y) vmlinux.lds # vDSO - this must be built first to generate the symbol offsets $(call objectify,$(arm64-obj-y)): $(obj)/vdso/vdso-offsets.h $(obj)/vdso/vdso-offsets.h: $(obj)/vdso - -# Hack for now -obj-y += topology.o - diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 5ec1723..36d09fe 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -39,6 +39,7 @@ #include <asm/atomic.h> #include <asm/cacheflush.h> #include <asm/cputype.h> +#include <asm/topology.h> #include <asm/mmu_context.h> #include <asm/pgtable.h> #include <asm/pgalloc.h> @@ -206,6 +207,8 @@ asmlinkage void __cpuinit secondary_start_kernel(void) local_irq_enable(); local_fiq_enable();
+ store_cpu_topology(cpu); + /* * OK, now it's safe to let the boot CPU continue. Wait for * the CPU migration code to notice that the CPU is online @@ -407,6 +410,9 @@ void __init smp_prepare_cpus(unsigned int max_cpus) int cpu, err; unsigned int ncores = num_possible_cpus();
+ init_cpu_topology(); + store_cpu_topology(smp_processor_id()); + /* * are we trying to boot more cores than exist? */ diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 5c8e69c..20fd521 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -1,3 +1,16 @@ +/* + * arch/arm64/kernel/topology.c + * + * Copyright (C) 2013 Linaro Limited. + * Written by: Hanjun Guo + * + * based on arch/arm/kernel/topology.c + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + #include <linux/cpu.h> #include <linux/cpumask.h> #include <linux/export.h> @@ -13,6 +26,113 @@ #include <asm/topology.h> #include <asm/cpu.h>
+DEFINE_PER_CPU(struct cputopo_arm64, cpu_topology); + +const struct cpumask *cpu_coregroup_mask(int cpu) +{ + return &cpu_topo(cpu).core_sibling; +} + +void update_siblings_masks(unsigned int cpuid) +{ + struct cputopo_arm64 *topo, *cpuid_topo = &cpu_topo(cpuid); + int cpu; + + /* update core and thread sibling masks */ + for_each_possible_cpu(cpu) { + topo = &cpu_topo(cpu); + + if (cpuid_topo->socket_id != topo->socket_id) + continue; + + cpumask_set_cpu(cpuid, &topo->core_sibling); + if (cpu != cpuid) + cpumask_set_cpu(cpu, &cpuid_topo->core_sibling); + + if (cpuid_topo->core_id != topo->core_id) + continue; + + cpumask_set_cpu(cpuid, &topo->thread_sibling); + if (cpu != cpuid) + cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling); + } + smp_wmb(); +} + +/* + * store_cpu_topology is called at boot when only one cpu is running + * and with the mutex cpu_hotplug.lock locked, when several cpus have booted, + * which prevents simultaneous write access to cpu_topology array + */ +void store_cpu_topology(unsigned int cpuid) +{ + struct cputopo_arm64 *cpuid_topo = &cpu_topo(cpuid); + unsigned int mpidr; + + /* If the cpu topology has been already set, just return */ + if (cpuid_topo->core_id != -1) + return; + + mpidr = read_cpuid_mpidr(); + + /* create cpu topology mapping */ + if ((mpidr & MPIDR_SMP_BITMASK) == MPIDR_SMP_VALUE) { + /* + * This is a multiprocessor system + * multiprocessor format & multiprocessor mode field are set + */ + + if (mpidr & MPIDR_MT_BITMASK) { + /* core performance interdependency */ + cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL_0(mpidr); + cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL_1(mpidr); + cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL_2(mpidr); + } else { + /* largely independent cores */ + cpuid_topo->thread_id = -1; + cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL_0(mpidr); + cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL_1(mpidr); + } + } else { + /* + * This is an uniprocessor system + * we are in multiprocessor format but uniprocessor system + * or in the old uniprocessor format + */ + cpuid_topo->thread_id = -1; + cpuid_topo->core_id = 0; + cpuid_topo->socket_id = -1; + } + + update_siblings_masks(cpuid); + + printk(KERN_INFO "CPU%u: thread %d, cpu %d, socket %d, mpidr %x\n", + cpuid, cpu_topo(cpuid).thread_id, + cpu_topo(cpuid).core_id, + cpu_topo(cpuid).socket_id, mpidr); +} + +/* + * init_cpu_topology is called at boot when only one cpu is running + * which prevent simultaneous write access to cpu_topology array + */ +void __init init_cpu_topology(void) +{ + unsigned int cpu; + + /* init core mask */ + for_each_possible_cpu(cpu) { + struct cputopo_arm64 *topo = &cpu_topo(cpu); + + topo->thread_id = -1; + topo->core_id = -1; + topo->socket_id = -1; + cpumask_clear(&topo->core_sibling); + cpumask_clear(&topo->thread_sibling); + } + smp_wmb(); +} + void arch_fix_phys_package_id(int num, u32 slot) { }
This patch is ACPI independent, can we send to upstream first?
On 23 July 2013 20:24, Hanjun Guo hanjun.guo@linaro.org wrote:
We can define the cpu topology of ARM64 platform from the affinity of processors which is defined in the MPIDR register. After we get the cpu topology, we can use it for sched_mc and sched_smt.
Signed-off-by: Hanjun Guo hanjun.guo@linaro.org
arch/arm64/Kconfig | 25 ++++++++ arch/arm64/include/asm/cputype.h | 13 ++++ arch/arm64/include/asm/topology.h | 35 +++++++++++ arch/arm64/kernel/Makefile | 5 +- arch/arm64/kernel/smp.c | 6 ++ arch/arm64/kernel/topology.c | 120 +++++++++++++++++++++++++++++++++++++ 6 files changed, 200 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index c967b11..67c1c53 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -144,6 +144,31 @@ config SMP
If you don't know what to do here, say N.+config ARM64_CPU_TOPOLOGY
bool "Support cpu topology definition"depends on SMP && ARM64default yhelpSupport ARM64 cpu topology definition. The MPIDR register definesaffinity between processors which is then used to describe thecpu
topology of an ARM64 System.+config SCHED_MC
bool "Multi-core scheduler support"depends on ARM64_CPU_TOPOLOGYhelpMulti-core scheduler support improves the CPU scheduler'sdecision
making when dealing with multi-core CPU chips at a cost ofslightly
increased overhead in some places. If unsure say N here.+config SCHED_SMT
bool "SMT scheduler support"depends on ARM64_CPU_TOPOLOGYhelpImproves the CPU scheduler's decision making when dealing withMultiThreading at a cost of slightly increased overhead in someplaces. If unsure say N here.config NR_CPUS int "Maximum number of CPUs (2-32)" range 2 32 diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index cf27494..75ac91c 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -30,6 +30,19 @@
#define MPIDR_HWID_BITMASK 0xff00ffffff
+#define MPIDR_SMP_BITMASK (0x3 << 30) +#define MPIDR_SMP_VALUE (0x2 << 30)
+#define MPIDR_MT_BITMASK (0x1 << 24)
+#define MPIDR_LEVEL_BITS 8 +#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
+#define MPIDR_AFFINITY_LEVEL_0(mpidr) ((mpidr) & MPIDR_LEVEL_MASK) +#define MPIDR_AFFINITY_LEVEL_1(mpidr) ((mpidr >> 8) & MPIDR_LEVEL_MASK) +#define MPIDR_AFFINITY_LEVEL_2(mpidr) ((mpidr >> 16) & MPIDR_LEVEL_MASK) +#define MPIDR_AFFINITY_LEVEL_3(mpidr) ((mpidr >> 32) & MPIDR_LEVEL_MASK)
#define read_cpuid(reg) ({ \ u64 __val; \ asm("mrs %0, " reg : "=r" (__val)); \ diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h index 22c9421..6436e73 100644 --- a/arch/arm64/include/asm/topology.h +++ b/arch/arm64/include/asm/topology.h @@ -1,8 +1,43 @@ #ifndef _ASM_ARM64_TOPOLOGY_H #define _ASM_ARM64_TOPOLOGY_H
+#ifdef CONFIG_ARM64_CPU_TOPOLOGY
+#include <linux/cpumask.h>
+struct cputopo_arm64 {
int thread_id;int core_id;int socket_id;cpumask_t thread_sibling;cpumask_t core_sibling;+};
+DECLARE_PER_CPU(struct cputopo_arm64, cpu_topology);
+#define cpu_topo(cpu) per_cpu(cpu_topology, cpu)
+#define topology_physical_package_id(cpu) (cpu_topo(cpu).socket_id) +#define topology_core_id(cpu) (cpu_topo(cpu).core_id) +#define topology_core_cpumask(cpu) (&cpu_topo(cpu).core_sibling) +#define topology_thread_cpumask(cpu) (&cpu_topo(cpu).thread_sibling)
+#define mc_capable() (cpu_topology[0].socket_id != -1) +#define smt_capable() (cpu_topology[0].thread_id != -1)
+void init_cpu_topology(void); +void store_cpu_topology(unsigned int cpuid); +const struct cpumask *cpu_coregroup_mask(int cpu); void arch_fix_phys_package_id(int num, u32 slot);
+#else
+static inline void arch_fix_phys_package_id(int num, u32 slot) {} +static inline void init_cpu_topology(void) { } +static inline void store_cpu_topology(unsigned int cpuid) { }
+#endif
#include <asm-generic/topology.h>
#endif /* _ASM_ARM64_TOPOLOGY_H */ diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index c5e29d5..a47c359 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -18,6 +18,7 @@ arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o smp_psci.o arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)+= hw_breakpoint.o arm64-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o +arm64-obj-$(CONFIG_ARM64_CPU_TOPOLOGY) += topology.o
obj-y += $(arm64-obj-y) vdso/ obj-m += $(arm64-obj-m) @@ -27,7 +28,3 @@ extra-y := $(head-y) vmlinux.lds # vDSO - this must be built first to generate the symbol offsets $(call objectify,$(arm64-obj-y)): $(obj)/vdso/vdso-offsets.h $(obj)/vdso/vdso-offsets.h: $(obj)/vdso
-# Hack for now -obj-y += topology.o
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 5ec1723..36d09fe 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -39,6 +39,7 @@ #include <asm/atomic.h> #include <asm/cacheflush.h> #include <asm/cputype.h> +#include <asm/topology.h> #include <asm/mmu_context.h> #include <asm/pgtable.h> #include <asm/pgalloc.h> @@ -206,6 +207,8 @@ asmlinkage void __cpuinit secondary_start_kernel(void) local_irq_enable(); local_fiq_enable();
store_cpu_topology(cpu);/* * OK, now it's safe to let the boot CPU continue. Wait for * the CPU migration code to notice that the CPU is online@@ -407,6 +410,9 @@ void __init smp_prepare_cpus(unsigned int max_cpus) int cpu, err; unsigned int ncores = num_possible_cpus();
init_cpu_topology();store_cpu_topology(smp_processor_id());/* * are we trying to boot more cores than exist? */diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 5c8e69c..20fd521 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -1,3 +1,16 @@ +/*
- arch/arm64/kernel/topology.c
- Copyright (C) 2013 Linaro Limited.
- Written by: Hanjun Guo
- based on arch/arm/kernel/topology.c
- This file is subject to the terms and conditions of the GNU General
Public
- License. See the file "COPYING" in the main directory of this archive
- for more details.
- */
#include <linux/cpu.h> #include <linux/cpumask.h> #include <linux/export.h> @@ -13,6 +26,113 @@ #include <asm/topology.h> #include <asm/cpu.h>
+DEFINE_PER_CPU(struct cputopo_arm64, cpu_topology);
+const struct cpumask *cpu_coregroup_mask(int cpu) +{
return &cpu_topo(cpu).core_sibling;+}
+void update_siblings_masks(unsigned int cpuid) +{
struct cputopo_arm64 *topo, *cpuid_topo = &cpu_topo(cpuid);int cpu;/* update core and thread sibling masks */for_each_possible_cpu(cpu) {topo = &cpu_topo(cpu);if (cpuid_topo->socket_id != topo->socket_id)continue;cpumask_set_cpu(cpuid, &topo->core_sibling);if (cpu != cpuid)cpumask_set_cpu(cpu, &cpuid_topo->core_sibling);if (cpuid_topo->core_id != topo->core_id)continue;cpumask_set_cpu(cpuid, &topo->thread_sibling);if (cpu != cpuid)cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling);}smp_wmb();+}
+/*
- store_cpu_topology is called at boot when only one cpu is running
- and with the mutex cpu_hotplug.lock locked, when several cpus have
booted,
- which prevents simultaneous write access to cpu_topology array
- */
+void store_cpu_topology(unsigned int cpuid) +{
struct cputopo_arm64 *cpuid_topo = &cpu_topo(cpuid);unsigned int mpidr;/* If the cpu topology has been already set, just return */if (cpuid_topo->core_id != -1)return;mpidr = read_cpuid_mpidr();/* create cpu topology mapping */if ((mpidr & MPIDR_SMP_BITMASK) == MPIDR_SMP_VALUE) {/** This is a multiprocessor system* multiprocessor format & multiprocessor mode field areset
*/if (mpidr & MPIDR_MT_BITMASK) {/* core performance interdependency */cpuid_topo->thread_id =MPIDR_AFFINITY_LEVEL_0(mpidr);
cpuid_topo->core_id =MPIDR_AFFINITY_LEVEL_1(mpidr);
cpuid_topo->socket_id =MPIDR_AFFINITY_LEVEL_2(mpidr);
} else {/* largely independent cores */cpuid_topo->thread_id = -1;cpuid_topo->core_id =MPIDR_AFFINITY_LEVEL_0(mpidr);
cpuid_topo->socket_id =MPIDR_AFFINITY_LEVEL_1(mpidr);
}} else {/** This is an uniprocessor system* we are in multiprocessor format but uniprocessor system* or in the old uniprocessor format*/cpuid_topo->thread_id = -1;cpuid_topo->core_id = 0;cpuid_topo->socket_id = -1;}update_siblings_masks(cpuid);printk(KERN_INFO "CPU%u: thread %d, cpu %d, socket %d, mpidr %x\n",cpuid, cpu_topo(cpuid).thread_id,cpu_topo(cpuid).core_id,cpu_topo(cpuid).socket_id, mpidr);+}
+/*
- init_cpu_topology is called at boot when only one cpu is running
- which prevent simultaneous write access to cpu_topology array
- */
+void __init init_cpu_topology(void) +{
unsigned int cpu;/* init core mask */for_each_possible_cpu(cpu) {struct cputopo_arm64 *topo = &cpu_topo(cpu);topo->thread_id = -1;topo->core_id = -1;topo->socket_id = -1;cpumask_clear(&topo->core_sibling);cpumask_clear(&topo->thread_sibling);}smp_wmb();+}
void arch_fix_phys_package_id(int num, u32 slot) { } -- 1.7.9.5
Hi Hanjun,
Yes this looks like a good candidate to send straight to upstream. Just keep linaro-acpi list in the CC so we can keep track of comments.
Thanks
Graeme
On 23/07/13 14:02, Hanjun Guo wrote:
This patch is ACPI independent, can we send to upstream first?
On 23 July 2013 20:24, Hanjun Guo hanjun.guo@linaro.org wrote:
We can define the cpu topology of ARM64 platform from the affinity of processors which is defined in the MPIDR register. After we get the cpu topology, we can use it for sched_mc and sched_smt.
Signed-off-by: Hanjun Guo hanjun.guo@linaro.org
arch/arm64/Kconfig | 25 ++++++++ arch/arm64/include/asm/cputype.h | 13 ++++ arch/arm64/include/asm/topology.h | 35 +++++++++++ arch/arm64/kernel/Makefile | 5 +- arch/arm64/kernel/smp.c | 6 ++ arch/arm64/kernel/topology.c | 120 +++++++++++++++++++++++++++++++++++++ 6 files changed, 200 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index c967b11..67c1c53 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -144,6 +144,31 @@ config SMP
If you don't know what to do here, say N.+config ARM64_CPU_TOPOLOGY
bool "Support cpu topology definition"depends on SMP && ARM64default yhelpSupport ARM64 cpu topology definition. The MPIDR register definesaffinity between processors which is then used to describe thecpu
topology of an ARM64 System.+config SCHED_MC
bool "Multi-core scheduler support"depends on ARM64_CPU_TOPOLOGYhelpMulti-core scheduler support improves the CPU scheduler'sdecision
making when dealing with multi-core CPU chips at a cost ofslightly
increased overhead in some places. If unsure say N here.+config SCHED_SMT
bool "SMT scheduler support"depends on ARM64_CPU_TOPOLOGYhelpImproves the CPU scheduler's decision making when dealing withMultiThreading at a cost of slightly increased overhead in someplaces. If unsure say N here.config NR_CPUS int "Maximum number of CPUs (2-32)" range 2 32 diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index cf27494..75ac91c 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -30,6 +30,19 @@
#define MPIDR_HWID_BITMASK 0xff00ffffff
+#define MPIDR_SMP_BITMASK (0x3 << 30) +#define MPIDR_SMP_VALUE (0x2 << 30)
+#define MPIDR_MT_BITMASK (0x1 << 24)
+#define MPIDR_LEVEL_BITS 8 +#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
+#define MPIDR_AFFINITY_LEVEL_0(mpidr) ((mpidr) & MPIDR_LEVEL_MASK) +#define MPIDR_AFFINITY_LEVEL_1(mpidr) ((mpidr >> 8) & MPIDR_LEVEL_MASK) +#define MPIDR_AFFINITY_LEVEL_2(mpidr) ((mpidr >> 16) & MPIDR_LEVEL_MASK) +#define MPIDR_AFFINITY_LEVEL_3(mpidr) ((mpidr >> 32) & MPIDR_LEVEL_MASK)
#define read_cpuid(reg) ({ \ u64 __val; \ asm("mrs %0, " reg : "=r" (__val)); \ diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h index 22c9421..6436e73 100644 --- a/arch/arm64/include/asm/topology.h +++ b/arch/arm64/include/asm/topology.h @@ -1,8 +1,43 @@ #ifndef _ASM_ARM64_TOPOLOGY_H #define _ASM_ARM64_TOPOLOGY_H
+#ifdef CONFIG_ARM64_CPU_TOPOLOGY
+#include <linux/cpumask.h>
+struct cputopo_arm64 {
int thread_id;int core_id;int socket_id;cpumask_t thread_sibling;cpumask_t core_sibling;+};
+DECLARE_PER_CPU(struct cputopo_arm64, cpu_topology);
+#define cpu_topo(cpu) per_cpu(cpu_topology, cpu)
+#define topology_physical_package_id(cpu) (cpu_topo(cpu).socket_id) +#define topology_core_id(cpu) (cpu_topo(cpu).core_id) +#define topology_core_cpumask(cpu) (&cpu_topo(cpu).core_sibling) +#define topology_thread_cpumask(cpu) (&cpu_topo(cpu).thread_sibling)
+#define mc_capable() (cpu_topology[0].socket_id != -1) +#define smt_capable() (cpu_topology[0].thread_id != -1)
+void init_cpu_topology(void); +void store_cpu_topology(unsigned int cpuid); +const struct cpumask *cpu_coregroup_mask(int cpu); void arch_fix_phys_package_id(int num, u32 slot);
+#else
+static inline void arch_fix_phys_package_id(int num, u32 slot) {} +static inline void init_cpu_topology(void) { } +static inline void store_cpu_topology(unsigned int cpuid) { }
+#endif
#include <asm-generic/topology.h>
#endif /* _ASM_ARM64_TOPOLOGY_H */ diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index c5e29d5..a47c359 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -18,6 +18,7 @@ arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o smp_psci.o arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)+= hw_breakpoint.o arm64-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o +arm64-obj-$(CONFIG_ARM64_CPU_TOPOLOGY) += topology.o
obj-y += $(arm64-obj-y) vdso/ obj-m += $(arm64-obj-m) @@ -27,7 +28,3 @@ extra-y := $(head-y) vmlinux.lds # vDSO - this must be built first to generate the symbol offsets $(call objectify,$(arm64-obj-y)): $(obj)/vdso/vdso-offsets.h $(obj)/vdso/vdso-offsets.h: $(obj)/vdso
-# Hack for now -obj-y += topology.o
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 5ec1723..36d09fe 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -39,6 +39,7 @@ #include <asm/atomic.h> #include <asm/cacheflush.h> #include <asm/cputype.h> +#include <asm/topology.h> #include <asm/mmu_context.h> #include <asm/pgtable.h> #include <asm/pgalloc.h> @@ -206,6 +207,8 @@ asmlinkage void __cpuinit secondary_start_kernel(void) local_irq_enable(); local_fiq_enable();
store_cpu_topology(cpu);/* * OK, now it's safe to let the boot CPU continue. Wait for * the CPU migration code to notice that the CPU is online@@ -407,6 +410,9 @@ void __init smp_prepare_cpus(unsigned int max_cpus) int cpu, err; unsigned int ncores = num_possible_cpus();
init_cpu_topology();store_cpu_topology(smp_processor_id());/* * are we trying to boot more cores than exist? */diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 5c8e69c..20fd521 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -1,3 +1,16 @@ +/*
- arch/arm64/kernel/topology.c
- Copyright (C) 2013 Linaro Limited.
- Written by: Hanjun Guo
- based on arch/arm/kernel/topology.c
- This file is subject to the terms and conditions of the GNU General
Public
- License. See the file "COPYING" in the main directory of this archive
- for more details.
- */
#include <linux/cpu.h> #include <linux/cpumask.h> #include <linux/export.h> @@ -13,6 +26,113 @@ #include <asm/topology.h> #include <asm/cpu.h>
+DEFINE_PER_CPU(struct cputopo_arm64, cpu_topology);
+const struct cpumask *cpu_coregroup_mask(int cpu) +{
return &cpu_topo(cpu).core_sibling;+}
+void update_siblings_masks(unsigned int cpuid) +{
struct cputopo_arm64 *topo, *cpuid_topo = &cpu_topo(cpuid);int cpu;/* update core and thread sibling masks */for_each_possible_cpu(cpu) {topo = &cpu_topo(cpu);if (cpuid_topo->socket_id != topo->socket_id)continue;cpumask_set_cpu(cpuid, &topo->core_sibling);if (cpu != cpuid)cpumask_set_cpu(cpu, &cpuid_topo->core_sibling);if (cpuid_topo->core_id != topo->core_id)continue;cpumask_set_cpu(cpuid, &topo->thread_sibling);if (cpu != cpuid)cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling);}smp_wmb();+}
+/*
- store_cpu_topology is called at boot when only one cpu is running
- and with the mutex cpu_hotplug.lock locked, when several cpus have
booted,
- which prevents simultaneous write access to cpu_topology array
- */
+void store_cpu_topology(unsigned int cpuid) +{
struct cputopo_arm64 *cpuid_topo = &cpu_topo(cpuid);unsigned int mpidr;/* If the cpu topology has been already set, just return */if (cpuid_topo->core_id != -1)return;mpidr = read_cpuid_mpidr();/* create cpu topology mapping */if ((mpidr & MPIDR_SMP_BITMASK) == MPIDR_SMP_VALUE) {/** This is a multiprocessor system* multiprocessor format & multiprocessor mode field areset
*/if (mpidr & MPIDR_MT_BITMASK) {/* core performance interdependency */cpuid_topo->thread_id =MPIDR_AFFINITY_LEVEL_0(mpidr);
cpuid_topo->core_id =MPIDR_AFFINITY_LEVEL_1(mpidr);
cpuid_topo->socket_id =MPIDR_AFFINITY_LEVEL_2(mpidr);
} else {/* largely independent cores */cpuid_topo->thread_id = -1;cpuid_topo->core_id =MPIDR_AFFINITY_LEVEL_0(mpidr);
cpuid_topo->socket_id =MPIDR_AFFINITY_LEVEL_1(mpidr);
}} else {/** This is an uniprocessor system* we are in multiprocessor format but uniprocessor system* or in the old uniprocessor format*/cpuid_topo->thread_id = -1;cpuid_topo->core_id = 0;cpuid_topo->socket_id = -1;}update_siblings_masks(cpuid);printk(KERN_INFO "CPU%u: thread %d, cpu %d, socket %d, mpidr %x\n",cpuid, cpu_topo(cpuid).thread_id,cpu_topo(cpuid).core_id,cpu_topo(cpuid).socket_id, mpidr);+}
+/*
- init_cpu_topology is called at boot when only one cpu is running
- which prevent simultaneous write access to cpu_topology array
- */
+void __init init_cpu_topology(void) +{
unsigned int cpu;/* init core mask */for_each_possible_cpu(cpu) {struct cputopo_arm64 *topo = &cpu_topo(cpu);topo->thread_id = -1;topo->core_id = -1;topo->socket_id = -1;cpumask_clear(&topo->core_sibling);cpumask_clear(&topo->thread_sibling);}smp_wmb();+}
void arch_fix_phys_package_id(int num, u32 slot) { } -- 1.7.9.5
Linaro-acpi mailing list Linaro-acpi@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-acpi
And patches@linaro.org as well in cc
On 23 July 2013 23:04, Andrea Gallo andrea.gallo@linaro.org wrote:
And patches@linaro.org as well in cc
ok, I will. and linaro-kernel@lists.linaro.org will be also in the CC list.
On 07/23/2013 07:17 AM, Graeme Gregory wrote:
Hi Hanjun,
Yes this looks like a good candidate to send straight to upstream. Just keep linaro-acpi list in the CC so we can keep track of comments.
Thanks
Graeme
On 23/07/13 14:02, Hanjun Guo wrote:
This patch is ACPI independent, can we send to upstream first?
Absolutely agreed -- independent patches should just go upstream first with a polite CC to us.
Note, too, that using the MPIDR registers for this sort of work was brought up repeatedly in discussing ACPI on ARM, so it seems like great minds think alike :)...
On 23 July 2013 20:24, Hanjun Guohanjun.guo@linaro.org wrote:
We can define the cpu topology of ARM64 platform from the affinity of processors which is defined in the MPIDR register. After we get the cpu topology, we can use it for sched_mc and sched_smt.
Signed-off-by: Hanjun Guohanjun.guo@linaro.org
arch/arm64/Kconfig | 25 ++++++++ arch/arm64/include/asm/cputype.h | 13 ++++ arch/arm64/include/asm/topology.h | 35 +++++++++++ arch/arm64/kernel/Makefile | 5 +- arch/arm64/kernel/smp.c | 6 ++ arch/arm64/kernel/topology.c | 120 +++++++++++++++++++++++++++++++++++++ 6 files changed, 200 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index c967b11..67c1c53 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -144,6 +144,31 @@ config SMP
If you don't know what to do here, say N.+config ARM64_CPU_TOPOLOGY
bool "Support cpu topology definition"depends on SMP && ARM64default yhelpSupport ARM64 cpu topology definition. The MPIDR register definesaffinity between processors which is then used to describe thecpu
topology of an ARM64 System.+config SCHED_MC
bool "Multi-core scheduler support"depends on ARM64_CPU_TOPOLOGYhelpMulti-core scheduler support improves the CPU scheduler'sdecision
making when dealing with multi-core CPU chips at a cost ofslightly
increased overhead in some places. If unsure say N here.+config SCHED_SMT
bool "SMT scheduler support"depends on ARM64_CPU_TOPOLOGYhelpImproves the CPU scheduler's decision making when dealing withMultiThreading at a cost of slightly increased overhead in someplaces. If unsure say N here.- config NR_CPUS int "Maximum number of CPUs (2-32)" range 2 32
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index cf27494..75ac91c 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -30,6 +30,19 @@
#define MPIDR_HWID_BITMASK 0xff00ffffff
+#define MPIDR_SMP_BITMASK (0x3 << 30) +#define MPIDR_SMP_VALUE (0x2 << 30)
+#define MPIDR_MT_BITMASK (0x1 << 24)
+#define MPIDR_LEVEL_BITS 8 +#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
+#define MPIDR_AFFINITY_LEVEL_0(mpidr) ((mpidr) & MPIDR_LEVEL_MASK) +#define MPIDR_AFFINITY_LEVEL_1(mpidr) ((mpidr >> 8) & MPIDR_LEVEL_MASK) +#define MPIDR_AFFINITY_LEVEL_2(mpidr) ((mpidr >> 16) & MPIDR_LEVEL_MASK) +#define MPIDR_AFFINITY_LEVEL_3(mpidr) ((mpidr >> 32) & MPIDR_LEVEL_MASK)
- #define read_cpuid(reg) ({ \ u64 __val; \ asm("mrs %0, " reg : "=r" (__val)); \
diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h index 22c9421..6436e73 100644 --- a/arch/arm64/include/asm/topology.h +++ b/arch/arm64/include/asm/topology.h @@ -1,8 +1,43 @@ #ifndef _ASM_ARM64_TOPOLOGY_H #define _ASM_ARM64_TOPOLOGY_H
+#ifdef CONFIG_ARM64_CPU_TOPOLOGY
+#include <linux/cpumask.h>
+struct cputopo_arm64 {
int thread_id;int core_id;int socket_id;cpumask_t thread_sibling;cpumask_t core_sibling;+};
+DECLARE_PER_CPU(struct cputopo_arm64, cpu_topology);
+#define cpu_topo(cpu) per_cpu(cpu_topology, cpu)
+#define topology_physical_package_id(cpu) (cpu_topo(cpu).socket_id) +#define topology_core_id(cpu) (cpu_topo(cpu).core_id) +#define topology_core_cpumask(cpu) (&cpu_topo(cpu).core_sibling) +#define topology_thread_cpumask(cpu) (&cpu_topo(cpu).thread_sibling)
+#define mc_capable() (cpu_topology[0].socket_id != -1) +#define smt_capable() (cpu_topology[0].thread_id != -1)
+void init_cpu_topology(void); +void store_cpu_topology(unsigned int cpuid); +const struct cpumask *cpu_coregroup_mask(int cpu); void arch_fix_phys_package_id(int num, u32 slot);
+#else
+static inline void arch_fix_phys_package_id(int num, u32 slot) {} +static inline void init_cpu_topology(void) { } +static inline void store_cpu_topology(unsigned int cpuid) { }
+#endif
#include <asm-generic/topology.h>
#endif /* _ASM_ARM64_TOPOLOGY_H */
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index c5e29d5..a47c359 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -18,6 +18,7 @@ arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o smp_psci.o arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)+= hw_breakpoint.o arm64-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o +arm64-obj-$(CONFIG_ARM64_CPU_TOPOLOGY) += topology.o
obj-y += $(arm64-obj-y) vdso/ obj-m += $(arm64-obj-m) @@ -27,7 +28,3 @@ extra-y := $(head-y) vmlinux.lds # vDSO - this must be built first to generate the symbol offsets $(call objectify,$(arm64-obj-y)): $(obj)/vdso/vdso-offsets.h $(obj)/vdso/vdso-offsets.h: $(obj)/vdso
-# Hack for now -obj-y += topology.o
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 5ec1723..36d09fe 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -39,6 +39,7 @@ #include <asm/atomic.h> #include <asm/cacheflush.h> #include <asm/cputype.h> +#include <asm/topology.h> #include <asm/mmu_context.h> #include <asm/pgtable.h> #include <asm/pgalloc.h> @@ -206,6 +207,8 @@ asmlinkage void __cpuinit secondary_start_kernel(void) local_irq_enable(); local_fiq_enable();
store_cpu_topology(cpu);/* * OK, now it's safe to let the boot CPU continue. Wait for * the CPU migration code to notice that the CPU is online@@ -407,6 +410,9 @@ void __init smp_prepare_cpus(unsigned int max_cpus) int cpu, err; unsigned int ncores = num_possible_cpus();
init_cpu_topology();store_cpu_topology(smp_processor_id());/* * are we trying to boot more cores than exist? */diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 5c8e69c..20fd521 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -1,3 +1,16 @@ +/*
- arch/arm64/kernel/topology.c
- Copyright (C) 2013 Linaro Limited.
- Written by: Hanjun Guo
- based on arch/arm/kernel/topology.c
- This file is subject to the terms and conditions of the GNU General
Public
- License. See the file "COPYING" in the main directory of this archive
- for more details.
- */
- #include <linux/cpu.h> #include <linux/cpumask.h> #include <linux/export.h>
@@ -13,6 +26,113 @@ #include <asm/topology.h> #include <asm/cpu.h>
+DEFINE_PER_CPU(struct cputopo_arm64, cpu_topology);
+const struct cpumask *cpu_coregroup_mask(int cpu) +{
return &cpu_topo(cpu).core_sibling;+}
+void update_siblings_masks(unsigned int cpuid) +{
struct cputopo_arm64 *topo, *cpuid_topo = &cpu_topo(cpuid);int cpu;/* update core and thread sibling masks */for_each_possible_cpu(cpu) {topo = &cpu_topo(cpu);if (cpuid_topo->socket_id != topo->socket_id)continue;cpumask_set_cpu(cpuid, &topo->core_sibling);if (cpu != cpuid)cpumask_set_cpu(cpu, &cpuid_topo->core_sibling);if (cpuid_topo->core_id != topo->core_id)continue;cpumask_set_cpu(cpuid, &topo->thread_sibling);if (cpu != cpuid)cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling);}smp_wmb();+}
+/*
- store_cpu_topology is called at boot when only one cpu is running
- and with the mutex cpu_hotplug.lock locked, when several cpus have
booted,
- which prevents simultaneous write access to cpu_topology array
- */
+void store_cpu_topology(unsigned int cpuid) +{
struct cputopo_arm64 *cpuid_topo = &cpu_topo(cpuid);unsigned int mpidr;/* If the cpu topology has been already set, just return */if (cpuid_topo->core_id != -1)return;mpidr = read_cpuid_mpidr();/* create cpu topology mapping */if ((mpidr & MPIDR_SMP_BITMASK) == MPIDR_SMP_VALUE) {/** This is a multiprocessor system* multiprocessor format & multiprocessor mode field areset
*/if (mpidr & MPIDR_MT_BITMASK) {/* core performance interdependency */cpuid_topo->thread_id =MPIDR_AFFINITY_LEVEL_0(mpidr);
cpuid_topo->core_id =MPIDR_AFFINITY_LEVEL_1(mpidr);
cpuid_topo->socket_id =MPIDR_AFFINITY_LEVEL_2(mpidr);
} else {/* largely independent cores */cpuid_topo->thread_id = -1;cpuid_topo->core_id =MPIDR_AFFINITY_LEVEL_0(mpidr);
cpuid_topo->socket_id =MPIDR_AFFINITY_LEVEL_1(mpidr);
}} else {/** This is an uniprocessor system* we are in multiprocessor format but uniprocessor system* or in the old uniprocessor format*/cpuid_topo->thread_id = -1;cpuid_topo->core_id = 0;cpuid_topo->socket_id = -1;}update_siblings_masks(cpuid);printk(KERN_INFO "CPU%u: thread %d, cpu %d, socket %d, mpidr %x\n",cpuid, cpu_topo(cpuid).thread_id,cpu_topo(cpuid).core_id,cpu_topo(cpuid).socket_id, mpidr);+}
+/*
- init_cpu_topology is called at boot when only one cpu is running
- which prevent simultaneous write access to cpu_topology array
- */
+void __init init_cpu_topology(void) +{
unsigned int cpu;/* init core mask */for_each_possible_cpu(cpu) {struct cputopo_arm64 *topo = &cpu_topo(cpu);topo->thread_id = -1;topo->core_id = -1;topo->socket_id = -1;cpumask_clear(&topo->core_sibling);cpumask_clear(&topo->thread_sibling);}smp_wmb();+}
- void arch_fix_phys_package_id(int num, u32 slot) { }
-- 1.7.9.5
Linaro-acpi mailing list Linaro-acpi@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-acpi
Linaro-acpi mailing list Linaro-acpi@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-acpi
On 2013-7-23 23:57, Al Stone wrote:
On 07/23/2013 07:17 AM, Graeme Gregory wrote:
Hi Hanjun,
Yes this looks like a good candidate to send straight to upstream. Just keep linaro-acpi list in the CC so we can keep track of comments.
OK, I will refactor the patch and send to upstream. I will keep all of you and the linaro-acpi in CC list.
Thanks
Graeme
On 23/07/13 14:02, Hanjun Guo wrote:
This patch is ACPI independent, can we send to upstream first?
Absolutely agreed -- independent patches should just go upstream first with a polite CC to us.
Note, too, that using the MPIDR registers for this sort of work was brought up repeatedly in discussing ACPI on ARM, so it seems like great minds think alike :)...
Great, so nice to hear that. I think MPIDR registers are necessary for APIC ID in MADT tables too.
Thanks Hanjun
-
Al Stone -
Andrea Gallo -
Graeme Gregory -
Hanjun Guo