- Linaro-acpi - lists.linaro.org

[PATCH 0/3] updates to linaro-image-lamp for better ACPI testing

by Graeme Gregory

Hi, Just a small series to enable better testing of ACPI in LAVA without having to fetch and built test suites with git. Thanks Graeme

10 years, 5 months

1
3
0 0

[PATCH 1/3] ACPI / processor: Update the comments in processor.h

by Hanjun Guo

In commit 46ba51e (ACPI / processor: Introduce ARCH_MIGHT_HAVE_ACPI_PDC), acpi_processor_set_pdc() was moved to processor_pdc.c, so update the comments accordingly. Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org> --- include/acpi/processor.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/acpi/processor.h b/include/acpi/processor.h index 9b9b6f2..cbb6cd3 100644 --- a/include/acpi/processor.h +++ b/include/acpi/processor.h @@ -313,11 +313,13 @@ static inline int acpi_processor_get_bios_limit(int cpu, unsigned int *limit) #endif /* CONFIG_CPU_FREQ */ /* in processor_core.c */ -void acpi_processor_set_pdc(acpi_handle handle); int acpi_get_apicid(acpi_handle, int type, u32 acpi_id); int acpi_map_cpuid(int apic_id, u32 acpi_id); int acpi_get_cpuid(acpi_handle, int type, u32 acpi_id); +/* in processor_pdc.c */ +void acpi_processor_set_pdc(acpi_handle handle); + /* in processor_throttling.c */ int acpi_processor_tstate_has_changed(struct acpi_processor *pr); int acpi_processor_get_throttling_info(struct acpi_processor *pr); -- 1.7.9.5

10 years, 5 months

3
9
0 0

leg-kernel tag leg-20141118.0 released

by Graeme Gregory

The leg-kernel release has been made and tagged as leg-201401118.0 This is based on mainline kernel v3.18-rc5 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: http://git.linaro.org/leg/acpi/leg-kernel.git/commit/380ad5d8817a03204e6a92… Notes :- 1) This release merges Seattle support from Redhat/AMD! https://git.linaro.org/leg/acpi/acpi.git/shortlog/refs/heads/acpi-topic-sea… 2) This release merges the Mustang support from Redhat/APM https://git.linaro.org/leg/acpi/acpi.git/shortlog/refs/heads/acpi-topic-mus… 3) This release disables STRICT_DEVMEM in distribution.conf, this is needed to work on FWTS for the short term and should not be considered a production change.

10 years, 5 months

1
0
0 0

[RFC PATCH 0/4] MMCFG refactoring + PCI ACPI probing for ARM64

by Tomasz Nowicki

The patch set can be break down into two logic parts: 1. patch 1,2 - MMCONFIG code refacoring. MMCFG ACPI table has no arch dependencies so it can be used across other architectures. 2. patch 3,4 aim for PCI ACPI probing on ARM64 Patches tested on Cavium ThunderX simulator with the latest ACPI ARM64 core set: http://www.serverphorums.com/read.php?12,997228 Tomasz Nowicki (4): x86, acpi, pci: Move arch-agnostic MMCFG code out of arch/x86/ directory. x86, acpi, pci: Isolate new PCI mmconfig entry insertion. arm64, acpi, pci: Add arch specific functions for mmconfig driver. arm64, acpi, pci: Provide arch-specific calls for PCI host bridge dirver (PNP0A03). arch/arm64/Kconfig | 3 + arch/arm64/include/asm/pci.h | 8 + arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/mmconfig.c | 69 +++++++ arch/arm64/kernel/pci.c | 401 +++++++++++++++++++++++++++++++++++++++-- arch/x86/include/asm/pci_x86.h | 29 --- arch/x86/pci/acpi.c | 1 + arch/x86/pci/init.c | 1 + arch/x86/pci/mmconfig-shared.c | 176 +----------------- arch/x86/pci/mmconfig_32.c | 1 + arch/x86/pci/mmconfig_64.c | 1 + drivers/acpi/Makefile | 1 + drivers/acpi/bus.c | 1 + drivers/acpi/mmconfig.c | 204 +++++++++++++++++++++ include/linux/mmconfig.h | 57 ++++++ include/linux/pci.h | 8 - 16 files changed, 738 insertions(+), 224 deletions(-) create mode 100644 arch/arm64/kernel/mmconfig.c create mode 100644 drivers/acpi/mmconfig.c create mode 100644 include/linux/mmconfig.h -- 1.9.1

10 years, 5 months

3
16
0 0

[PATCH] acpi: ignore FACS table missing, if HW_REDUCED_ACPI is set.

by Fu Wei

acpi: ignore FACS table missing, if HW_REDUCED_ACPI is set. (ACPI Revision 5.1 Errata A) Signed-off-by: Fu Wei <fu.wei(a)linaro.org> --- src/lib/include/fwts_acpi.h | 1 + src/lib/src/fwts_acpi_tables.c | 13 ++++++++++--- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/src/lib/include/fwts_acpi.h b/src/lib/include/fwts_acpi.h index 24ebc84..73a3461 100644 --- a/src/lib/include/fwts_acpi.h +++ b/src/lib/include/fwts_acpi.h @@ -46,6 +46,7 @@ extern const char *fwts_acpi_fadt_preferred_pm_profile[]; #define FWTS_ACPI_FADT_PREFERRED_PM_PROFILE(x) \ ((x) > 8) ? "Reserved" : fwts_acpi_fadt_preferred_pm_profile[x] +#define FWTS_ACPI_FADT_FLAGS_HW_REDUCED_ACPI (1<<20) /* 5.2.3.1 Generic Address Structure */ typedef struct { diff --git a/src/lib/src/fwts_acpi_tables.c b/src/lib/src/fwts_acpi_tables.c index 56498e0..41cf6ea 100644 --- a/src/lib/src/fwts_acpi_tables.c +++ b/src/lib/src/fwts_acpi_tables.c @@ -311,7 +311,7 @@ static int fwts_acpi_handle_fadt_tables( } /* Is it sane? */ if (addr == 0) { - fwts_log_error(fw, "Failed to load %s: Cannot determine " + fwts_log_warning(fw, "Failed to load %s: Cannot determine " "address of %s from FADT, fields %s and %s are zero.", name, name, name_addr32, name_addr64); return FWTS_ERROR; @@ -320,7 +320,7 @@ static int fwts_acpi_handle_fadt_tables( addr = (off_t)*addr32; /* Is it sane? */ if (addr == 0) { - fwts_log_error(fw, "Failed to load %s: Cannot determine " + fwts_log_warning(fw, "Failed to load %s: Cannot determine " "address of %s from FADT, field %s is zero.", name, name, name_addr32); return FWTS_ERROR; @@ -375,12 +375,19 @@ static int fwts_acpi_handle_fadt( "FACS", "FIRMWARE_CTRL", "X_FIRMWARE_CTRL", &fadt->firmware_control, &fadt->x_firmware_ctrl, provenance) != FWTS_OK) { - return FWTS_ERROR; + if (fadt->flags && FWTS_ACPI_FADT_FLAGS_HW_REDUCED_ACPI) { + fwts_log_info(fw, "IGNORE the missing FACS " + "in Hardware-reduced ACPI"); + } else { + fwts_log_error(fw, "Missing FACS!"); + return FWTS_ERROR; + } } /* Determine DSDT addr and load it */ if (fwts_acpi_handle_fadt_tables(fw, fadt, "DSDT", "DSTD", "X_DSDT", &fadt->dsdt, &fadt->x_dsdt, provenance) != FWTS_OK) { + fwts_log_error(fw, "Failed to load DSDT!"); return FWTS_ERROR; } return FWTS_OK; -- 1.9.1

10 years, 5 months

1
1
0 0

[PATCH v10 0/1] PCC: Platform Communication Channel

by Ashwin Chaugule

Changes since V9: - Default to PCC subspace headers as defined in ACPI v5.1 Changes since V8: - Removed unncessary header files. - Added kerneldoc comments. - Added intro about PCC in pcc.c Changes since V7: - Added timeout to tx method in case the remote dies. - Restructured usage of acpi_status. Had inverted logic previously. Changes since V6: - Cosmetic changes based on Lv's suggestions Changes since V5: - Optimize loop that matches channel request. - Use platform_create_bundle. - Replace ioread/writes. - Remove redundant code and headers. - Restructure common mailbox macros. - Reformat PCC cmd parsing. Changes since V4: - Folded PCC Mailbox helpers into pcc.c Changes since V3: - Added PCC helper functions to work around "struct device" limitations. - PCC driver changes to work with PCC specific Mailbox helpers. Changes since V2: - Rebased on top of git://git.linaro.org/landing-teams/working/fujitsu/integration.git branch mailbox-for-3.17 - Added PCC API to mailbox framework as per Arnd's suggestion to allow usage without ACPI. Changes since V1: - Integration with Mailbox framework - https://lkml.org/lkml/2014/5/15/49 This patchset adds support for the PCC (Platform Communication Channel) interface as described in the current ACPI 5.0 spec. See Section 14 of the ACPI spec - http://acpi.info/DOWNLOADS/ACPI_5_Errata%20A.pdf for more details on how PCC works. In brief PCC is a generic means for PCC clients, to talk to the firmware. The PCC register space is typically memory mapped IO and uses a doorbell mechanism to communicate synchronously from the OS to the firmware. The PCC driver is completely agnostic to the protocol implemented by the PCC clients. It only implements the enumeration of PCC channels and the low level transport mechanism and leaves the rest to the PCC clients. The PCC is meant to be useable in the future by clients such as CPPC (Collaborative Processor Performance Control), RAS (Reliability, Availability and Serviceability) and MPST (Memory Power State Tables) and possibly others. Ashwin Chaugule (1): Mailbox: Add support for Platform Communication Channel drivers/mailbox/Kconfig | 12 ++ drivers/mailbox/Makefile | 2 + drivers/mailbox/mailbox.c | 4 +- drivers/mailbox/mailbox.h | 16 ++ drivers/mailbox/pcc.c | 367 ++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 398 insertions(+), 3 deletions(-) create mode 100644 drivers/mailbox/mailbox.h create mode 100644 drivers/mailbox/pcc.c -- 1.9.1

10 years, 5 months

5
41
0 0

A new fwts test result (using the latest leg kernel)

by Fu Wei

Hi our dear ACPI experts, I ran my ci job yesterday night. then I run a test on my new leg Image, because I recompiled the FWTS in the test , so the test took a long time. https://validation.linaro.org/scheduler/job/198839/log_file The result.log is attached. UPDATE: (1)disabling STATIC_DEVMEM is working, it's not a blocker for FWTS in short term. (2)we test the latest kernel, so the result should be better Please let me know what are the rest problem we need to fix , according to the test log. Great thanks for your time! -- Best regards, Fu Wei Software Engineer From Red Hat LEG Team Linaro.org | Open source software for ARM SoCs Ph: +86 186 2020 4684 (mobile) IRC: fuwei Skype: tekkamanninja Room 1512, Regus One Corporate Avenue,Level 15, One Corporate Avenue,222 Hubin Road,Huangpu District, Shanghai,China 200021

10 years, 6 months

1
0
0 0

leg-kernel tag leg-20141111.0 released

by Graeme Gregory

The leg-kernel release has been made and tagged as leg-201401111.0 This is based on mainline kernel v3.18-rc4 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: https://git.linaro.org/leg/acpi/leg-kernel.git/commit/1a315a2d7b69d1b9c9c49… Notes :- 1) This release merges Seattle support from Redhat/AMD! https://git.linaro.org/leg/acpi/acpi.git/shortlog/refs/heads/acpi-topic-sea… 2) This release merges the Mustang support from Redhat/APM https://git.linaro.org/leg/acpi/acpi.git/shortlog/refs/heads/acpi-topic-mus… 3) This release disables STRICT_DEVMEM in distribution.conf, this is needed to work on FWTS for the short term and should not be considered a production change.

10 years, 6 months

1
0
0 0

[PATCH] mailbox: enable non-DT/ACPI clients to use the api

by Jassi Brar

The Mailbox API so far discounted controllers and clients that may not have a DT based channel mapping capability, as in ACPI. Allow such mailbox clients to ask for a mailbox channel by simply specifying a token. The token would be globally unique among channels provided by such controllers... which shouldn't be a problem because practically non-DT means ACPI and ACPI specifies just one controller instance called the Platform Communications Channel (PCC) that could have max 256 subspaces (channels or mailboxes). So this is simply going to be the value from 'Signature' field (first 4bytes) of the SharedMemory Region corresponding to the subspace/channel the client is interested in. Signed-off-by: Jassi Brar <jaswinder.singh(a)linaro.org> --- drivers/mailbox/mailbox.c | 50 +++++++++++++++++++++----------------- include/linux/mailbox_controller.h | 7 ++++++ 2 files changed, 35 insertions(+), 22 deletions(-) diff --git a/drivers/mailbox/mailbox.c b/drivers/mailbox/mailbox.c index afcb430..8260451 100644 --- a/drivers/mailbox/mailbox.c +++ b/drivers/mailbox/mailbox.c @@ -296,36 +296,42 @@ struct mbox_chan *mbox_request_channel(struct mbox_client *cl, int index) { struct device *dev = cl->dev; struct mbox_controller *mbox; - struct of_phandle_args spec; - struct mbox_chan *chan; + struct mbox_chan *chan = NULL; unsigned long flags; int ret; - if (!dev || !dev->of_node) { - pr_debug("%s: No owner device node\n", __func__); - return ERR_PTR(-ENODEV); - } - mutex_lock(&con_mutex); - if (of_parse_phandle_with_args(dev->of_node, "mboxes", - "#mbox-cells", index, &spec)) { - dev_dbg(dev, "%s: can't parse \"mboxes\" property\n", __func__); - mutex_unlock(&con_mutex); - return ERR_PTR(-ENODEV); - } - - chan = NULL; - list_for_each_entry(mbox, &mbox_cons, node) - if (mbox->dev->of_node == spec.np) { - chan = mbox->of_xlate(mbox, &spec); - break; + if (!dev || !dev->of_node) { /* If it's an ACPI client */ + list_for_each_entry(mbox, &mbox_cons, node) { + if (!mbox->global_xlate) + continue; + chan = mbox->global_xlate(mbox, index); + if (chan && !chan->cl) + break; + } + } else { + struct of_phandle_args spec; + + if (of_parse_phandle_with_args(dev->of_node, "mboxes", + "#mbox-cells", index, &spec)) { + dev_dbg(dev, "%s: can't parse \"mboxes\" property\n", + __func__); + mutex_unlock(&con_mutex); + return ERR_PTR(-ENODEV); } - of_node_put(spec.np); + list_for_each_entry(mbox, &mbox_cons, node) + if (mbox->dev->of_node == spec.np) { + chan = mbox->of_xlate(mbox, &spec); + break; + } + + of_node_put(spec.np); + } if (!chan || chan->cl || !try_module_get(mbox->dev->driver->owner)) { - dev_dbg(dev, "%s: mailbox not free\n", __func__); + pr_err("%s: mailbox not available\n", __func__); mutex_unlock(&con_mutex); return ERR_PTR(-EBUSY); } @@ -344,7 +350,7 @@ struct mbox_chan *mbox_request_channel(struct mbox_client *cl, int index) ret = chan->mbox->ops->startup(chan); if (ret) { - dev_err(dev, "Unable to startup the chan (%d)\n", ret); + pr_err("Unable to startup the chan (%d)\n", ret); mbox_free_channel(chan); chan = ERR_PTR(ret); } diff --git a/include/linux/mailbox_controller.h b/include/linux/mailbox_controller.h index d4cf96f..76871b2 100644 --- a/include/linux/mailbox_controller.h +++ b/include/linux/mailbox_controller.h @@ -67,6 +67,11 @@ struct mbox_chan_ops { * @txpoll_period: If 'txdone_poll' is in effect, the API polls for * last TX's status after these many millisecs * @of_xlate: Controller driver specific mapping of channel via DT + * @global_xlate: Controller driver specific mapping of channel for + * non-DT based clients (like ACPI). The 'global_id' + * argument is a token to uniquely identify the mbox_chan + * fromm those provided by more than one such controllers. + * 'of_xlate' takes precedence for DT based clients. * @poll: API private. Used to poll for TXDONE on all channels. * @node: API private. To hook into list of controllers. */ @@ -80,6 +85,8 @@ struct mbox_controller { unsigned txpoll_period; struct mbox_chan *(*of_xlate)(struct mbox_controller *mbox, const struct of_phandle_args *sp); + struct mbox_chan *(*global_xlate)(struct mbox_controller *mbox, + int global_id); /* Internal to API */ struct timer_list poll; struct list_head node; -- 1.8.1.2

10 years, 6 months

1
0
0 0

leg-kernel tag leg-20141107.0 released

by Graeme Gregory

The leg-kernel release has been made and tagged as leg-201401107.0 This is based on mainline kernel v3.18-rc3 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: https://git.linaro.org/leg/acpi/leg-kernel.git/commit/0aab83c05d7f2dc467d76… Notes :- 1) This release merges Seattle support from Redhat/AMD! https://git.linaro.org/leg/acpi/acpi.git/shortlog/refs/heads/acpi-topic-sea… 2) This release disables STRICT_DEVMEM in distribution.conf, this is needed to work on FWTS for the short term and should not be considered a production change.

10 years, 6 months

1
0
0 0

leg-kernel tag leg-20141106.0 released

by Graeme Gregory

The leg-kernel release has been made and tagged as leg-201401106.0 This is based on mainline kernel v3.18-rc3 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: https://git.linaro.org/leg/acpi/leg-kernel.git/commit/91d55a0bbfc3548e3a09e… Notes :- 1) This release merges Seattle support from Redhat/AMD! https://git.linaro.org/leg/acpi/acpi.git/shortlog/refs/heads/acpi-topic-sea…

10 years, 6 months

1
0
0 0

[PATCH v9] PCC: Platform Communication Channel

by Ashwin Chaugule

Changes since V8: - Removed unncessary header files. - Added kerneldoc comments. - Added intro about PCC in pcc.c Changes since V7: - Added timeout to tx method in case the remote dies. - Restructured usage of acpi_status. Had inverted logic previously. Changes since V6: - Cosmetic changes based on Lv's suggestions Changes since V5: - Optimize loop that matches channel request. - Use platform_create_bundle. - Replace ioread/writes. - Remove redundant code and headers. - Restructure common mailbox macros. - Reformat PCC cmd parsing. Changes since V4: - Folded PCC Mailbox helpers into pcc.c Changes since V3: - Added PCC helper functions to work around "struct device" limitations. - PCC driver changes to work with PCC specific Mailbox helpers. Changes since V2: - Rebased on top of git://git.linaro.org/landing-teams/working/fujitsu/integration.git branch mailbox-for-3.17 - Added PCC API to mailbox framework as per Arnd's suggestion to allow usage without ACPI. Changes since V1: - Integration with Mailbox framework - https://lkml.org/lkml/2014/5/15/49 This patchset adds support for the PCC (Platform Communication Channel) interface as described in the current ACPI 5.0 spec. See Section 14 of the ACPI spec - http://acpi.info/DOWNLOADS/ACPI_5_Errata%20A.pdf for more details on how PCC works. In brief PCC is a generic means for PCC clients, to talk to the firmware. The PCC register space is typically memory mapped IO and uses a doorbell mechanism to communicate synchronously from the OS to the firmware. The PCC driver is completely agnostic to the protocol implemented by the PCC clients. It only implements the enumeration of PCC channels and the low level transport mechanism and leaves the rest to the PCC clients. The PCC is meant to be useable in the future by clients such as CPPC (Collaborative Processor Performance Control), RAS (Reliability, Availability and Serviceability) and MPST (Memory Power State Tables) and possibly others. Ashwin Chaugule (1): Mailbox: Add support for Platform Communication Channel drivers/mailbox/Kconfig | 12 ++ drivers/mailbox/Makefile | 2 + drivers/mailbox/mailbox.c | 4 +- drivers/mailbox/mailbox.h | 16 ++ drivers/mailbox/pcc.c | 369 ++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 400 insertions(+), 3 deletions(-) create mode 100644 drivers/mailbox/mailbox.h create mode 100644 drivers/mailbox/pcc.c -- 1.9.1

10 years, 6 months

1
3
0 0

leg-kernel tag leg-20141105.0 released

by Graeme Gregory

The leg-kernel release has been made and tagged as leg-201401105.0 This is based on mainline kernel v3.18-rc3 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: https://git.linaro.org/leg/acpi/leg-kernel.git/commit/664f66862558283aab860… Notes :-

10 years, 6 months

1
0
0 0

[RFC PATCH 3/7] hw/arm/virt-acpi: Generate RSDP and XSDT, add helper functions

by Alexander Spyridakis

RSDP points to XSDT which in turn points to other tables. In the case of RSDP things are straightforward as we can point to XSDT just by adding the binary blob base address plus the size of RSDP. For XSDT we traverse the table array and point every other table by calculating their size (exception being FACS and DSDT which are pointed from FADT). Finally implement a common header and checksum helper functions for usage in all generated ACPI tables. Signed-off-by: Alexander Spyridakis <a.spyridakis(a)virtualopensystems.com> Signed-off-by: Alvise Rigo <a.rigo(a)virtualopensystems.com> --- hw/arm/virt-acpi.c | 93 +++++++++++++++++++++++++++++++++++++++++++-- include/hw/acpi/acpi-defs.h | 9 +++++ include/hw/arm/virt-acpi.h | 6 +++ 3 files changed, 104 insertions(+), 4 deletions(-) diff --git a/hw/arm/virt-acpi.c b/hw/arm/virt-acpi.c index 5c8df45..0d7bb99 100644 --- a/hw/arm/virt-acpi.c +++ b/hw/arm/virt-acpi.c @@ -21,16 +21,101 @@ static void *acpi_table[NUM_ACPI_TABLES]; static int acpi_size[NUM_ACPI_TABLES]; +/* + * Many of the ACPI tables use the same header structure + * This is a common function to fill such information. + */ +static void acpi_fill_common_header_data(void *table, const char *signature, + uint8_t revision, int length) +{ + AcpiTableHeader *h = (AcpiTableHeader *)table; + + memcpy(&h->signature, signature, sizeof(h->signature)); + memcpy(h->oem_id, ACPI_VIRT_QEMU_STR_4, sizeof(h->oem_id)); + memcpy(h->oem_table_id, ACPI_VIRT_MACH_STR_8, sizeof(h->oem_table_id)); + h->revision = revision; + h->length = cpu_to_le32(length); +} + +/* + * Called at the very end of an ACPI table. + * Adding all the data bytes, plus the checksum should equal to zero. + */ +static void acpi_do_checksum(void *table, uint32_t length, uint8_t *checksum) +{ + uint8_t sum, *ptr; + + sum = 0; + ptr = table; + + *checksum = 0; + while (length--) { + sum = (uint8_t)(sum + (*ptr++)); + } + + ptr = table; + *checksum = (uint8_t) (0xff - sum + 1); +} + static void acpi_create_rsdp(void) { - acpi_table[RSDP] = NULL; - acpi_size[RSDP] = 0; + AcpiRsdpDescriptor *rsdp; + + rsdp = g_malloc0(sizeof(*rsdp)); + + /* Set table header information */ + memcpy(&rsdp->signature, "RSD PTR ", sizeof(rsdp->signature)); + memcpy(rsdp->oem_id, ACPI_VIRT_QEMU_STR_6, sizeof(rsdp->oem_id)); + rsdp->length = cpu_to_le32(sizeof(*rsdp)); + rsdp->revision = 0x02; + + /* Point to XSDT */ + rsdp->xsdt_physical_address = cpu_to_le64(ACPI_BASE_ADDRESS + rsdp->length); + + /* Calculate normal and extended checksum */ + acpi_do_checksum(rsdp, + offsetof(AcpiRsdpDescriptor, length), &rsdp->checksum); + acpi_do_checksum(rsdp, rsdp->length, &rsdp->extended_checksum); + + acpi_table[RSDP] = (void *)rsdp; + acpi_size[RSDP] = rsdp->length; } static void acpi_create_xsdt(void) { - acpi_table[XSDT] = NULL; - acpi_size[XSDT] = 0; + AcpiXsdtDescriptor *xsdt; + int i, xsdt_size; + + /* + * The final size of XSDT is the table size plus the number + * of pointed tables multiplied by the table_offset_entry size. + * + * The initial xsdt table size already includes one pointed table and + * assuming that FADT is the last pointed table we can calculate the + * total based on that. + */ + xsdt_size = sizeof(*xsdt) + + ((FADT - (XSDT + 1)) * sizeof(xsdt->table_offset_entry)); + xsdt = g_malloc0(xsdt_size); + + /* Set table header information */ + acpi_fill_common_header_data(xsdt, "XSDT", 1, xsdt_size); + + /* Point first table included by default in the xsdt structure */ + xsdt->table_offset_entry[0] = cpu_to_le64( + ACPI_BASE_ADDRESS + acpi_size[RSDP] + xsdt->length); + + /* Point all other tables (excluding FACS and DSDT) */ + for (i = XSDT; i < FADT - 1; i++) { + xsdt->table_offset_entry[i] = + xsdt->table_offset_entry[i - 1] + acpi_size[i + 1]; + } + + /* Calculate checksum */ + acpi_do_checksum(xsdt, xsdt->length, &xsdt->checksum); + + acpi_table[XSDT] = (void *)xsdt; + acpi_size[XSDT] = xsdt->length; } static void acpi_create_madt(uint32_t smp_cpus, diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index c4468f8..779f872 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -88,6 +88,15 @@ struct AcpiTableHeader /* ACPI common table header */ typedef struct AcpiTableHeader AcpiTableHeader; /* + * Extended System Description Table (XSDT) + */ +struct AcpiXsdtDescriptor { + ACPI_TABLE_HEADER_DEF + uint64_t table_offset_entry[1]; /* Array of pointers to ACPI tables */ +} QEMU_PACKED; +typedef struct AcpiXsdtDescriptor AcpiXsdtDescriptor; + +/* * ACPI 1.0 Fixed ACPI Description Table (FADT) */ struct AcpiFadtDescriptorRev1 diff --git a/include/hw/arm/virt-acpi.h b/include/hw/arm/virt-acpi.h index 5098118..66a73eb 100644 --- a/include/hw/arm/virt-acpi.h +++ b/include/hw/arm/virt-acpi.h @@ -23,6 +23,12 @@ #define NUM_ACPI_TABLES 7 +#define ACPI_VIRT_QEMU_STR_4 "QEMU" +#define ACPI_VIRT_QEMU_STR_6 "QEMU " +#define ACPI_VIRT_MACH_STR_8 "MACHVIRT" + +#define ACPI_BASE_ADDRESS 0x47000000 + enum { RSDP, XSDT, -- 1.9.1

10 years, 6 months

1
0
0 0

[RFC PATCH 5/7] hw/arm/virt-acpi: GIC and Arch Timer definitions in MADT and GTDT

by Alexander Spyridakis

ACPI v5.1 defines GTDT for ARM devices as a place to describe timer related information in the system. MADT is also updated with a number of relevant subtables that can describe GIC enabled ARM platforms. For GTDT the Arch Timer interrupts must be provided, in the case of MADT the GICC and GICD subtables are used to define the GIC regions. Signed-off-by: Alexander Spyridakis <a.spyridakis(a)virtualopensystems.com> --- hw/arm/virt-acpi.c | 65 +++++++++++++++++++++++++++++++++++++--- include/hw/acpi/acpi-defs.h | 73 ++++++++++++++++++++++++++++++++++++++++++++- include/hw/arm/virt-acpi.h | 6 ++++ 3 files changed, 139 insertions(+), 5 deletions(-) diff --git a/hw/arm/virt-acpi.c b/hw/arm/virt-acpi.c index aca0434..a53a620 100644 --- a/hw/arm/virt-acpi.c +++ b/hw/arm/virt-acpi.c @@ -121,14 +121,71 @@ static void acpi_create_xsdt(void) static void acpi_create_madt(uint32_t smp_cpus, const struct acpi_madt_info *info) { - acpi_table[MADT] = NULL; - acpi_size[MADT] = 0; + AcpiMultipleApicTable *madt; + AcpiMadtGenericInterrupt *gicc; + AcpiMadtGenericDistributor *gicd; + int i, madt_size; + + madt_size = sizeof(*madt) + (smp_cpus * sizeof(*gicc) + sizeof(*gicd)); + madt = g_malloc0(madt_size); + + acpi_fill_common_header_data(madt, "APIC", 1, madt_size); + + madt->local_apic_address = *info->gic_cpu_base_addr; + + /* Point at the end of the madt structure */ + gicc = (AcpiMadtGenericInterrupt *)(madt + 1); + + /* GICC subtable, one for each cpu in the guest*/ + for (i = 0; i < smp_cpus; i++) { + gicc->type = ACPI_APIC_GENERIC_INTERRUPT; + gicc->length = sizeof(*gicc); + + gicc->base_address = *info->gic_cpu_base_addr; + gicc->cpu_interface_number = i; + gicc->arm_mpidr = i; + gicc->uid = i; + gicc->flags = 0x01; + + gicc++; + } + + /* GIC Distributor subtable */ + gicd = (AcpiMadtGenericDistributor *)(gicc); + gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR; + gicd->length = sizeof(*gicd); + gicd->base_address = *info->gic_dist_base_addr; + + acpi_do_checksum(madt, madt->length, &madt->checksum); + + acpi_table[MADT] = (void *)madt; + acpi_size[MADT] = madt->length; } static void acpi_create_gtdt(const struct acpi_gtdt_info *irqs) { - acpi_table[GTDT] = NULL; - acpi_size[GTDT] = 0; + AcpiGenericTimerTable *gtdt; + + gtdt = g_malloc0(sizeof(*gtdt)); + acpi_fill_common_header_data(gtdt, "GTDT", 1, sizeof(*gtdt)); + + /* The interrupt values are the same with the device tree when adding 16 */ + gtdt->secure_el1_interrupt = irqs->timer_s_el1; + gtdt->secure_el1_flags = ACPI_EDGE_SENSITIVE; + + gtdt->non_secure_el1_interrupt = irqs->timer_ns_el1; + gtdt->non_secure_el1_flags = ACPI_EDGE_SENSITIVE; + + gtdt->virtual_timer_interrupt = irqs->timer_virt; + gtdt->virtual_timer_flags = ACPI_EDGE_SENSITIVE; + + gtdt->non_secure_el2_interrupt = irqs->timer_ns_el2; + gtdt->non_secure_el2_flags = ACPI_EDGE_SENSITIVE; + + acpi_do_checksum(gtdt, gtdt->length, &gtdt->checksum); + + acpi_table[GTDT] = (void *)gtdt; + acpi_size[GTDT] = gtdt->length; } static void acpi_create_fadt(void) diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index ebbd2d0..f5e5222 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -257,7 +257,13 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable; #define ACPI_APIC_IO_SAPIC 6 #define ACPI_APIC_LOCAL_SAPIC 7 #define ACPI_APIC_XRUPT_SOURCE 8 -#define ACPI_APIC_RESERVED 9 /* 9 and greater are reserved */ +#define ACPI_APIC_LOCAL_X2APIC 9 +#define ACPI_APIC_LOCAL_X2APIC_NMI 10 +#define ACPI_APIC_GENERIC_INTERRUPT 11 +#define ACPI_APIC_GENERIC_DISTRIBUTOR 12 +#define ACPI_APIC_GENERIC_MSI_FRAME 13 +#define ACPI_APIC_GENERIC_REDISTRIBUTOR 14 +#define ACPI_APIC_RESERVED 15 /* 15 and greater are reserved */ /* * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE) @@ -305,6 +311,71 @@ struct AcpiMadtLocalNmi { } QEMU_PACKED; typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi; +struct AcpiMadtGenericInterrupt { + ACPI_SUB_HEADER_DEF + uint16_t reserved; + uint32_t cpu_interface_number; + uint32_t uid; + uint32_t flags; + uint32_t parking_version; + uint32_t performance_interrupt; + uint64_t parked_address; + uint64_t base_address; + uint64_t gicv_base_address; + uint64_t gich_base_address; + uint32_t vgic_interrupt; + uint64_t gicr_base_address; + uint64_t arm_mpidr; +} QEMU_PACKED; +typedef struct AcpiMadtGenericInterrupt AcpiMadtGenericInterrupt; + +struct AcpiMadtGenericDistributor { + ACPI_SUB_HEADER_DEF + uint16_t reserved; + uint32_t gic_id; + uint64_t base_address; + uint32_t global_irq_base; + uint32_t reserved2; +} QEMU_PACKED; +typedef struct AcpiMadtGenericDistributor AcpiMadtGenericDistributor; + +/* + * Generic Timer Description Table (GTDT) + */ + +#define ACPI_GTDT_INTERRUPT_MODE (1) +#define ACPI_GTDT_INTERRUPT_POLARITY (1<<1) +#define ACPI_GTDT_ALWAYS_ON (1<<2) + +/* Triggering */ + +#define ACPI_LEVEL_SENSITIVE (uint8_t) 0x00 +#define ACPI_EDGE_SENSITIVE (uint8_t) 0x01 + +/* Polarity */ + +#define ACPI_ACTIVE_HIGH (uint8_t) 0x00 +#define ACPI_ACTIVE_LOW (uint8_t) 0x01 +#define ACPI_ACTIVE_BOTH (uint8_t) 0x02 + +struct AcpiGenericTimerTable { + ACPI_TABLE_HEADER_DEF + uint64_t counter_block_addresss; + uint32_t reserved; + uint32_t secure_el1_interrupt; + uint32_t secure_el1_flags; + uint32_t non_secure_el1_interrupt; + uint32_t non_secure_el1_flags; + uint32_t virtual_timer_interrupt; + uint32_t virtual_timer_flags; + uint32_t non_secure_el2_interrupt; + uint32_t non_secure_el2_flags; + uint64_t counter_read_block_address; + uint32_t platform_timer_count; + uint32_t platform_timer_offset; +} QEMU_PACKED; +typedef struct AcpiGenericTimerTable AcpiGenericTimerTable; + /* * HPET Description Table */ diff --git a/include/hw/arm/virt-acpi.h b/include/hw/arm/virt-acpi.h index 66a73eb..216a3a2 100644 --- a/include/hw/arm/virt-acpi.h +++ b/include/hw/arm/virt-acpi.h @@ -41,9 +41,15 @@ enum { }; struct acpi_gtdt_info { + uint32_t timer_virt; + uint32_t timer_s_el1; + uint32_t timer_ns_el1; + uint32_t timer_ns_el2; }; struct acpi_madt_info { + const hwaddr *gic_cpu_base_addr; + const hwaddr *gic_dist_base_addr; }; struct acpi_dsdt_info { -- 1.9.1

10 years, 6 months

1
0
0 0

[RFC PATCH 6/7] hw/arm/virt-acpi: Generation of DSDT including virt devices

by Alexander Spyridakis

DSDT consists of the usual common table header plus a definition block in AML encoding which describes all devices in the platform. After initializing DSDT with header information the namespace is created which is followed by the device encodings. The devices are described using the Resource Template for the 32-Bit Fixed Memory Range and the Extended Interrupt Descriptors. Additional helper functions are implemented to add devices with the Resource Template and calculating their multiple size fields which are not fixed. The following devices are included in the DSDT: - CPUs - UART - RTC - NAND Flash - virtio-mmio Signed-off-by: Alexander Spyridakis <a.spyridakis(a)virtualopensystems.com> --- hw/arm/virt-acpi.c | 284 +++++++++++++++++++++++++++++++++++++++++++- include/hw/acpi/acpi-defs.h | 34 ++++++ include/hw/arm/virt-acpi.h | 9 ++ 3 files changed, 325 insertions(+), 2 deletions(-) diff --git a/hw/arm/virt-acpi.c b/hw/arm/virt-acpi.c index a53a620..be490e7 100644 --- a/hw/arm/virt-acpi.c +++ b/hw/arm/virt-acpi.c @@ -22,6 +22,258 @@ static void *acpi_table[NUM_ACPI_TABLES]; static int acpi_size[NUM_ACPI_TABLES]; /* + * Package length encoding: + * The package length can range from 1 to 4 bytes. For a package size less than + * 64, only 1 byte is needed, bits 0 - 5 represent the size and the rest should + * be zero. In case of larger package sizes, for the first byte (Package Lead + * Byte), bits 0 - 3 hold the least significant nibble of the size value, bits + * 4 - 5 are reserved and must be zero, bits 6 - 7 signify how many size bytes + * are following. + */ +static void *acpi_calc_size(uint8_t *buf, uint8_t *end, bool resource) +{ + uint8_t *ret, *ptr = buf; + unsigned int size = end - buf; + unsigned int i, shift, byte_num = 1; + + if (size < (1 << 6)) { + byte_num = 1; + } else if (size < (1 << 12)) { + byte_num = 2; + } else if (size < (1 << 20)) { + byte_num = 3; + } else if (size < (1 << 28)) { + byte_num = 4; + } + + if (resource) { + memmove(ptr + (byte_num * 2) + 1, buf, size); + size += (byte_num * 2) + 1; + } else { + memmove(ptr + byte_num, buf, size); + size += byte_num; + } + + *ptr++ = byte_num == 1 ? size : (size & 0x0F) | ((byte_num - 1) << 6); + + shift = 4; + for (i = 1; i < byte_num; i++) { + *ptr++ = size >> shift; + shift += 8; + } + + /* In the case of a resource template we have to add another size + * value just after the package size. This field needs to be + * prefixed by a byte signifying how many bytes the size is. */ + if (resource) { + switch (byte_num) { + case 1: + *ptr++ = ACPI_AML_BYTE_PREFIX; + break; + case 2: + *ptr++ = ACPI_AML_WORD_PREFIX; + break; + case 3: + *ptr++ = ACPI_AML_DWORD_PREFIX; + break; + case 4: + *ptr++ = ACPI_AML_QWORD_PREFIX; + break; + } + + shift = 0; + for (i = 0; i < byte_num; i++) { + *ptr++ = (size - byte_num - 2) >> shift; + shift += 8; + } + } + + ret = buf + size; + return ret; +} + +static void *acpi_dsdt_init_device(uint8_t *buf, const char *name, + const char *hid, int uid) +{ + uint8_t *ptr = buf; + + /* DeviceOp */ + *ptr++ = ACPI_AML_DEVICE_OP; + *ptr++ = ACPI_AML_OP_PREFIX; + + /* Device name */ + ptr = mempcpy(ptr, name, 4); + *ptr++ = ACPI_AML_NAME_OP; + + /* Hardware ID */ + ptr = mempcpy(ptr, "_HID", 4); + *ptr++ = ACPI_AML_STRING_PREFIX; + ptr = mempcpy(ptr, hid, 9); + *ptr++ = ACPI_AML_NAME_OP; + + /* Unique ID - Values greater than one need the byte prefix */ + ptr = mempcpy(ptr, "_UID", 4); + if (uid > 1) { + *ptr++ = ACPI_AML_BYTE_PREFIX; + } + *ptr++ = uid; + + return ptr; +} + +static void *acpi_add_res_memory32(uint8_t *buf, hwaddr addr, + hwaddr size, uint8_t rw_flag) +{ + AcpiAmlResourceFixedMemory32 *memory = (AcpiAmlResourceFixedMemory32 *)buf; + + memory->descriptor_type = ACPI_AML_RESOURCE_MEMORY32; + memory->resource_length = sizeof(*memory) - 3; + + memory->flags = rw_flag; + memory->address = addr; + memory->address_length = size; + + return (void *)memory + sizeof(*memory); +} + +static void *acpi_add_res_extended_irq(uint8_t *buf, uint8_t irq_flags, int irq) +{ + AcpiAmlResourceExtendedIrq *ext_irq = (AcpiAmlResourceExtendedIrq *)buf; + + ext_irq->descriptor_type = ACPI_AML_RESOURCE_EXTENDED_IRQ; + ext_irq->resource_length = sizeof(*ext_irq) - 3; + + ext_irq->flags = irq_flags; + ext_irq->interrupt_count = 0x01; + ext_irq->interrupts[0] = irq; + + return (void *)ext_irq + sizeof(*ext_irq); +} + +/* + * Create a device definition based on the ACPI ResourceTemplate: + * First the name, hardware and unique ID segments are created, + * then the resource template regions are added to define the + * address, size and interrupts of the device. + * Finally, the End Tag is used to signify the end of the device, + * and the total length is calculated. + */ +static void *acpi_dsdt_add_simple_resource(uint8_t *buf, const char *name, + const char *hid, int uid, + hwaddr base, hwaddr size, + int irq, uint8_t irq_flags) +{ + uint8_t *res_len, *ptr = buf; + + ptr = acpi_dsdt_init_device(ptr, name, hid, uid); + + /* Skip the creation of a resource template if it is not provided */ + if (!size && !irq) { + goto ret; + } + + /* Resource template */ + *ptr++ = ACPI_AML_NAME_OP; + ptr = mempcpy(ptr, "_CRS", 4); + *ptr++ = ACPI_AML_BUFFER_PREFIX; + + /* Point to resource size for later */ + res_len = ptr; + + /* Add resource template regions */ + if (size) { + ptr = acpi_add_res_memory32(ptr, base, size, 0x01); + } + if (irq) { + ptr = acpi_add_res_extended_irq(ptr, irq_flags, irq); + } + + /* End the resource template */ + *ptr++ = ACPI_AML_END_TAG; + *ptr++ = 0x00; + + /* Update resource size */ + ptr = acpi_calc_size(res_len, ptr, 1); + +ret: + /* Calculate total device size */ + ptr = acpi_calc_size(buf + 2, ptr, 0); + + return ptr; +} + +static void *acpi_dsdt_add_cpus(uint8_t *buf, int cpus) +{ + int i; + char name[5]; + uint8_t *ptr = buf; + + /* In the case of CPUs there is no need for a resource template */ + for (i = 0; i < cpus; i++) { + snprintf(name, 5, "CPU%u", i); + ptr = acpi_dsdt_add_simple_resource(ptr, name, "ACPI0007", + i, 0, 0, 0, 0); + } + + return ptr; +} + +static void *acpi_dsdt_add_uart(uint8_t *buf, const hwaddr *uart_addr, + const int *uart_irq) +{ + uint8_t *ptr = buf; + + ptr = acpi_dsdt_add_simple_resource(ptr, "COM0", "ARMH0011", 0, + uart_addr[0], uart_addr[1], *uart_irq + 32, 0x01); + return ptr; +} + +static void *acpi_dsdt_add_rtc(uint8_t *buf, const hwaddr *rtc_addrs, + const int *rtc_irq) +{ + uint8_t *ptr = buf; + int irq = *rtc_irq + 32; + + ptr = acpi_dsdt_add_simple_resource(ptr, "RTC0", "LNRO0013", 0, + rtc_addrs[0], rtc_addrs[1], irq, 0x01); + + return ptr; +} + +static void *acpi_dsdt_add_flash(uint8_t *buf, const hwaddr *flash_addrs) +{ + uint8_t *ptr = buf; + hwaddr base = flash_addrs[0]; + hwaddr size = flash_addrs[1]; + + ptr = acpi_dsdt_add_simple_resource(ptr, "FLS0", "LNRO0015", + 0, base, size, 0, 0); + ptr = acpi_dsdt_add_simple_resource(ptr, "FLS1", "LNRO0015", + 1, base + size, size, 0, 0); + return ptr; +} + +static void *acpi_dsdt_add_virtio(uint8_t *buf, const hwaddr *mmio_addrs, + const int *mmio_irq, int num) +{ + int i; + char name[5]; + uint8_t *ptr = buf; + hwaddr base = mmio_addrs[0]; + hwaddr size = mmio_addrs[1]; + int irq = *mmio_irq + 32; + + for (i = 0; i < num; i++) { + snprintf(name, 5, "VR%02u", i); + ptr = acpi_dsdt_add_simple_resource(ptr, name, "LNRO0005", + i, base, size, irq + i, 0x01); + base += size; + } + + return ptr; +} + +/* * Many of the ACPI tables use the same header structure * This is a common function to fill such information. */ @@ -235,8 +487,36 @@ static void acpi_create_facs(void) static void acpi_create_dsdt(int smp_cpus, const struct acpi_dsdt_info *info) { - acpi_table[DSDT] = NULL; - acpi_size[DSDT] = 0; + uint8_t *ptr; + AcpiTableHeader *header; + + /* As we don't know the size of DSDT beforehand, allocate a chunk of + * memory and pass this to all other calls that add device definitions */ + acpi_table[DSDT] = g_malloc0(ACPI_DSDT_MAX_SIZE); + ptr = acpi_table[DSDT]; + header = (AcpiTableHeader *)acpi_table[DSDT]; + + acpi_fill_common_header_data(ptr, "DSDT", 1, sizeof(AcpiTableHeader)); + ptr = acpi_table[DSDT] + sizeof(AcpiTableHeader); + + /* Scope and namespace, length will be filled at the end */ + *ptr++ = ACPI_AML_SCOPE_OP; + ptr = mempcpy(ptr, "_SB_", 4); + + /* Add device definitions */ + ptr = acpi_dsdt_add_cpus(ptr, smp_cpus); + ptr = acpi_dsdt_add_uart(ptr, info->uart_addr, info->uart_irq); + ptr = acpi_dsdt_add_rtc(ptr, info->rtc_addr, info->rtc_irq); + ptr = acpi_dsdt_add_flash(ptr, info->flash_addr); + ptr = acpi_dsdt_add_virtio(ptr, info->virtio_mmio_addr, + info->virtio_mmio_irq, info->virtio_mmio_num); + + /* Table and namespace size calculation */ + ptr = acpi_calc_size(acpi_table[DSDT] + sizeof(*header) + 1, ptr, 0); + acpi_size[DSDT] = (void *)ptr - acpi_table[DSDT]; + header->length = acpi_size[DSDT]; + + acpi_do_checksum(acpi_table[DSDT], acpi_size[DSDT], &header->checksum); } void acpi_build_tables(int smp_cpus, diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index f5e5222..dc4ae46 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -227,6 +227,40 @@ typedef struct AcpiFacsDescriptorRev5_1 AcpiFacsDescriptorRev5_1; * Differentiated System Description Table (DSDT) */ +#define ACPI_AML_SCOPE_OP 0x10 +#define ACPI_AML_DEVICE_OP 0x5B +#define ACPI_AML_NAME_OP 0x08 +#define ACPI_AML_OP_PREFIX 0x82 +#define ACPI_AML_BYTE_PREFIX 0x0A +#define ACPI_AML_WORD_PREFIX 0x0B +#define ACPI_AML_DWORD_PREFIX 0x0C +#define ACPI_AML_QWORD_PREFIX 0x0E +#define ACPI_AML_STRING_PREFIX 0x0D +#define ACPI_AML_BUFFER_PREFIX 0x11 +#define ACPI_AML_END_TAG 0x79 +#define ACPI_AML_RESOURCE_MEMORY32 0x86 +#define ACPI_AML_RESOURCE_EXTENDED_IRQ 0x89 + +#define AML_RESOURCE_LARGE_HEADER_COMMON \ + uint8_t descriptor_type;\ + uint16_t resource_length; + +struct AcpiAmlResourceFixedMemory32 { + AML_RESOURCE_LARGE_HEADER_COMMON + uint8_t flags; + uint32_t address; + uint32_t address_length; +} QEMU_PACKED; +typedef struct AcpiAmlResourceFixedMemory32 AcpiAmlResourceFixedMemory32; + +struct AcpiAmlResourceExtendedIrq { + AML_RESOURCE_LARGE_HEADER_COMMON + uint8_t flags; + uint8_t interrupt_count; + uint32_t interrupts[1]; +} QEMU_PACKED; +typedef struct AcpiAmlResourceExtendedIrq AcpiAmlResourceExtendedIrq; + /* * MADT values and structures */ diff --git a/include/hw/arm/virt-acpi.h b/include/hw/arm/virt-acpi.h index 216a3a2..39bb14d 100644 --- a/include/hw/arm/virt-acpi.h +++ b/include/hw/arm/virt-acpi.h @@ -28,6 +28,7 @@ #define ACPI_VIRT_MACH_STR_8 "MACHVIRT" #define ACPI_BASE_ADDRESS 0x47000000 +#define ACPI_DSDT_MAX_SIZE 0x4000 enum { RSDP, @@ -53,6 +54,14 @@ struct acpi_madt_info { }; struct acpi_dsdt_info { + const hwaddr *uart_addr; + const int *uart_irq; + const hwaddr *virtio_mmio_addr; + const int *virtio_mmio_irq; + int virtio_mmio_num; + const hwaddr *rtc_addr; + const int *rtc_irq; + const hwaddr *flash_addr; }; void acpi_build_tables(int smp_cpus, -- 1.9.1

10 years, 6 months

1
0
0 0

[RFC PATCH 7/7] hw/arm/virt: Enable dynamic generation of ACPI v5.1 tables

by Alexander Spyridakis

Expose the needed device information to the table generation insfrastructure and assemble the final compacted ACPI binary blob in the guest memory. Signed-off-by: Alvise Rigo <a.rigo(a)virtualopensystems.com> --- hw/arm/boot.c | 26 +++++++++++++++++++++++++ hw/arm/virt-acpi.c | 18 +++++++++++++++++- hw/arm/virt.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++---- include/hw/arm/arm.h | 2 ++ 4 files changed, 95 insertions(+), 5 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index bffbea5..74c8eb5 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -179,6 +179,11 @@ static inline bool have_dtb(const struct arm_boot_info *info) return info->dtb_filename || info->get_dtb; } +static inline bool have_acpi(const struct arm_boot_info *info) +{ + return info->get_acpi; +} + #define WRITE_WORD(p, value) do { \ stl_phys_notdirty(&address_space_memory, p, value); \ p += 4; \ @@ -438,6 +443,20 @@ fail: return -1; } +static int load_acpi(hwaddr addr, const struct arm_boot_info *binfo, + hwaddr addr_limit) +{ + void *acpi_blob = NULL; + int acpi_size; + + acpi_blob = binfo->get_acpi(binfo, &acpi_size); + rom_add_blob_fixed("acpi", acpi_blob, acpi_size, binfo->acpi_base_addr); + g_free(acpi_blob); + /* TODO: check to not write outside memory boundaries */ + + return 0; +} + static void do_cpu_reset(void *opaque) { ARMCPU *cpu = opaque; @@ -497,6 +516,13 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); } + /* load ACPI blob */ + if (have_acpi(info)) { + if (load_acpi(info->acpi_base_addr, info, 0) < 0) { + exit(1); + } + } + /* Load the kernel. */ if (!info->kernel_filename) { diff --git a/hw/arm/virt-acpi.c b/hw/arm/virt-acpi.c index be490e7..19e6779 100644 --- a/hw/arm/virt-acpi.c +++ b/hw/arm/virt-acpi.c @@ -535,5 +535,21 @@ void acpi_build_tables(int smp_cpus, uint32_t acpi_make_blob(void **blob_ptr) { - return 0; + uint8_t *acpi_blob_ptr = NULL; + uint32_t blob_size, n; + + for (n = RSDP, blob_size = 0; n <= DSDT; n++) { + blob_size += acpi_size[n]; + } + + *blob_ptr = (void *)g_malloc0(blob_size); + acpi_blob_ptr = *blob_ptr; + + for (n = RSDP; n <= DSDT; n++) { + memcpy(acpi_blob_ptr, acpi_table[n], acpi_size[n]); + acpi_blob_ptr += acpi_size[n]; + g_free(acpi_table[n]); + } + + return blob_size; } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 78f618d..5b40292 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -42,6 +42,8 @@ #include "exec/address-spaces.h" #include "qemu/bitops.h" #include "qemu/error-report.h" +#include "hw/acpi/acpi-defs.h" +#include "hw/arm/virt-acpi.h" #define NUM_VIRTIO_TRANSPORTS 32 @@ -59,6 +61,11 @@ #define GIC_FDT_IRQ_PPI_CPU_START 8 #define GIC_FDT_IRQ_PPI_CPU_WIDTH 8 +#define ARCH_TIMER_VIRT_IRQ 11 +#define ARCH_TIMER_S_EL1_IRQ 13 +#define ARCH_TIMER_NS_EL1_IRQ 14 +#define ARCH_TIMER_NS_EL2_IRQ 10 + enum { VIRT_FLASH, VIRT_MEM, @@ -83,6 +90,8 @@ typedef struct VirtBoardInfo { int smp_cpus; void *fdt; int fdt_size; + void *acpi; + int acpi_size; uint32_t clock_phandle; } VirtBoardInfo; @@ -119,6 +128,29 @@ static const int a15irqmap[] = { [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ }; +static const struct acpi_madt_info madt_info = { + &a15memmap[VIRT_GIC_CPU].base, + &a15memmap[VIRT_GIC_DIST].base +}; + +static const struct acpi_dsdt_info dsdt_info = { + .uart_addr = &a15memmap[VIRT_UART].base, + .uart_irq = &a15irqmap[VIRT_UART], + .virtio_mmio_addr = &a15memmap[VIRT_MMIO].base, + .virtio_mmio_irq = &a15irqmap[VIRT_MMIO], + .virtio_mmio_num = NUM_VIRTIO_TRANSPORTS, + .rtc_addr = &a15memmap[VIRT_RTC].base, + .rtc_irq = &a15irqmap[VIRT_RTC], + .flash_addr = &a15memmap[VIRT_FLASH].base, +}; + +static const struct acpi_gtdt_info gtdt_info = { + ARCH_TIMER_VIRT_IRQ + 16, + ARCH_TIMER_S_EL1_IRQ + 16, + ARCH_TIMER_NS_EL1_IRQ + 16, + ARCH_TIMER_NS_EL2_IRQ + 16 +}; + static VirtBoardInfo machines[] = { { .cpu_model = "cortex-a15", @@ -259,10 +291,10 @@ static void fdt_add_timer_nodes(const VirtBoardInfo *vbi) "arm,armv7-timer"); } qemu_fdt_setprop_cells(vbi->fdt, "/timer", "interrupts", - GIC_FDT_IRQ_TYPE_PPI, 13, irqflags, - GIC_FDT_IRQ_TYPE_PPI, 14, irqflags, - GIC_FDT_IRQ_TYPE_PPI, 11, irqflags, - GIC_FDT_IRQ_TYPE_PPI, 10, irqflags); + GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, + GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, + GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, + GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); } static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi) @@ -527,6 +559,14 @@ static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) return board->fdt; } +static void *machvirt_acpi(const struct arm_boot_info *binfo, int *acpi_size) +{ + const VirtBoardInfo *board = (const VirtBoardInfo *)binfo; + + *acpi_size = board->acpi_size; + return board->acpi; +} + static void machvirt_init(MachineState *machine) { qemu_irq pic[NUM_IRQS]; @@ -604,6 +644,10 @@ static void machvirt_init(MachineState *machine) */ create_virtio_devices(vbi, pic); + /* Build ACPI tables and form the binary blob */ + acpi_build_tables(vbi->smp_cpus, &gtdt_info, &madt_info, &dsdt_info); + vbi->acpi_size = acpi_make_blob(&vbi->acpi); + vbi->bootinfo.ram_size = machine->ram_size; vbi->bootinfo.kernel_filename = machine->kernel_filename; vbi->bootinfo.kernel_cmdline = machine->kernel_cmdline; @@ -612,6 +656,8 @@ static void machvirt_init(MachineState *machine) vbi->bootinfo.board_id = -1; vbi->bootinfo.loader_start = vbi->memmap[VIRT_MEM].base; vbi->bootinfo.get_dtb = machvirt_dtb; + vbi->bootinfo.acpi_base_addr = ACPI_BASE_ADDRESS; + vbi->bootinfo.get_acpi = machvirt_acpi; arm_load_kernel(ARM_CPU(first_cpu), &vbi->bootinfo); } diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h index cefc9e6..806faaf 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/arm.h @@ -27,6 +27,7 @@ struct arm_boot_info { const char *initrd_filename; const char *dtb_filename; hwaddr loader_start; + hwaddr acpi_base_addr; /* multicore boards that use the default secondary core boot functions * need to put the address of the secondary boot code, the boot reg, * and the GIC address in the next 3 values, respectively. boards that @@ -61,6 +62,7 @@ struct arm_boot_info { * the user it should implement this hook. */ void (*modify_dtb)(const struct arm_boot_info *info, void *fdt); + void *(*get_acpi)(const struct arm_boot_info *info, int *size); /* Used internally by arm_boot.c */ int is_linux; hwaddr initrd_start; -- 1.9.1

10 years, 6 months

1
0
0 0

[RFC PATCH 4/7] hw/arm/virt-acpi: Generate FACS and FADT, update ACPI headers

by Alexander Spyridakis

FADT points to FACS and DSDT and additionally, in the case of mach virt, it is also used to set the Hardware Reduced bit and enable PSCI SMP booting through HVC. For FACS the table is created as a mockup, as with the Hardware Reduced bit set it will not be used. Update the header definitions for FADT and FACS taking into account the new additions of ACPI v5.1 in `include/hw/acpi/acpi-defs.h` Signed-off-by: Alexander Spyridakis <a.spyridakis(a)virtualopensystems.com> Signed-off-by: Alvise Rigo <a.rigo(a)virtualopensystems.com> --- hw/arm/virt-acpi.c | 41 +++++++++++-- include/hw/acpi/acpi-defs.h | 141 ++++++++++++++++++++++++++++++-------------- 2 files changed, 134 insertions(+), 48 deletions(-) diff --git a/hw/arm/virt-acpi.c b/hw/arm/virt-acpi.c index 0d7bb99..aca0434 100644 --- a/hw/arm/virt-acpi.c +++ b/hw/arm/virt-acpi.c @@ -133,14 +133,47 @@ static void acpi_create_gtdt(const struct acpi_gtdt_info *irqs) static void acpi_create_fadt(void) { - acpi_table[FADT] = NULL; - acpi_size[FADT] = 0; + AcpiFacpDescriptorRev5_1 *fadt; + hwaddr facs_offset; + int i; + + fadt = g_malloc0(sizeof(*fadt)); + acpi_fill_common_header_data(fadt, "FACP", 5, sizeof(*fadt)); + + /* Hardware Reduced = 1 and use PSCI 0.2+ and with HVC */ + fadt->flags = cpu_to_le32(1 << ACPI_FADT_F_HW_REDUCED_ACPI); + fadt->arm_boot_flags = cpu_to_le16((1 << ACPI_FADT_ARM_USE_PSCI_G_0_2) | + (1 << ACPI_FADT_ARM_PSCI_USE_HVC)); + + /* ACPI v5.1 (fadt->revision.fadt->minor_revision) */ + fadt->minor_revision = 0x1; + + acpi_size[FADT] = fadt->length; + + /* Calculate FACS and DSDT table offsets */ + for (i = RSDP, facs_offset = 0; i < FACS; ++i) { + facs_offset += acpi_size[i]; + } + fadt->Xfacs = cpu_to_le64(ACPI_BASE_ADDRESS + facs_offset); + fadt->Xdsdt = cpu_to_le64(fadt->Xfacs + acpi_size[FACS]); + + acpi_do_checksum(fadt, fadt->length, &fadt->checksum); + + acpi_table[FADT] = (void *)fadt; } static void acpi_create_facs(void) { - acpi_table[FACS] = NULL; - acpi_size[FACS] = 0; + AcpiFacsDescriptorRev5_1 *facs; + + facs = g_malloc0(sizeof(*facs)); + + memcpy(&facs->signature, "FACS", sizeof(facs->signature)); + facs->length = cpu_to_le32(sizeof(*facs)); + facs->version = 0x02; + + acpi_table[FACS] = (void *)facs; + acpi_size[FACS] = facs->length; } static void acpi_create_dsdt(int smp_cpus, const struct acpi_dsdt_info *info) diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index 779f872..ebbd2d0 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -97,46 +97,49 @@ struct AcpiXsdtDescriptor { typedef struct AcpiXsdtDescriptor AcpiXsdtDescriptor; /* - * ACPI 1.0 Fixed ACPI Description Table (FADT) + * ACPI Fixed ACPI Description Table (FADT) */ +#define ACPI_FADT_COMMON_DEF /* FADT common definition */ \ + ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \ + uint32_t firmware_ctrl; /* Physical address of FACS */ \ + uint32_t dsdt; /* Physical address of DSDT */ \ + uint8_t model; /* System Interrupt Model */ \ + uint8_t reserved1; /* Reserved */ \ + uint16_t sci_int; /* System vector of SCI interrupt */ \ + uint32_t smi_cmd; /* Port address of SMI command port */ \ + uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */ \ + uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */ \ + uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */ \ + uint8_t reserved2; /* Reserved - must be zero */ \ + uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */ \ + uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */ \ + uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */ \ + uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */ \ + uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */ \ + uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */ \ + uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */ \ + uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */ \ + uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */ \ + uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */ \ + uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */ \ + uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */ \ + uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */ \ + uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */ \ + uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */ \ + uint8_t reserved3; /* Reserved */ \ + uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */ \ + uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */ \ + uint16_t flush_size; /* Size of area read to flush caches */ \ + uint16_t flush_stride; /* Stride used in flushing caches */ \ + uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */ \ + uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */ \ + uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */ \ + uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */ \ + uint8_t century; /* Index to century in RTC CMOS RAM */ + struct AcpiFadtDescriptorRev1 { - ACPI_TABLE_HEADER_DEF /* ACPI common table header */ - uint32_t firmware_ctrl; /* Physical address of FACS */ - uint32_t dsdt; /* Physical address of DSDT */ - uint8_t model; /* System Interrupt Model */ - uint8_t reserved1; /* Reserved */ - uint16_t sci_int; /* System vector of SCI interrupt */ - uint32_t smi_cmd; /* Port address of SMI command port */ - uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */ - uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */ - uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */ - uint8_t reserved2; /* Reserved - must be zero */ - uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */ - uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */ - uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */ - uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */ - uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */ - uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */ - uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */ - uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */ - uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */ - uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */ - uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */ - uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */ - uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */ - uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */ - uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */ - uint8_t reserved3; /* Reserved */ - uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */ - uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */ - uint16_t flush_size; /* Size of area read to flush caches */ - uint16_t flush_stride; /* Stride used in flushing caches */ - uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */ - uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */ - uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */ - uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */ - uint8_t century; /* Index to century in RTC CMOS RAM */ + ACPI_FADT_COMMON_DEF uint8_t reserved4; /* Reserved */ uint8_t reserved4a; /* Reserved */ uint8_t reserved4b; /* Reserved */ @@ -144,6 +147,43 @@ struct AcpiFadtDescriptorRev1 } QEMU_PACKED; typedef struct AcpiFadtDescriptorRev1 AcpiFadtDescriptorRev1; +struct acpi_generic_address { + uint8_t space_id; /* Address space where struct or register exists */ + uint8_t bit_width; /* Size in bits of given register */ + uint8_t bit_offset; /* Bit offset within the register */ + uint8_t access_width; /* Minimum Access size (ACPI 3.0) */ + uint64_t address; /* 64-bit address of struct or register */ +} QEMU_PACKED; + +struct AcpiFacpDescriptorRev5_1 { + ACPI_FADT_COMMON_DEF + uint16_t boot_flags; /* IA-PC Boot Architecture Flags (see below for individual flags) */ + uint8_t reserved; /* Reserved, must be zero */ + uint32_t flags; /* Miscellaneous flag bits (see below for individual flags) */ + struct acpi_generic_address reset_register; /* 64-bit address of the Reset register */ + uint8_t reset_value; /* Value to write to the reset_register port to reset the system */ + uint16_t arm_boot_flags; /* ARM-Specific Boot Flags (see below for individual flags) (ACPI 5.1) */ + uint8_t minor_revision; /* FADT Minor Revision (ACPI 5.1) */ + uint64_t Xfacs; /* 64-bit physical address of FACS */ + uint64_t Xdsdt; /* 64-bit physical address of DSDT */ + struct acpi_generic_address xpm1a_event_block; /* 64-bit Extended Power Mgt 1a Event Reg Blk address */ + struct acpi_generic_address xpm1b_event_block; /* 64-bit Extended Power Mgt 1b Event Reg Blk address */ + struct acpi_generic_address xpm1a_control_block; /* 64-bit Extended Power Mgt 1a Control Reg Blk address */ + struct acpi_generic_address xpm1b_control_block; /* 64-bit Extended Power Mgt 1b Control Reg Blk address */ + struct acpi_generic_address xpm2_control_block; /* 64-bit Extended Power Mgt 2 Control Reg Blk address */ + struct acpi_generic_address xpm_timer_block; /* 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */ + struct acpi_generic_address xgpe0_block; /* 64-bit Extended General Purpose Event 0 Reg Blk address */ + struct acpi_generic_address xgpe1_block; /* 64-bit Extended General Purpose Event 1 Reg Blk address */ + struct acpi_generic_address sleep_control; /* 64-bit Sleep Control register (ACPI 5.0) */ + struct acpi_generic_address sleep_status; /* 64-bit Sleep Status register (ACPI 5.0) */ +} QEMU_PACKED; +typedef struct AcpiFacpDescriptorRev5_1 AcpiFacpDescriptorRev5_1; + +enum { + ACPI_FADT_ARM_USE_PSCI_G_0_2, + ACPI_FADT_ARM_PSCI_USE_HVC, +}; + /* * ACPI 1.0 Root System Description Table (RSDT) */ @@ -156,20 +196,33 @@ struct AcpiRsdtDescriptorRev1 typedef struct AcpiRsdtDescriptorRev1 AcpiRsdtDescriptorRev1; /* - * ACPI 1.0 Firmware ACPI Control Structure (FACS) + * ACPI Firmware ACPI Control Structure (FACS) */ +#define ACPI_FACS_COMMON_DEF /* FACS common definition */ \ + uint32_t signature; /* ACPI Signature */ \ + uint32_t length; /* Length of structure, in bytes */ \ + uint32_t hardware_signature; /* Hardware configuration signature */ \ + uint32_t firmware_waking_vector; /* ACPI OS waking vector */ \ + uint32_t global_lock; /* Global Lock */ \ + uint32_t flags; + struct AcpiFacsDescriptorRev1 { - uint32_t signature; /* ACPI Signature */ - uint32_t length; /* Length of structure, in bytes */ - uint32_t hardware_signature; /* Hardware configuration signature */ - uint32_t firmware_waking_vector; /* ACPI OS waking vector */ - uint32_t global_lock; /* Global Lock */ - uint32_t flags; + ACPI_FACS_COMMON_DEF uint8_t resverved3 [40]; /* Reserved - must be zero */ } QEMU_PACKED; typedef struct AcpiFacsDescriptorRev1 AcpiFacsDescriptorRev1; +struct AcpiFacsDescriptorRev5_1 { + ACPI_FACS_COMMON_DEF + uint64_t xfirmware_waking_vector; /* 64-bit version of the Firmware Waking Vector (ACPI 2.0+) */ + uint8_t version; /* Version of this table (ACPI 2.0+) */ + uint8_t reserved [3]; /* Reserved, must be zero */ + uint32_t ospm_flags; /* Flags to be set by OSPM (ACPI 4.0) */ + uint8_t reserved1 [24]; /* Reserved, must be zero */ +} QEMU_PACKED; +typedef struct AcpiFacsDescriptorRev5_1 AcpiFacsDescriptorRev5_1; + /* * Differentiated System Description Table (DSDT) */ -- 1.9.1

10 years, 6 months

1
0
0 0

[RFC PATCH v2 0/3] CPPC as PID backend

by Ashwin Chaugule

This patchset introduces CPPC(Collaborative Processor Performance Control) as a backend to the PID governor. The PID governor from intel_pstate.c maps cleanly onto some CPPC interfaces. e.g. The CPU performance requests are made on a continuous scale as against discrete pstate levels. The CPU performance feedback over an interval is gauged using platform specific counters which are also described by CPPC. Although CPPC describes several other registers to provide more hints to the platform, Linux as of today does not have the infrastructure to make use of those registers. Some of the CPPC specific information could be made available from the scheduler as part of the CPUfreq and Scheduler intergration work. Until then PID can be used as the front end for CPPC. This implementation was tested using a Thinkpad X240 Laptop which seemed to have CPPC and PCC tables in its ACPI firmware. However, it seems as though some addresses pointed to by the tables do not exist. This patchset also shows the hacks that were made in order to work around those limitations and test the control flow. This patchset builds on top of the PCC driver which is being reviewed separately[3]. Changes since V1: - Create a new driver based on Dirks suggestion. - Fold in CPPC backend hooks into main driver. Changes since V0: [1] - Split intel_pstate.c into a generic PID governor and platform specific backend. - Add CPPC accessors as PID backend. CPPC: ==== CPPC (Collaborative Processor Performance Control) is a new way to control CPU performance using an abstract continous scale as against a discretized P-state scale which is tied to CPU frequency only. It is defined in the ACPI 5.0+ spec. In brief, the basic operation involves: - OS makes a CPU performance request. (Can provide min and max tolerable bounds) - Platform (such as BMC) is free to optimize request within requested bounds depending on power/thermal budgets etc. - Platform conveys its decision back to OS The communication between OS and platform occurs through another medium called (PCC) Platform communication Channel. This is a generic mailbox like mechanism which includes doorbell semantics to indicate register updates. The PCC driver is being discussed in a separate patchset [3] and is not included here, since CPPC is only one client of PCC. Finer details about the PCC and CPPC spec are available in the latest ACPI 5.1 specification.[2] [1] - http://lwn.net/Articles/608715/ [2] - http://www.uefi.org/sites/default/files/resources/ACPI_5_1release.pdf [3] - http://comments.gmane.org/gmane.linux.acpi.devel/71171 Ashwin Chaugule (3): PCC HACKS: Update PCC comm region with MSR data CPPC as a PID controller backend CPPC HACKS drivers/cpufreq/Kconfig | 12 + drivers/cpufreq/Makefile | 1 + drivers/cpufreq/acpi_pid.c | 1085 ++++++++++++++++++++++++++++++++++++++++++++ drivers/mailbox/pcc.c | 125 ++++- 4 files changed, 1207 insertions(+), 16 deletions(-) create mode 100644 drivers/cpufreq/acpi_pid.c -- 1.9.1

10 years, 6 months

2
8
0 0

leg-kernel tag leg-20141013.0 released

by Graeme Gregory

The leg-kernel release has been made and tagged as leg-201401013.0 This is based on mainline kernel v3.17 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: http://git.linaro.org/leg/acpi/leg-kernel.git/commit/a0f69f9cba4d2fa5007b08… Notes :-

10 years, 7 months

1
0
0 0

[PATCH v8 0/2] PCC: Platform Communication Channel

by Ashwin Chaugule

Changes since V7: - Added timeout to tx method in case the remote dies. - Restructured usage of acpi_status. Had inverted logic previously. Changes since V6: - Cosmetic changes based on Lv's suggestions Changes since V5: - Optimize loop that matches channel request. - Use platform_create_bundle. - Replace ioread/writes. - Remove redundant code and headers. - Restructure common mailbox macros. - Reformat PCC cmd parsing. Changes since V4: - Folded PCC Mailbox helpers into pcc.c Changes since V3: - Added PCC helper functions to work around "struct device" limitations. - PCC driver changes to work with PCC specific Mailbox helpers. Changes since V2: - Rebased on top of git://git.linaro.org/landing-teams/working/fujitsu/integration.git branch mailbox-for-3.17 - Added PCC API to mailbox framework as per Arnd's suggestion to allow usage without ACPI. Changes since V1: - Integration with Mailbox framework - https://lkml.org/lkml/2014/5/15/49 This patchset adds support for the PCC (Platform Communication Channel) interface as described in the current ACPI 5.0 spec. See Section 14 of the ACPI spec - http://acpi.info/DOWNLOADS/ACPI_5_Errata%20A.pdf for more details on how PCC works. In brief PCC is a generic means for PCC clients, to talk to the firmware. The PCC register space is typically memory mapped IO and uses a doorbell mechanism to communicate synchronously from the OS to the firmware. The PCC driver is completely agnostic to the protocol implemented by the PCC clients. It only implements the enumeration of PCC channels and the low level transport mechanism and leaves the rest to the PCC clients. The PCC is meant to be useable in the future by clients such as CPPC (Collaborative Processor Performance Control), RAS (Reliability, Availability and Serviceability) and MPST (Memory Power State Tables) and possibly others. Ashwin Chaugule (2): Mailbox: Add support for Platform Communication Channel PCC test drivers/mailbox/Kconfig | 12 ++ drivers/mailbox/Makefile | 2 + drivers/mailbox/mailbox.c | 4 +- drivers/mailbox/mailbox.h | 16 +++ drivers/mailbox/pcc-test.c | 204 +++++++++++++++++++++++++++++++ drivers/mailbox/pcc.c | 292 +++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 527 insertions(+), 3 deletions(-) create mode 100644 drivers/mailbox/mailbox.h create mode 100644 drivers/mailbox/pcc-test.c create mode 100644 drivers/mailbox/pcc.c -- 1.9.1

10 years, 7 months

3
6
0 0

[RFC 0/2] Enable KVM on ARM when booting with ACPI

by Alexander Spyridakis

KVM on ARM relies on device tree information, which is not available when booting with ACPI. In the case of VGIC we need to extract the relevant data from the MADT table and probe it accordingly. For the architected timer, we need to expose the correct interrupt line to KVM from the GTDT table. This series has been tested on the Foundation Model 0.8 build 5206 and is based on the "Introduce ACPI for ARM64 based on ACPI 5.1" patch series from Hanjun Guo. Alexander Spyridakis (2): ARM64 / ACPI: VGIC probe support with ACPI ARM64 / ACPI: Point KVM to the virtual timer interrupt when booting with ACPI include/kvm/arm_vgic.h | 6 ++++ virt/kvm/arm/arch_timer.c | 48 ++++++++++++++++++------- virt/kvm/arm/vgic-v2.c | 91 +++++++++++++++++++++++++++++++++++++++++++++++ virt/kvm/arm/vgic.c | 27 ++++++++------ 4 files changed, 150 insertions(+), 22 deletions(-) -- 1.9.1

10 years, 7 months

5
12
0 0

leg-kernel tag leg-20141002.0 released

by Graeme Gregory

The leg-kernel release has been made and tagged as leg-201401002.0 This is based on mainline kernel v3.17-rc7 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: https://git.linaro.org/leg/acpi/leg-kernel.git/commit/0ff59633762361c2dcc93… Notes :-

10 years, 7 months

1
0
0 0

[PATCH v7 0/2] PCC: Platform Communication Channel

by Ashwin Chaugule

Changes since V6: - Cosmetic changes based on Lv's suggestions Changes since V5: - Optimize loop that matches channel request. - Use platform_create_bundle. - Replace ioread/writes. - Remove redundant code and headers. - Restructure common mailbox macros. - Reformat PCC cmd parsing. Changes since V4: - Folded PCC Mailbox helpers into pcc.c Changes since V3: - Added PCC helper functions to work around "struct device" limitations. - PCC driver changes to work with PCC specific Mailbox helpers. Changes since V2: - Rebased on top of git://git.linaro.org/landing-teams/working/fujitsu/integration.git branch mailbox-for-3.17 - Added PCC API to mailbox framework as per Arnd's suggestion to allow usage without ACPI. Changes since V1: - Integration with Mailbox framework - https://lkml.org/lkml/2014/5/15/49 This patchset adds support for the PCC (Platform Communication Channel) interface as described in the current ACPI 5.0 spec. See Section 14 of the ACPI spec - http://acpi.info/DOWNLOADS/ACPI_5_Errata%20A.pdf for more details on how PCC works. In brief PCC is a generic means for PCC clients, to talk to the firmware. The PCC register space is typically memory mapped IO and uses a doorbell mechanism to communicate synchronously from the OS to the firmware. The PCC driver is completely agnostic to the protocol implemented by the PCC clients. It only implements the enumeration of PCC channels and the low level transport mechanism and leaves the rest to the PCC clients. The PCC is meant to be useable in the future by clients such as CPPC (Collaborative Processor Performance Control), RAS (Reliability, Availability and Serviceability) and MPST (Memory Power State Tables) and possibly others. Ashwin Chaugule (2): Mailbox: Add support for Platform Communication Channel PCC test drivers/mailbox/Kconfig | 12 ++ drivers/mailbox/Makefile | 2 + drivers/mailbox/mailbox.c | 4 +- drivers/mailbox/mailbox.h | 16 +++ drivers/mailbox/pcc-test.c | 203 ++++++++++++++++++++++++++++++++ drivers/mailbox/pcc.c | 282 +++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 516 insertions(+), 3 deletions(-) create mode 100644 drivers/mailbox/mailbox.h create mode 100644 drivers/mailbox/pcc-test.c create mode 100644 drivers/mailbox/pcc.c -- 1.9.1

10 years, 7 months

3
13
0 0

[PATCH v4 00/18] Introduce ACPI for ARM64 based on ACPI 5.1

by Hanjun Guo

ACPI 5.1 has been released and now be freely available for download [1]. It fixed some major gaps to run ACPI on ARM, this patch just follow the ACPI 5.1 spec and prepare the code to run ACPI on ARM64. ACPI 5.1 has some major changes for the following tables and method which are essential for ARM platforms: 1) MADT table updates. 2) FADT updates for PSCI 3) GTDT This patch set is the ARM64 ACPI core patches covered MADT, FADT and GTDT, platform board specific drivers are not covered by this patch set, but we provided drivers for Juno to boot with ACPI only for review purpose. We first introduce acpi.c and its related head file which are needed by ACPI core, and then get RSDP to extract all the ACPI boot-time tables. When all the boot-time tables (FADT, MADT, GTDT) are ready, then parse them to init the sytem when booted. Specifically, a) we use FADT to init PSCI and use PSCI to boot SMP; b) Use MADT for GIC init and SMP init; c) GTDT for arch timer init. This patch set is based on 3.17-rc4 and was tested by Graeme on Juno and FVP base model boot with ACPI only OK, if you want to test them, you can pull from acpi-5.1-v4 branch in leg/acpi repo: git://git.linaro.org/leg/acpi/acpi.git Updates since v3: - Compile out sleep.c on ARM64 when ACPI enabled - refactor the GIC init code to address the comments from Marc and Arnd - refactor the SMP init code to fix some logic problem when PSCI is not present, also address some of Grant and Lorenzo's comments - reorder the patch series and move ACPI table changes to the front of patch set - rebase on top of 3.17-rc4 Updates since v2: - Refactor the code to make SMP/PSCI init with less sperated init path by Tomasz - make ACPI depend on EXPERT - Address lots of comments from Catalin, Sudeep, Geoff - Add Juno device ACPI driver patches for review Updates since v1: - Set ACPI default off on ARM64 suggested by Olof; - Rebase the patch set on top of linux-next branch/linux-pm tree which includes the ACPICA for full ACPI 5.1 support. - Update the document as suggested; - Adress lots of comments from Mark, Sudeep, Randy, Naresh, Olof, Geoff and more... [1]: http://www.uefi.org/sites/default/files/resources/ACPI_5_1release.pdf Al Stone (3): ARM64 / ACPI: Get RSDP and ACPI boot-time tables ARM64 / ACPI: Introduce early_param for "acpi" ARM64 / ACPI: Select ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled on ARM64 Ashwin Chaugule (1): ACPI / table: Add new function to get table entries Graeme Gregory (4): ARM64 / ACPI: Introduce sleep-arm.c ARM64 / ACPI: If we chose to boot from acpi then disable FDT ARM64 / ACPI: Enable ARM64 in Kconfig Documentation: ACPI for ARM64 Hanjun Guo (8): ARM64: Move the init of cpu_logical_map(0) before unflatten_device_tree() ARM64 / ACPI: Make PCI optional for ACPI on ARM64 ARM64 / ACPI: Parse FADT table to get PSCI flags for PSCI init ACPI / table: Print GIC information when MADT is parsed ARM64 / ACPI: Parse MADT for SMP initialization ACPI / processor: Make it possible to get CPU hardware ID via GICC ARM64 / ACPI: Introduce ACPI_IRQ_MODEL_GIC and register device's gsi ARM64 / ACPI: Parse GTDT to initialize arch timer Tomasz Nowicki (2): ACPI / table: Count matched and successfully parsed entries without specifying max entries ARM64 / ACPI: Add GICv2 specific ACPI boot support Documentation/arm64/arm-acpi.txt | 218 +++++++++++++++++++++ Documentation/kernel-parameters.txt | 3 +- arch/arm64/Kconfig | 3 + arch/arm64/include/asm/acenv.h | 18 ++ arch/arm64/include/asm/acpi.h | 96 ++++++++++ arch/arm64/include/asm/cpu_ops.h | 1 + arch/arm64/include/asm/pci.h | 11 ++ arch/arm64/include/asm/psci.h | 3 +- arch/arm64/include/asm/smp.h | 5 +- arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/acpi.c | 351 ++++++++++++++++++++++++++++++++++ arch/arm64/kernel/cpu_ops.c | 4 +- arch/arm64/kernel/psci.c | 78 +++++--- arch/arm64/kernel/setup.c | 23 ++- arch/arm64/kernel/smp.c | 2 +- arch/arm64/kernel/time.c | 7 + drivers/acpi/Kconfig | 6 +- drivers/acpi/Makefile | 6 +- drivers/acpi/bus.c | 3 + drivers/acpi/internal.h | 5 + drivers/acpi/processor_core.c | 37 ++++ drivers/acpi/sleep-arm.c | 28 +++ drivers/acpi/tables.c | 115 +++++++++-- drivers/clocksource/arm_arch_timer.c | 117 ++++++++++-- drivers/irqchip/irq-gic.c | 106 ++++++++++ drivers/irqchip/irqchip.c | 3 + include/linux/acpi.h | 5 + include/linux/clocksource.h | 6 + include/linux/irqchip/arm-gic-acpi.h | 31 +++ include/linux/pci.h | 37 +++- 30 files changed, 1238 insertions(+), 91 deletions(-) create mode 100644 Documentation/arm64/arm-acpi.txt create mode 100644 arch/arm64/include/asm/acenv.h create mode 100644 arch/arm64/include/asm/acpi.h create mode 100644 arch/arm64/include/asm/pci.h create mode 100644 arch/arm64/kernel/acpi.c create mode 100644 drivers/acpi/sleep-arm.c create mode 100644 include/linux/irqchip/arm-gic-acpi.h -- 1.7.9.5

10 years, 7 months

14
82
0 0

[PATCH v3 00/17] Introduce ACPI for ARM64 based on ACPI 5.1

by Hanjun Guo

ACPI 5.1 has been released and now be freely available for download [1]. It fixed some major gaps to run ACPI on ARM, this patch just follow the ACPI 5.1 spec and prepare the code to run ACPI on ARM64. ACPI 5.1 has some major changes for the following tables and method which are essential for ARM platforms: 1) MADT table updates. 2) FADT updates for PSCI 3) GTDT This patch set is the ARM64 ACPI core patches covered MADT, FADT and GTDT, platform board specific drivers are not covered by this patch set, but we provide drivers for Juno to boot with ACPI only in the follwing patch set for review purpose. We first introduce acpi.c and its related head file which are needed by ACPI core, and then get RSDP to extract all the ACPI boot-time tables. When all the boot-time tables (FADT, MADT, GTDT) are ready, then parse them to init the sytem when booted. Specifically, a) we use FADT to init PSCI and use PSCI to boot SMP; b) Use MADT for GIC init and SMP init; c) GTDT for arch timer init. This patch set is based on 3.17-rc2 and was tested by Graeme on Juno and FVP base model boot with ACPI only OK, if you want to test them, you can pull from acpi-5.1-v3 branch in leg/acpi repo: git://git.linaro.org/leg/acpi/acpi.git Updates since v2: - Refactor the code to make SMP/PSCI init with less sperated init path by Tomasz - make ACPI depend on EXPERT - Address lots of comments from Catalin, Sudeep, Geoff - Add Juno device ACPI driver patches for review Updates since v1: - Set ACPI default off on ARM64 suggested by Olof; - Rebase the patch set on top of linux-next branch/linux-pm tree which includes the ACPICA for full ACPI 5.1 support. - Update the document as suggested; - Adress lots of comments from Mark, Sudeep, Randy, Naresh, Olof, Geoff and more... [1]: http://www.uefi.org/sites/default/files/resources/ACPI_5_1release.pdf Al Stone (3): ARM64 / ACPI: Get RSDP and ACPI boot-time tables ARM64 / ACPI: Introduce early_param for "acpi" ARM64 / ACPI: Select ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled on ARM64 Ashwin Chaugule (1): ACPI / table: Add new function to get table entries Graeme Gregory (4): ARM64 / ACPI: Introduce lowlevel suspend function ARM64 / ACPI: If we chose to boot from acpi then disable FDT ARM64 / ACPI: Enable ARM64 in Kconfig Documentation: ACPI for ARM64 Hanjun Guo (8): ARM64: Move the init of cpu_logical_map(0) before unflatten_device_tree() ARM64 / ACPI: Make PCI optional for ACPI on ARM64 ARM64 / ACPI: Parse FADT table to get PSCI flags for PSCI init ACPI / table: Print GIC information when MADT is parsed ARM64 / ACPI: Parse MADT for SMP initialization ACPI / processor: Make it possible to get CPU hardware ID via GICC ARM64 / ACPI: Introduce ACPI_IRQ_MODEL_GIC and register device's gsi ARM64 / ACPI: Parse GTDT to initialize arch timer Tomasz Nowicki (1): ARM64 / ACPI: Add GICv2 specific ACPI boot support Documentation/arm64/arm-acpi.txt | 218 +++++++++++++++++++++ Documentation/kernel-parameters.txt | 3 +- arch/arm64/Kconfig | 3 + arch/arm64/include/asm/acenv.h | 18 ++ arch/arm64/include/asm/acpi.h | 108 ++++++++++ arch/arm64/include/asm/cpu_ops.h | 1 + arch/arm64/include/asm/pci.h | 11 ++ arch/arm64/include/asm/psci.h | 3 +- arch/arm64/include/asm/smp.h | 5 +- arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/acpi.c | 359 ++++++++++++++++++++++++++++++++++ arch/arm64/kernel/cpu_ops.c | 4 +- arch/arm64/kernel/irq.c | 5 + arch/arm64/kernel/psci.c | 78 +++++--- arch/arm64/kernel/setup.c | 23 ++- arch/arm64/kernel/smp.c | 2 +- arch/arm64/kernel/time.c | 7 + drivers/acpi/Kconfig | 6 +- drivers/acpi/Makefile | 2 +- drivers/acpi/bus.c | 3 + drivers/acpi/internal.h | 5 + drivers/acpi/processor_core.c | 37 ++++ drivers/acpi/tables.c | 113 +++++++++-- drivers/clocksource/arm_arch_timer.c | 117 +++++++++-- drivers/irqchip/irq-gic.c | 114 +++++++++++ include/linux/acpi.h | 5 + include/linux/clocksource.h | 6 + include/linux/irqchip/arm-gic-acpi.h | 33 ++++ include/linux/pci.h | 37 +++- 29 files changed, 1237 insertions(+), 90 deletions(-) create mode 100644 Documentation/arm64/arm-acpi.txt create mode 100644 arch/arm64/include/asm/acenv.h create mode 100644 arch/arm64/include/asm/acpi.h create mode 100644 arch/arm64/include/asm/pci.h create mode 100644 arch/arm64/kernel/acpi.c create mode 100644 include/linux/irqchip/arm-gic-acpi.h -- 1.7.9.5

10 years, 7 months

17
86
0 0

[RFC PATCH for Juno 0/2] Drivers for Juno to boot from ACPI

by Hanjun Guo

This patch set is example of the sort of driver changes needed to boot Juno using ACPI tables, which using the ACPI tables devloped for MS Windows and published by ARM [1]. For the smsc911x driver, it is based on the following ASL fragment which is part of DSDT for Juno: // LAN9118 Ethernet // Device(ETH0) { Name(_HID, "ARMH9118") Name(_UID, Zero) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0x1A000000, 0x1000) Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 192 } }) } UART driver is just for review purpose, ARM is working on a more functional UART driver that does not poll to transmit. But it shows how to initialise SBSA compatible UART without clock definitions in DSDT. You also can refer to the boot log from [2]. [1]: https://github.com/ARM-software/edk2/tree/juno-acpi/ArmPlatformPkg/ArmJunoP… [2]: http://www.xora.org.uk/2014/08/29/juno-booting-from-acpi-tables/ Graeme Gregory (2): net: smsc911x add support for probing from ACPI tty: SBSA compatible UART drivers/net/ethernet/smsc/smsc911x.c | 38 ++++ drivers/tty/Kconfig | 6 + drivers/tty/Makefile | 1 + drivers/tty/sbsauart.c | 328 ++++++++++++++++++++++++++++++++++ 4 files changed, 373 insertions(+) create mode 100644 drivers/tty/sbsauart.c -- 1.7.9.5

10 years, 7 months

11
31
0 0

[RFC v1 0/6] CPPC as a PID backend

by Ashwin Chaugule

This patchset introduces CPPC(Collaborative Processor Performance Control) as a backend to the PID governor. The PID governor from intel_pstate.c maps cleanly onto some CPPC interfaces. e.g. The CPU performance requests are made on a continuous scale as against discrete pstate levels. The CPU performance feedback over an interval is gauged using platform specific counters which are also described by CPPC. Although CPPC describes several other registers to provide more hints to the platform, Linux as of today does not have the infrastructure to make use of those registers. Some of the CPPC specific information could be made available from the scheduler as part of the CPUfreq and Scheduler intergration work. Until then PID can be used as the front end for CPPC. Beyond code restructuring and renaming, this patchset does not change the logic from the intel_pstate.c driver. Kernel compilation times were compared with the original intel_pstate.c, intel backend(intel_pid_ctrl.c) and the CPPC backend and no significant overheads were noticed. Testing was performed on a Thinkpad X240 laptop. PID_CTRL + INTEL_PSTATE: ======================= real 5m37.742s user 18m42.575s sys 1m0.521s PID_CTRL + CPPC_PID_CTRL: ======================== real 5m48.321s user 18m24.487s sys 0m59.327s ORIGINAL INTEL_PSTATE: ====================== real 5m40.642s user 18m37.411s sys 1m0.185s The complete patchset including the PCC hacks used for testing is available in [4]. Changes since V0: [1] - Split intel_pstate.c into a generic PID governor and platform specific backend. - Add CPPC accessors as PID backend. CPPC: ==== CPPC (Collaborative Processor Performance Control) is a new way to control CPU performance using an abstract continous scale as against a discretized P-state scale which is tied to CPU frequency only. It is defined in the ACPI 5.0+ spec. In brief, the basic operation involves: - OS makes a CPU performance request. (Can provide min and max tolerable bounds) - Platform (such as BMC) is free to optimize request within requested bounds depending on power/thermal budgets etc. - Platform conveys its decision back to OS The communication between OS and platform occurs through another medium called (PCC) Platform communication Channel. This is a generic mailbox like mechanism which includes doorbell semantics to indicate register updates. The PCC driver is being discussed in a separate patchset [3] and is not included here, since CPPC is only one client of PCC. Finer details about the PCC and CPPC spec are available in the latest ACPI 5.1 specification.[2] [1] - http://lwn.net/Articles/608715/ [2] - http://www.uefi.org/sites/default/files/resources/ACPI_5_1release.pdf [3] - http://comments.gmane.org/gmane.linux.acpi.devel/70299 [4] - http://git.linaro.org/people/ashwin.chaugule/leg-kernel.git/shortlog/refs/h… Ashwin Chaugule (6): PID Controller governor PID: Move Turbo detection into backend driver PID: Move Baytrail specific accessors into backend driver PID: Add new function pointers to read multiple registers PID: Rename counters to make them more generic PID: Add CPPC (Collaborative Processor Performance) backend driver Documentation/cpu-freq/intel-pstate.txt | 43 -- Documentation/cpu-freq/pid_ctrl.txt | 41 ++ drivers/cpufreq/Kconfig | 19 + drivers/cpufreq/Kconfig.x86 | 2 +- drivers/cpufreq/Makefile | 4 +- drivers/cpufreq/cppc_pid_ctrl.c | 406 +++++++++++++ drivers/cpufreq/intel_pid_ctrl.c | 408 +++++++++++++ drivers/cpufreq/intel_pstate.c | 1012 ------------------------------- drivers/cpufreq/pid_ctrl.c | 615 +++++++++++++++++++ drivers/cpufreq/pid_ctrl.h | 113 ++++ 10 files changed, 1606 insertions(+), 1057 deletions(-) delete mode 100644 Documentation/cpu-freq/intel-pstate.txt create mode 100644 Documentation/cpu-freq/pid_ctrl.txt create mode 100644 drivers/cpufreq/cppc_pid_ctrl.c create mode 100644 drivers/cpufreq/intel_pid_ctrl.c delete mode 100644 drivers/cpufreq/intel_pstate.c create mode 100644 drivers/cpufreq/pid_ctrl.c create mode 100644 drivers/cpufreq/pid_ctrl.h -- 1.9.1

10 years, 8 months

2
10
0 0

leg-kernel tag leg-20140908.0 released

by G Gregory

The leg-kernel release has been made and tagged as leg-20140908.0 This is based on mainline kernel v3.17-rc4 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: https://git.linaro.org/leg/acpi/leg-kernel.git/commit/99fe5441d3aec97594381… Notes :-

10 years, 8 months

1
0
0 0

[PATCH v6 0/2] PCC: Platform Communication Channel

by Ashwin Chaugule

Changes since V5: - Optimize loop that matches channel request. - Use platform_create_bundle. - Replace ioread/writes. - Remove redundant code and headers. - Restructure common mailbox macros. - Reformat PCC cmd parsing. Changes since V4: - Folded PCC Mailbox helpers into pcc.c Changes since V3: - Added PCC helper functions to work around "struct device" limitations. - PCC driver changes to work with PCC specific Mailbox helpers. Changes since V2: - Rebased on top of git://git.linaro.org/landing-teams/working/fujitsu/integration.git branch mailbox-for-3.17 - Added PCC API to mailbox framework as per Arnd's suggestion to allow usage without ACPI. Changes since V1: - Integration with Mailbox framework - https://lkml.org/lkml/2014/5/15/49 This patchset adds support for the PCC (Platform Communication Channel) interface as described in the current ACPI 5.0 spec. See Section 14 of the ACPI spec - http://acpi.info/DOWNLOADS/ACPI_5_Errata%20A.pdf for more details on how PCC works. In brief PCC is a generic means for PCC clients, to talk to the firmware. The PCC register space is typically memory mapped IO and uses a doorbell mechanism to communicate synchronously from the OS to the firmware. The PCC driver is completely agnostic to the protocol implemented by the PCC clients. It only implements the enumeration of PCC channels and the low level transport mechanism and leaves the rest to the PCC clients. The PCC is meant to be useable in the future by clients such as CPPC (Collaborative Processor Performance Control), RAS (Reliability, Availability and Serviceability) and MPST (Memory Power State Tables) and possibly others. Ashwin Chaugule (2): Mailbox: Add support for Platform Communication Channel PCC test drivers/mailbox/Kconfig | 12 ++ drivers/mailbox/Makefile | 2 + drivers/mailbox/mailbox.c | 4 +- drivers/mailbox/mailbox.h | 16 +++ drivers/mailbox/pcc-test.c | 203 +++++++++++++++++++++++++++++++++ drivers/mailbox/pcc.c | 279 +++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 513 insertions(+), 3 deletions(-) create mode 100644 drivers/mailbox/mailbox.h create mode 100644 drivers/mailbox/pcc-test.c create mode 100644 drivers/mailbox/pcc.c -- 1.9.1

10 years, 8 months

2
7
0 0

[PATCH v5 0/2] PCC: Platform Communication Channel

by Ashwin Chaugule

Changes since V4: - Folded PCC Mailbox helpers into pcc.c Changes since V3: - Added PCC helper functions to work around "struct device" limitations. - PCC driver changes to work with PCC specific Mailbox helpers. Changes since V2: - Rebased on top of git://git.linaro.org/landing-teams/working/fujitsu/integration.git branch mailbox-for-3.17 - Added PCC API to mailbox framework as per Arnd's suggestion to allow usage without ACPI. Changes since V1: - Integration with Mailbox framework - https://lkml.org/lkml/2014/5/15/49 This patchset adds support for the PCC (Platform Communication Channel) interface as described in the current ACPI 5.0 spec. See Section 14 of the ACPI spec - http://acpi.info/DOWNLOADS/ACPI_5_Errata%20A.pdf for more details on how PCC works. In brief PCC is a generic means for PCC clients, to talk to the firmware. The PCC register space is typically memory mapped IO and uses a doorbell mechanism to communicate synchronously from the OS to the firmware. The PCC driver is completely agnostic to the protocol implemented by the PCC clients. It only implements the enumeration of PCC channels and the low level transport mechanism and leaves the rest to the PCC clients. The PCC is meant to be useable in the future by clients such as CPPC (Collaborative Processor Performance Control), RAS (Reliability, Availability and Serviceability) and MPST (Memory Power State Tables) and possibly others. Ashwin Chaugule (2): Mailbox: Add support for Platform Communication Channel PCC test drivers/mailbox/Kconfig | 12 ++ drivers/mailbox/Makefile | 2 + drivers/mailbox/mailbox.c | 4 - drivers/mailbox/pcc-test.c | 207 ++++++++++++++++++++++++++ drivers/mailbox/pcc.c | 297 +++++++++++++++++++++++++++++++++++++ include/linux/mailbox_controller.h | 4 + 6 files changed, 522 insertions(+), 4 deletions(-) create mode 100644 drivers/mailbox/pcc-test.c create mode 100644 drivers/mailbox/pcc.c -- 1.9.1

10 years, 8 months

4
12
0 0

[PATCH v4 0/4] PCC: Platform Communication Channel

by Ashwin Chaugule

Changes since V3: - Added PCC helper functions to work around "struct device" limitations. - PCC driver changes to work with PCC specific Mailbox helpers. Changes since V2: - Rebased on top of git://git.linaro.org/landing-teams/working/fujitsu/integration.git branch mailbox-for-3.17 - Added PCC API to mailbox framework as per Arnd's suggestion to allow usage without ACPI. Changes since V1: - Integration with Mailbox framework - https://lkml.org/lkml/2014/5/15/49 This patchset adds support for the PCC (Platform Communication Channel) interface as described in the current ACPI 5.0 spec. See Section 14 of the ACPI spec - http://acpi.info/DOWNLOADS/ACPI_5_Errata%20A.pdf for more details on how PCC works. In brief PCC is a generic means for PCC clients, to talk to the firmware. The PCC register space is typically memory mapped IO and uses a doorbell mechanism to communicate synchronously from the OS to the firmware. The PCC driver is completely agnostic to the protocol implemented by the PCC clients. It only implements the enumeration of PCC channels and the low level transport mechanism and leaves the rest to the PCC clients. The PCC is meant to be useable in the future by clients such as CPPC (Collaborative Processor Performance Control), RAS (Reliability, Availability and Serviceability) and MPST (Memory Power State Tables) and possibly others. Ashwin Chaugule (4): Mailbox: Prepare to add PCC Mailbox support Mailbox: Add PCC Mailbox Helper functions Mailbox: Add support for Platform Communication Channel PCC test drivers/mailbox/Kconfig | 19 +++ drivers/mailbox/Makefile | 4 + drivers/mailbox/mailbox.c | 10 +- drivers/mailbox/pcc-test.c | 208 +++++++++++++++++++++++++++++++ drivers/mailbox/pcc.c | 245 +++++++++++++++++++++++++++++++++++++ drivers/mailbox/pcc_mailbox.c | 136 ++++++++++++++++++++ include/linux/mailbox_controller.h | 4 + 7 files changed, 619 insertions(+), 7 deletions(-) create mode 100644 drivers/mailbox/pcc-test.c create mode 100644 drivers/mailbox/pcc.c create mode 100644 drivers/mailbox/pcc_mailbox.c -- 1.9.1

10 years, 8 months

2
6
0 0

[PATCH v4 0/4] PCC: Platform Communication Channel

by Ashwin Chaugule

Changes since V3: - Added PCC helper functions to work around "struct device" limitations. - PCC driver changes to work with PCC specific Mailbox helpers. Changes since V2: - Rebased on top of git://git.linaro.org/landing-teams/working/fujitsu/integration.git branch mailbox-for-3.17 - Added PCC API to mailbox framework as per Arnd's suggestion to allow usage without ACPI. Changes since V1: - Integration with Mailbox framework - https://lkml.org/lkml/2014/5/15/49 This patchset adds support for the PCC (Platform Communication Channel) interface as described in the current ACPI 5.0 spec. See Section 14 of the ACPI spec - http://acpi.info/DOWNLOADS/ACPI_5_Errata%20A.pdf for more details on how PCC works. In brief PCC is a generic means for PCC clients, to talk to the firmware. The PCC register space is typically memory mapped IO and uses a doorbell mechanism to communicate synchronously from the OS to the firmware. The PCC driver is completely agnostic to the protocol implemented by the PCC clients. It only implements the enumeration of PCC channels and the low level transport mechanism and leaves the rest to the PCC clients. The PCC is meant to be useable in the future by clients such as CPPC (Collaborative Processor Performance Control), RAS (Reliability, Availability and Serviceability) and MPST (Memory Power State Tables) and possibly others. Ashwin Chaugule (4): Mailbox: Prepare to add PCC Mailbox support Mailbox: Add PCC Mailbox Helper functions Mailbox: Add support for Platform Communication Channel PCC test drivers/mailbox/Kconfig | 19 +++ drivers/mailbox/Makefile | 4 + drivers/mailbox/mailbox.c | 10 +- drivers/mailbox/pcc-test.c | 208 +++++++++++++++++++++++++++++++ drivers/mailbox/pcc.c | 245 +++++++++++++++++++++++++++++++++++++ drivers/mailbox/pcc_mailbox.c | 136 ++++++++++++++++++++ include/linux/mailbox_controller.h | 4 + 7 files changed, 619 insertions(+), 7 deletions(-) create mode 100644 drivers/mailbox/pcc-test.c create mode 100644 drivers/mailbox/pcc.c create mode 100644 drivers/mailbox/pcc_mailbox.c -- 1.9.1

10 years, 8 months

1
0
0 0

[PATCH v3 0/3] PCC: Platform Communication Channel

by Ashwin Chaugule

This patchset adds support for the PCC (Platform Communication Channel) interface as described in the current ACPI 5.0 spec. See Section 14 of the ACPI spec - http://acpi.info/DOWNLOADS/ACPI_5_Errata%20A.pdf for more details on how PCC works. In brief PCC is a generic means for PCC clients, to talk to the firmware. The PCC register space is typically memory mapped IO and uses a doorbell mechanism to communicate synchronously from the OS to the firmware. The PCC driver is completely agnostic to the protocol implemented by the PCC clients. It only implements the enumeration of PCC channels and the low level transport mechanism and leaves the rest to the PCC clients. The PCC is meant to be useable in the future by clients such as CPPC (Collaborative Processor Performance Control), RAS (Reliability, Availability and Serviceability) and MPST (Memory Power State Tables) and possibly others. Changes since V2: - Rebased on top of git://git.linaro.org/landing-teams/working/fujitsu/integration.git branch mailbox-for-3.17 - Added PCC API to mailbox framework as per Arnd's suggestion to allow usage without ACPI. Changes since V1: -Integration with Mailbox framework - https://lkml.org/lkml/2014/5/15/49 Ashwin Chaugule (3): Mailbox: Add support for PCC mailbox and channels Add support for Platform Communication Channel PCC-test: Test driver to trigger PCC commands drivers/mailbox/Kconfig | 12 ++ drivers/mailbox/Makefile | 2 + drivers/mailbox/mailbox.c | 118 +++++++++++++++++-- drivers/mailbox/pcc-test.c | 208 +++++++++++++++++++++++++++++++++ drivers/mailbox/pcc.c | 228 +++++++++++++++++++++++++++++++++++++ include/linux/mailbox_client.h | 6 + include/linux/mailbox_controller.h | 1 + 7 files changed, 568 insertions(+), 7 deletions(-) create mode 100644 drivers/mailbox/pcc-test.c create mode 100644 drivers/mailbox/pcc.c -- 1.9.1

10 years, 8 months

3
28
0 0

leg-kernel tag leg-20140901.0 released

by G Gregory

The leg-kernel release has been made and tagged as leg-20140901.0 This is based on mainline kernel v3.17-rc2 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: http://git.linaro.org/leg/acpi/leg-kernel.git/commit/cb30fb9031ff08b9586245… Notes :-

10 years, 8 months

1
0
0 0

[PATCH] ACPI: Add GPIO-signaled event emulator.

by Tomasz Nowicki

GPIO-signaled events is quite new thing in Linux kernel. There are not many board which can take advantage of it. However, GPIO events are very useful feature during work on ACPI subsystems. This commit emulates GPIO h/w behaviour and consists on write operation to debugfs file. GPIO device instance is still required in DSDT table along with _AEI resources and event methods. Please, see Kconfig help and driver head section for more details regarding tool usage. Signed-off-by: Tomasz Nowicki <tomasz.nowicki(a)linaro.org> --- drivers/acpi/Kconfig | 10 ++ drivers/acpi/Makefile | 1 + drivers/acpi/gpio-acpi-evt-emu.c | 195 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 206 insertions(+) create mode 100644 drivers/acpi/gpio-acpi-evt-emu.c diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index fd54a74..8b9b74d 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -122,6 +122,16 @@ config ACPI_BUTTON To compile this driver as a module, choose M here: the module will be called button. +config ACPI_GPIO_EVT_EMULATE + bool "ACPI GPIO-signaled Events Emulation Support" + depends on DEBUG_FS + default n + help + This will enable your system to emulate GPIO-signaled event through + proc file system. User needs to trigger event method by + echo 1 > /sys/kernel/debug/acpi/events/<GPIO DEVICE>/<PIN> + (where, GPIO DEVICE is a GPIO device name and PIN is a pin number). + config ACPI_VIDEO tristate "Video" depends on X86 && BACKLIGHT_CLASS_DEVICE diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile index 9fa20ff..24f9d8f 100644 --- a/drivers/acpi/Makefile +++ b/drivers/acpi/Makefile @@ -55,6 +55,7 @@ acpi-$(CONFIG_ACPI_PROCFS_POWER) += cm_sbs.o ifdef CONFIG_ACPI_VIDEO acpi-y += video_detect.o endif +acpi-$(CONFIG_ACPI_GPIO_EVT_EMULATE) += gpio-acpi-evt-emu.o # These are (potentially) separate modules diff --git a/drivers/acpi/gpio-acpi-evt-emu.c b/drivers/acpi/gpio-acpi-evt-emu.c new file mode 100644 index 0000000..c39f501 --- /dev/null +++ b/drivers/acpi/gpio-acpi-evt-emu.c @@ -0,0 +1,195 @@ +/* + * Code to emulate GPIO-signaled events. + * + * The sole purpose of this module is to help with GPIO event triggering. + * Usage: + * 1. See the list of available GPIO devices and associated pins under: + * /sys/kernel/debug/acpi/events/<GPIO DEVICE>/<PIN>. Only pins which are to + * be used as GPIO-signaled events will be listed (_AEI resources). + * + * 2. Trigger method corresponding to device pin number: + * $ echo 1 > /sys/kernel/debug/acpi/events/<GPIO DEVICE>/<PIN> + */ + +/* + * Copyright (C) 2014, Linaro Ltd. + * Author: Tomasz Nowicki <tomasz.nowicki(a)linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/module.h> +#include <linux/uaccess.h> +#include <linux/debugfs.h> +#include <linux/acpi.h> + +#include "acpica/accommon.h" +#include "acpica/acnamesp.h" + +#include "internal.h" + +#define _COMPONENT ACPI_SYSTEM_COMPONENT +ACPI_MODULE_NAME("gpio_acpi_evt_emu"); + +struct gpio_pin_parent_data { + acpi_handle handle; + struct dentry *debugfs_dir; + char *name; + unsigned int evt_count; +}; + +struct gpio_pin_data { + struct list_head list; + acpi_handle handle; + unsigned int pin; +}; + +static struct dentry *acpi_evt_debugfs_dir; +static LIST_HEAD(pin_data_list); + +static int gpio_evt_trigger(void *data, u64 val) +{ + struct gpio_pin_data *pin_data = (struct gpio_pin_data *)data; + int pin = pin_data->pin; + + if (ACPI_FAILURE(acpi_execute_simple_method(pin_data->handle, NULL, + pin <= 255 ? 0 : pin))) + pr_err(PREFIX "evaluating event method failed\n"); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(gpio_evt_emu_fops, NULL, gpio_evt_trigger, "%llu\n"); + +static acpi_status gpio_list_resource(struct acpi_resource *ares, void *context) +{ + struct acpi_resource_gpio *agpio = &ares->data.gpio; + struct gpio_pin_parent_data *parent_data = context; + struct dentry *pin_debugfs_dir; + struct gpio_pin_data *pin_data; + acpi_handle evt_handle; + acpi_status status; + char str_pin[5]; + char ev_name[5]; + int pin; + + if (ares->type != ACPI_RESOURCE_TYPE_GPIO) + return AE_OK; + + if (agpio->connection_type != ACPI_RESOURCE_GPIO_TYPE_INT) + return AE_OK; + + pin_data = kmalloc(sizeof(*pin_data), GFP_KERNEL); + if (!pin_data) + return AE_NO_MEMORY; + + pin = agpio->pin_table[0]; + snprintf(str_pin, 5, "%d", pin); + pin_debugfs_dir = debugfs_create_file(str_pin, S_IWUSR, + parent_data->debugfs_dir, + pin_data, + &gpio_evt_emu_fops); + if (!pin_debugfs_dir) { + status = AE_NULL_ENTRY; + goto fail; + } + + if (pin <= 255) + sprintf(ev_name, "_%c%02X", + agpio->triggering == ACPI_EDGE_SENSITIVE ? 'E' : 'L', + pin); + else + sprintf(ev_name, "_EVT"); + + status = acpi_get_handle(parent_data->handle, ev_name, &evt_handle); + if (ACPI_FAILURE(status)) { + pr_err(PREFIX "getting handle to <%s> of <%s> failed, there is no method related to 0x%02X pin\n", + ev_name, parent_data->name, pin); + goto fail; + } + + pin_data->handle = evt_handle; + pin_data->pin = pin; + list_add_tail(&pin_data->list, &pin_data_list); + + parent_data->evt_count++; + + return AE_OK; +fail: + kfree(pin_data); + return status; +} + +static acpi_status gpio_find_resource(acpi_handle handle, u32 lvl, + void *context, void **rv) +{ + struct acpi_namespace_node *node; + struct dentry *gpio_debugfs_dir; + struct gpio_pin_parent_data parent_data; + char gpio_name[5]; + + node = acpi_ns_validate_handle(handle); + if (!node) { + pr_err(PREFIX "Mapping GPIO handle to node failed\n"); + return AE_BAD_PARAMETER; + } + + snprintf(gpio_name, 5, "%s", node->name.ascii); + gpio_debugfs_dir = debugfs_create_dir(gpio_name, acpi_evt_debugfs_dir); + if (gpio_debugfs_dir == NULL) + return AE_OK; + + parent_data.debugfs_dir = gpio_debugfs_dir; + parent_data.handle = handle; + parent_data.name = gpio_name; + parent_data.evt_count = 0; + + acpi_walk_resources(handle, METHOD_NAME__AEI, gpio_list_resource, + &parent_data); + + if (!parent_data.evt_count) + debugfs_remove(gpio_debugfs_dir); + + return AE_OK; +} + +static int __init gpio_evt_emu_init(void) +{ + if (acpi_debugfs_dir == NULL) + return -ENOENT; + + acpi_evt_debugfs_dir = debugfs_create_dir("events", acpi_debugfs_dir); + if (acpi_evt_debugfs_dir == NULL) + return -ENOENT; + + acpi_get_devices(NULL, gpio_find_resource, NULL, NULL); + + return 0; +} + +static void __exit gpio_evt_emu_deinit(void) +{ + struct gpio_pin_data *pin_data, *temp; + + list_for_each_entry_safe(pin_data, temp, &pin_data_list, list) + kfree(pin_data); + + debugfs_remove_recursive(acpi_evt_debugfs_dir); +} + +module_init(gpio_evt_emu_init); +module_exit(gpio_evt_emu_deinit); + +MODULE_DESCRIPTION("GPIO-signaled events emulator"); +MODULE_LICENSE("GPL"); -- 1.9.1

10 years, 8 months

3
7
0 0

[PATCH v2 00/18] Introduce ACPI for ARM64 based on ACPI 5.1

by Hanjun Guo

ACPI 5.1 has been released and now be freely available for download [1]. It fixed some major gaps to run ACPI on ARM, this patch just follow the ACPI 5.1 spec and prepare the code to run ACPI on ARM64. ACPI 5.1 has some major changes for the following tables and method which are essential for ARM platforms: 1) MADT table updates. New fields were introduced to cover MPIDR and virtualization in GICC, and introduce GICR and GIC MSI frame structure to cover GICv3 and GICv2m (this patch set only cover GICv2). 2) FADT updates for PSCI New fields were introduced to cover PSCI and ACPI can use psci to boot SMP and other PSCI related functions. 3) GTDT GTDT was updated to support arch timer, memory-mapped tiemr, SBSA watchdog timer, in this patch, only arch timer tested on Juno board, so only arch timer init is available. 4) _DSD _DSD (Device Specific Data) will provide some key values which presented by FDT before, it makes possible that some devices can be emumerated in ACPI way, please refer to the document provided in this patch set for detail. This patch set is the ARM64 ACPI core patches covered MADT, FADT and GTDT, _DSD is not covered in this patch set. We first introduce acpi.c and its related head file which are needed by ACPI core, and then get RSDP to extract all the ACPI boot-time tables. When all the boot-time tables (FADT, MADT, GTDT) are ready, then parse them to init the sytem when booted. Specifically, a) we use FADT to init PSCI and use PSCI to boot SMP; b) Use MADT for GIC init and SMP init; c) GTDT for arch timer init. This patch set is based on Rafael's linux-pm tree/linux-next branch, and I already compiled it OK with: a) each patch applied on ARM64 with CONFIG_ACPI=y; b) CONFIG_ACPI=n on ARM64; c) CONFIG_ACPI=y on x86. Updates since v1: - Set ACPI default off on ARM64 suggested by Olof; - Rebase the patch set on top of linux-next branch/linux-pm tree which includes the ACPICA for full ACPI 5.1 support. - Update the document as suggested; - Adress lots of comments from Mark, Sudeep, Randy, Naresh, Olof, Geoff and more... [1] http://www.uefi.org/sites/default/files/resources/ACPI_5_1release.pdf Al Stone (3): ARM64 / ACPI: Get RSDP and ACPI boot-time tables ARM64 / ACPI: Select ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled on ARM64 ARM64 / ACPI: Introduce early_param for "acpi" and set ACPI default off Ashwin Chaugule (1): ACPI / table: Add new function to get table entries Graeme Gregory (4): ARM64 / ACPI: Introduce lowlevel suspend function ARM64 / ACPI: If we chose to boot from acpi then disable FDT ARM64 / ACPI: Enable ARM64 in Kconfig Documentation: ACPI for ARM64 Hanjun Guo (9): ARM64: Move the init of cpu_logical_map(0) before unflatten_device_tree() ARM64 / ACPI: Make PCI optional for ACPI on ARM64 ARM64 / ACPI: Parse FADT table to get PSCI flags for PSCI init ARM64 / ACPI: Parse MADT to map logical cpu to MPIDR and get cpu_possible/present_map ACPI / table: Print GIC information when MADT is parsed ARM64 / ACPI: Get the enable method for SMP initialization in ACPI way ACPI / processor: Make it possible to get CPU hardware ID via GICC ARM64 / ACPI: Introduce ACPI_IRQ_MODEL_GIC and register device's gsi ARM64 / ACPI: Parse GTDT to initialize arch timer Tomasz Nowicki (1): ARM64 / ACPI: Add GICv2 specific ACPI boot support Documentation/arm64/arm-acpi.txt | 215 +++++++++++++++++++ Documentation/kernel-parameters.txt | 5 +- arch/arm64/Kconfig | 3 + arch/arm64/include/asm/acenv.h | 18 ++ arch/arm64/include/asm/acpi.h | 113 ++++++++++ arch/arm64/include/asm/cpu.h | 11 + arch/arm64/include/asm/pci.h | 11 + arch/arm64/include/asm/smp.h | 3 +- arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/acpi.c | 380 ++++++++++++++++++++++++++++++++++ arch/arm64/kernel/cpu_ops.c | 62 +++++- arch/arm64/kernel/irq.c | 5 + arch/arm64/kernel/psci.c | 89 ++++++-- arch/arm64/kernel/setup.c | 13 +- arch/arm64/kernel/smp.c | 37 +++- arch/arm64/kernel/time.c | 7 + drivers/acpi/Kconfig | 6 +- drivers/acpi/Makefile | 2 +- drivers/acpi/bus.c | 3 + drivers/acpi/internal.h | 5 + drivers/acpi/processor_core.c | 37 ++++ drivers/acpi/tables.c | 109 ++++++++-- drivers/clocksource/arm_arch_timer.c | 117 +++++++++-- drivers/irqchip/irq-gic.c | 114 ++++++++++ include/linux/acpi.h | 5 + include/linux/clocksource.h | 6 + include/linux/irqchip/arm-gic-acpi.h | 36 ++++ include/linux/pci.h | 37 +++- 28 files changed, 1359 insertions(+), 91 deletions(-) create mode 100644 Documentation/arm64/arm-acpi.txt create mode 100644 arch/arm64/include/asm/acenv.h create mode 100644 arch/arm64/include/asm/acpi.h create mode 100644 arch/arm64/include/asm/cpu.h create mode 100644 arch/arm64/include/asm/pci.h create mode 100644 arch/arm64/kernel/acpi.c create mode 100644 include/linux/irqchip/arm-gic-acpi.h -- 1.7.9.5

10 years, 8 months

11
66
0 0

[RFC 0/3] Experimental patchset for CPPC

by Ashwin Chaugule

Hello, Apologies in advance for a lengthy cover letter. Hopefully it has all the required information so you dont need to read the ACPI spec. ;) This patchset introduces the ideas behind CPPC (Collaborative Processor Performance Control) and implements support for controlling CPU performance using the existing PID (Proportional-Integral-Derivative) controller (from intel_pstate.c) and some CPPC semantics. The patchwork is not a final proposal of the CPPC implementation. I've had to hack some sections due to lack of hardware, details of which are in the Testing section. There are several bits of information which are needed in order to make CPPC work great on Linux based platforms and I'm hoping to start a wider discussion on how to address the missing bits. The following sections briefly introduce CPPC and later highlight the information which is missing. More importantly, I'm also looking for ideas on how to support CPPC in the short term, given that we will soon be seeing products based on ARM64 and X86 which support CPPC.[1] Although we may not have all the information, we could make it work with existing governors in a way this patchset demonstrates. Hopefully, this approach is acceptable for mainline inclusion in the short term. Finer details about the CPPC spec are available in the latest ACPI 5.1 specification.[2] If these issues are being discussed on some other thread or elsewhere, or if someone is already working on it, please let me know. Also, please correct me if I have misunderstood anything. What is CPPC: ============= CPPC is the new interface for CPU performance control between the OS and the platform defined in ACPI 5.0+. The interface is built on an abstract representation of CPU performance rather than raw frequency. Basic operation consists of: * Platform enumerates supported performance range to OS * OS requests desired performance level over some time window along with min and max instantaneous limits * Platform is free to optimize power/performance within bounds provided by OS * Platform provides telemetry back to OS on delivered performance Communication with the OS is abstracted via another ACPI construct called Platform Communication Channel (PCC) which is essentially a generic shared memory channel with doorbell interrupts going back and forth. This abstraction allows the “platform” for CPPC to be a variety of different entities – driver, firmware, BMC, etc. CPPC describes the following registers: * HighestPerformance: (read from platform) Indicates the highest level of performance the processor is theoretically capable of achieving, given ideal operating conditions. * Nominal Performance: (read from platform) Indicates the highest sustained performance level of the processor. This is the highest operating performance level the CPU is expected to deliver continuously. * LowestNonlinearPerformance: (read from platform) Indicates the lowest performance level of the processor with non- linear power savings. * LowestPerformance: (read from platform) Indicates the lowest performance level of the processor. * GuaranteedPerformanceRegister: (read from platform) Optional. If supported, contains register to read the current guaranteed performance from. This is current max sustained performance of the CPU taking into account all budgeting constraints. This can change at runtime and is notified to the OS via ACPI notification mechanisms. * DesiredPerformanceRegister: (write to platform) Register to write desired performance level from the OS. * MinimumPerformanceRegister: (write to platform) Optional. This is the min allowable performance as requested by the OS. * MaximumPerformanceRegister: (write to platform) Optional. This is the max allowable performance as requested by the OS. * PerformanceReductionToleranceRegister (write to platform) Optional. This is the deviation below the desired perf value as requested by the OS. If the Time window register(below) is supported, then this value is the min performance on average over the time window that the OS desires. * TimeWindowRegister: (write to platform) Optional. The OS requests desired performance over this time window. * CounterWraparoundTime: (read from platform) Optional. Min time before the performance counters wrap around. * ReferencePerformanceCounterRegister: (read from platform) A counter that increments proportionally to the reference performance of the processor. * DeliveredPerformanceCounterRegister: (read from platform) Delivered perf = reference perf * delta(delivered perf ctr)/delta(ref perf ctr) * PerformanceLimitedRegister: (read from platform) This is set by the platform in the event that it has to limit available performance due to thermal or budgeting constraints. * CPPCEnableRegister: (read/write from platform) Enable/disable CPPC * AutonomousSelectionEnable: Platform decides CPU performance level w/o OS assist. * AutonomousActivityWindowRegister: This influences the increase or decrease in cpu performance of the platforms autonomous selection policy. * EnergyPerformancePreferenceRegister: Provides a energy or perf bias hint to the platform when in autonomous mode. * Reference Performance: (read from platform) Indicates the rate at which the reference counter increments. Whats missing in CPPC: ===================== Currently CPPC makes no mention of power. However, this could be added in future versions of the spec. e.g. although CPPC works off of a continuous range of CPU perf levels, we could discretize the scale such that we only extract points where the power level changes substantially between CPU perf levels and export this information to the scheduler. Whats missing in the kernel: ============================ We may have some of this information in the scheduler, but I couldn't see a good way to extract it for CPPC yet. (1) An intelligent way to provide a min/max bound and a desired value for CPU performance. (2) A timing window for the platform to deliver requested performance within bounds. This could be a kind of sampling interval between consecutive reads of delivered cpu performance. (3) Centralized decision making by any CPU in a freq domain for all its siblings. The last point needs some elaboration: I see that the CPUfreq layer allows defining "related CPUs" and that we can have the same policy for CPUs in the same freq domain and one governor per policy. However, from what I could tell, there are at least 2 baked in assumptions in this layer which break things at least for platforms like ARM (Please correct me if I'm wrong!) (a) All CPUs run at the exact same max, min and cur freq. (b) Any CPU always gets exactly the freq it asked for. So, although the CPUFreq layer is capable of making somewhat centralized cpufreq decisions for CPUs under the same policy, it seems to be deciding things under the wrong/inapplicable assumptions. Moreover only one CPU is in charge of policy handling at a time and the policy handling is shifted to another CPU in the domain, only if the former CPU is hotplugged out. Not having a proper centralized decision maker adversely affects power saving possibilities in platforms that can't distinguish when a CPU requests a specific freq and then goes to sleep. This potentially has the effect of keeping other CPUs in the domain running at a much higher frequency than required, while the initial requester is deep asleep. So, for point (3), I'm not sure which path we should take among the following: (I) Fix cpufreq layer and add CPPC support as a cpufreq_driver. (a) Change every call to get freq to make it read h/w registers and then snap value back to freq table. This way, cpufreq can keep its idea of freq current. However, this may end up waking CPUs to read counters, unless they are mem mapped. (b) Allow any CPU in the "related_cpus" mask to make policy decisions on behalf of siblings. So the policy maker switching is not tied to hotplug. (II) Not touch CPUfreq and use the PID algorithm instead, but change the busyness calculation to accumulate busyness values from all CPUs in common domain. Requires implementation of domain awareness. (III) Address these issues in the upcoming CPUfreq/CPUidle integration layer(?) (IV) Handle it in the platform or lose out. I understand this has some potential for adding latency to cpu freq requests so it may not be possible for all platforms. (V) ..? For points (1) and (2), the long term solution IMHO is to work it out along with the scheduler CPUFreq/CPUidle integration. But its not clear to me what would be the best short term approach. I'd greatly appreciate any suggestions/comments. If anyone is already working on these issues, please CC me as well. Test setup: ========== For the sake of experiments, I used the Thinkpad x240 laptop, which advertises CPPC tables in its ACPI firmware. The PCC and CPPC drivers included in this patchset are able to parse the tables and get all the required addresses. However, it seems that this laptop doesn't implement PCC doorbell and the firmware side of CPPC. The PCC doorbell calls would just wait forever. Not sure whats going on there. So, I had to hack it and emulate what the platform would've done to some extent. I extracted the PID algo from intel_pstate.c and modified it with CPPC function wrappers. It shouldn't be hard to replace PID with anything else we think is suitable. In the long term, I hope we can make CPPC calls directly from the scheduler. There are two versions of the low level CPPC accessors. The one included in the patchset is how I'd imagine it would work with platforms that completely implement CPPC in firmware. The other version is here [5]. This should help with DT or platforms with broken firmware, enablement purposes etc. I ran a simple kernel compilation with intel_pstate.c and the CPPC modified version as the governors and saw no real difference in compile times. So no new overheads added. I verified that CPU freq requests were taken by reading out the PERF_STATUS register. [1] - See the HWP section 14.4 http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-3… [2] - http://www.uefi.org/sites/default/files/resources/ACPI_5_1release.pdf [3] - https://plus.google.com/+TheodoreTso/posts/2vEekAsG2QT [4] - https://plus.google.com/+ArjanvandeVen/posts/dLn9T4ehywL [5] - http://git.linaro.org/people/ashwin.chaugule/leg-kernel.git/blob/236d901d31… Ashwin Chaugule (3): ACPI: Add support for Platform Communication Channel CPPC: Add support for Collaborative Processor Performance Control CPPC: Add ACPI accessors to CPC registers drivers/acpi/Kconfig | 10 + drivers/acpi/Makefile | 1 + drivers/acpi/pcc.c | 301 +++++++++++++++ drivers/cpufreq/Kconfig | 19 + drivers/cpufreq/Makefile | 2 + drivers/cpufreq/cppc.c | 874 ++++++++++++++++++++++++++++++++++++++++++++ drivers/cpufreq/cppc.h | 181 +++++++++ drivers/cpufreq/cppc_acpi.c | 80 ++++ 8 files changed, 1468 insertions(+) create mode 100644 drivers/acpi/pcc.c create mode 100644 drivers/cpufreq/cppc.c create mode 100644 drivers/cpufreq/cppc.h create mode 100644 drivers/cpufreq/cppc_acpi.c -- 1.9.1

10 years, 8 months

4
24
0 0

[RFC] ACPI: Add GPIO-signaled event simulator.

by Tomasz Nowicki

GPIO signaled events is quite new thing in Linux kernel. AFAIK, there are not many board which can take advantage of it. However, GPIO events are very useful feature during work on ACPI subsystems. This commit emulates GPIO h/w behaviour and consists on read/write operation to debugfs file. GPIO device instance is still required in DSDT table along with _AEI resources and event methods. Reading from file provides pin to GPIO device map e.g. : $ cat /sys/kernel/debug/acpi/gpio_event GPIO device name: /__SB.GPI0 Available GPIO pin map: /__SB.GPI0 <-> pin 0x100 Based on that, user can trigger method corresponding to device pin number: $ echo "/__SB.GPI0 0x100" > /sys/kernel/debug/acpi/gpio_event Please, see Kconfig help and driver head section for more details regarding tool usage. Signed-off-by: Tomasz Nowicki <tomasz.nowicki(a)linaro.org> --- drivers/acpi/Kconfig | 11 +++ drivers/acpi/Makefile | 1 + drivers/acpi/gpio_evt_emu.c | 207 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 219 insertions(+) create mode 100644 drivers/acpi/gpio_evt_emu.c diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index fd54a74..59e4c67 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -122,6 +122,17 @@ config ACPI_BUTTON To compile this driver as a module, choose M here: the module will be called button. +config ACPI_GPIO_EVT_EMULATE + bool "ACPI GPIO-signaled Events Emulation Support" + depends on DEBUG_FS + default n + help + This will enable your system to emulate GPIO-signaled event through + proc file system /sys/kernel/debug/acpi/gpio_event. User needs to print + available GPIO devices and pin map (cat path_to_proc_file) so that he + knows how to trigger given event by echo "XXX YYY" > path_to_proc_file + (where, XXX is a path to GPIO device and YYY is a pin number). + config ACPI_VIDEO tristate "Video" depends on X86 && BACKLIGHT_CLASS_DEVICE diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile index 9fa20ff..fb3c335 100644 --- a/drivers/acpi/Makefile +++ b/drivers/acpi/Makefile @@ -55,6 +55,7 @@ acpi-$(CONFIG_ACPI_PROCFS_POWER) += cm_sbs.o ifdef CONFIG_ACPI_VIDEO acpi-y += video_detect.o endif +acpi-$(CONFIG_ACPI_GPIO_EVT_EMULATE) += gpio_evt_emu.o # These are (potentially) separate modules diff --git a/drivers/acpi/gpio_evt_emu.c b/drivers/acpi/gpio_evt_emu.c new file mode 100644 index 0000000..a2f762c --- /dev/null +++ b/drivers/acpi/gpio_evt_emu.c @@ -0,0 +1,207 @@ +/* + * Code to emulate GPIO-signaled events. + * + * The sole purpose of this module is to help with GPIO event triggering. + * Suggested way of using: + * 1. Perform walk of the namespac device tree looking for GPIO devices + * with associated _AEI resources e.g.: + * $ cat /sys/kernel/debug/acpi/gpio_event + * GPIO device name: /__SB.GPI0 + * Available GPIO pin map: + * /__SB.GPI0 <-> pin 0x100 + * + * 2. Trigger method corresponding to device pin number: + * $ echo "/__SB.GPI0 0x100" > /sys/kernel/debug/acpi/gpio_event + */ + +/* + * Copyright (C) 2014, Linaro Ltd. + * Author: Tomasz Nowicki <tomasz.nowicki(a)linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/module.h> +#include <linux/uaccess.h> +#include <linux/debugfs.h> +#include <linux/acpi.h> + +#include "acpica/accommon.h" +#include "acpica/acnamesp.h" + +#include "internal.h" + +static struct dentry *gpio_evt_dentry; + +static void gpio_trigger_event(char *gpio_path, u32 pin) +{ + acpi_handle gpio_handle, evt_handle; + char ev_name[5]; + + if (ACPI_FAILURE(acpi_get_handle(NULL, gpio_path, &gpio_handle))) { + pr_err(PREFIX "getting handle to <%s> failed\n", gpio_path); + return; + } + + if (pin <= 255) + sprintf(ev_name, "_L%02X", pin); + else + sprintf(ev_name, "_EVT"); + + + if (ACPI_FAILURE(acpi_get_handle(gpio_handle, ev_name, &evt_handle))) { + pr_err(PREFIX "getting handle to <%s.%s> failed, there is no method related to 0x%02X pin\n", + gpio_path, ev_name, pin); + return; + } + + if (ACPI_FAILURE(acpi_execute_simple_method(evt_handle, NULL, + pin <= 255 ? 0 : pin))) + pr_err(PREFIX "evaluating <%s._EVT for pin %d> failed\n", + gpio_path, pin); + + return; +} + +static ssize_t gpio_evt_write(struct file *file, const char __user *user_buf, + size_t count, loff_t *ppos) +{ + u32 pin_number; + char *gpio_path = NULL; + char *pin_str = NULL; + const char *delim = " "; + char *temp_buf = NULL; + char *temp_buf_addr = NULL; + + temp_buf = kmalloc(count+1, GFP_ATOMIC); + if (!temp_buf) { + pr_warn(PREFIX "%s: Memory allocation failed\n", __func__); + return count; + } + temp_buf[count] = '\0'; + temp_buf_addr = temp_buf; + if (copy_from_user(temp_buf, user_buf, count)) + goto out; + + gpio_path = strsep(&temp_buf, delim); + pin_str = strsep(&temp_buf, delim); + + if (gpio_path && pin_str) { + ssize_t ret; + unsigned long val; + + ret = kstrtoul(pin_str, 10, &val); + if (ret) { + pr_warn(PREFIX "unknown event\n"); + goto out; + } + + pin_number = (u32)val; + } else { + pr_warn(PREFIX "unknown device\n"); + goto out; + } + + pr_info(PREFIX "ACPI device name is <%s>, pin number is <%d>\n", + gpio_path, pin_number); + + gpio_trigger_event(gpio_path, pin_number); + +out: + kfree(temp_buf_addr); + return count; +} + +static acpi_status gpio_list_resource(struct acpi_resource *ares, + void *context) +{ + struct acpi_resource_gpio *agpio; + struct seq_file *m = context; + int pin; + + if (!m) + return AE_OK; + + if (ares->type != ACPI_RESOURCE_TYPE_GPIO) + return AE_OK; + + agpio = &ares->data.gpio; + if (agpio->connection_type != ACPI_RESOURCE_GPIO_TYPE_INT) + return AE_OK; + + pin = agpio->pin_table[0]; + seq_printf(m, "%s <-> pin %d\n", agpio->resource_source.string_ptr, + pin); + + return AE_OK; +} + +static acpi_status gpio_find_resource(acpi_handle handle, u32 lvl, + void *context, void **rv) +{ + struct acpi_namespace_node *node; + struct seq_file *m = context; + + if (ACPI_FAILURE(acpi_walk_resources(handle, METHOD_NAME__AEI, + gpio_list_resource, NULL))) + return AE_OK; + + node = acpi_ns_validate_handle(handle); + if (!node) { + pr_err(PREFIX "Mapping GPIO handle to node failed\n"); + return AE_OK; + } + + seq_printf(m, "GPIO device name: %4.4s\nAvailable GPIO pin map:\n", + ACPI_CAST_PTR(char, &node->name)); + acpi_walk_resources(handle, METHOD_NAME__AEI, gpio_list_resource, + context); + return AE_OK; +} + +static int gpio_evt_show(struct seq_file *m, void *v) +{ + acpi_get_devices(NULL, gpio_find_resource, m, NULL); + return 0; +} + +static int gpio_evt_open(struct inode *inode, struct file *file) +{ + return single_open(file, gpio_evt_show, NULL); +} + +static const struct file_operations gpio_evt_emu_fops = { + .open = gpio_evt_open, + .write = gpio_evt_write, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int __init gpio_evt_emu_init(void) +{ + if (acpi_debugfs_dir == NULL) + return -ENOENT; + + gpio_evt_dentry = debugfs_create_file("gpio_event", S_IWUSR, + acpi_debugfs_dir, NULL, &gpio_evt_emu_fops); + if (gpio_evt_dentry == NULL) + return -ENODEV; + + return 0; +} + +device_initcall(gpio_evt_emu_init); +ACPI_MODULE_NAME("acpi_evt_emu"); +MODULE_LICENSE("GPL"); -- 1.9.1

10 years, 8 months

4
8
0 0

[PATCH 1/2] ACPI 5.1: Add missing flag definitions for GTDT

by Hanjun Guo

The flag definitions of TimerFlags and VirtualTimerFlags in struct acpi_gtdt_timer_entry is missing, fix it. Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org> --- Those two patches are for ACPICA, I will send them to Bob and Lv. --- source/include/actbl3.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/source/include/actbl3.h b/source/include/actbl3.h index b30e80f..1e59241 100644 --- a/source/include/actbl3.h +++ b/source/include/actbl3.h @@ -432,6 +432,10 @@ typedef struct acpi_gtdt_timer_entry } ACPI_GTDT_TIMER_ENTRY; +/* Flag Definitions: TimerFlags and VirtualTimerFlags above */ + +#define ACPI_GTDT_GT_INTERRUPT_TRIGGER_MODE (1) +#define ACPI_GTDT_GT_INTERRUPT_POLARITY (1<<1) /* Flag Definitions: CommonFlags above */ -- 1.7.9.5

10 years, 9 months

1
1
0 0

leg-kernel tag leg-20140730.0 released

by G Gregory

The leg-kernel release has been made and tagged as leg-20140730.0 This is based on mainline kernel v3.16-rc7 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: http://git.linaro.org/leg/acpi/leg-kernel.git/commit/2189d8891fd5ae91eeaa56… Notes :- 1) This is the first version of leg-kernel to be based on ACPI 5.1 release.

10 years, 9 months

1
0
0 0

[PATCH] ACPI:GPIO: Add GPIO description on JUNO

by Yi Li

Add the general description for GPIO on JUNO board. Define pin number 256 as power button function (for demo) in this patch. However,JUNO has no GPIO controller in hardware, Using GPIO event emulation which can trigger the GPIO action, then test the GPIO-signal event model for ACPI. Signed-off-by: Yi Li <yi.li(a)linaro.org> --- ArmPlatformPkg/ArmJunoPkg/AcpiTables/juno/dsdt.asl | 42 ++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/ArmPlatformPkg/ArmJunoPkg/AcpiTables/juno/dsdt.asl b/ArmPlatformPkg/ArmJunoPkg/AcpiTables/juno/dsdt.asl index 5bfd521..e4e9cad 100644 --- a/ArmPlatformPkg/ArmJunoPkg/AcpiTables/juno/dsdt.asl +++ b/ArmPlatformPkg/ArmJunoPkg/AcpiTables/juno/dsdt.asl @@ -58,6 +58,48 @@ DefinitionBlock ( } } + //GPIO controller description + Device (GPO0) + { + Name (_HID, "LNRO0009") + Name (_ADR, 0) + Name (_UID, 0) + + Name (_CRS, ResourceTemplate () { + //GPIO Register Interface(demo,need to modify by the real h/w setting) + Memory32Fixed (ReadWrite, 0x1c010000, 0x1000) + + //Interrupt vector 0x80 for GPIO controller(demo,need to modify by the real h/w setting) + Interrupt (ResourceConsumer, Edge, ActiveLow, Exclusive) {0x80} + }) + + Name (_AEI,ResourceTemplate () { + //Assume GPIO256 as PowerButton + GpioInt(Edge, ActiveLow, ExclusiveAndWake, PullUp, , " \\_SB.GPO0") {0x100} + }) + + //Handle all ACPI Events signaled by GPIO Controller GPO0 + Method (_EVT, 0x1, Serialized) + { + //Arg0 - EventNumber. An Integer indicating the event number. + //(Controller-relative zero-based GPIO pin number) of the current event. + //Must be in the range 0x0000 - 0xffff. + Switch (ToInteger(Arg0)) + { + //Pin number 256 + Case (0x100) + { + //Notify OSPM the power button is pressed + Notify (PWRB, 0x80) + } + Default + { + + } + } + } + } + //Power button device description Device (PWRB) { -- 1.7.9.5

10 years, 9 months

1
0
0 0

[PATCH] ACPI:PB: Add the power button device on JUNO

by Yi Li

Add the power button description on juno board, notify power button with 0x80 value, the OS will detect the power button is pressed, how to deal with the event which depends on OS's policy. Usually the acpid deamon will call the specific script to let OS shutdown. Signed-off-by: Yi Li <yi.li(a)linaro.org> --- ArmPlatformPkg/ArmJunoPkg/AcpiTables/juno/dsdt.asl | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/ArmPlatformPkg/ArmJunoPkg/AcpiTables/juno/dsdt.asl b/ArmPlatformPkg/ArmJunoPkg/AcpiTables/juno/dsdt.asl index bdee349..5bfd521 100644 --- a/ArmPlatformPkg/ArmJunoPkg/AcpiTables/juno/dsdt.asl +++ b/ArmPlatformPkg/ArmJunoPkg/AcpiTables/juno/dsdt.asl @@ -58,6 +58,19 @@ DefinitionBlock ( } } + //Power button device description + Device (PWRB) + { + Name (_HID, EISAID("PNP0C0C")) + Name (_ADR, 0) + Name (_UID, 0) + + Method (_STA, 0x0, Notserialized) + { + Return (0x0F) + } + } + // apb_pclk Device (CLK0) { Name (_HID, "LNRO0008") -- 1.7.9.5

10 years, 9 months

1
0
0 0

[PATCH 0/3] Update APM XGene tables to ACPI 5.1

by al.stone＠linaro.org

From: Al Stone <al.stone(a)linaro.org> These patches are my best guess at initial ACPI tables for XGene, in accordance with the new ACPI 5.1 specification. These have not been fully tested yet but that process has been started. Al Stone (3): APM / XGene: Minor cleanup of some of the basics APM / XGene: Update core tables to replace ACPI 5.1 changes APM / XGene: Add in empty SSDT for future use in developing complete tables platforms/APMXGene.acpi/APMXGene.manifest | 1 + platforms/APMXGene.acpi/Apic.asl | 262 ++-- platforms/APMXGene.acpi/Dsdt.asl | 2215 ++++++++++++++++------------- platforms/APMXGene.acpi/Facp.asl | 57 +- platforms/APMXGene.acpi/Gtdt.asl | 87 +- platforms/APMXGene.acpi/Rsdp.asl | 2 +- platforms/APMXGene.acpi/Ssdt.asl | 21 + platforms/APMXGene.acpi/Xsdt.asl | 10 +- 8 files changed, 1508 insertions(+), 1147 deletions(-) create mode 100644 platforms/APMXGene.acpi/Ssdt.asl -- 1.9.3

10 years, 9 months

3
6
0 0

libacpica for aarch64 - package/source?

by Claudio Fontana

Hello, what is the current state of libacpica for aarch64? Are packages available from Linaro (static libs and includes would be best)? Is it available on which linaro trees? Is anything already in upstream libacpica? Thank you, Claudio

10 years, 9 months

2
1
0 0

[PATCH v5 0/3] APEI: Make APEI architecture independent.

by Tomasz Nowicki

APEI is currently implemented so that it depends on x86 hardware. The primary dependency is that GHES uses the x86 NMI for hardware error notification and MCE for memory error handling. These patches remove that dependency. Other APEI features such as error reporting via external IRQ, error serialization, or error injection, do not require changes to use them on non-x86 architectures. The following patch set eliminates the APEI Kconfig x86 dependency by making these changes: - treat NMI notification as GHES architecture - HAVE_ACPI_APEI_NMI - group and wrap around #ifdef CONFIG_HAVE_ACPI_APEI_NMI code which is used only for NMI path - identify architectural boxes and abstract it accordingly (tlb flush and MCE) - rework ioremap for both IRQ and NMI context NMI code is kept in ghes.c file since NMI and IRQ context are tightly coupled. Note, these patches introduce no functional changes for x86. The NMI notification feature is hard selected for x86. Architectures that want to use this feature should also provide NMI code infrastructure. V1->V2 - address Borislav's comment - abstract arch-specific calls instead of wrapping into the #ifdef V2->V3 - address Robert's comment - disable ACPI_APEI_NMI selection so that it is hard selected by arch Kconfig - rename ACPI_APEI_NMI to ARCH_HAS_ACPI_APEI_NMI V3->V4 - do not abstract NMI calls for archs which do not support it - merge some of patches to make review process easier V4->V5 - markers for preprocessor statements (#else, #endif) around long code block Tomasz Nowicki (3): apei, mce: Factor out APEI architecture specific MCE calls. acpi, apei, ghes: Make NMI error notification to be GHES architecture extension. acpi, apei, ghes: Factor out ioremap virtual memory for IRQ and NMI context. arch/x86/Kconfig | 2 + arch/x86/kernel/acpi/Makefile | 1 + arch/x86/kernel/acpi/apei.c | 62 +++++++++++++++ drivers/acpi/apei/Kconfig | 8 +- drivers/acpi/apei/apei-base.c | 13 ++++ drivers/acpi/apei/ghes.c | 173 +++++++++++++++++++++++++++--------------- drivers/acpi/apei/hest.c | 29 +------ include/acpi/apei.h | 4 + include/linux/nmi.h | 4 + 9 files changed, 204 insertions(+), 92 deletions(-) create mode 100644 arch/x86/kernel/acpi/apei.c -- 1.9.1

10 years, 9 months

3
6
0 0

[PATCH v3 0/3] Clean up ACPI core to prepare for running ACPI on ARM64

by Hanjun Guo

This patch set have no function change for x86 and ia64 and just do some clean up to prepare for running ACPI on ARM64. This patch set is splited out from the patch set [1] "[PATCH v4 00/13] Enable ACPI on ARM64 in Kconfig" and hope it can be merged first before ARM64 ACPI core patches. [1]: https://lkml.org/lkml/2014/6/26/627 update from v2: Don not select ACPI_LEGACY_TABLES_LOOKUP on IA64 which is catched by Peter. update from v1: 1. Drop "Make EC debugfs depend on X86 || IA64 in Kconfig"; 2. Rename ACPI_SCAN_BIOS_NOT_EFI to ACPI_LEGACY_TABLES_LOOKUP suggested by Rafael; 3. Rename ARCH_HAS_ACPI_PDC to ARCH_MIGHT_HAVE_ACPI_PDC suggested by Rafael; 4. Remove the help for ARCH_MIGHT_HAVE_ACPI_PDC because it can't be selected; 5. Rename acpi_arch_is_smp() to acpi_has_cpu_in_madt() to be more explicit and easy understanding. Graeme Gregory (2): ACPI: ARM64 does not have a BIOS add config for BIOS table scan. ACPI: Don't use acpi_lapic in ACPI core code Hanjun Guo (1): ACPI / processor: Introduce ARCH_HAS_ACPI_PDC arch/ia64/Kconfig | 1 + arch/ia64/include/asm/acpi.h | 5 + arch/x86/Kconfig | 2 + arch/x86/include/asm/acpi.h | 5 + drivers/acpi/Kconfig | 6 ++ drivers/acpi/Makefile | 1 + drivers/acpi/acpi_processor.c | 2 +- drivers/acpi/internal.h | 5 + drivers/acpi/osl.c | 4 +- drivers/acpi/processor_core.c | 198 --------------------------------------- drivers/acpi/processor_pdc.c | 206 +++++++++++++++++++++++++++++++++++++++++ 11 files changed, 235 insertions(+), 200 deletions(-) create mode 100644 drivers/acpi/processor_pdc.c -- 1.7.9.5

10 years, 9 months

2
4
0 0

[PATCH v2 0/3] Clean up ACPI core to prepare for running ACPI on ARM64

by Hanjun Guo

This patch set have no function change for x86 and ia64 and just do some clean up to prepare for running ACPI on ARM64. This patch set is splited out from the patch set [1] "[PATCH v4 00/13] Enable ACPI on ARM64 in Kconfig" and hope it can be merged first before ARM64 ACPI core patches. [1]: https://lkml.org/lkml/2014/6/26/627 update from v1: 1. Drop "Make EC debugfs depend on X86 || IA64 in Kconfig"; 2. Rename ACPI_SCAN_BIOS_NOT_EFI to ACPI_LEGACY_TABLES_LOOKUP suggested by Rafael; 3. Rename ARCH_HAS_ACPI_PDC to ARCH_MIGHT_HAVE_ACPI_PDC suggested by Rafael; 4. Remove the help for ARCH_MIGHT_HAVE_ACPI_PDC because it can't be selected; 5. Rename acpi_arch_is_smp() to acpi_has_cpu_in_madt() to be more explicit and easy understanding. Graeme Gregory (2): ACPI: ARM64 does not have a BIOS add config for BIOS table scan. ACPI: Don't use acpi_lapic in ACPI core code Hanjun Guo (1): ACPI / processor: Introduce ARCH_HAS_ACPI_PDC arch/ia64/Kconfig | 2 + arch/ia64/include/asm/acpi.h | 5 + arch/x86/Kconfig | 2 + arch/x86/include/asm/acpi.h | 5 + drivers/acpi/Kconfig | 6 ++ drivers/acpi/Makefile | 1 + drivers/acpi/acpi_processor.c | 2 +- drivers/acpi/internal.h | 5 + drivers/acpi/osl.c | 4 +- drivers/acpi/processor_core.c | 198 --------------------------------------- drivers/acpi/processor_pdc.c | 206 +++++++++++++++++++++++++++++++++++++++++ 11 files changed, 236 insertions(+), 200 deletions(-) create mode 100644 drivers/acpi/processor_pdc.c -- 1.7.9.5

10 years, 9 months

4
12
0 0

[PATCH 0/4] Clean up ACPI core to prepare for running ACPI on ARM64

by Hanjun Guo

This patch set have no function change for x86 and ia64 and just do some clean up to prepare for running ACPI on ARM64. This patch set is splited out from the patch set [1] "[PATCH v4 00/13] Enable ACPI on ARM64 in Kconfig" and hope it can be merged first before ARM64 ACPI core patches. [1]: https://lkml.org/lkml/2014/6/26/627 Graeme Gregory (2): ACPI: ARM64 does not have a BIOS add config for BIOS table scan. ACPI: Don't use acpi_lapic in ACPI core code Hanjun Guo (2): ACPI / processor: Introduce ARCH_HAS_ACPI_PDC ACPI: Make EC debugfs depend on X86 || IA64 in Kconfig arch/ia64/Kconfig | 2 + arch/ia64/include/asm/acpi.h | 5 + arch/x86/Kconfig | 2 + arch/x86/include/asm/acpi.h | 5 + drivers/acpi/Kconfig | 14 +++ drivers/acpi/Makefile | 1 + drivers/acpi/acpi_processor.c | 2 +- drivers/acpi/internal.h | 5 + drivers/acpi/osl.c | 4 +- drivers/acpi/processor_core.c | 198 --------------------------------------- drivers/acpi/processor_pdc.c | 206 +++++++++++++++++++++++++++++++++++++++++ 11 files changed, 244 insertions(+), 200 deletions(-) create mode 100644 drivers/acpi/processor_pdc.c -- 1.7.9.5

10 years, 10 months

2
12
0 0

[PATCH v4 0/3] APEI: Make APEI architecture independent.

by Tomasz Nowicki

APEI is currently implemented so that it depends on x86 hardware. The primary dependency is that GHES uses the x86 NMI for hardware error notification and MCE for memory error handling. These patches remove that dependency. Other APEI features such as error reporting via external IRQ, error serialization, or error injection, do not require changes to use them on non-x86 architectures. The following patch set eliminates the APEI Kconfig x86 dependency by making these changes: - treat NMI notification as GHES architecture - HAVE_ACPI_APEI_NMI - group and wrap around #ifdef CONFIG_HAVE_ACPI_APEI_NMI code which is used only for NMI path - identify architectural boxes and abstract it accordingly (tlb flush and MCE) - rework ioremap for both IRQ and NMI context NMI code is kept in ghes.c file since NMI and IRQ context are tightly coupled. Note, these patches introduce no functional changes for x86. The NMI notification feature is hard selected for x86. Architectures that want to use this feature should also provide NMI code infrastructure. V1->V2 - address Borislav's comment - abstract arch-specific calls instead of wrapping into the #ifdef V2->V3 - address Robert's comment - disable ACPI_APEI_NMI selection so that it is hard selected by arch Kconfig - rename ACPI_APEI_NMI to ARCH_HAS_ACPI_APEI_NMI V3->V4 - do not abstract NMI calls for archs which do not support it - merge some of patches to make review process easier Tomasz Nowicki (3): apei, mce: Factor out APEI architecture specific MCE calls. acpi, apei, ghes: Make NMI error notification to be GHES architecture extension. acpi, apei, ghes: Factor out ioremap virtual memory for IRQ and NMI context. arch/x86/Kconfig | 2 + arch/x86/kernel/acpi/Makefile | 1 + arch/x86/kernel/acpi/apei.c | 62 +++++++++++++++ drivers/acpi/apei/Kconfig | 8 +- drivers/acpi/apei/apei-base.c | 13 ++++ drivers/acpi/apei/ghes.c | 173 ++++++++++++++++++++++++++--------------- drivers/acpi/apei/hest.c | 29 +------ include/acpi/apei.h | 4 + include/linux/nmi.h | 4 + 9 files changed, 204 insertions(+), 92 deletions(-) create mode 100644 arch/x86/kernel/acpi/apei.c -- 1.7.9.5

10 years, 10 months

2
8
0 0

[PATCH v4 00/13] Enable ACPI on ARM64 in Kconfig

by Hanjun Guo

This patch set is the first part of ARM64 ACPI core patches to running ACPI on ARM64, it just handle some compile errors when ACPI is introduced to ARM64 platform and enable ACPI on ARM64 in Kconfig. Following core patch sets for ACPI based SMP/GIC/Arch Timer initialization to enable ACPI on ARM64 are under interally review and will send out when ACPI 5.1 is released. patch 1~3 are cleanups for ACPI core; patch 4~13 are arch dependent code for ARM64 ACPI; This patch set is based on linux-next branch of Rafael's linux-pm tree, and PCI patches for ARM64 from Liviu: Support for creating generic host_bridge from device tree https://lkml.org/lkml/2014/3/14/279 Add support for PCI in AArch64 http://comments.gmane.org/gmane.linux.ports.arm.kernel/309392 Changes since v3: - Introduce three new patches - acpi: arm64 does not have a BIOS add config for BIOS table scan - ACPI: Don't use acpi_lapic in ACPI core code - ARM64 / ACPI: if we chose to boot from acpi then disable FDT - Rebase on the latest linux-next branch of Rafael's tree, and introduce asm/acenv.h for ARM64; - Introduce ARCH_HAS_ACPI_PDC to move all the _PDC related code to a single place and make x86 and ia64 select ARCH_HAS_ACPI_PDC; - Fix some checpatch warning; - Fix broken Signed-off-by chain; - Remove duplicate interface macros for ACPICA pointed out by Mark Rutland and Zheng Lv; - Redefine ACPI_FLUSH_CPU_CACHE(); - Stub out some PCI functions suggested by Arnd and already merged into 3.16 Comments still need to be addressed: - Empty PCI implementation in arch/arm64 which suggested by Arnd; - suspend and sleep on ARM64 platform pointed out by Lorenzo; Changes since v2: - Make ACPI depend on PCI on ARM64 - rework all the patches and seperate some of the patches into fine-grained, and add some comments and changelog to make it easier for review. Al Stone (3): ARM64 / ACPI: Introduce arm-core.c and its related head file ARM64 / ACPI: Introduce early_param for "acpi" ARM64 / ACPI: Select ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled on ARM64 Graeme Gregory (6): acpi: arm64 does not have a BIOS add config for BIOS table scan. ACPI: Don't use acpi_lapic in ACPI core code ARM64 : Add dummy asm/cpu.h ARM64 / ACPI: Introduce lowlevel suspend function ARM64 / ACPI: if we chose to boot from acpi then disable FDT ARM64 / ACPI: Enable ARM64 in Kconfig Hanjun Guo (4): ACPI / processor: Introduce ARCH_HAS_ACPI_PDC ARM64 / ACPI: Introduce arch_fix_phys_package_id() for cpu topology ARM64 / ACPI: Introduce PCI functions for ACPI on ARM64 ACPI: Make EC debugfs depend on X86 || IA64 in Kconfig Documentation/kernel-parameters.txt | 3 +- arch/arm64/Kconfig | 3 + arch/arm64/include/asm/acenv.h | 18 +++ arch/arm64/include/asm/acpi.h | 61 +++++++++++ arch/arm64/include/asm/cpu.h | 11 ++ arch/arm64/include/asm/pci.h | 6 + arch/arm64/include/asm/topology.h | 2 + arch/arm64/kernel/pci.c | 28 +++++ arch/arm64/kernel/setup.c | 7 +- arch/arm64/kernel/topology.c | 14 +++ arch/ia64/Kconfig | 2 + arch/ia64/include/asm/acpi.h | 5 + arch/x86/Kconfig | 2 + arch/x86/include/asm/acpi.h | 5 + drivers/acpi/Kconfig | 19 +++- drivers/acpi/Makefile | 3 + drivers/acpi/acpi_processor.c | 2 +- drivers/acpi/internal.h | 5 + drivers/acpi/osl.c | 4 +- drivers/acpi/plat/Makefile | 1 + drivers/acpi/plat/arm-core.c | 138 +++++++++++++++++++++++ drivers/acpi/processor_core.c | 198 --------------------------------- drivers/acpi/processor_pdc.c | 206 +++++++++++++++++++++++++++++++++++ 23 files changed, 539 insertions(+), 204 deletions(-) create mode 100644 arch/arm64/include/asm/acenv.h create mode 100644 arch/arm64/include/asm/acpi.h create mode 100644 arch/arm64/include/asm/cpu.h create mode 100644 drivers/acpi/plat/Makefile create mode 100644 drivers/acpi/plat/arm-core.c create mode 100644 drivers/acpi/processor_pdc.c -- 1.7.9.5

10 years, 10 months

5
23
0 0

[RFC v2 0/3] ACPI Platform Communication Channel driver

by Ashwin Chaugule

Hello, This patchset adds initial support for the PCC (Platform Communication Channel) interface as described in the current ACPI 5.0a spec. See Section 14 of the ACPI spec - http://acpi.info/DOWNLOADS/ACPI_5_Errata%20A.pdf for more details on how PCC works. In brief PCC (Platform Communication Channel) is a generic means for PCC clients, to talk to the firmware. The PCC register space is typically memory mapped IO and uses a doorbell mechanism to communicate synchronously from the OS to the firmware. The PCC driver is completely agnostic to the protocol implemented by the PCC clients. It only implements the enumeration of PCC channels and the low level transport mechanism and leaves the rest to the PCC clients. The PCC is meant to be useable in the future by clients such as CPPC (Collaborative Processor Performance Control), RAS (Reliability, Availability and Serviceability) and MPST (Memory Power State Tables) and possibly others. While the PCC clients will come as following patches whenever they're ready, I wanted to get feedback on this common driver and hope that it could be merged upstream. This should hopefully help various folks that are working on drivers that rely on the PCC interface. Cheers, Ashwin === Testing Methodology === The PCC test driver in [2/2] is a simple driver that was used to demonstrate how PCC clients would use the PCC driver. The PCC driver was tested by sending multiple PCC READS and PCC WRITES across a shared memory region on an MSM ARMv7 platform. This memory is shared between an apps processor and a power controller processor. So, one end of the PCC channel is the PCC test driver running on the apps processor and the other end is a debugger script (running on a JTAG debugger) thats attached to the power processor. The debugger script is busy looping on the doorbell address waiting for a bit to flip. This bit indicates a synchronous communication from the apps processor. The doorbell is rung when the OS sends a PCC READ or PCC WRITE command. The PCC communication channel is simply a few fake 32 bit registers that are incremented by the OS and the debugger script. The OS increments the registers and then sends the PCC WRITE command. On a PCC READ, the script increments these registers and then OS reads them back. The values are always incremented by 1 by either end, so we know what value to expect for each PCC READ/WRITE. === Changelog === Changes since V1: - Integration with Mailbox framework - https://lkml.org/lkml/2014/5/15/49 Ashwin Chaugule (3): Mailbox: Add support for ACPI ACPI: Add support for Platform Communication Channel PCC test driver drivers/acpi/Makefile | 2 +- drivers/acpi/pcc-test.c | 208 ++++++++++++++++++++++++++++++++++ drivers/acpi/pcc.c | 225 +++++++++++++++++++++++++++++++++++++ drivers/mailbox/Kconfig | 11 ++ drivers/mailbox/mailbox.c | 155 ++++++++++++++++--------- include/linux/mailbox_client.h | 3 + include/linux/mailbox_controller.h | 6 + 7 files changed, 557 insertions(+), 53 deletions(-) create mode 100644 drivers/acpi/pcc-test.c create mode 100644 drivers/acpi/pcc.c -- 1.8.3.2

10 years, 10 months

2
21
0 0

[PATCH v3 0/5] APEI: Make APEI architecture independent.

by Tomasz Nowicki

APEI is currently implemented so that it depends on x86 hardware. The primary dependency is that GHES uses the x86 NMI for hardware error notification and MCE for memory error handling. These patches remove that dependency. Other APEI features such as error reporting via external IRQ, error serialization, or error injection, do not require changes to use them on non-x86 architectures. The following patch set eliminates the APEI Kconfig x86 dependency by making these changes: - treat NMI notification as GHES feature - ARCH_HAS_ACPI_APEI_NMI - reorganize GHES notification type init/deinitialization so that we can decide in run time whether NMI is supported or not - identify architectural boxes and abstract it accordingly (NMI and MCE) - rework ioremap for both IRQ and NMI context NMI code is kept in ghes.c file since NMI and IRQ context are tightly coupled. Note, these patches introduce no functional changes for x86. The NMI notification feature is hard selected for x86. Architectures that want to use this feature should also provide NMI code infrastructure. V1->V2 - address Borislav's comment - abstract arch-specific calls instead of wrapping into the #ifdef V2->V3 - address Robert's comment - disable ACPI_APEI_NMI selection so that it is hard selected by arch Kconfig - rename ACPI_APEI_NMI to ARCH_HAS_ACPI_APEI_NMI Tomasz Nowicki (5): apei, mce: Factor out APEI architecture specific MCE calls. acpi, apei, ghes: Introduce ARCH_HAS_ACPI_APEI_NMI to make NMI error notification a GHES feature. acpi, apei, ghes: Introduce more generic mechanism to init/deinit GHES error notifications. apei, ghes, nmi: Factor out NMI arch-specific calls. acpi, apei, ghes: Factor out ioremap virtual memory for IRQ and NMI context. arch/x86/Kconfig | 1 + arch/x86/kernel/acpi/Makefile | 1 + arch/x86/kernel/acpi/apei.c | 87 ++++++++++++ drivers/acpi/apei/Kconfig | 8 +- drivers/acpi/apei/apei-base.c | 32 +++++ drivers/acpi/apei/ghes.c | 301 +++++++++++++++++++++++++---------------- drivers/acpi/apei/hest.c | 29 +--- include/acpi/apei.h | 11 ++ 8 files changed, 327 insertions(+), 143 deletions(-) create mode 100644 arch/x86/kernel/acpi/apei.c -- 1.7.9.5

10 years, 10 months

3
18
0 0

leg-kernel tag leg-20140614.0 released

by Graeme Gregory

The leg-kernel release has been made and tagged as leg-20140614.0 This is based on mainline kernel v3.15 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: https://git.linaro.org/leg/acpi/leg-kernel.git/commit/380fd57c0626a74594446… Notes :-

10 years, 10 months

1
0
0 0

[PATCH v2 0/5] APEI: Make APEI architecture independent.

by Tomasz Nowicki

APEI is currently implemented so that it depends on x86 hardware. The primary dependency is that GHES uses the x86 NMI for hardware error notification and MCE for memory error handling. These patches remove that dependency. Other APEI features such as error reporting via external IRQ, error serialization, or error injection, do not require changes to use them on non-x86 architectures. The following patch set eliminates the APEI Kconfig x86 dependency by making these changes: - treat NMI notification as GHES feature - CONFIG_ACPI_APEI_NMI - reorganize GHES notification type init/deinitialization so that we can decide in run time whether NMI is supported or not - identify architectural boxes and abstract it accordingly (NMI and MCE) - rework ioremap for both IRQ and NMI context NMI code is kept in ghes.c file since NMI and IRQ context are tightly coupled. Note, these patches introduce no functional changes for x86. The NMI notification feature is selected for x86 by default. Architectures that want to use this feature should also provide NMI code infrastructure. V1->V2 - address Borislav comment - abstract arch-specific calls instead of wrapping into the #ifdef Tomasz Nowicki (5): apei, mce: Factor out APEI architecture specific MCE calls. acpi, apei, ghes: Introduce ACPI_APEI_NMI to make NMI error notification a GHES feature. acpi, apei, ghes: Introduce more generic mechanism to init/deinit GHES error notifications. apei, ghes, nmi: Factor out NMI arch-specific calls. acpi, apei, ghes: Factor out ioremap virtual memory for IRQ and NMI context. arch/x86/kernel/acpi/Makefile | 1 + arch/x86/kernel/acpi/apei.c | 87 ++++++++++++ drivers/acpi/apei/Kconfig | 10 +- drivers/acpi/apei/apei-base.c | 32 +++++ drivers/acpi/apei/ghes.c | 301 +++++++++++++++++++++++++---------------- drivers/acpi/apei/hest.c | 26 +--- include/acpi/apei.h | 11 ++ 7 files changed, 328 insertions(+), 140 deletions(-) create mode 100644 arch/x86/kernel/acpi/apei.c -- 1.7.9.5

10 years, 11 months

2
10
0 0

[RFC PATCH 0/3] ACPI: Add vexpress-sysreg

by naresh.bhat＠linaro.org

From: Naresh Bhat <naresh.bhat(a)linaro.org> Add vexpress sysreg probe support, platform ID and remove dts binding. Logs on the v8 model are as below root@genericarmv8:/sys# find . -name LINA0009* ./bus/acpi/devices/LINA0009:00 ./bus/platform/devices/LINA0009:00 ./bus/platform/drivers/vexpress-sysreg/LINA0009:00 ./devices/platform/LINA0009:00 ./devices/LNXSYSTM:00/device:00/ACPI0004:01/ACPI0004:02/LINA0009:00 root@genericarmv8:/sys# Naresh Bhat (3): v2m_sysreg: Add ACPI probing for SYSREG ACPI: Add vexpress sysreg platform ID arm64: dts: remove the vexpress-sysreg binding arch/arm64/boot/dts/foundation-v8-acpi.dts | 6 +++--- drivers/acpi/acpi_platform.c | 3 ++- drivers/mfd/vexpress-sysreg.c | 9 +++++++++ 3 files changed, 14 insertions(+), 4 deletions(-) -- 1.7.9.5

10 years, 11 months

5
7
0 0

[PATCH] acpi: arm64 does not have a BIOS add config for BIOS table scan.

by Graeme Gregory

With the addition of ARM64 that does not have a traditional BIOS to scan add a config option which is selected on x86 and ia64 to do the traditional BIOS scanning for tables. Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org> --- arch/ia64/Kconfig | 1 + arch/x86/Kconfig | 1 + drivers/acpi/Kconfig | 3 +++ drivers/acpi/osl.c | 4 +++- 4 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index 12c3afe..42a210f6 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig @@ -46,6 +46,7 @@ config IA64 select MODULES_USE_ELF_RELA select ARCH_USE_CMPXCHG_LOCKREF select HAVE_ARCH_AUDITSYSCALL + select ACPI_SCAN_BIOS_NOT_EFI default y help The Itanium Processor Family is Intel's 64-bit successor to diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 25d2c6f..d89c6060 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -130,6 +130,7 @@ config X86 select HAVE_CC_STACKPROTECTOR select GENERIC_CPU_AUTOPROBE select HAVE_ARCH_AUDITSYSCALL + select ACPI_SCAN_BIOS_NOT_EFI config INSTRUCTION_DECODER def_bool y diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index d726e17..1550ea8 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -40,6 +40,9 @@ menuconfig ACPI <http://www.acpi.info> <http://www.uefi.org/acpi/specs> +config ACPI_SCAN_BIOS_NOT_EFI + bool + if ACPI config ACPI_SLEEP diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c index 147bc1b..54f8247 100644 --- a/drivers/acpi/osl.c +++ b/drivers/acpi/osl.c @@ -258,12 +258,14 @@ acpi_physical_address __init acpi_os_get_root_pointer(void) "System description tables not found\n"); return 0; } - } else { + } else if (IS_ENABLED(CONFIG_ACPI_SCAN_BIOS_NOT_EFI)) { acpi_physical_address pa = 0; acpi_find_root_pointer(&pa); return pa; } + + return 0; } /* Must be called with 'acpi_ioremap_lock' or RCU read lock held. */ -- 2.0.0

10 years, 11 months

3
3
0 0

leg-kernel tag leg-20140603.0 released

by Graeme Gregory

The leg-kernel release has been made and tagged as leg-20140603.0 This is based on mainline kernel v3.15-rc8 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: http://git.linaro.org/leg/acpi/leg-kernel.git/commit/379f632a429b7d9768efd0… Notes :- This release contains the PCC driver written by Ashwin Chaugule for testing.

10 years, 11 months

1
0
0 0

[RFC 0/2] Experimental support for PCC and CPPC

by Ashwin Chaugule

This series contains experimental patchwork for PCC and CPPC as defined in the current ACPI5.0a spec. The PCC patch was tested on an ARMv7 platform and on a hacked up PCC emulator. The CPPC part is only compile tested. Both are very much a WIP. Any feedback and help with testing would be highly appreciated! Ashwin Chaugule (2): ACPI: Add support for Platform Communication Channel CPPC: Initial support for Collaborative Processor Performance Control arch/arm64/Kconfig | 2 + drivers/acpi/Kconfig | 10 ++ drivers/acpi/Makefile | 2 +- drivers/acpi/pcc.c | 209 +++++++++++++++++++++++++++++ drivers/cpufreq/Kconfig | 11 +- drivers/cpufreq/Makefile | 1 + drivers/cpufreq/cppc-cpufreq.c | 298 +++++++++++++++++++++++++++++++++++++++++ 7 files changed, 531 insertions(+), 2 deletions(-) create mode 100644 drivers/acpi/pcc.c create mode 100644 drivers/cpufreq/cppc-cpufreq.c -- 1.8.3.2

10 years, 11 months

3
6
0 0

[RFC 0/2] ACPI Platform Communication Channel driver

by Ashwin Chaugule

Hello, This patchset adds initial support for the PCC (Platform Communication Channel) interface as described in the current ACPI 5.0a spec. See Section 14 of the ACPI spec - http://acpi.info/DOWNLOADS/ACPI_5_Errata%20A.pdf for more details on how PCC works. In brief PCC (Platform Communication Channel) is a generic means for PCC clients, to talk to the firmware. The PCC register space is typically memory mapped IO and uses a doorbell mechanism to communicate synchronously from the OS to the firmware. The PCC driver is completely agnostic to the protocol implemented by the PCC clients. It only implements the enumeration of PCC channels and the low level transport mechanism and leaves the rest to the PCC clients. The PCC is meant to be useable in the future by clients such as CPPC (Collaborative Processor Performance Control), RAS (Reliability, Availability and Serviceability) and MPST (Memory Power State Tables) and possibly others. While the PCC clients will come as following patches whenever they're ready, I wanted to get feedback on this common driver and hope that it could be merged upstream. This should hopefully help various folks that are working on drivers that rely on the PCC interface. Cheers, Ashwin === Testing Methodology === The PCC test driver in [2/2] is a simple driver that was used to demonstrate how PCC clients would use the PCC driver. The PCC driver was tested by sending multiple PCC READS and PCC WRITES across a shared memory region on an MSM ARMv7 platform. This memory is shared between an apps processor and a power controller processor. So, one end of the PCC channel is the PCC test driver running on the apps processor and the other end is a debugger script (running on a JTAG debugger) thats attached to the power processor. The debugger script is busy looping on the doorbell address waiting for a bit to flip. This bit indicates a synchronous communication from the apps processor. The doorbell is rung when the OS sends a PCC READ or PCC WRITE command. The PCC communication channel is simply a few fake 32 bit registers that are incremented by the OS and the debugger script. The OS increments the registers and then sends the PCC WRITE command. On a PCC READ, the script increments these registers and then OS reads them back. The values are always incremented by 1 by either end, so we know what value to expect for each PCC READ/WRITE. Ashwin Chaugule (2): ACPI: Add support for Platform Communication Channel PCC Test driver drivers/acpi/Kconfig | 10 +++ drivers/acpi/Makefile | 2 +- drivers/acpi/pcc-test.c | 172 +++++++++++++++++++++++++++++++++++++++++++ drivers/acpi/pcc.c | 192 ++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 375 insertions(+), 1 deletion(-) create mode 100644 drivers/acpi/pcc-test.c create mode 100644 drivers/acpi/pcc.c -- 1.8.3.2

10 years, 11 months

4
7
0 0

[PATCH] PCI: Turn pcibios_penalize_isa_irq() into __weak function

by Hanjun Guo

pcibios_penalize_isa_irq() is only useful for x86 now, and legacy ISA is not used by some architectures, so make pcibios_penalize_isa_irq() as __weak function to simplify the code, this will prevent new platform from introducing dummy stub function for pcibios_penalize_isa_irq() too. Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org> --- arch/alpha/include/asm/pci.h | 5 ----- arch/arm/include/asm/pci.h | 5 ----- arch/blackfin/include/asm/pci.h | 5 ----- arch/cris/include/asm/pci.h | 1 - arch/frv/include/asm/pci.h | 2 -- arch/frv/mb93090-mb00/pci-irq.c | 4 ---- arch/ia64/include/asm/pci.h | 6 ------ arch/microblaze/include/asm/pci.h | 5 ----- arch/mips/include/asm/pci.h | 5 ----- arch/mn10300/include/asm/pci.h | 1 - arch/mn10300/unit-asb2305/pci-irq.c | 4 ---- arch/parisc/include/asm/pci.h | 5 ----- arch/powerpc/include/asm/pci.h | 5 ----- arch/sh/include/asm/pci.h | 5 ----- arch/sparc/include/asm/pci_32.h | 5 ----- arch/sparc/include/asm/pci_64.h | 5 ----- arch/unicore32/include/asm/pci.h | 5 ----- arch/x86/include/asm/pci.h | 1 - arch/xtensa/include/asm/pci.h | 5 ----- drivers/pci/pci.c | 11 +++++++++++ include/linux/pci.h | 1 + 21 files changed, 12 insertions(+), 79 deletions(-) diff --git a/arch/alpha/include/asm/pci.h b/arch/alpha/include/asm/pci.h index d01afb7..f7f680f 100644 --- a/arch/alpha/include/asm/pci.h +++ b/arch/alpha/include/asm/pci.h @@ -59,11 +59,6 @@ struct pci_controller { extern void pcibios_set_master(struct pci_dev *dev); -extern inline void pcibios_penalize_isa_irq(int irq, int active) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - /* IOMMU controls. */ /* The PCI address space does not equal the physical memory address space. diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h index 680a83e..7e95d85 100644 --- a/arch/arm/include/asm/pci.h +++ b/arch/arm/include/asm/pci.h @@ -31,11 +31,6 @@ static inline int pci_proc_domain(struct pci_bus *bus) } #endif /* CONFIG_PCI_DOMAINS */ -static inline void pcibios_penalize_isa_irq(int irq, int active) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - /* * The PCI address space does equal the physical memory address space. * The networking and block device layers use this boolean for bounce diff --git a/arch/blackfin/include/asm/pci.h b/arch/blackfin/include/asm/pci.h index 74352c4..c737909 100644 --- a/arch/blackfin/include/asm/pci.h +++ b/arch/blackfin/include/asm/pci.h @@ -10,9 +10,4 @@ #define PCIBIOS_MIN_IO 0x00001000 #define PCIBIOS_MIN_MEM 0x10000000 -static inline void pcibios_penalize_isa_irq(int irq) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - #endif /* _ASM_BFIN_PCI_H */ diff --git a/arch/cris/include/asm/pci.h b/arch/cris/include/asm/pci.h index f666734..cc2399c 100644 --- a/arch/cris/include/asm/pci.h +++ b/arch/cris/include/asm/pci.h @@ -20,7 +20,6 @@ void pcibios_config_init(void); struct pci_bus * pcibios_scan_root(int bus); void pcibios_set_master(struct pci_dev *dev); -void pcibios_penalize_isa_irq(int irq); struct irq_routing_table *pcibios_get_irq_routing_table(void); int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq); diff --git a/arch/frv/include/asm/pci.h b/arch/frv/include/asm/pci.h index ef03baf..2035a4d 100644 --- a/arch/frv/include/asm/pci.h +++ b/arch/frv/include/asm/pci.h @@ -24,8 +24,6 @@ struct pci_dev; extern void pcibios_set_master(struct pci_dev *dev); -extern void pcibios_penalize_isa_irq(int irq); - #ifdef CONFIG_MMU extern void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *dma_handle); extern void consistent_free(void *vaddr); diff --git a/arch/frv/mb93090-mb00/pci-irq.c b/arch/frv/mb93090-mb00/pci-irq.c index c677b9d..1c35c93 100644 --- a/arch/frv/mb93090-mb00/pci-irq.c +++ b/arch/frv/mb93090-mb00/pci-irq.c @@ -55,10 +55,6 @@ void __init pcibios_fixup_irqs(void) } } -void __init pcibios_penalize_isa_irq(int irq) -{ -} - void pcibios_enable_irq(struct pci_dev *dev) { pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); diff --git a/arch/ia64/include/asm/pci.h b/arch/ia64/include/asm/pci.h index 7d41cc0..52af5ed 100644 --- a/arch/ia64/include/asm/pci.h +++ b/arch/ia64/include/asm/pci.h @@ -50,12 +50,6 @@ struct pci_dev; extern unsigned long ia64_max_iommu_merge_mask; #define PCI_DMA_BUS_IS_PHYS (ia64_max_iommu_merge_mask == ~0UL) -static inline void -pcibios_penalize_isa_irq (int irq, int active) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - #include <asm-generic/pci-dma-compat.h> #ifdef CONFIG_PCI diff --git a/arch/microblaze/include/asm/pci.h b/arch/microblaze/include/asm/pci.h index 935f9be..3355240 100644 --- a/arch/microblaze/include/asm/pci.h +++ b/arch/microblaze/include/asm/pci.h @@ -44,11 +44,6 @@ struct pci_dev; */ #define pcibios_assign_all_busses() 0 -static inline void pcibios_penalize_isa_irq(int irq, int active) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - #ifdef CONFIG_PCI extern void set_pci_dma_ops(struct dma_map_ops *dma_ops); extern struct dma_map_ops *get_pci_dma_ops(void); diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index 12d6842..974b0e3 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h @@ -73,11 +73,6 @@ extern unsigned long PCIBIOS_MIN_MEM; extern void pcibios_set_master(struct pci_dev *dev); -static inline void pcibios_penalize_isa_irq(int irq, int active) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - #define HAVE_PCI_MMAP extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, diff --git a/arch/mn10300/include/asm/pci.h b/arch/mn10300/include/asm/pci.h index 1663238..5f70af2 100644 --- a/arch/mn10300/include/asm/pci.h +++ b/arch/mn10300/include/asm/pci.h @@ -48,7 +48,6 @@ extern void unit_pci_init(void); #define PCIBIOS_MIN_MEM 0xB8000000 void pcibios_set_master(struct pci_dev *dev); -void pcibios_penalize_isa_irq(int irq); /* Dynamic DMA mapping stuff. * i386 has everything mapped statically. diff --git a/arch/mn10300/unit-asb2305/pci-irq.c b/arch/mn10300/unit-asb2305/pci-irq.c index 77439da..fcb28ce 100644 --- a/arch/mn10300/unit-asb2305/pci-irq.c +++ b/arch/mn10300/unit-asb2305/pci-irq.c @@ -40,10 +40,6 @@ void __init pcibios_fixup_irqs(void) } } -void __init pcibios_penalize_isa_irq(int irq) -{ -} - void pcibios_enable_irq(struct pci_dev *dev) { pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); diff --git a/arch/parisc/include/asm/pci.h b/arch/parisc/include/asm/pci.h index 4651540..20df2b0 100644 --- a/arch/parisc/include/asm/pci.h +++ b/arch/parisc/include/asm/pci.h @@ -215,11 +215,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, } #endif -static inline void pcibios_penalize_isa_irq(int irq, int active) -{ - /* We don't need to penalize isa irq's */ -} - static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) { return channel ? 15 : 14; diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h index 95145a1..1b0739b 100644 --- a/arch/powerpc/include/asm/pci.h +++ b/arch/powerpc/include/asm/pci.h @@ -46,11 +46,6 @@ struct pci_dev; #define pcibios_assign_all_busses() \ (pci_has_flag(PCI_REASSIGN_ALL_BUS)) -static inline void pcibios_penalize_isa_irq(int irq, int active) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - #define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) { diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h index bff96c2..5b45115 100644 --- a/arch/sh/include/asm/pci.h +++ b/arch/sh/include/asm/pci.h @@ -70,11 +70,6 @@ extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, enum pci_mmap_state mmap_state, int write_combine); extern void pcibios_set_master(struct pci_dev *dev); -static inline void pcibios_penalize_isa_irq(int irq, int active) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - /* Dynamic DMA mapping stuff. * SuperH has everything mapped statically like x86. */ diff --git a/arch/sparc/include/asm/pci_32.h b/arch/sparc/include/asm/pci_32.h index dc50329..53e9b49 100644 --- a/arch/sparc/include/asm/pci_32.h +++ b/arch/sparc/include/asm/pci_32.h @@ -16,11 +16,6 @@ #define PCI_IRQ_NONE 0xffffffff -static inline void pcibios_penalize_isa_irq(int irq, int active) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - /* Dynamic DMA mapping stuff. */ #define PCI_DMA_BUS_IS_PHYS (0) diff --git a/arch/sparc/include/asm/pci_64.h b/arch/sparc/include/asm/pci_64.h index 1633b71..c6c7396 100644 --- a/arch/sparc/include/asm/pci_64.h +++ b/arch/sparc/include/asm/pci_64.h @@ -16,11 +16,6 @@ #define PCI_IRQ_NONE 0xffffffff -static inline void pcibios_penalize_isa_irq(int irq, int active) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - /* The PCI address space does not equal the physical memory * address space. The networking and block device layers use * this boolean for bounce buffer decisions. diff --git a/arch/unicore32/include/asm/pci.h b/arch/unicore32/include/asm/pci.h index f5e108f..654407e 100644 --- a/arch/unicore32/include/asm/pci.h +++ b/arch/unicore32/include/asm/pci.h @@ -18,11 +18,6 @@ #include <asm-generic/pci.h> #include <mach/hardware.h> /* for PCIBIOS_MIN_* */ -static inline void pcibios_penalize_isa_irq(int irq, int active) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - #ifdef CONFIG_PCI static inline void pci_dma_burst_advice(struct pci_dev *pdev, enum pci_dma_burst_strategy *strat, diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index 96ae4f4..0892ea0 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -68,7 +68,6 @@ void pcibios_config_init(void); void pcibios_scan_root(int bus); void pcibios_set_master(struct pci_dev *dev); -void pcibios_penalize_isa_irq(int irq, int active); struct irq_routing_table *pcibios_get_irq_routing_table(void); int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq); diff --git a/arch/xtensa/include/asm/pci.h b/arch/xtensa/include/asm/pci.h index 614be03..5d52dc4 100644 --- a/arch/xtensa/include/asm/pci.h +++ b/arch/xtensa/include/asm/pci.h @@ -22,11 +22,6 @@ extern struct pci_controller* pcibios_alloc_controller(void); -static inline void pcibios_penalize_isa_irq(int irq) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - /* Assume some values. (We should revise them, if necessary) */ #define PCIBIOS_MIN_IO 0x2000 diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 7325d43..57c330f 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1468,6 +1468,17 @@ void __weak pcibios_release_device(struct pci_dev *dev) {} */ void __weak pcibios_disable_device (struct pci_dev *dev) {} +/** + * pcibios_penalize_isa_irq - provide arch specific hooks when penalize isa irq + * @irq: isa irq to penalize + * @active: irq active or not + * + * Permits the platform to provide architecture specific functionality when + * penalize isa irq. This is the default implementation. Architecture + * implementations can override this. + */ +void __weak pcibios_penalize_isa_irq(int irq, int active) {} + static void do_pci_disable_device(struct pci_dev *dev) { u16 pci_command; diff --git a/include/linux/pci.h b/include/linux/pci.h index aab57b4..da8f7d5 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1579,6 +1579,7 @@ int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); int pcibios_add_device(struct pci_dev *dev); void pcibios_release_device(struct pci_dev *dev); +void pcibios_penalize_isa_irq(int irq, int active); #ifdef CONFIG_HIBERNATE_CALLBACKS extern struct dev_pm_ops pcibios_pm_ops; -- 1.7.9.5

10 years, 11 months

3
3
0 0

[PATCH 0/7] APEI: Make APEI architecture independent.

by Tomasz Nowicki

APEI is currently implemented so that it depends on x86 hardware. The primary dependency is that GHES uses the x86 NMI for hardware error notification. These patches remove that dependency. Other APEI features such as error reporting via external IRQ, error serialization, or error injection, do not require changes to use them on non-x86 architectures. The following patch set eliminates the APEI Kconfig x86 dependency by making these changes: - replace arch specific calls with more generic one - treat NMI notification as GHES feature - CONFIG_ACPI_APEI_NMI - isolate NMI related code - reorganize function logic NMI code is kept in ghes.c file since NMI and IRQ context are tightly coupled. Note, these patches introduce no functional changes for x86. The NMI notification feature is selected for x86 by default. Architectures that want to use this feature should also provide NMI code infrastructure. Tomasz Nowicki (7): apei, mce: Call MCE-specific code only for X86 architecture. acpi, apei, ghes: Introduce more generic mechanism to init/deinit GHES error notifications. ACPI, APEI, GHES: Introduce ACPI_NMI to make NMI error notification a GHES feature. acpi, apei, ghes: Factor out NMI error notification context. acpi, apei, ghes: Attach NMI init/deinit functions while CONFIG_ACPI_NMI is enabled. acpi, apei, ghes: Make unmapping functionality independent from architecture. acpi, apei, ghes: Factor out ioremap virtual memory for IRQ and NMI context. drivers/acpi/apei/Kconfig | 10 +- drivers/acpi/apei/ghes.c | 329 ++++++++++++++++++++++++++++----------------- drivers/acpi/apei/hest.c | 8 +- 3 files changed, 218 insertions(+), 129 deletions(-) -- 1.7.9.5

10 years, 11 months

4
32
0 0

[GIT PULL] PSCI v0.2 support and DT bindings

by Ashwin Chaugule

Hi Christoffer, Marc Please pull in the ARM and ARM64 PSCIv0.2 patchwork from the git branch below. These patches have been under review on LKAML since early March and are now ACK'd. Also, since these patches are dependent on the UAPI header file (uapi/linux/psci.h) added by the KVM PSCIv0.2 patchwork, it makes sense to submit the whole PSCIv0.2 patchwork (KVM and core) as one set. Cheers, Ashwin The following changes since commit 4447a208f7fc2e2dff8c6a8df2a1fd6dd72fb3e2: ARM/ARM64: KVM: Advertise KVM_CAP_ARM_PSCI_0_2 to user space (2014-04-30 04:18:58 -0700) are available in the git repository at: git://git.linaro.org/people/ashwin.chaugule/leg-kernel.git kvm-next-psci-v0.2 for you to fetch changes up to c814ca029e1015bb0ecec312f4bb9751ba1a711a: ARM: Check if a CPU has gone offline (2014-05-15 10:16:30 -0400) ---------------------------------------------------------------- Ashwin Chaugule (3): PSCI: Add initial support for PSCIv0.2 functions Documentation: devicetree: Add new binding for PSCIv0.2 ARM: Check if a CPU has gone offline Documentation/devicetree/bindings/arm/psci.txt | 37 +++- arch/arm/include/asm/psci.h | 7 +- arch/arm/kernel/psci.c | 196 +++++++++++++++++---- arch/arm/kernel/psci_smp.c | 33 ++++ arch/arm64/include/asm/cpu_ops.h | 2 + arch/arm64/include/asm/psci.h | 2 +- arch/arm64/kernel/psci.c | 231 +++++++++++++++++++++---- arch/arm64/kernel/smp.c | 22 +++ 8 files changed, 452 insertions(+), 78 deletions(-)

10 years, 11 months

3
2
0 0

[PATCH v10 0/3] PSCI v0.2 support and DT bindings

by Ashwin Chaugule

This patchset introduces some functions as defined in the PSCI v0.2 spec and a corresponding DT binding to differentiate it from previous PSCI versions. Since PSCIv0.2 has standard function IDs, it is possible to statically assign them rather than depend on values from DT. This patchset depends on the PSCI header (/uapi/linux/psci.h) introduced by http://www.spinics.net/lists/arm-kernel/msg319712.html which is now merged in the ARM KVM tree next branch. Changes in v10: - Documented explicit use of case dual PSCI bindings for hypervisors. - Corrected POWER_STATE macros as per new definitions. - Added arm64 cpu_kill cpu-op and tied it to psci affinity info. - Misc cleanups in prints. Changes in v9: - Rebased on top of KVM "next" - https://git.kernel.org/cgit/linux/kernel/git/kvmarm/kvmarm.git/log/?h=next Changes in v8: - Replace msleep(100) with 10 x msleep(10) Changes in v7: - Add two new functions: SYSTEM_OFF and SYSTEM_RESET as defined in PSCIv0.2. - Added a delay before calling cpu_kill to avoid race with cpu_die. Changes in v6: - rebase on top of uapi/linux/psci.h introduced by Anups patch http://www.spinics.net/lists/arm-kernel/msg319712.html - rebase on top of Catalins tree tip. Changes in v5: - Add uapi/linux/psci.h to kbuild - ret with err if PSCI_ID_VERSION is not implemented. Changes in v4: - Correct copyright banner format. - Check if PSCI Version ID is supported. - Add all PSCI RET codes in uapi header. - Explicitely ret 1 from psci_cpu_kill() Changes in v3: - Roll up common functionality for getting conduit method. - Remove #defines for ARM32 and ARM64 in uapi/linux/psci.h - Remove functions not supported by PSCI v0.1 - Misc cleanups. - Add PSCI_AFFINITY_INFO return types in uapi header. - Changed function names for PSCI v0.1 and PSCI v0.2 - Added copyright info to uapi header. - Fixed args to affinity_info call. - Fix typo in psci_init definition when PSCI is not defined. Changes in v2: - Add AFFINITY_INFO and MIGRATE_INFO_TYPE functions. - Add binding Documentation. - Add function to get PSCI version. - Add common #defines in uapi/linux/psci.h - Implement cpu_kill and check if CPU is dead via AFFINITY_INFO. - Misc cleanups. Changes in v1: - Add new binding "arm, psci-0.2" - Separate conduit and PSCI function assignment methods. Ashwin Chaugule (3): PSCI: Add initial support for PSCIv0.2 functions Documentation: devicetree: Add new binding for PSCIv0.2 ARM: Check if a CPU has gone offline Documentation/devicetree/bindings/arm/psci.txt | 37 +++- arch/arm/include/asm/psci.h | 7 +- arch/arm/kernel/psci.c | 196 +++++++++++++++++---- arch/arm/kernel/psci_smp.c | 33 ++++ arch/arm64/include/asm/cpu_ops.h | 2 + arch/arm64/include/asm/psci.h | 2 +- arch/arm64/kernel/psci.c | 231 +++++++++++++++++++++---- arch/arm64/kernel/smp.c | 22 +++ 8 files changed, 452 insertions(+), 78 deletions(-) -- 1.8.3.2

10 years, 12 months

2
6
0 0

[PATCH v9 0/3] PSCI v0.2 support and DT bindings

by Ashwin Chaugule

This patchset introduces some functions as defined in the PSCI v0.2 spec and a corresponding DT binding to differentiate it from previous PSCI versions. Since PSCIv0.2 has standard function IDs, it is possible to statically assign them rather than depend on values from DT. This patchset depends on the PSCI header (/uapi/linux/psci.h) introduced by http://www.spinics.net/lists/arm-kernel/msg319712.html which is now merged in the ARM KVM tree next branch. Changes in v9: - Rebased on top of KVM "next" - https://git.kernel.org/cgit/linux/kernel/git/kvmarm/kvmarm.git/log/?h=next Changes in v8: - Replace msleep(100) with 10 x msleep(10) Changes in v7: - Add two new functions: SYSTEM_OFF and SYSTEM_RESET as defined in PSCIv0.2. - Added a delay before calling cpu_kill to avoid race with cpu_die. Changes in v6: - rebase on top of uapi/linux/psci.h introduced by Anups patch http://www.spinics.net/lists/arm-kernel/msg319712.html - rebase on top of Catalins tree tip. Changes in v5: - Add uapi/linux/psci.h to kbuild - ret with err if PSCI_ID_VERSION is not implemented. Changes in v4: - Correct copyright banner format. - Check if PSCI Version ID is supported. - Add all PSCI RET codes in uapi header. - Explicitely ret 1 from psci_cpu_kill() Changes in v3: - Roll up common functionality for getting conduit method. - Remove #defines for ARM32 and ARM64 in uapi/linux/psci.h - Remove functions not supported by PSCI v0.1 - Misc cleanups. - Add PSCI_AFFINITY_INFO return types in uapi header. - Changed function names for PSCI v0.1 and PSCI v0.2 - Added copyright info to uapi header. - Fixed args to affinity_info call. - Fix typo in psci_init definition when PSCI is not defined. Changes in v2: - Add AFFINITY_INFO and MIGRATE_INFO_TYPE functions. - Add binding Documentation. - Add function to get PSCI version. - Add common #defines in uapi/linux/psci.h - Implement cpu_kill and check if CPU is dead via AFFINITY_INFO. - Misc cleanups. Changes in v1: - Add new binding "arm, psci-0.2" - Separate conduit and PSCI function assignment methods. Ashwin Chaugule (3): PSCI: Add initial support for PSCIv0.2 functions Documentation: devicetree: Add new binding for PSCIv0.2 ARM: Check if a CPU has gone offline Documentation/devicetree/bindings/arm/psci.txt | 35 ++++- arch/arm/include/asm/psci.h | 7 +- arch/arm/kernel/psci.c | 196 +++++++++++++++++++----- arch/arm/kernel/psci_smp.c | 31 ++++ arch/arm64/include/asm/psci.h | 2 +- arch/arm64/kernel/psci.c | 200 ++++++++++++++++++++----- 6 files changed, 393 insertions(+), 78 deletions(-) -- 1.8.3.2

10 years, 12 months

4
13
0 0

leg-kernel tag leg-20140430.0 released

by Graeme Gregory

The leg-kernel release has been made and tagged as leg-20140430.0 This is based on mainline kernel v3.15-rc3 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: https://git.linaro.org/leg/acpi/leg-kernel.git/commit/0a612ef9e654e1a94f65a… Notes :-

10 years, 12 months

3
4
0 0

leg-kernel tag leg-20140513.0 released

by Graeme Gregory

The leg-kernel release has been made and tagged as leg-20140513.0 This is based on mainline kernel v3.15-rc5 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: https://git.linaro.org/leg/acpi/leg-kernel.git/commit/4bfbe91b10e1d6438cdf7… Notes :-

10 years, 12 months

1
0
0 0

Re: [Linaro-acpi] [RFC 2/2] CPPC: Initial support for Collaborative Processor Performance Control

by Jonghwan Choi

Does it need a hardware change for using CPPC? > +static int cppc_cpufreq_target(struct cpufreq_policy *policy, > + unsigned int target_freq, > + unsigned int relation) > +{ > + unsigned int cpu = policy->cpu; > + struct cpc_desc *current_cpu_cpc = per_cpu(cpc_desc, cpu); > + struct cpufreq_freqs freqs; > + u16 status; > + > + freqs.old = policy->cur; > + freqs.new = target_freq; > + > + cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE); > + > + /* Set CPU Perf thresholds and current desired perf value. */ > + acpi_write(policy->max, &current_cpu_cpc->pcc_regs[MAX_PERF]); > + > + acpi_write(policy->min, &current_cpu_cpc->pcc_regs[MIN_PERF]); > + > + acpi_write(target_freq, &current_cpu_cpc->pcc_regs[DESIRED_PERF]); > + > + status = send_pcc_cmd(CMD_WRITE, 0, PCC_SUBSPACE_IDX, > comm_base_addr); > + if (status & CMD_COMPLETE) { > + pr_debug("Failed to set target CPU perf for CPU:%d, > status:%d\n", > + cpu, status); > + return -EINVAL; > + } > + > + return 0; > +} -> Don't need cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE)? > + /* Base address returned from PCC subspace desc needs to ioremap'd. > + * Used by the client to send/recv data from platform. > + */ > + comm_base_addr = ioremap_nocache(pcc_comm_base_addr, len); > + > + if (comm_base_addr) { ->Should be if (!comm_base_addr) ? > + pr_err("Could not map PCC communicate channel\n"); > + ret = -ENOMEM; > + goto out_err; > + } > + Thanks Best Regards.

10 years, 12 months

3
3
0 0

Question about FADT length

by Hanjun Guo

Hi, I ran into some compile errors when I was prototyping the code for the proposals in ASWG, it turns out that some field in FADT is changed and "reserved4[0]" used in ACPI_FADT_V2_SIZE will cause the error. So my question is that the length of very version of FADT is fixed, why not use a constant value for this puspose? Here is the code: /* * Sizes of the various flavors of FADT. We need to look closely * at the FADT length because the version number essentially tells * us nothing because of many BIOS bugs where the version does not * match the expected length. In other words, the length of the * FADT is the bottom line as to what the version really is. * * For reference, the values below are as follows: * FADT V1 size: 0x074 * FADT V2 size: 0x084 * FADT V3 size: 0x0F4 * FADT V4 size: 0x0F4 * FADT V5 size: 0x10C */ #define ACPI_FADT_V1_SIZE (u32) (ACPI_FADT_OFFSET (flags) + 4) #define ACPI_FADT_V2_SIZE (u32) (ACPI_FADT_OFFSET (reserved4[0]) + 3) #define ACPI_FADT_V3_SIZE (u32) (ACPI_FADT_OFFSET (sleep_control)) #define ACPI_FADT_V5_SIZE (u32) (sizeof (struct acpi_table_fadt)) Why not #define ACPI_FADT_V1_SIZE 0x074 ? Did I miss something? any clarify will be appreciated :) Thanks Hanjun

10 years, 12 months

2
3
0 0

[PATCH] ACPI / PCI: Stub out pci_acpi_crs_quirks() and make it x86 specific

by Hanjun Guo

For pci_acpi_crs_quirks(), ia64 already doesn't use it, and we can not foresee it should be used in ARM64, so stub out pci_acpi_crs_quirks() to avoid introducing platform specific dummy stub function. Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org> --- arch/ia64/include/asm/acpi.h | 1 - include/acpi/acpi_drivers.h | 5 +++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/ia64/include/asm/acpi.h b/arch/ia64/include/asm/acpi.h index d651102..97cb160 100644 --- a/arch/ia64/include/asm/acpi.h +++ b/arch/ia64/include/asm/acpi.h @@ -92,7 +92,6 @@ ia64_acpi_release_global_lock (unsigned int *lock) #endif #define acpi_processor_cstate_check(x) (x) /* no idle limits on IA64 :) */ static inline void disable_acpi(void) { } -static inline void pci_acpi_crs_quirks(void) { } #ifdef CONFIG_IA64_GENERIC const char *acpi_get_sysname (void); diff --git a/include/acpi/acpi_drivers.h b/include/acpi/acpi_drivers.h index d504613..ea6428b 100644 --- a/include/acpi/acpi_drivers.h +++ b/include/acpi/acpi_drivers.h @@ -96,7 +96,12 @@ struct pci_dev *acpi_get_pci_dev(acpi_handle); /* Arch-defined function to add a bus to the system */ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root); + +#ifdef CONFIG_X86 void pci_acpi_crs_quirks(void); +#else +static inline void pci_acpi_crs_quirks(void) { } +#endif /* -------------------------------------------------------------------------- Processor -- 1.7.9.5

11 years

3
3
0 0

[PATCH v3 part1 00/11] Enable ACPI on ARM64 in Kconfig

by Hanjun Guo

This patch set is the first part of ARM64 ACPI core patches to running ACPI on ARM64, it just handle some compile errors when ACPI is introduced to ARM64 platform and enable ACPI on ARM64 in Kconfig. Following core patch sets for ACPI based SMP/GIC/Arch Timer initialization to enable ACPI on ARM64 are still waited untill some ACPI proposals approved by ASWG. This patch set is based on 3.15-rc2 and PCI patches for ARM64 from Liviu: Support for creating generic host_bridge from device tree https://lkml.org/lkml/2014/3/14/279 Add support for PCI in AArch64 http://comments.gmane.org/gmane.linux.ports.arm.kernel/309392 We did 3 review cycles inside linaro ACPI team, and I had compiled all the patches ok on arm64 with: - CONFIG_ACPI=n and CONFIG_PCI=n; - CONFIG_ACPI=n and CONFIG_PCI=y; - CONFIG_ACPI=y and CONFIG_PCI=y; And compiled ok on x86. Changes since v2: - Make ACPI depend on PCI on ARM64 - rework all the patches and seperate some of the patches into fine-grained, and add some comments and changelog to make it easier for review. Hanjun Guo (11): ACPI / processor: Rework _PDC related stuff to make it more arch-independent ARM64 / ACPI: Introduce the skeleton of _PDC related for ARM64 ARM64 : Add dummy asm/cpu.h ARM64 / ACPI: Introduce arm-core.c and its related head file ARM64 / ACPI: Introduce early_param for "acpi" ARM64 / ACPI: Introduce lowlevel suspend function ARM64 / ACPI: Introduce arch_fix_phys_package_id() for cpu topology ARM64 / ACPI: Introduce PCI functions for ACPI on ARM64 ARM64 / ACPI: Enable ARM64 in Kconfig ARM64 / ACPI: Select ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled on ARM64 ACPI: Make EC depend on X86 || IA64 in Kconfig arch/arm64/Kconfig | 3 + arch/arm64/include/asm/acpi.h | 94 +++++++++++++++++++++++++ arch/arm64/include/asm/cpu.h | 11 +++ arch/arm64/include/asm/pci.h | 11 +++ arch/arm64/include/asm/topology.h | 2 + arch/arm64/kernel/pci.c | 34 +++++++++ arch/arm64/kernel/setup.c | 4 ++ arch/arm64/kernel/topology.c | 14 ++++ arch/ia64/include/asm/acpi.h | 5 +- arch/ia64/kernel/acpi.c | 15 ++++ arch/x86/include/asm/acpi.h | 19 +---- arch/x86/kernel/acpi/cstate.c | 27 ++++++++ drivers/acpi/Kconfig | 6 +- drivers/acpi/Makefile | 2 + drivers/acpi/plat/Makefile | 1 + drivers/acpi/plat/arm-core.c | 138 +++++++++++++++++++++++++++++++++++++ drivers/acpi/processor_core.c | 19 +---- 17 files changed, 363 insertions(+), 42 deletions(-) create mode 100644 arch/arm64/include/asm/acpi.h create mode 100644 arch/arm64/include/asm/cpu.h create mode 100644 drivers/acpi/plat/Makefile create mode 100644 drivers/acpi/plat/arm-core.c -- 1.7.9.5

11 years

8
38
0 0

[PATCH linaro-acpi] [RFC 7/7] acpi: Allow ACPI_PROCESSOR for ARM64

by Jonghwan Choi

Enable C-State support for ARM64. Signed-off-by: Jonghwan Choi <jhbird.choi(a)samsung.com> --- drivers/acpi/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index ff5c83c..e434a3e 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -143,7 +143,7 @@ config ACPI_PROCESSOR tristate "Processor" select THERMAL select CPU_IDLE - depends on X86 || IA64 + depends on X86 || IA64 || ARM64 default y help This driver installs ACPI as the idle handler for Linux and uses -- 1.7.10.4

11 years

1
0
0 0

[PATCH linaro-acpi] [RFC 6/7] acpi: Add ACPI cpuidle support for ARM

by Jonghwan Choi

To support C-State for arm64, added arch-specific function and FFH(Functional Fixed Hardware) related function. Signed-off-by: Jonghwan Choi <jhbird.choi(a)samsung.com> --- arch/arm64/include/asm/acpi.h | 12 +++++++ arch/arm64/include/asm/irqflags.h | 6 ++++ arch/arm64/include/asm/processor.h | 3 ++ arch/arm64/kernel/Makefile | 4 +++ arch/arm64/kernel/cstate.c | 67 ++++++++++++++++++++++++++++++++++++ arch/arm64/kernel/process.c | 6 ++++ drivers/acpi/processor_idle.c | 14 -------- 7 files changed, 98 insertions(+), 14 deletions(-) create mode 100644 arch/arm64/kernel/cstate.c diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h index dff95da..34e591a 100644 --- a/arch/arm64/include/asm/acpi.h +++ b/arch/arm64/include/asm/acpi.h @@ -92,6 +92,14 @@ extern int arm_cpu_to_apicid[NR_CPUS]; extern int gic_acpi_init(void); extern int cpu_acpi_read_ops(int cpu); +/* + * Check if the CPU can handle C2 and deeper + */ +static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate) +{ + return max_cstate; +} + #else /* !CONFIG_ACPI */ #define acpi_disabled 1 /* ACPI sometimes enabled on ARM */ #define acpi_noirq 1 /* ACPI sometimes enabled on ARM */ @@ -110,4 +118,8 @@ static inline int cpu_acpi_read_ops(int cpu) #endif +#define ARCH_HAS_POWER_INIT 1 + +#define acpi_unlazy_tlb(x) + #endif /*_ASM_ARM64_ACPI_H*/ diff --git a/arch/arm64/include/asm/irqflags.h b/arch/arm64/include/asm/irqflags.h index 11cc941..8ab3bd7 100644 --- a/arch/arm64/include/asm/irqflags.h +++ b/arch/arm64/include/asm/irqflags.h @@ -19,6 +19,7 @@ #ifdef __KERNEL__ #include <asm/ptrace.h> +#include <asm/barrier.h> /* * CPU interrupt mask handling. @@ -113,5 +114,10 @@ static inline int arch_irqs_disabled_flags(unsigned long flags) #define local_dbg_enable() asm("msr daifclr, #8" : : : "memory") #define local_dbg_disable() asm("msr daifset, #8" : : : "memory") +static inline void arch_safe_halt(void) +{ + arch_local_irq_enable(); + wfi(); +} #endif #endif diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index 50ce951..dca0939 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -47,6 +47,9 @@ #define ARCH_LOW_ADDRESS_LIMIT PHYS_MASK #endif /* __KERNEL__ */ +enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, + IDLE_POLL}; + struct debug_info { /* Have we suspended stepping by a debugger? */ int suspended_step; diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index db63a0a..b829268 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -26,6 +26,10 @@ arm64-obj-$(CONFIG_JUMP_LABEL) += jump_label.o arm64-obj-$(CONFIG_KGDB) += kgdb.o arm64-obj-$(CONFIG_EFI) += efi.o efi-stub.o efi-entry.o +ifneq ($(CONFIG_ACPI_PROCESSOR),) +arm64-obj-y += cstate.o +endif + obj-y += $(arm64-obj-y) vdso/ obj-m += $(arm64-obj-m) head-y := head.o diff --git a/arch/arm64/kernel/cstate.c b/arch/arm64/kernel/cstate.c new file mode 100644 index 0000000..00c22cd --- /dev/null +++ b/arch/arm64/kernel/cstate.c @@ -0,0 +1,67 @@ +/* + * Based on arch/x86/kernel/acpi/cstate.c + * + * Copyright (C) 2005 Intel Corporation + * Venkatesh Pallipadi <venkatesh.pallipadi(a)intel.com> + * - Added _PDC for SMP C-states on Intel CPUs + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/acpi.h> +#include <linux/cpu.h> +#include <linux/cpu_pm.h> + +#include <acpi/processor.h> +#include <asm/acpi.h> +#include <asm/cpu.h> +#include <asm/suspend.h> + +/* + * Initialize bm_flags based on the CPU cache properties + * On SMP it depends on cache configuration + * - When cache is not shared among all CPUs, we flush cache + * before entering C3. + * - When cache is shared among all CPUs, we use bm_check + * mechanism as in UP case + * + * This routine is called only after all the CPUs are online + */ +void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags, + unsigned int cpu) +{ + struct cpuinfo_arm *c = &cpu_data(cpu); + + flags->bm_check = 0; + flags->bm_control = 0; + + /* To Do */ +} +EXPORT_SYMBOL(acpi_processor_power_init_bm_check); + +int acpi_processor_ffh_cstate_probe(unsigned int cpu, + struct acpi_processor_cx *cx, struct acpi_power_register *reg) +{ + /* To Do */ + return 0; +} +EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe); + +void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cx) +{ + cpu_pm_enter(); + /* + * Pass idle state index to cpu_suspend which in turn will call + * the CPU ops suspend protocol with idle index as a parameter. + * + * Some states would not require context to be saved and flushed + * to DRAM, so calling cpu_suspend would not be stricly necessary. + * When power domains specifications for ARM CPUs are finalized then + * this code can be optimized to prevent saving registers if not + * needed. + */ + cpu_suspend(cx->type); + + cpu_pm_exit(); +} +EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_enter); diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 6391485..8ce1610 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -94,6 +94,12 @@ void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd); EXPORT_SYMBOL_GPL(arm_pm_restart); /* + * Idle related variables and functions + */ +unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; +EXPORT_SYMBOL(boot_option_idle_override); + +/* * This is our default idle handler. */ void arch_cpu_idle(void) diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index fae22f4..3dca36d 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -70,10 +70,8 @@ static DEFINE_PER_CPU(struct acpi_processor_cx * [CPUIDLE_STATE_MAX], static int disabled_by_idle_boot_param(void) { -#ifdef CONFIG_X86 return boot_option_idle_override == IDLE_POLL || boot_option_idle_override == IDLE_HALT; -#endif } /* @@ -120,9 +118,7 @@ static struct dmi_system_id processor_power_dmi_table[] = { static void acpi_safe_halt(void) { if (!tif_need_resched()) { -#ifdef CONFIG_X86 safe_halt(); -#endif local_irq_disable(); } } @@ -437,7 +433,6 @@ static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) } else { continue; } -#ifdef CONFIG_X86 if (cx.type == ACPI_STATE_C1 && (boot_option_idle_override == IDLE_NOMWAIT)) { /* @@ -453,7 +448,6 @@ static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) cx.entry_method = ACPI_CSTATE_HALT; snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); } -#endif } else { snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x", cx.address); @@ -754,11 +748,7 @@ static int acpi_idle_play_dead(struct cpuidle_device *dev, int index) while (1) { if (cx->entry_method == ACPI_CSTATE_HALT) -#ifdef CONFIG_X86 safe_halt(); -#else - ; -#endif else if (cx->entry_method == ACPI_CSTATE_SYSTEMIO) { inb(cx->address); /* See comment in acpi_idle_do_entry() */ @@ -853,9 +843,7 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev, } } -#ifdef CONFIG_X86 acpi_unlazy_tlb(smp_processor_id()); -#endif /* Tell the scheduler that we are going deep-idle: */ sched_clock_idle_sleep_event(); @@ -1133,9 +1121,7 @@ int acpi_processor_power_init(struct acpi_processor *pr) if (!first_run) { dmi_check_system(processor_power_dmi_table); -#ifdef CONFIG_X86 max_cstate = acpi_processor_cstate_check(max_cstate); -#endif if (max_cstate < ACPI_C_STATES_MAX) printk(KERN_NOTICE "ACPI: processor limited to max C-state %d\n", -- 1.7.10.4

11 years

1
0
0 0

[PATCH linaro-acpi] [RFC 5/7] cpufreq: Add ACPI cpufreq support for ARM

by Jonghwan Choi

Separated acpi-cpufreq into 3 parts. acpi-cpufreq has a common code for both x86 and arm. acpi-cpufreq_x86 is for x86-specific codes and acpi-cpufreq_arm is for arm-specific codes. Signed-off-by: Jonghwan Choi <jhbird.choi(a)samsung.com> --- drivers/cpufreq/Makefile | 6 + drivers/cpufreq/acpi-cpufreq.c | 394 +++++------------------------------- drivers/cpufreq/acpi-cpufreq.h | 69 +++++++ drivers/cpufreq/acpi-cpufreq_arm.c | 46 +++++ drivers/cpufreq/acpi-cpufreq_x86.c | 300 +++++++++++++++++++++++++++ 5 files changed, 471 insertions(+), 344 deletions(-) create mode 100644 drivers/cpufreq/acpi-cpufreq.h create mode 100644 drivers/cpufreq/acpi-cpufreq_arm.c create mode 100644 drivers/cpufreq/acpi-cpufreq_x86.c diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index bfeb0fb..eda425a 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -14,6 +14,12 @@ obj-$(CONFIG_CPU_FREQ_GOV_COMMON) += cpufreq_governor.o obj-$(CONFIG_GENERIC_CPUFREQ_CPU0) += cpufreq-cpu0.o obj-$(CONFIG_ACPI_CPUFREQ) += acpi-cpufreq.o +ifdef CONFIG_X86 +obj-$(CONFIG_ACPI_CPUFREQ) += acpi-cpufreq_x86.o +endif +ifdef CONFIG_ARM64 +obj-$(CONFIG_ACPI_CPUFREQ) += acpi-cpufreq_arm.o +endif ############################################################################ ###### # x86 drivers. diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c index 80662b1..6f9749b 100644 --- a/drivers/cpufreq/acpi-cpufreq.c +++ b/drivers/cpufreq/acpi-cpufreq.c @@ -42,39 +42,17 @@ #include <acpi/processor.h> -#ifdef CONFIG_X86 -#include <asm/msr.h> -#endif +#include <asm/cpu.h> #include <asm/processor.h> -#include <asm/cpufeature.h> + +#include "acpi-cpufreq.h" MODULE_AUTHOR("Paul Diefenbaugh, Dominik Brodowski"); MODULE_DESCRIPTION("ACPI Processor P-States Driver"); MODULE_LICENSE("GPL"); -#define PFX "acpi-cpufreq: " - -enum { - UNDEFINED_CAPABLE = 0, - SYSTEM_INTEL_MSR_CAPABLE, - SYSTEM_AMD_MSR_CAPABLE, - SYSTEM_IO_CAPABLE, -}; - -#define INTEL_MSR_RANGE (0xffff) -#define AMD_MSR_RANGE (0x7) - -#define MSR_K7_HWCR_CPB_DIS (1ULL << 25) - -struct acpi_cpufreq_data { - struct acpi_processor_performance *acpi_data; - struct cpufreq_frequency_table *freq_table; - unsigned int resume; - unsigned int cpu_feature; - cpumask_var_t freqdomain_cpus; -}; - static DEFINE_PER_CPU(struct acpi_cpufreq_data *, acfreq_data); +static struct acpi_cpufreq_common *acpi; /* acpi_perf_data is a pointer to percpu data. */ static struct acpi_processor_performance __percpu *acpi_perf_data; @@ -82,66 +60,12 @@ static struct acpi_processor_performance __percpu *acpi_perf_data; static struct cpufreq_driver acpi_cpufreq_driver; static unsigned int acpi_pstate_strict; -static struct msr __percpu *msrs; - -static bool boost_state(unsigned int cpu) -{ -#ifdef CONFIG_X86 - u32 lo, hi; - u64 msr; - - switch (boot_cpu_data.x86_vendor) { - case X86_VENDOR_INTEL: - rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi); - msr = lo | ((u64)hi << 32); - return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); - case X86_VENDOR_AMD: - rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi); - msr = lo | ((u64)hi << 32); - return !(msr & MSR_K7_HWCR_CPB_DIS); - } -#endif - return false; -} - -static void boost_set_msrs(bool enable, const struct cpumask *cpumask) -{ - u32 cpu; - u32 msr_addr; - u64 msr_mask; - -#ifdef CONFIG_X86 - switch (boot_cpu_data.x86_vendor) { - case X86_VENDOR_INTEL: - msr_addr = MSR_IA32_MISC_ENABLE; - msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE; - break; - case X86_VENDOR_AMD: - msr_addr = MSR_K7_HWCR; - msr_mask = MSR_K7_HWCR_CPB_DIS; - break; - default: - return; - } - - rdmsr_on_cpus(cpumask, msr_addr, msrs); - - for_each_cpu(cpu, cpumask) { - struct msr *reg = per_cpu_ptr(msrs, cpu); - if (enable) - reg->q &= ~msr_mask; - else - reg->q |= msr_mask; - } - - wrmsr_on_cpus(cpumask, msr_addr, msrs); -#endif -} static int _store_boost(int val) { get_online_cpus(); - boost_set_msrs(val, cpu_online_mask); + if (acpi->ops->update_boost) + acpi->ops->update_boost(val, cpu_online_mask); put_online_cpus(); pr_debug("Core Boosting %sabled.\n", val ? "en" : "dis"); @@ -157,13 +81,12 @@ static ssize_t show_freqdomain_cpus(struct cpufreq_policy *policy, char *buf) cpufreq_freq_attr_ro(freqdomain_cpus); -#ifdef CONFIG_X86_ACPI_CPUFREQ_CPB static ssize_t store_boost(const char *buf, size_t count) { int ret; unsigned long val = 0; - if (!acpi_cpufreq_driver.boost_supported) + if (!acpi->boost_supported) return -EINVAL; ret = kstrtoul(buf, 10, &val); @@ -187,25 +110,6 @@ static ssize_t show_cpb(struct cpufreq_policy *policy, char *buf) } cpufreq_freq_attr_rw(cpb); -#endif - -static int check_est_cpu(unsigned int cpuid) -{ -#ifdef CONFIG_X86 - struct cpuinfo_x86 *cpu = &cpu_data(cpuid); - - return cpu_has(cpu, X86_FEATURE_EST); -#endif -} - -static int check_amd_hwpstate_cpu(unsigned int cpuid) -{ -#ifdef CONFIG_X86 - struct cpuinfo_x86 *cpu = &cpu_data(cpuid); - - return cpu_has(cpu, X86_FEATURE_HW_PSTATE); -#endif -} static unsigned extract_io(u32 value, struct acpi_cpufreq_data *data) { @@ -221,75 +125,39 @@ static unsigned extract_io(u32 value, struct acpi_cpufreq_data *data) return 0; } -static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data) -{ - int i; - struct acpi_processor_performance *perf; -#ifdef CONFIG_X86 - if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) - msr &= AMD_MSR_RANGE; - else - msr &= INTEL_MSR_RANGE; -#endif - - perf = data->acpi_data; - - for (i = 0; data->freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { - if (msr == perf->states[data->freq_table[i].driver_data].status) - return data->freq_table[i].frequency; - } - return data->freq_table[0].frequency; -} static unsigned extract_freq(u32 val, struct acpi_cpufreq_data *data) { switch (data->cpu_feature) { case SYSTEM_INTEL_MSR_CAPABLE: case SYSTEM_AMD_MSR_CAPABLE: - return extract_msr(val, data); + return acpi->ops->extract_freq(val, data); case SYSTEM_IO_CAPABLE: + case SYSTEM_MEMORY_CAPABLE: return extract_io(val, data); default: return 0; } } -struct msr_addr { - u32 reg; -}; - -struct io_addr { - u16 port; - u8 bit_width; -}; - -struct drv_cmd { - unsigned int type; - const struct cpumask *mask; - union { - struct msr_addr msr; - struct io_addr io; - } addr; - u32 val; -}; - /* Called via smp_call_function_single(), on the target CPU */ static void do_drv_read(void *_cmd) { struct drv_cmd *cmd = _cmd; - u32 h; switch (cmd->type) { case SYSTEM_INTEL_MSR_CAPABLE: case SYSTEM_AMD_MSR_CAPABLE: -#ifdef CONFIG_X86 - rdmsr(cmd->addr.msr.reg, cmd->val, h); -#endif + acpi->ops->drv_read(cmd); break; case SYSTEM_IO_CAPABLE: acpi_os_read_port((acpi_io_address)cmd->addr.io.port, &cmd->val, (u32)cmd->addr.io.bit_width); + case SYSTEM_MEMORY_CAPABLE: + acpi_os_read_memory((acpi_physical_address)cmd->addr.mem.addr, + (u64*)&cmd->val, + cmd->addr.mem.bit_width); break; default: break; @@ -300,25 +168,20 @@ static void do_drv_read(void *_cmd) static void do_drv_write(void *_cmd) { struct drv_cmd *cmd = _cmd; - u32 lo, hi; switch (cmd->type) { case SYSTEM_INTEL_MSR_CAPABLE: -#ifdef CONFIG_X86 - rdmsr(cmd->addr.msr.reg, lo, hi); - lo = (lo & ~INTEL_MSR_RANGE) | (cmd->val & INTEL_MSR_RANGE); - wrmsr(cmd->addr.msr.reg, lo, hi); -#endif - break; case SYSTEM_AMD_MSR_CAPABLE: -#ifdef CONFIG_X86 - wrmsr(cmd->addr.msr.reg, cmd->val, 0); -#endif + acpi->ops->drv_write(cmd); break; case SYSTEM_IO_CAPABLE: acpi_os_write_port((acpi_io_address)cmd->addr.io.port, cmd->val, (u32)cmd->addr.io.bit_width); + case SYSTEM_MEMORY_CAPABLE: + acpi_os_write_memory((acpi_physical_address)cmd->addr.mem.addr, + (u64)cmd->val, + cmd->addr.mem.bit_width); break; default: break; @@ -347,34 +210,13 @@ static void drv_write(struct drv_cmd *cmd) static u32 get_cur_val(const struct cpumask *mask) { - struct acpi_processor_performance *perf; struct drv_cmd cmd; if (unlikely(cpumask_empty(mask))) return 0; - switch (per_cpu(acfreq_data, cpumask_first(mask))->cpu_feature) { -#ifdef CONFIG_X86 - case SYSTEM_INTEL_MSR_CAPABLE: - cmd.type = SYSTEM_INTEL_MSR_CAPABLE; - cmd.addr.msr.reg = MSR_IA32_PERF_CTL; - break; - case SYSTEM_AMD_MSR_CAPABLE: - cmd.type = SYSTEM_AMD_MSR_CAPABLE; - cmd.addr.msr.reg = MSR_AMD_PERF_CTL; - break; -#endif - case SYSTEM_IO_CAPABLE: - cmd.type = SYSTEM_IO_CAPABLE; - perf = per_cpu(acfreq_data, cpumask_first(mask))->acpi_data; - cmd.addr.io.port = perf->control_register.address; - cmd.addr.io.bit_width = perf->control_register.bit_width; - break; - default: - return 0; - } - cmd.mask = mask; + drv_read(&cmd); pr_debug("get_cur_val = %u\n", cmd.val); @@ -453,36 +295,14 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy, } } - switch (data->cpu_feature) { -#ifdef CONFIG_X86 - case SYSTEM_INTEL_MSR_CAPABLE: - cmd.type = SYSTEM_INTEL_MSR_CAPABLE; - cmd.addr.msr.reg = MSR_IA32_PERF_CTL; - cmd.val = (u32) perf->states[next_perf_state].control; - break; - case SYSTEM_AMD_MSR_CAPABLE: - cmd.type = SYSTEM_AMD_MSR_CAPABLE; - cmd.addr.msr.reg = MSR_AMD_PERF_CTL; - cmd.val = (u32) perf->states[next_perf_state].control; - break; -#endif - case SYSTEM_IO_CAPABLE: - cmd.type = SYSTEM_IO_CAPABLE; - cmd.addr.io.port = perf->control_register.address; - cmd.addr.io.bit_width = perf->control_register.bit_width; - cmd.val = (u32) perf->states[next_perf_state].control; - break; - default: - result = -ENODEV; - goto out; - } - /* cpufreq holds the hotplug lock, so we are safe from here on */ if (policy->shared_type != CPUFREQ_SHARED_TYPE_ANY) cmd.mask = policy->cpus; else cmd.mask = cpumask_of(policy->cpu); + cmd.val = (u32) perf->states[next_perf_state].control; + drv_write(&cmd); if (acpi_pstate_strict) { @@ -540,44 +360,6 @@ static void free_acpi_perf_data(void) free_percpu(acpi_perf_data); } -static int boost_notify(struct notifier_block *nb, unsigned long action, - void *hcpu) -{ - unsigned cpu = (long)hcpu; - const struct cpumask *cpumask; - - cpumask = get_cpu_mask(cpu); - - /* - * Clear the boost-disable bit on the CPU_DOWN path so that - * this cpu cannot block the remaining ones from boosting. On - * the CPU_UP path we simply keep the boost-disable flag in - * sync with the current global state. - */ - - switch (action) { - case CPU_UP_PREPARE: - case CPU_UP_PREPARE_FROZEN: - boost_set_msrs(acpi_cpufreq_driver.boost_enabled, cpumask); - break; - - case CPU_DOWN_PREPARE: - case CPU_DOWN_PREPARE_FROZEN: - boost_set_msrs(1, cpumask); - break; - - default: - break; - } - - return NOTIFY_OK; -} - - -static struct notifier_block boost_nb = { - .notifier_call = boost_notify, -}; - /* * acpi_cpufreq_early_init - initialize ACPI P-States library * @@ -639,29 +421,6 @@ static const struct dmi_system_id sw_any_bug_dmi_table[] = { }, { } }; - -static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c) -{ - /* Intel Xeon Processor 7100 Series Specification Update - * http://www.intel.com/Assets/PDF/specupdate/314554.pdf - * AL30: A Machine Check Exception (MCE) Occurring during an - * Enhanced Intel SpeedStep Technology Ratio Change May Cause - * Both Processor Cores to Lock Up. */ -#ifdef CONFIG_X86 - if (c->x86_vendor == X86_VENDOR_INTEL) { - if ((c->x86 == 15) && - (c->x86_model == 6) && - (c->x86_mask == 8)) { - printk(KERN_INFO "acpi-cpufreq: Intel(R) " - "Xeon(R) 7100 Errata AL30, processors may " - "lock up on frequency changes: disabling " - "acpi-cpufreq.\n"); - return -ENODEV; - } - } -#endif - return 0; -} #endif static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) @@ -671,11 +430,7 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) unsigned int cpu = policy->cpu; struct acpi_cpufreq_data *data; unsigned int result = 0; -#ifdef CONFIG_X86 - struct cpuinfo_x86 *c = &cpu_data(policy->cpu); -#else - struct cpuinfo_x86 *c = NULL; -#endif + void *c = &cpu_data(policy->cpu); struct acpi_processor_performance *perf; #ifdef CONFIG_SMP static int blacklisted; @@ -686,9 +441,11 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) #ifdef CONFIG_SMP if (blacklisted) return blacklisted; - blacklisted = acpi_cpufreq_blacklist(c); - if (blacklisted) - return blacklisted; + if (acpi->ops->arch_check) { + blacklisted = acpi->ops->arch_check(c); + if (blacklisted) + return blacklisted; + } #endif data = kzalloc(sizeof(*data), GFP_KERNEL); @@ -703,10 +460,8 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) data->acpi_data = per_cpu_ptr(acpi_perf_data, cpu); per_cpu(acfreq_data, cpu) = data; -#ifdef CONFIG_X86 - if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) + if (acpi->const_loops) acpi_cpufreq_driver.flags |= CPUFREQ_CONST_LOOPS; -#endif result = acpi_processor_register_performance(data->acpi_data, cpu); if (result) @@ -734,7 +489,7 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) #endif } - if (check_amd_hwpstate_cpu(cpu) && !acpi_pstate_strict) { + if (acpi->feature_hw_pstate && !acpi_pstate_strict) { cpumask_clear(policy->cpus); cpumask_set_cpu(cpu, policy->cpus); #ifdef CONFIG_X86 @@ -757,34 +512,7 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) goto err_unreg; } - switch (perf->control_register.space_id) { - case ACPI_ADR_SPACE_SYSTEM_IO: -#ifdef CONFIG_X86 - if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && - boot_cpu_data.x86 == 0xf) { - pr_debug("AMD K8 systems must use native drivers.\n"); - result = -ENODEV; - goto err_unreg; - } -#endif - pr_debug("SYSTEM IO addr space\n"); - data->cpu_feature = SYSTEM_IO_CAPABLE; - break; - case ACPI_ADR_SPACE_FIXED_HARDWARE: - pr_debug("HARDWARE addr space\n"); - if (check_est_cpu(cpu)) { - data->cpu_feature = SYSTEM_INTEL_MSR_CAPABLE; - break; - } - if (check_amd_hwpstate_cpu(cpu)) { - data->cpu_feature = SYSTEM_AMD_MSR_CAPABLE; - break; - } - result = -ENODEV; - goto err_unreg; - default: - pr_debug("Unknown addr space %d\n", - (u32) (perf->control_register.space_id)); + if (acpi->ops->arch_feature(data)) { result = -ENODEV; goto err_unreg; } @@ -933,39 +661,14 @@ static struct cpufreq_driver acpi_cpufreq_driver = { static void __init acpi_cpufreq_boost_init(void) { -#ifdef CONFIG_X86 - if (boot_cpu_has(X86_FEATURE_CPB) || boot_cpu_has(X86_FEATURE_IDA)) { - msrs = msrs_alloc(); - - if (!msrs) - return; - - acpi_cpufreq_driver.boost_supported = true; - acpi_cpufreq_driver.boost_enabled = boost_state(0); - - cpu_notifier_register_begin(); - - /* Force all MSRs to the same value */ - boost_set_msrs(acpi_cpufreq_driver.boost_enabled, - cpu_online_mask); - - __register_cpu_notifier(&boost_nb); - - cpu_notifier_register_done(); - } -#endif + if (acpi->ops->arch_boost_init) + acpi->ops->arch_boost_init(acpi); } static void acpi_cpufreq_boost_exit(void) { -#ifdef CONFIG_X86 - if (msrs) { - unregister_cpu_notifier(&boost_nb); - - msrs_free(msrs); - msrs = NULL; - } -#endif + if (acpi->ops->arch_boost_exit) + acpi->ops->arch_boost_exit(); } static int __init acpi_cpufreq_init(void) @@ -985,14 +688,23 @@ static int __init acpi_cpufreq_init(void) if (ret) return ret; -#ifdef CONFIG_X86_ACPI_CPUFREQ_CPB + acpi = kzalloc(sizeof(*acpi), GFP_KERNEL); + if (!acpi) + return -ENOMEM; + + if (arch_acpi_cpufreq_init(acpi)) { + kfree(acpi); + return -ENOMEM; + } + + /* this is a sysfs file with a strange name and an even stranger * semantic - per CPU instantiation, but system global effect. * Lets enable it only on AMD CPUs for compatibility reasons and * only if configured. This is considered legacy code, which * will probably be removed at some point in the future. */ - if (check_amd_hwpstate_cpu(0)) { + if (acpi->feature_hw_pstate) { struct freq_attr **iter; pr_debug("adding sysfs entry for cpb\n"); @@ -1004,11 +716,12 @@ static int __init acpi_cpufreq_init(void) if (iter[1] == NULL) *iter = &cpb; } -#endif + acpi_cpufreq_boost_init(); ret = cpufreq_register_driver(&acpi_cpufreq_driver); if (ret) { + kfree(acpi); free_acpi_perf_data(); acpi_cpufreq_boost_exit(); } @@ -1024,6 +737,8 @@ static void __exit acpi_cpufreq_exit(void) cpufreq_unregister_driver(&acpi_cpufreq_driver); free_acpi_perf_data(); + + kfree(acpi); } module_param(acpi_pstate_strict, uint, 0644); @@ -1034,15 +749,6 @@ MODULE_PARM_DESC(acpi_pstate_strict, late_initcall(acpi_cpufreq_init); module_exit(acpi_cpufreq_exit); -#ifdef CONFIG_X86 -static const struct x86_cpu_id acpi_cpufreq_ids[] = { - X86_FEATURE_MATCH(X86_FEATURE_ACPI), - X86_FEATURE_MATCH(X86_FEATURE_HW_PSTATE), - {} -}; -MODULE_DEVICE_TABLE(x86cpu, acpi_cpufreq_ids); -#endif - static const struct acpi_device_id processor_device_ids[] = { {ACPI_PROCESSOR_OBJECT_HID, }, {ACPI_PROCESSOR_DEVICE_HID, }, diff --git a/drivers/cpufreq/acpi-cpufreq.h b/drivers/cpufreq/acpi-cpufreq.h new file mode 100644 index 0000000..ddef14f --- /dev/null +++ b/drivers/cpufreq/acpi-cpufreq.h @@ -0,0 +1,69 @@ +#ifndef _ACPI_CPUFREQ_H +#define _ACPI_CPUFREQ_H + +#define PFX "acpi-cpufreq: " + +enum { + UNDEFINED_CAPABLE = 0, + SYSTEM_INTEL_MSR_CAPABLE, + SYSTEM_AMD_MSR_CAPABLE, + SYSTEM_IO_CAPABLE, + SYSTEM_MEMORY_CAPABLE, +}; + +struct msr_addr { + u32 reg; +}; + +struct io_addr { + u16 port; + u32 bit_width; +}; + +struct mem_addr { + u64 addr; + u32 bit_width; +}; + +struct drv_cmd { + unsigned int type; + const struct cpumask *mask; + union { + struct msr_addr msr; + struct io_addr io; + struct mem_addr mem; + } addr; + u32 val; +}; + +struct acpi_cpufreq_data; +struct acpi_cpufreq_common; + +struct acpi_cpufreq_ops { + int (*arch_check)(void *info); + int (*arch_feature)(struct acpi_cpufreq_data *data); + void (*arch_boost_init)(struct acpi_cpufreq_common *acpi); + void (*arch_boost_exit)(void); + void (*drv_read)(struct drv_cmd *cmd); + void (*drv_write)(struct drv_cmd *cmd); + void (*update_boost)(bool enable, const struct cpumask *cpumask); + unsigned (*extract_freq)(u32 val, struct acpi_cpufreq_data *data); +}; + +struct acpi_cpufreq_data { + struct acpi_processor_performance *acpi_data; + struct cpufreq_frequency_table *freq_table; + unsigned int resume; + unsigned int cpu_feature; + cpumask_var_t freqdomain_cpus; +}; + +struct acpi_cpufreq_common { + struct acpi_cpufreq_ops *ops; + bool boost_supported; + bool feature_hw_pstate; + bool const_loops; +}; + +int arch_acpi_cpufreq_init(struct acpi_cpufreq_common *common); +#endif /* _ACPI_CPUFREQ_H */ diff --git a/drivers/cpufreq/acpi-cpufreq_arm.c b/drivers/cpufreq/acpi-cpufreq_arm.c new file mode 100644 index 0000000..60ec8aa --- /dev/null +++ b/drivers/cpufreq/acpi-cpufreq_arm.c @@ -0,0 +1,46 @@ +#include <linux/acpi.h> +#include <linux/cpu.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/uaccess.h> + +#include <acpi/processor.h> + +#include <asm/cpu.h> +#include <asm/processor.h> + +#include "acpi-cpufreq.h" + +static int arm_arch_feature(struct acpi_cpufreq_data *data) +{ + struct acpi_processor_performance *perf; + int result = 0; + + perf = data->acpi_data; + + switch (perf->control_register.space_id) { + case ACPI_ADR_SPACE_SYSTEM_MEMORY: + pr_debug("SYSTEM Memory addr space\n"); + data->cpu_feature = SYSTEM_MEMORY_CAPABLE; + break; + default: + pr_debug("Unknown addr space %d\n", + (u32) (perf->control_register.space_id)); + result = -ENODEV; + break; + } + + return result; +} + +static struct acpi_cpufreq_ops arm_ops = { + .arch_feature = arm_arch_feature, +}; + +int arch_acpi_cpufreq_init(struct acpi_cpufreq_common *common) +{ + common->ops = &arm_ops; + + return 0; +} + diff --git a/drivers/cpufreq/acpi-cpufreq_x86.c b/drivers/cpufreq/acpi-cpufreq_x86.c new file mode 100644 index 0000000..5fe36e4 --- /dev/null +++ b/drivers/cpufreq/acpi-cpufreq_x86.c @@ -0,0 +1,300 @@ +#include <linux/module.h> +#include <linux/acpi.h> +#include <linux/cpu.h> +#include <linux/cpufreq.h> +#include <linux/io.h> + +#include <acpi/processor.h> + +#include <asm/msr.h> +#include <asm/cpufeature.h> +#include <asm/processor.h> + +#include "acpi-cpufreq.h" + +#define INTEL_MSR_RANGE (0xffff) +#define AMD_MSR_RANGE (0x7) + +#define MSR_K7_HWCR_CPB_DIS (1ULL << 25) + +static struct msr __percpu *msrs; + +static void x86_boost_set_msrs(bool enable, const struct cpumask *cpumask) +{ + u32 cpu; + u32 msr_addr; + u64 msr_mask; + + switch (boot_cpu_data.x86_vendor) { + case X86_VENDOR_INTEL: + msr_addr = MSR_IA32_MISC_ENABLE; + msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE; + break; + case X86_VENDOR_AMD: + msr_addr = MSR_K7_HWCR; + msr_mask = MSR_K7_HWCR_CPB_DIS; + break; + default: + return; + } + + rdmsr_on_cpus(cpumask, msr_addr, msrs); + + for_each_cpu(cpu, cpumask) { + struct msr *reg = per_cpu_ptr(msrs, cpu); + if (enable) + reg->q &= ~msr_mask; + else + reg->q |= msr_mask; + } + + wrmsr_on_cpus(cpumask, msr_addr, msrs); +} + +static bool boost_state(unsigned int cpu) +{ + u32 lo, hi; + u64 msr; + + switch (boot_cpu_data.x86_vendor) { + case X86_VENDOR_INTEL: + rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi); + msr = lo | ((u64)hi << 32); + return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); + case X86_VENDOR_AMD: + rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi); + msr = lo | ((u64)hi << 32); + return !(msr & MSR_K7_HWCR_CPB_DIS); + } + return false; +} + +#ifdef CONFIG_SMP +static int x86_arch_check(void *data) +{ + struct cpuinfo_x86 *c = data; + /* Intel Xeon Processor 7100 Series Specification Update + * http://www.intel.com/Assets/PDF/specupdate/314554.pdf + * AL30: A Machine Check Exception (MCE) Occurring during an + * Enhanced Intel SpeedStep Technology Ratio Change May Cause + * Both Processor Cores to Lock Up. */ + if (c->x86_vendor == X86_VENDOR_INTEL) { + if ((c->x86 == 15) && + (c->x86_model == 6) && + (c->x86_mask == 8)) { + printk(KERN_INFO "acpi-cpufreq: Intel(R) " + "Xeon(R) 7100 Errata AL30, processors may " + "lock up on frequency changes: disabling " + "acpi-cpufreq.\n"); + return -ENODEV; + } + } + return 0; +} +#else +#define x86_arch_check NULL +#endif + +static void x86_do_drv_read(struct drv_cmd *cmd) +{ + u32 h; + + switch (cmd->type) { + case SYSTEM_INTEL_MSR_CAPABLE: + cmd->addr.msr.reg = MSR_IA32_PERF_CTL; + rdmsr(cmd->addr.msr.reg, cmd->val, h); + break; + case SYSTEM_AMD_MSR_CAPABLE: + cmd->addr.msr.reg = MSR_AMD_PERF_CTL; + rdmsr(cmd->addr.msr.reg, cmd->val, h); + break; + default: + break; + } +} + +/* Called via smp_call_function_many(), on the target CPUs */ +static void x86_do_drv_write(struct drv_cmd *cmd) +{ + u32 lo, hi; + + switch (cmd->type) { + case SYSTEM_INTEL_MSR_CAPABLE: + cmd->addr.msr.reg = MSR_IA32_PERF_CTL; + rdmsr(cmd->addr.msr.reg, lo, hi); + lo = (lo & ~INTEL_MSR_RANGE) | (cmd->val & INTEL_MSR_RANGE); + wrmsr(cmd->addr.msr.reg, lo, hi); + break; + case SYSTEM_AMD_MSR_CAPABLE: + cmd->addr.msr.reg = MSR_AMD_PERF_CTL; + wrmsr(cmd->addr.msr.reg, cmd->val, 0); + break; + default: + break; + } +} + +static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data) +{ + int i; + struct acpi_processor_performance *perf; + + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) + msr &= AMD_MSR_RANGE; + else + msr &= INTEL_MSR_RANGE; + + perf = data->acpi_data; + + for (i = 0; data->freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { + if (msr == perf->states[data->freq_table[i].driver_data].status) + return data->freq_table[i].frequency; + } + return data->freq_table[0].frequency; +} + +unsigned x86_extract_freq(u32 val, struct acpi_cpufreq_data *data) +{ + switch (data->cpu_feature) { + case SYSTEM_INTEL_MSR_CAPABLE: + case SYSTEM_AMD_MSR_CAPABLE: + return extract_msr(val, data); + default: + return 0; + } +} + +static int boost_notify(struct notifier_block *nb, unsigned long action, + void *hcpu) +{ + unsigned cpu = (long)hcpu; + const struct cpumask *cpumask; + + cpumask = get_cpu_mask(cpu); + + /* + * Clear the boost-disable bit on the CPU_DOWN path so that + * this cpu cannot block the remaining ones from boosting. On + * the CPU_UP path we simply keep the boost-disable flag in + * sync with the current global state. + */ + + switch (action) { + case CPU_UP_PREPARE: + case CPU_UP_PREPARE_FROZEN: + x86_boost_set_msrs(boost_state(0), cpumask); + break; + + case CPU_DOWN_PREPARE: + case CPU_DOWN_PREPARE_FROZEN: + x86_boost_set_msrs(1, cpumask); + break; + + default: + break; + } + + return NOTIFY_OK; +} + +static struct notifier_block boost_nb = { + .notifier_call = boost_notify, +}; + +static void x86_arch_boost_init(struct acpi_cpufreq_common *acpi) +{ + if (boot_cpu_has(X86_FEATURE_CPB) || boot_cpu_has(X86_FEATURE_IDA)) { + msrs = msrs_alloc(); + + if (!msrs) + return; + + acpi->boost_supported = true; + + get_online_cpus(); + + x86_boost_set_msrs(boost_state(0), cpu_online_mask); + + register_cpu_notifier(&boost_nb); + + put_online_cpus(); + } +} + +static void x86_arch_boost_exit(void) +{ + if (msrs) { + unregister_cpu_notifier(&boost_nb); + + msrs_free(msrs); + msrs = NULL; + } +} + +static int x86_arch_feature(struct acpi_cpufreq_data *data) +{ + struct acpi_processor_performance *perf; + int result = 0; + + perf = data->acpi_data; + + switch (perf->control_register.space_id) { + case ACPI_ADR_SPACE_SYSTEM_IO: + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && + boot_cpu_data.x86 == 0xf) { + pr_debug("AMD K8 systems must use native drivers.\n"); + result = -ENODEV; + break; + } + pr_debug("SYSTEM IO addr space\n"); + data->cpu_feature = SYSTEM_IO_CAPABLE; + break; + case ACPI_ADR_SPACE_FIXED_HARDWARE: + pr_debug("HARDWARE addr space\n"); + if (boot_cpu_has(X86_FEATURE_EST)) { + data->cpu_feature = SYSTEM_INTEL_MSR_CAPABLE; + break; + } + if (boot_cpu_has(X86_FEATURE_HW_PSTATE)) { + data->cpu_feature = SYSTEM_AMD_MSR_CAPABLE; + break; + } + result = -ENODEV; + break; + default: + pr_debug("Unknown addr space %d\n", + (u32) (perf->control_register.space_id)); + result = -ENODEV; + break; + } + + return result; +} + +static struct acpi_cpufreq_ops x86_ops = { + .arch_check = x86_arch_check, + .arch_feature = x86_arch_feature, + .arch_boost_init = x86_arch_boost_init, + .arch_boost_exit = x86_arch_boost_exit, + .drv_read = x86_do_drv_read, + .drv_write = x86_do_drv_write, + .update_boost = x86_boost_set_msrs, + .extract_freq = x86_extract_freq, +}; + +int __init arch_acpi_cpufreq_init(struct acpi_cpufreq_common *acpi) +{ + acpi->ops = &x86_ops; + + acpi->feature_hw_pstate = boot_cpu_has(X86_FEATURE_HW_PSTATE); + acpi->const_loops = boot_cpu_has(X86_FEATURE_CONSTANT_TSC); + + return 0; +} + +static const struct x86_cpu_id acpi_cpufreq_ids[] = { + X86_FEATURE_MATCH(X86_FEATURE_ACPI), + X86_FEATURE_MATCH(X86_FEATURE_HW_PSTATE), + {} +}; +MODULE_DEVICE_TABLE(x86cpu, acpi_cpufreq_ids); -- 1.7.10.4

11 years

1
0
0 0

[PATCH linaro-acpi] [RFC 3/7] acpi: Use Hacks to allow compilation on arm environment

by Jonghwan Choi

To allow compilation of drivers & acpi with arm, use some hacks, Later, these hacks will be replaced with proper solutions. Signed-off-by: Jonghwan Choi <jhbird.choi(a)samsung.com> --- drivers/acpi/acpi_processor.c | 4 +++ drivers/acpi/processor_idle.c | 14 +++++++++++ drivers/cpufreq/acpi-cpufreq.c | 53 +++++++++++++++++++++++++++++++++++----- 3 files changed, 65 insertions(+), 6 deletions(-) diff --git a/drivers/acpi/acpi_processor.c b/drivers/acpi/acpi_processor.c index c29c2c3..6a89856 100644 --- a/drivers/acpi/acpi_processor.c +++ b/drivers/acpi/acpi_processor.c @@ -177,6 +177,7 @@ static int acpi_processor_hotadd_init(struct acpi_processor *pr) cpu_maps_update_begin(); cpu_hotplug_begin(); +#ifdef CONFIG_X86 ret = acpi_map_lsapic(pr->handle, pr->apic_id, &pr->id); if (ret) goto out; @@ -186,6 +187,7 @@ static int acpi_processor_hotadd_init(struct acpi_processor *pr) acpi_unmap_lsapic(pr->id); goto out; } +#endif /* * CPU got hot-added, but cpu_data is not initialized yet. Set a flag @@ -457,8 +459,10 @@ static void acpi_processor_remove(struct acpi_device *device) cpu_hotplug_begin(); /* Remove the CPU. */ +#ifdef CONFIG_X86 arch_unregister_cpu(pr->id); acpi_unmap_lsapic(pr->id); +#endif cpu_hotplug_done(); cpu_maps_update_done(); diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index 3dca36d..fae22f4 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -70,8 +70,10 @@ static DEFINE_PER_CPU(struct acpi_processor_cx * [CPUIDLE_STATE_MAX], static int disabled_by_idle_boot_param(void) { +#ifdef CONFIG_X86 return boot_option_idle_override == IDLE_POLL || boot_option_idle_override == IDLE_HALT; +#endif } /* @@ -118,7 +120,9 @@ static struct dmi_system_id processor_power_dmi_table[] = { static void acpi_safe_halt(void) { if (!tif_need_resched()) { +#ifdef CONFIG_X86 safe_halt(); +#endif local_irq_disable(); } } @@ -433,6 +437,7 @@ static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) } else { continue; } +#ifdef CONFIG_X86 if (cx.type == ACPI_STATE_C1 && (boot_option_idle_override == IDLE_NOMWAIT)) { /* @@ -448,6 +453,7 @@ static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) cx.entry_method = ACPI_CSTATE_HALT; snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); } +#endif } else { snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x", cx.address); @@ -748,7 +754,11 @@ static int acpi_idle_play_dead(struct cpuidle_device *dev, int index) while (1) { if (cx->entry_method == ACPI_CSTATE_HALT) +#ifdef CONFIG_X86 safe_halt(); +#else + ; +#endif else if (cx->entry_method == ACPI_CSTATE_SYSTEMIO) { inb(cx->address); /* See comment in acpi_idle_do_entry() */ @@ -843,7 +853,9 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev, } } +#ifdef CONFIG_X86 acpi_unlazy_tlb(smp_processor_id()); +#endif /* Tell the scheduler that we are going deep-idle: */ sched_clock_idle_sleep_event(); @@ -1121,7 +1133,9 @@ int acpi_processor_power_init(struct acpi_processor *pr) if (!first_run) { dmi_check_system(processor_power_dmi_table); +#ifdef CONFIG_X86 max_cstate = acpi_processor_cstate_check(max_cstate); +#endif if (max_cstate < ACPI_C_STATES_MAX) printk(KERN_NOTICE "ACPI: processor limited to max C-state %d\n", diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c index 000e4e0..80662b1 100644 --- a/drivers/cpufreq/acpi-cpufreq.c +++ b/drivers/cpufreq/acpi-cpufreq.c @@ -42,7 +42,9 @@ #include <acpi/processor.h> +#ifdef CONFIG_X86 #include <asm/msr.h> +#endif #include <asm/processor.h> #include <asm/cpufeature.h> @@ -84,6 +86,7 @@ static struct msr __percpu *msrs; static bool boost_state(unsigned int cpu) { +#ifdef CONFIG_X86 u32 lo, hi; u64 msr; @@ -97,6 +100,7 @@ static bool boost_state(unsigned int cpu) msr = lo | ((u64)hi << 32); return !(msr & MSR_K7_HWCR_CPB_DIS); } +#endif return false; } @@ -106,6 +110,7 @@ static void boost_set_msrs(bool enable, const struct cpumask *cpumask) u32 msr_addr; u64 msr_mask; +#ifdef CONFIG_X86 switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_INTEL: msr_addr = MSR_IA32_MISC_ENABLE; @@ -130,6 +135,7 @@ static void boost_set_msrs(bool enable, const struct cpumask *cpumask) } wrmsr_on_cpus(cpumask, msr_addr, msrs); +#endif } static int _store_boost(int val) @@ -185,16 +191,20 @@ cpufreq_freq_attr_rw(cpb); static int check_est_cpu(unsigned int cpuid) { +#ifdef CONFIG_X86 struct cpuinfo_x86 *cpu = &cpu_data(cpuid); return cpu_has(cpu, X86_FEATURE_EST); +#endif } static int check_amd_hwpstate_cpu(unsigned int cpuid) { +#ifdef CONFIG_X86 struct cpuinfo_x86 *cpu = &cpu_data(cpuid); return cpu_has(cpu, X86_FEATURE_HW_PSTATE); +#endif } static unsigned extract_io(u32 value, struct acpi_cpufreq_data *data) @@ -215,11 +225,12 @@ static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data) { int i; struct acpi_processor_performance *perf; - +#ifdef CONFIG_X86 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) msr &= AMD_MSR_RANGE; else msr &= INTEL_MSR_RANGE; +#endif perf = data->acpi_data; @@ -271,7 +282,9 @@ static void do_drv_read(void *_cmd) switch (cmd->type) { case SYSTEM_INTEL_MSR_CAPABLE: case SYSTEM_AMD_MSR_CAPABLE: +#ifdef CONFIG_X86 rdmsr(cmd->addr.msr.reg, cmd->val, h); +#endif break; case SYSTEM_IO_CAPABLE: acpi_os_read_port((acpi_io_address)cmd->addr.io.port, @@ -291,12 +304,16 @@ static void do_drv_write(void *_cmd) switch (cmd->type) { case SYSTEM_INTEL_MSR_CAPABLE: +#ifdef CONFIG_X86 rdmsr(cmd->addr.msr.reg, lo, hi); lo = (lo & ~INTEL_MSR_RANGE) | (cmd->val & INTEL_MSR_RANGE); wrmsr(cmd->addr.msr.reg, lo, hi); +#endif break; case SYSTEM_AMD_MSR_CAPABLE: +#ifdef CONFIG_X86 wrmsr(cmd->addr.msr.reg, cmd->val, 0); +#endif break; case SYSTEM_IO_CAPABLE: acpi_os_write_port((acpi_io_address)cmd->addr.io.port, @@ -337,6 +354,7 @@ static u32 get_cur_val(const struct cpumask *mask) return 0; switch (per_cpu(acfreq_data, cpumask_first(mask))->cpu_feature) { +#ifdef CONFIG_X86 case SYSTEM_INTEL_MSR_CAPABLE: cmd.type = SYSTEM_INTEL_MSR_CAPABLE; cmd.addr.msr.reg = MSR_IA32_PERF_CTL; @@ -345,6 +363,7 @@ static u32 get_cur_val(const struct cpumask *mask) cmd.type = SYSTEM_AMD_MSR_CAPABLE; cmd.addr.msr.reg = MSR_AMD_PERF_CTL; break; +#endif case SYSTEM_IO_CAPABLE: cmd.type = SYSTEM_IO_CAPABLE; perf = per_cpu(acfreq_data, cpumask_first(mask))->acpi_data; @@ -435,6 +454,7 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy, } switch (data->cpu_feature) { +#ifdef CONFIG_X86 case SYSTEM_INTEL_MSR_CAPABLE: cmd.type = SYSTEM_INTEL_MSR_CAPABLE; cmd.addr.msr.reg = MSR_IA32_PERF_CTL; @@ -445,6 +465,7 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy, cmd.addr.msr.reg = MSR_AMD_PERF_CTL; cmd.val = (u32) perf->states[next_perf_state].control; break; +#endif case SYSTEM_IO_CAPABLE: cmd.type = SYSTEM_IO_CAPABLE; cmd.addr.io.port = perf->control_register.address; @@ -484,7 +505,7 @@ static unsigned long acpi_cpufreq_guess_freq(struct acpi_cpufreq_data *data, unsigned int cpu) { struct acpi_processor_performance *perf = data->acpi_data; - +#ifdef CONFIG_X86 if (cpu_khz) { /* search the closest match to cpu_khz */ unsigned int i; @@ -501,11 +522,11 @@ acpi_cpufreq_guess_freq(struct acpi_cpufreq_data *data, unsigned int cpu) } perf->state = perf->state_count-1; return freqn; - } else { - /* assume CPU is at P0... */ - perf->state = 0; - return perf->states[0].core_frequency * 1000; } +#endif + /* assume CPU is at P0... */ + perf->state = 0; + return perf->states[0].core_frequency * 1000; } static void free_acpi_perf_data(void) @@ -626,6 +647,7 @@ static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c) * AL30: A Machine Check Exception (MCE) Occurring during an * Enhanced Intel SpeedStep Technology Ratio Change May Cause * Both Processor Cores to Lock Up. */ +#ifdef CONFIG_X86 if (c->x86_vendor == X86_VENDOR_INTEL) { if ((c->x86 == 15) && (c->x86_model == 6) && @@ -637,6 +659,7 @@ static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c) return -ENODEV; } } +#endif return 0; } #endif @@ -648,7 +671,11 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) unsigned int cpu = policy->cpu; struct acpi_cpufreq_data *data; unsigned int result = 0; +#ifdef CONFIG_X86 struct cpuinfo_x86 *c = &cpu_data(policy->cpu); +#else + struct cpuinfo_x86 *c = NULL; +#endif struct acpi_processor_performance *perf; #ifdef CONFIG_SMP static int blacklisted; @@ -676,8 +703,10 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) data->acpi_data = per_cpu_ptr(acpi_perf_data, cpu); per_cpu(acfreq_data, cpu) = data; +#ifdef CONFIG_X86 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) acpi_cpufreq_driver.flags |= CPUFREQ_CONST_LOOPS; +#endif result = acpi_processor_register_performance(data->acpi_data, cpu); if (result) @@ -700,13 +729,17 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) dmi_check_system(sw_any_bug_dmi_table); if (bios_with_sw_any_bug && !policy_is_shared(policy)) { policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; +#ifdef CONFIG_X86 cpumask_copy(policy->cpus, cpu_core_mask(cpu)); +#endif } if (check_amd_hwpstate_cpu(cpu) && !acpi_pstate_strict) { cpumask_clear(policy->cpus); cpumask_set_cpu(cpu, policy->cpus); +#ifdef CONFIG_X86 cpumask_copy(data->freqdomain_cpus, cpu_sibling_mask(cpu)); +#endif policy->shared_type = CPUFREQ_SHARED_TYPE_HW; pr_info_once(PFX "overriding BIOS provided _PSD data\n"); } @@ -726,12 +759,14 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) switch (perf->control_register.space_id) { case ACPI_ADR_SPACE_SYSTEM_IO: +#ifdef CONFIG_X86 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && boot_cpu_data.x86 == 0xf) { pr_debug("AMD K8 systems must use native drivers.\n"); result = -ENODEV; goto err_unreg; } +#endif pr_debug("SYSTEM IO addr space\n"); data->cpu_feature = SYSTEM_IO_CAPABLE; break; @@ -898,6 +933,7 @@ static struct cpufreq_driver acpi_cpufreq_driver = { static void __init acpi_cpufreq_boost_init(void) { +#ifdef CONFIG_X86 if (boot_cpu_has(X86_FEATURE_CPB) || boot_cpu_has(X86_FEATURE_IDA)) { msrs = msrs_alloc(); @@ -917,16 +953,19 @@ static void __init acpi_cpufreq_boost_init(void) cpu_notifier_register_done(); } +#endif } static void acpi_cpufreq_boost_exit(void) { +#ifdef CONFIG_X86 if (msrs) { unregister_cpu_notifier(&boost_nb); msrs_free(msrs); msrs = NULL; } +#endif } static int __init acpi_cpufreq_init(void) @@ -995,12 +1034,14 @@ MODULE_PARM_DESC(acpi_pstate_strict, late_initcall(acpi_cpufreq_init); module_exit(acpi_cpufreq_exit); +#ifdef CONFIG_X86 static const struct x86_cpu_id acpi_cpufreq_ids[] = { X86_FEATURE_MATCH(X86_FEATURE_ACPI), X86_FEATURE_MATCH(X86_FEATURE_HW_PSTATE), {} }; MODULE_DEVICE_TABLE(x86cpu, acpi_cpufreq_ids); +#endif static const struct acpi_device_id processor_device_ids[] = { {ACPI_PROCESSOR_OBJECT_HID, }, -- 1.7.10.4

11 years

1
0
0 0

[PATCH linaro-acpi] [RFC 4/7] arm64: Added cpu_data() macro for compilation

by Jonghwan Choi

Cpu_data macro is used to get cpu-related information in acpi-cpufreq driver. But there is no cpu_data macro in arm. For using cpu_data macro in both x86 and arm, I added cpu_data macro in arm and exported "DEFINE_PER_CPU(struct cpu, cpu_info)". Signed-off-by: Jonghwan Choi <jhbird.choi(a)samsung.com> --- arch/arm64/include/asm/cpu.h | 3 ++- arch/arm64/kernel/setup.c | 5 +++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h index 8625eb1..69db3e7 100644 --- a/arch/arm64/include/asm/cpu.h +++ b/arch/arm64/include/asm/cpu.h @@ -20,6 +20,7 @@ struct cpuinfo_arm { #endif }; -DECLARE_PER_CPU(struct cpuinfo_arm, cpu_data); +DECLARE_PER_CPU(struct cpuinfo_arm, cpu_info); +#define cpu_data(cpu) per_cpu(cpu_info, cpu) #endif diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c index 51fdb2c..149c3da 100644 --- a/arch/arm64/kernel/setup.c +++ b/arch/arm64/kernel/setup.c @@ -410,14 +410,15 @@ static int __init arm64_device_init(void) } arch_initcall(arm64_device_init); -static DEFINE_PER_CPU(struct cpu, cpu_data); +DEFINE_PER_CPU(struct cpu, cpu_info); +EXPORT_PER_CPU_SYMBOL(cpu_info); static int __init topology_init(void) { int i; for_each_possible_cpu(i) { - struct cpu *cpu = &per_cpu(cpu_data, i); + struct cpu *cpu = &per_cpu(cpu_info, i); cpu->hotpluggable = 1; register_cpu(cpu, i); } -- 1.7.10.4

11 years

1
0
0 0

[PATCH linaro-acpi] [RFC 2/7] cpufreq: Change CONFIG_ name from X86_ACPI_CPUFREQ to

by Jonghwan Choi

To use acpi_cpufreq in both x86 and arm64, change the CONFIG_'s name and location. Signed-off-by: Jonghwan Choi <jhbird.choi(a)samsung.com> --- drivers/cpufreq/Kconfig | 16 ++++++++++++++++ drivers/cpufreq/Kconfig.x86 | 26 +++++--------------------- drivers/cpufreq/Makefile | 2 +- 3 files changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig index cb5b936..cbc7925 100644 --- a/drivers/cpufreq/Kconfig +++ b/drivers/cpufreq/Kconfig @@ -232,6 +232,22 @@ depends on ARM || ARM64 source "drivers/cpufreq/Kconfig.arm" endmenu +config ACPI_CPUFREQ + tristate "ACPI Processor P-States driver" + depends on ACPI_PROCESSOR + help + This driver adds a CPUFreq driver which utilizes the ACPI + Processor Performance States. + This driver also supports Intel Enhanced Speedstep and newer + AMD CPUs. + + To compile this driver as a module, choose M here: the + module will be called acpi-cpufreq. + + For details, take a look at <file:Documentation/cpu-freq/>. + + If in doubt, say N. + menu "AVR32 CPU frequency scaling drivers" depends on AVR32 diff --git a/drivers/cpufreq/Kconfig.x86 b/drivers/cpufreq/Kconfig.x86 index d369349..fc3a3d7 100644 --- a/drivers/cpufreq/Kconfig.x86 +++ b/drivers/cpufreq/Kconfig.x86 @@ -29,26 +29,10 @@ config X86_PCC_CPUFREQ If in doubt, say N. -config X86_ACPI_CPUFREQ - tristate "ACPI Processor P-States driver" - depends on ACPI_PROCESSOR - help - This driver adds a CPUFreq driver which utilizes the ACPI - Processor Performance States. - This driver also supports Intel Enhanced Speedstep and newer - AMD CPUs. - - To compile this driver as a module, choose M here: the - module will be called acpi-cpufreq. - - For details, take a look at <file:Documentation/cpu-freq/>. - - If in doubt, say N. - config X86_ACPI_CPUFREQ_CPB default y bool "Legacy cpb sysfs knob support for AMD CPUs" - depends on X86_ACPI_CPUFREQ && CPU_SUP_AMD + depends on ACPI_CPUFREQ && CPU_SUP_AMD help The powernow-k8 driver used to provide a sysfs knob called "cpb" to disable the Core Performance Boosting feature of AMD CPUs. This @@ -113,7 +97,7 @@ config X86_POWERNOW_K7_ACPI config X86_POWERNOW_K8 tristate "AMD Opteron/Athlon64 PowerNow!" - depends on ACPI && ACPI_PROCESSOR && X86_ACPI_CPUFREQ + depends on ACPI && ACPI_PROCESSOR && ACPI_CPUFREQ help This adds the CPUFreq driver for K8/early Opteron/Athlon64 processors. Support for K10 and newer processors is now in acpi-cpufreq. @@ -125,7 +109,7 @@ config X86_POWERNOW_K8 config X86_AMD_FREQ_SENSITIVITY tristate "AMD frequency sensitivity feedback powersave bias" - depends on CPU_FREQ_GOV_ONDEMAND && X86_ACPI_CPUFREQ && CPU_SUP_AMD + depends on CPU_FREQ_GOV_ONDEMAND && ACPI_CPUFREQ && CPU_SUP_AMD help This adds AMD-specific powersave bias function to the ondemand governor, which allows it to make more power-conscious frequency @@ -157,7 +141,7 @@ config X86_SPEEDSTEP_CENTRINO depends on X86_32 || (X86_64 && ACPI_PROCESSOR) help This is deprecated and this functionality is now merged into - acpi_cpufreq (X86_ACPI_CPUFREQ). Use that driver instead of + acpi_cpufreq (ACPI_CPUFREQ). Use that driver instead of speedstep_centrino. This adds the CPUFreq driver for Enhanced SpeedStep enabled mobile CPUs. This means Intel Pentium M (Centrino) CPUs @@ -265,7 +249,7 @@ config X86_E_POWERSAVER This adds the CPUFreq driver for VIA C7 processors. However, this driver does not have any safeguards to prevent operating the CPU out of spec and is thus considered dangerous. Please use the regular ACPI cpufreq - driver, enabled by CONFIG_X86_ACPI_CPUFREQ. + driver, enabled by CONFIG_ACPI_CPUFREQ. If in doubt, say N. diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index 54a05c9..bfeb0fb 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_CPU_FREQ_GOV_INTERACTIVE) += cpufreq_interactive.o obj-$(CONFIG_CPU_FREQ_GOV_COMMON) += cpufreq_governor.o obj-$(CONFIG_GENERIC_CPUFREQ_CPU0) += cpufreq-cpu0.o +obj-$(CONFIG_ACPI_CPUFREQ) += acpi-cpufreq.o ############################################################################ ###### # x86 drivers. @@ -21,7 +22,6 @@ obj-$(CONFIG_GENERIC_CPUFREQ_CPU0) += cpufreq-cpu0.o # powernow-k8 can load then. ACPI is preferred to all other hardware-specific drivers. # speedstep-* is preferred over p4-clockmod. -obj-$(CONFIG_X86_ACPI_CPUFREQ) += acpi-cpufreq.o obj-$(CONFIG_X86_POWERNOW_K8) += powernow-k8.o obj-$(CONFIG_X86_PCC_CPUFREQ) += pcc-cpufreq.o obj-$(CONFIG_X86_POWERNOW_K6) += powernow-k6.o -- 1.7.10.4

11 years

1
0
0 0

[PATCH linaro-acpi] [RFC1/7] ACPI: Fix compile error in arch/x86/kernel/setup.c

by Jonghwan Choi

Fix "arch/x86/kernel/setup.c:1150:2: error: implicit declaration of function 'early_acpi_boot_init Add missing early_acpi_boot_init in acpi.h Signed-off-by: Jonghwan Choi <jhbird.choi(a)samsung.com> --- include/linux/acpi.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/acpi.h b/include/linux/acpi.h index ca3290d..307612f 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -115,6 +115,7 @@ static inline void acpi_initrd_override(void *data, size_t size) char * __acpi_map_table (unsigned long phys_addr, unsigned long size); void __acpi_unmap_table(char *map, unsigned long size); +int early_acpi_boot_init(void); int acpi_boot_init (void); void acpi_boot_table_init (void); int acpi_mps_check (void); -- 1.7.10.4

11 years

1
0
0 0

[PATCH linaro-acpi] [RFC 0/7] ACPI: Add ACPI cpufreq & cpuidle support for ARM

by Jonghwan Choi

Hi all, I would like to support acpi cpufreq & cpuidle for ARM. For supporting that, I tried to implement acpi cpufreq & cpuidle for ARM with ACPI. This patch is based on http://git.linaro.org/leg/acpi/leg-kernel.git. [CPUFREQ] I tried to separate this code into 3 parts which are common, x86-specific and arm-specific code. But as you know, there are too much x86-specific code in acpi-cpufreq.c When I tried to implement acpi-cpufreq-arm, there were a lot of compile error(due to x86-specific code). So I used #ifdef CONFIG_X86 to solve those errors.(and some hack codes) Later I will remove "#ifdef CONFIG_X86". And, if "ARM64 / ACPI: Introduce arch_register/unregister_cpu() for arm64" is merged, Then I can remove #ifdef for arch_un/register_cpu. [CPUIDLE] As Sudeep mentioned, I tried to use FFH. So I made cstate.c file in arm/arm64/kernel.(based on arch/x86/kernel/acpi/cstate.c) But I am not sure whether I implemented it properly. Jonghwan Choi (7): ACPI-Fix-compile-error-in-arch-x86-kernel-setup.c.patch cpufreq-Change-CONFIG_-name-from-X86_ACPI_CPUFREQ-to.patch acpi-Use-Hacks-to-allow-compilation-on-arm-environme.patch arm64-Change-struct-cpuinfo_arm.patch cpufreq-Add-ACPI-cpufreq-support-for-ARM.patch acpi-Add-ACPI-cpuidle-support-for-ARM.patch acpi-Allow-ACPI_PROCESSOR-for-ARM64.patch Thanks Best Regards

11 years

1
0
0 0

[PATCH] DSDT: remove clocks

by Graeme Gregory

This patch is prototype and goes with the equivalent patch for pl011 uart. It just just to show the new structure of DSDT if we continue with this way of doing clocks. Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org> --- platforms/rtsm_ve-aemv8a.acpi/dsdt.asl | 110 +++++---------------------------- 1 file changed, 17 insertions(+), 93 deletions(-) diff --git a/platforms/rtsm_ve-aemv8a.acpi/dsdt.asl b/platforms/rtsm_ve-aemv8a.acpi/dsdt.asl index 43ac170..3222e2f 100644 --- a/platforms/rtsm_ve-aemv8a.acpi/dsdt.asl +++ b/platforms/rtsm_ve-aemv8a.acpi/dsdt.asl @@ -347,33 +347,6 @@ DefinitionBlock ( } } - Device (CLK0) { - Name (_HID, "LNRO0008") - Name (_UID, 0) - - Method (FREQ, 0x0, NotSerialized) { - Return (24000000) - } - } - - Device (CLK1) { - Name (_HID, "LNRO0008") - Name (_UID, 1) - - Method (FREQ, 0x0, NotSerialized) { - Return (1000000) - } - } - - Device (CLK2) { - Name (_HID, "LNRO0008") - Name (_UID, 2) - - Method (FREQ, 0x0, NotSerialized) { - Return (32768) - } - } - Device (FPGA) { Name (_HID, "ACPI0004") Name (_UID, 0) @@ -494,20 +467,6 @@ DefinitionBlock ( Name (_HID, "AMBA0000") Name (_UID, 0) - /* Define 'apb_pclk' as a default clock source since it is - common with devices below */ - - Method(_DSM, 4, NotSerialized) { - Store (Package (2) - { - "clock-name", "apb_pclk \\_SB.SMB.CLK0", - }, Local0) - - DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) - - Return (Local0) - } - Device (SCT0) { Name (_HID, "LNRO000C") Name (_UID, 0) @@ -518,17 +477,6 @@ DefinitionBlock ( }) Return (RBUF) } - Method(_DSM, 4, Serialized) { - Store (Package (4) - { - "clock-name", "refclk \\_SB.SMB.CLK2", - "clock-name", "timclk \\_SB.SMB.CLK1", - }, Local0) - - DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) - - Return (Local0) - } } Device (AAC0) { @@ -557,16 +505,6 @@ DefinitionBlock ( }) Return (RBUF) } - Method(_DSM, 4, Serialized) { - Store (Package (2) - { - "clock-name", "MCLK \\_SB.SMB.CLK0", - }, Local0) - - DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) - - Return (Local0) - } } Device (KMI0) { @@ -581,16 +519,6 @@ DefinitionBlock ( }) Return (RBUF) } - Method(_DSM, 4, Serialized) { - Store (Package (2) - { - "clock-name", "KMIREFCLK \\_SB.SMB.CLK0", - }, Local0) - - DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) - - Return (Local0) - } } Device (KMI1) { @@ -605,16 +533,6 @@ DefinitionBlock ( }) Return (RBUF) } - Method(_DSM, 4, NotSerialized) { - Store (Package (2) - { - "clock-name", "KMIREFCLK \\_SB.SMB.CLK0", - }, Local0) - - DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) - - Return (Local0) - } } Device (SER0) { @@ -629,6 +547,10 @@ DefinitionBlock ( }) Return (RBUF) } + + Name (_PRP, Package() { + Package(2) {"clock-rate", 24000000} + }) } Device (SER1) { @@ -643,7 +565,11 @@ DefinitionBlock ( }) Return (RBUF) } - } + + Name (_PRP, Package() { + Package(2) {"clock-rate", 24000000} + }) + } Device (SER2) { Name (_HID, "LNRO000A") @@ -657,6 +583,10 @@ DefinitionBlock ( }) Return (RBUF) } + + Name (_PRP, Package() { + Package(2) {"clock-rate", 24000000} + }) } Device (SER3) { @@ -671,6 +601,10 @@ DefinitionBlock ( }) Return (RBUF) } + + Name (_PRP, Package() { + Package(2) {"clock-rate", 24000000} + }) } Device (WDT0) { @@ -741,16 +675,6 @@ DefinitionBlock ( }) Return (RBUF) } - Method(_DSM, 4, Serialized) { - Store (Package (2) - { - "clock-name", "CCLDCLK \\_SB.SMB.CLK0", - }, Local0) - - DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) - - Return (Local0) - } } } // End of AMBA -- 1.9.1

11 years

1
0
0 0

[PATCH] serial: amba-pl011: chance ACPI support to be clockless

by Graeme Gregory

Instead of making clock devices in ACPI which is non standard assume that the firmware is going to handle clock enable/disable for us and just read the clock rate from _PRP in ASL. This is currently prototype as it needs a new amba bus driver for ACPI as trying to interleive ACPI support in old driver leaves a mess of nested ifs. Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org> --- drivers/tty/serial/amba-pl011.c | 74 +++++++++++++++++++++++++++++++---------- 1 file changed, 57 insertions(+), 17 deletions(-) diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c index dacf0a0..7ec29ea 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -58,6 +58,7 @@ #include <linux/pinctrl/consumer.h> #include <linux/sizes.h> #include <linux/io.h> +#include <linux/acpi.h> #define UART_NR 14 @@ -1482,11 +1483,13 @@ static int pl011_hwinit(struct uart_port *port) /* * Try to enable the clock producer. */ - retval = clk_prepare_enable(uap->clk); - if (retval) - goto out; + if (uap->clk) { + retval = clk_prepare_enable(uap->clk); + if (retval) + goto out; - uap->port.uartclk = clk_get_rate(uap->clk); + uap->port.uartclk = clk_get_rate(uap->clk); + } /* Clear pending error and receive interrupts */ writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS | @@ -1604,7 +1607,8 @@ static int pl011_startup(struct uart_port *port) return 0; clk_dis: - clk_disable_unprepare(uap->clk); + if (uap->clk) + clk_disable_unprepare(uap->clk); return retval; } @@ -2011,9 +2015,13 @@ static int __init pl011_console_setup(struct console *co, char *options) /* Allow pins to be muxed in and configured */ pinctrl_pm_select_default_state(uap->port.dev); - ret = clk_prepare(uap->clk); - if (ret) - return ret; + if (uap->clk) { + ret = clk_prepare(uap->clk); + if (ret) + return ret; + + uap->port.uartclk = clk_get_rate(uap->clk); + } if (dev_get_platdata(uap->port.dev)) { struct amba_pl011_data *plat; @@ -2023,8 +2031,6 @@ static int __init pl011_console_setup(struct console *co, char *options) plat->init(); } - uap->port.uartclk = clk_get_rate(uap->clk); - if (options) uart_parse_options(options, &baud, &parity, &bits, &flow); else @@ -2091,10 +2097,47 @@ static int pl011_probe_dt_alias(int index, struct device *dev) return ret; } +static int pl011_dt_probe(int index, struct uart_amba_port *uap, + struct device *dev) +{ + int ret; + + ret = pl011_probe_dt_alias(index, dev); + + uap->clk = devm_clk_get(dev, NULL); + if (IS_ERR(uap->clk)) + ret = PTR_ERR(uap->clk); + + return ret; +} + +static int pl011_acpi_probe(struct uart_amba_port *uap, acpi_handle handle, + struct device *dev) +{ + struct acpi_device *acpi_dev; + int ret; + u32 clkrate = 0; + + if (acpi_bus_get_device(handle, &acpi_dev)) { + dev_dbg(dev, "ACPI device not found in %s!\n", __func__); + return -ENODEV; + } + + ret = acpi_dev_get_property_u32(acpi_dev, "clock-rate", &clkrate); + + if (!ret) + uap->port.uartclk = clkrate; + + dev_info(dev, "clkrate %d from AML\n", clkrate); + + return ret; +} + static int pl011_probe(struct amba_device *dev, const struct amba_id *id) { struct uart_amba_port *uap; struct vendor_data *vendor = id->data; + acpi_handle handle = ACPI_HANDLE(&dev->dev); void __iomem *base; int i, ret; @@ -2114,7 +2157,10 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id) goto out; } - i = pl011_probe_dt_alias(i, &dev->dev); + if (handle) + pl011_acpi_probe(uap, handle, &dev->dev); + else + pl011_dt_probe(i, uap, &dev->dev); base = devm_ioremap(&dev->dev, dev->res.start, resource_size(&dev->res)); @@ -2123,12 +2169,6 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id) goto out; } - uap->clk = devm_clk_get(&dev->dev, NULL); - if (IS_ERR(uap->clk)) { - ret = PTR_ERR(uap->clk); - goto out; - } - uap->vendor = vendor; uap->lcrh_rx = vendor->lcrh_rx; uap->lcrh_tx = vendor->lcrh_tx; -- 1.9.1

11 years

1
0
0 0

[PATCH v8 0/3] PSCI v0.2 support and DT bindings

by Ashwin Chaugule

This patchset introduces some functions as defined in the PSCI v0.2 spec and a corresponding DT binding to differentiate it from previous PSCI versions. Since PSCIv0.2 has standard function IDs, it is possible to statically assign them rather than depend on values from DT. This patchset depends on the PSCI header (/uapi/linux/psci.h) introduced by http://www.spinics.net/lists/arm-kernel/msg319712.html Changes in v8: - Replace msleep(100) with 10 x msleep(10) Changes in v7: - Add two new functions: SYSTEM_OFF and SYSTEM_RESET as defined in PSCIv0.2. - Added a delay before calling cpu_kill to avoid race with cpu_die. Changes in v6: - rebase on top of uapi/linux/psci.h introduced by Anups patch http://www.spinics.net/lists/arm-kernel/msg319712.html - rebase on top of Catalins tree tip. Changes in v5: - Add uapi/linux/psci.h to kbuild - ret with err if PSCI_ID_VERSION is not implemented. Changes in v4: - Correct copyright banner format. - Check if PSCI Version ID is supported. - Add all PSCI RET codes in uapi header. - Explicitely ret 1 from psci_cpu_kill() Changes in v3: - Roll up common functionality for getting conduit method. - Remove #defines for ARM32 and ARM64 in uapi/linux/psci.h - Remove functions not supported by PSCI v0.1 - Misc cleanups. - Add PSCI_AFFINITY_INFO return types in uapi header. - Changed function names for PSCI v0.1 and PSCI v0.2 - Added copyright info to uapi header. - Fixed args to affinity_info call. - Fix typo in psci_init definition when PSCI is not defined. Changes in v2: - Add AFFINITY_INFO and MIGRATE_INFO_TYPE functions. - Add binding Documentation. - Add function to get PSCI version. - Add common #defines in uapi/linux/psci.h - Implement cpu_kill and check if CPU is dead via AFFINITY_INFO. - Misc cleanups. Changes in v1: - Add new binding "arm, psci-0.2" - Separate conduit and PSCI function assignment methods. Ashwin Chaugule (3): PSCI: Add initial support for PSCIv0.2 functions Documentation: devicetree: Add new binding for PSCIv0.2 ARM: Check if a CPU has gone offline Documentation/devicetree/bindings/arm/psci.txt | 35 ++++- arch/arm/include/asm/psci.h | 7 +- arch/arm/kernel/psci.c | 196 +++++++++++++++++++----- arch/arm/kernel/psci_smp.c | 32 ++++ arch/arm64/include/asm/psci.h | 2 +- arch/arm64/kernel/psci.c | 200 ++++++++++++++++++++----- include/uapi/linux/psci.h | 5 + 7 files changed, 399 insertions(+), 78 deletions(-) -- 1.8.3.2

11 years

4
11
0 0

[PATCH v7 0/3] PSCI v0.2 support and DT bindings

by Ashwin Chaugule

This patchset introduces some functions as defined in the PSCI v0.2 spec and a corresponding DT binding to differentiate it from previous PSCI versions. Since PSCIv0.2 has standard function IDs, it is possible to statically assign them rather than depend on values from DT. This patchset depends on the PSCI header (/uapi/linux/psci.h) introduced by http://www.spinics.net/lists/arm-kernel/msg319712.html Changes in v7: - Add two new functions: SYSTEM_OFF and SYSTEM_RESET as defined in PSCIv0.2. - Added a delay before calling cpu_kill to avoid race with cpu_die. Changes in v6: - rebase on top of uapi/linux/psci.h introduced by Anups patch http://www.spinics.net/lists/arm-kernel/msg319712.html - rebase on top of Catalins tree tip. Changes in v5: - Add uapi/linux/psci.h to kbuild - ret with err if PSCI_ID_VERSION is not implemented. Changes in v4: - Correct copyright banner format. - Check if PSCI Version ID is supported. - Add all PSCI RET codes in uapi header. - Explicitely ret 1 from psci_cpu_kill() Changes in v3: - Roll up common functionality for getting conduit method. - Remove #defines for ARM32 and ARM64 in uapi/linux/psci.h - Remove functions not supported by PSCI v0.1 - Misc cleanups. - Add PSCI_AFFINITY_INFO return types in uapi header. - Changed function names for PSCI v0.1 and PSCI v0.2 - Added copyright info to uapi header. - Fixed args to affinity_info call. - Fix typo in psci_init definition when PSCI is not defined. Changes in v2: - Add AFFINITY_INFO and MIGRATE_INFO_TYPE functions. - Add binding Documentation. - Add function to get PSCI version. - Add common #defines in uapi/linux/psci.h - Implement cpu_kill and check if CPU is dead via AFFINITY_INFO. - Misc cleanups. Changes in v1: - Add new binding "arm, psci-0.2" - Separate conduit and PSCI function assignment methods. *** BLURB HERE *** Ashwin Chaugule (3): PSCI: Add initial support for PSCIv0.2 functions Documentation: devicetree: Add new binding for PSCIv0.2 ARM: Check if a CPU has gone offline Documentation/devicetree/bindings/arm/psci.txt | 35 ++++- arch/arm/include/asm/psci.h | 7 +- arch/arm/kernel/psci.c | 196 +++++++++++++++++++----- arch/arm/kernel/psci_smp.c | 32 ++++ arch/arm64/include/asm/psci.h | 2 +- arch/arm64/kernel/psci.c | 200 ++++++++++++++++++++----- include/uapi/linux/psci.h | 5 + 7 files changed, 399 insertions(+), 78 deletions(-) -- 1.8.3.2

11 years

2
5
0 0

leg-kernel tag leg-20140425.0 released

by Graeme Gregory

The leg-kernel release has been made and tagged as leg-20140425.0 This is based on mainline kernel v3.15-rc2 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: https://git.linaro.org/leg/acpi/leg-kernel.git/commit/e094433f0d6833e1b9b5f… Notes :-

11 years

1
0
0 0

[PATCH v6 0/3] PSCI v0.2 support and DT bindings

by Ashwin Chaugule

This patchset introduces some functions as defined in the PSCI v0.2 spec and a corresponding DT binding to differentiate it from previous PSCI versions. Since PSCIv0.2 has standard function IDs, it is possible to statically assign them rather than depend on values from DT. This patchset depends on the PSCI header (/uapi/linux/psci.h) introduced by http://www.spinics.net/lists/arm-kernel/msg319712.html Changes in v6: - rebase on top of uapi/linux/psci.h introduced by Anups patch http://www.spinics.net/lists/arm-kernel/msg319712.html - rebase on top of Catalins tree tip. Changes in v5: - Add uapi/linux/psci.h to kbuild - ret with err if PSCI_ID_VERSION is not implemented. Changes in v4: - Correct copyright banner format. - Check if PSCI Version ID is supported. - Add all PSCI RET codes in uapi header. - Explicitely ret 1 from psci_cpu_kill() Changes in v3: - Roll up common functionality for getting conduit method. - Remove #defines for ARM32 and ARM64 in uapi/linux/psci.h - Remove functions not supported by PSCI v0.1 - Misc cleanups. - Add PSCI_AFFINITY_INFO return types in uapi header. - Changed function names for PSCI v0.1 and PSCI v0.2 - Added copyright info to uapi header. - Fixed args to affinity_info call. - Fix typo in psci_init definition when PSCI is not defined. Changes in v2: - Add AFFINITY_INFO and MIGRATE_INFO_TYPE functions. - Add binding Documentation. - Add function to get PSCI version. - Add common #defines in uapi/linux/psci.h - Implement cpu_kill and check if CPU is dead via AFFINITY_INFO. - Misc cleanups. Changes in v1: - Add new binding "arm, psci-0.2" - Separate conduit and PSCI function assignment methods. Ashwin Chaugule (3): PSCI: Add initial support for PSCIv0.2 functions Documentation: devicetree: Add new binding for PSCIv0.2 ARM: Check if a CPU has gone offline Documentation/devicetree/bindings/arm/psci.txt | 35 ++++- arch/arm/include/asm/psci.h | 7 +- arch/arm/kernel/psci.c | 179 +++++++++++++++++++----- arch/arm/kernel/psci_smp.c | 21 +++ arch/arm64/include/asm/psci.h | 2 +- arch/arm64/kernel/psci.c | 183 ++++++++++++++++++++----- include/uapi/linux/psci.h | 5 + 7 files changed, 354 insertions(+), 78 deletions(-) -- 1.8.3.2

11 years

5
14
0 0

[PATCH linaro-acpi] [RFC] cpufreq: Add ACPI cpufreq support for ARM

by Jonghwan Choi

Hi all, I would like to support acpi-cpufreq for ARM. For that, Firstly, I made new file which is a apci-freq-arm.c. But some people, such as Rafael, Sudeep and Hanjun Guo, worried about that. What ther are worried about is there are too many duplicate code between acpi-cpufreq.c and acpi-cpifre-arm.c So, I tried to separate this code into 3 parts which are common, x86-specific and arm-specific code. I tried to separate soc-specific code from acpi-cpufreq.c as much as possible. But as you know, there are too much x86-specific code in acpi-cpufreq.c When I tried to implement acpi-cpufreq-arm, there were a lot of compile error(due to x86-specific code). So I used #ifdef CONFIG_X86 to solve those errors.(and some hack codes) In this patch, I mostly focused on cpufreq. Later I will remove #ifdef CONFIG_X86. I would like your reviews and comments. This patch is based on "http://git.linaro.org/leg/acpi/leg-kernel.git" Last commit : commit a493444ce7f1792b44897160454149dc31ca208b Author: Graeme Gregory <graeme.gregory(a)linaro.org> Date: Tue Feb 11 09:21:17 2014 +0000 linaro-configs: add enterprise-distro.conf Signed-off-by: Graeme Gregory graeme.gregory(a)linaro.org Thanks Best Regards Signed-off-by: Jonghwan Choi <jhbird.choi(a)samsung.com> --- arch/arm64/Kconfig | 12 ++ arch/arm64/include/asm/cpu.h | 3 +- arch/arm64/include/asm/processor.h | 2 + arch/arm64/kernel/process.c | 6 + arch/arm64/kernel/setup.c | 5 +- drivers/acpi/Kconfig | 3 +- drivers/acpi/acpi_processor.c | 4 + drivers/acpi/processor_idle.c | 12 ++ drivers/cpufreq/Kconfig | 2 +- drivers/cpufreq/Kconfig.arm | 16 ++ drivers/cpufreq/Makefile | 3 +- drivers/cpufreq/acpi-cpufreq.c | 419 +++++------------------------------- drivers/cpufreq/acpi-cpufreq.h | 68 ++++++ drivers/cpufreq/acpi-cpufreq_arm.c | 88 ++++++++ drivers/cpufreq/acpi-cpufreq_x86.c | 334 ++++++++++++++++++++++++++++ include/linux/acpi.h | 1 + 16 files changed, 604 insertions(+), 373 deletions(-) create mode 100644 drivers/cpufreq/acpi-cpufreq.h create mode 100644 drivers/cpufreq/acpi-cpufreq_arm.c create mode 100644 drivers/cpufreq/acpi-cpufreq_x86.c diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 94cc542..e150e60 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -108,6 +108,13 @@ config IOMMU_HELPER config KERNEL_MODE_NEON def_bool y +config ARCH_HAS_CPUFREQ + bool + help + Internal node to signify that the ARCH has CPUFREQ support + and that the relevant menu configurations are displayed for + it. + source "init/Kconfig" source "kernel/Kconfig.freezer" @@ -116,6 +123,7 @@ menu "Platform selection" config ARCH_VEXPRESS bool "ARMv8 software model (Versatile Express)" + select ARCH_HAS_CPUFREQ select ARCH_REQUIRE_GPIOLIB select COMMON_CLK_VERSATILE select POWER_RESET_VEXPRESS @@ -325,6 +333,10 @@ endmenu menu "CPU Power Management" +if ARCH_HAS_CPUFREQ +source "drivers/cpufreq/Kconfig" +endif + source "drivers/cpuidle/Kconfig" endmenu diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h index 8625eb1..69db3e7 100644 --- a/arch/arm64/include/asm/cpu.h +++ b/arch/arm64/include/asm/cpu.h @@ -20,6 +20,7 @@ struct cpuinfo_arm { #endif }; -DECLARE_PER_CPU(struct cpuinfo_arm, cpu_data); +DECLARE_PER_CPU(struct cpuinfo_arm, cpu_info); +#define cpu_data(cpu) per_cpu(cpu_info, cpu) #endif diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index 50ce951..7196873 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -47,6 +47,8 @@ #define ARCH_LOW_ADDRESS_LIMIT PHYS_MASK #endif /* __KERNEL__ */ +enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, + IDLE_POLL}; struct debug_info { /* Have we suspended stepping by a debugger? */ int suspended_step; diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 1c0a9be..1c985a9 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -86,6 +86,12 @@ void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd); EXPORT_SYMBOL_GPL(arm_pm_restart); /* + * Idle related variables and functions */ unsigned long +boot_option_idle_override = IDLE_NO_OVERRIDE; +EXPORT_SYMBOL(boot_option_idle_override); + +/* * This is our default idle handler. */ void arch_cpu_idle(void) diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c index fecf272..99b973b 100644 --- a/arch/arm64/kernel/setup.c +++ b/arch/arm64/kernel/setup.c @@ -377,14 +377,15 @@ static int __init arm64_device_init(void) } arch_initcall(arm64_device_init); -static DEFINE_PER_CPU(struct cpu, cpu_data); +DEFINE_PER_CPU(struct cpu, cpu_info); +EXPORT_PER_CPU_SYMBOL(cpu_info); static int __init topology_init(void) { int i; for_each_possible_cpu(i) { - struct cpu *cpu = &per_cpu(cpu_data, i); + struct cpu *cpu = &per_cpu(cpu_info, i); cpu->hotpluggable = 1; register_cpu(cpu, i); } diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index cbc5dfc..961211f 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -152,7 +152,7 @@ config ACPI_PROCESSOR tristate "Processor" select THERMAL select CPU_IDLE - depends on X86 || IA64 + depends on X86 || IA64 || ARM64 default y help This driver installs ACPI as the idle handler for Linux and uses diff --git a/drivers/acpi/acpi_processor.c b/drivers/acpi/acpi_processor.c index c29c2c3..6a89856 100644 --- a/drivers/acpi/acpi_processor.c +++ b/drivers/acpi/acpi_processor.c @@ -177,6 +177,7 @@ static int acpi_processor_hotadd_init(struct acpi_processor *pr) cpu_maps_update_begin(); cpu_ho\\12.36.155.51\jhbirdchoi\Kernel\leg-kerneltplug_begin(); +#ifdef CONFIG_X86 ret = acpi_map_lsapic(pr->handle, pr->apic_id, &pr->id); if (ret) goto out; @@ -186,6 +187,7 @@ static int acpi_processor_hotadd_init(struct acpi_processor *pr) acpi_unmap_lsapic(pr->id); goto out; } +#endif /* * CPU got hot-added, but cpu_data is not initialized yet. Set a flag @@ -457,8 +459,10 @@ static void acpi_processor_remove(struct acpi_device *device) cpu_hotplug_begin(); /* Remove the CPU. */ +#ifdef CONFIG_X86 arch_unregister_cpu(pr->id); acpi_unmap_lsapic(pr->id); +#endif cpu_hotplug_done(); cpu_maps_update_done(); diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index 3dca36d..0556a0a 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -70,8 +70,10 @@ static DEFINE_PER_CPU(struct acpi_processor_cx * [CPUIDLE_STATE_MAX], static int disabled_by_idle_boot_param(void) { +#ifdef CONFIG_X86 return boot_option_idle_override == IDLE_POLL || boot_option_idle_override == IDLE_HALT; +#endif } /* @@ -118,7 +120,9 @@ static struct dmi_system_id processor_power_dmi_table[] = { static void acpi_safe_halt(void) { if (!tif_need_resched()) { +#ifdef CONFIG_X86 safe_halt(); +#endif local_irq_disable(); } } @@ -748,7 +752,11 @@ static int acpi_idle_play_dead(struct cpuidle_device *dev, int index) while (1) { if (cx->entry_method == ACPI_CSTATE_HALT) +#ifdef CONFIG_X86 safe_halt(); +#else + acpi_safe_halt(); +#endif else if (cx->entry_method == ACPI_CSTATE_SYSTEMIO) { inb(cx->address); /* See comment in acpi_idle_do_entry() */ @@ -843,7 +851,9 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev, } } +#ifdef CONFIG_X86 acpi_unlazy_tlb(smp_processor_id()); +#endif /* Tell the scheduler that we are going deep-idle: */ sched_clock_idle_sleep_event(); @@ -1121,7 +1131,9 @@ int acpi_processor_power_init(struct acpi_processor *pr) if (!first_run) { dmi_check_system(processor_power_dmi_table); +#ifdef CONFIG_X86 max_cstate = acpi_processor_cstate_check(max_cstate); +#endif if (max_cstate < ACPI_C_STATES_MAX) printk(KERN_NOTICE "ACPI: processor limited to max C-state %d\n", diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig index 3a7202d..6417406 100644 --- a/drivers/cpufreq/Kconfig +++ b/drivers/cpufreq/Kconfig @@ -228,7 +228,7 @@ source "drivers/cpufreq/Kconfig.x86" endmenu menu "ARM CPU frequency scaling drivers" -depends on ARM +depends on ARM64 source "drivers/cpufreq/Kconfig.arm" endmenu diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 3129749..ef00a4c 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -16,6 +16,21 @@ config ARM_DT_BL_CPUFREQ This enables probing via DT for Generic CPUfreq driver for ARM big.LITTLE platform. This gets frequency tables from DT. +config ARM_ACPI_CPUFREQ + tristate "ACPI Processor P-States driver" + depends on ACPI_PROCESSOR + help + This driver adds a CPUFreq driver which utilizes the ACPI + Processor Performance States. + This driver also supports ARM CPUs. + + To compile this driver as a module, choose M here: the + module will be called acpi-cpufreq. + + For details, take a look at <file:Documentation/cpu-freq/>. + + If in doubt, say N. + config ARM_EXYNOS_CPUFREQ bool @@ -249,3 +264,4 @@ config ARM_VEXPRESS_SPC_CPUFREQ help This add the CPUfreq driver support for Versatile Express big.LITTLE platforms using SPC for power management. + diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index 0fd80cb..83e44f6 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -21,7 +21,8 @@ obj-$(CONFIG_GENERIC_CPUFREQ_CPU0) += cpufreq-cpu0.o # powernow-k8 can load then. ACPI is preferred to all other hardware-specific drivers. # speedstep-* is preferred over p4-clockmod. -obj-$(CONFIG_X86_ACPI_CPUFREQ) += acpi-cpufreq.o +obj-$(CONFIG_X86_ACPI_CPUFREQ) += acpi-cpufreq.o acpi-cpufreq_x86.o +obj-$(CONFIG_ARM_ACPI_CPUFREQ) += acpi-cpufreq.o acpi-cpufreq_arm.o obj-$(CONFIG_X86_POWERNOW_K8) += powernow-k8.o obj-$(CONFIG_X86_PCC_CPUFREQ) += pcc-cpufreq.o obj-$(CONFIG_X86_POWERNOW_K6) += powernow-k6.o diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c index 18448a7..26bf7112 100644 --- a/drivers/cpufreq/acpi-cpufreq.c +++ b/drivers/cpufreq/acpi-cpufreq.c @@ -42,37 +42,17 @@ #include <acpi/processor.h> -#include <asm/msr.h> +#include <asm/cpu.h> #include <asm/processor.h> -#include <asm/cpufeature.h> + +#include "acpi-cpufreq.h" MODULE_AUTHOR("Paul Diefenbaugh, Dominik Brodowski"); MODULE_DESCRIPTION("ACPI Processor P-States Driver"); MODULE_LICENSE("GPL"); -#define PFX "acpi-cpufreq: " - -enum { - UNDEFINED_CAPABLE = 0, - SYSTEM_INTEL_MSR_CAPABLE, - SYSTEM_AMD_MSR_CAPABLE, - SYSTEM_IO_CAPABLE, -}; - -#define INTEL_MSR_RANGE (0xffff) -#define AMD_MSR_RANGE (0x7) - -#define MSR_K7_HWCR_CPB_DIS (1ULL << 25) - -struct acpi_cpufreq_data { - struct acpi_processor_performance *acpi_data; - struct cpufreq_frequency_table *freq_table; - unsigned int resume; - unsigned int cpu_feature; - cpumask_var_t freqdomain_cpus; -}; - static DEFINE_PER_CPU(struct acpi_cpufreq_data *, acfreq_data); +static struct acpi_cpufreq_common *acpi; /* acpi_perf_data is a pointer to percpu data. */ static struct acpi_processor_performance __percpu *acpi_perf_data; @@ -80,62 +60,12 @@ static struct acpi_processor_performance __percpu *acpi_perf_data; static struct cpufreq_driver acpi_cpufreq_driver; static unsigned int acpi_pstate_strict; -static struct msr __percpu *msrs; - -static bool boost_state(unsigned int cpu) -{ - u32 lo, hi; - u64 msr; - - switch (boot_cpu_data.x86_vendor) { - case X86_VENDOR_INTEL: - rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi); - msr = lo | ((u64)hi << 32); - return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); - case X86_VENDOR_AMD: - rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi); - msr = lo | ((u64)hi << 32); - return !(msr & MSR_K7_HWCR_CPB_DIS); - } - return false; -} - -static void boost_set_msrs(bool enable, const struct cpumask *cpumask) -{ - u32 cpu; - u32 msr_addr; - u64 msr_mask; - - switch (boot_cpu_data.x86_vendor) { - case X86_VENDOR_INTEL: - msr_addr = MSR_IA32_MISC_ENABLE; - msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE; - break; - case X86_VENDOR_AMD: - msr_addr = MSR_K7_HWCR; - msr_mask = MSR_K7_HWCR_CPB_DIS; - break; - default: - return; - } - - rdmsr_on_cpus(cpumask, msr_addr, msrs); - - for_each_cpu(cpu, cpumask) { - struct msr *reg = per_cpu_ptr(msrs, cpu); - if (enable) - reg->q &= ~msr_mask; - else - reg->q |= msr_mask; - } - - wrmsr_on_cpus(cpumask, msr_addr, msrs); -} static int _store_boost(int val) { get_online_cpus(); - boost_set_msrs(val, cpu_online_mask); + if (acpi->ops->update_boost) + acpi->ops->update_boost(val, cpu_online_mask); put_online_cpus(); pr_debug("Core Boosting %sabled.\n", val ? "en" : "dis"); @@ -151,13 +81,12 @@ static ssize_t show_freqdomain_cpus(struct cpufreq_policy *policy, char *buf) cpufreq_freq_attr_ro(freqdomain_cpus); -#ifdef CONFIG_X86_ACPI_CPUFREQ_CPB static ssize_t store_boost(const char *buf, size_t count) { int ret; unsigned long val = 0; - if (!acpi_cpufreq_driver.boost_supported) + if (!acpi->boost_supported) return -EINVAL; ret = kstrtoul(buf, 10, &val); @@ -181,131 +110,23 @@ static ssize_t show_cpb(struct cpufreq_policy *policy, char *buf) } cpufreq_freq_attr_rw(cpb); -#endif - -static int check_est_cpu(unsigned int cpuid) -{ - struct cpuinfo_x86 *cpu = &cpu_data(cpuid); - - return cpu_has(cpu, X86_FEATURE_EST); -} - -static int check_amd_hwpstate_cpu(unsigned int cpuid) -{ - struct cpuinfo_x86 *cpu = &cpu_data(cpuid); - - return cpu_has(cpu, X86_FEATURE_HW_PSTATE); -} - -static unsigned extract_io(u32 value, struct acpi_cpufreq_data *data) -{ - struct acpi_processor_performance *perf; - int i; - - perf = data->acpi_data; - - for (i = 0; i < perf->state_count; i++) { - if (value == perf->states[i].status) - return data->freq_table[i].frequency; - } - return 0; -} - -static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data) -{ - int i; - struct acpi_processor_performance *perf; - - if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) - msr &= AMD_MSR_RANGE; - else - msr &= INTEL_MSR_RANGE; - - perf = data->acpi_data; - - for (i = 0; data->freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { - if (msr == perf->states[data->freq_table[i].driver_data].status) - return data->freq_table[i].frequency; - } - return data->freq_table[0].frequency; -} - -static unsigned extract_freq(u32 val, struct acpi_cpufreq_data *data) -{ - switch (data->cpu_feature) { - case SYSTEM_INTEL_MSR_CAPABLE: - case SYSTEM_AMD_MSR_CAPABLE: - return extract_msr(val, data); - case SYSTEM_IO_CAPABLE: - return extract_io(val, data); - default: - return 0; - } -} - -struct msr_addr { - u32 reg; -}; - -struct io_addr { - u16 port; - u8 bit_width; -}; - -struct drv_cmd { - unsigned int type; - const struct cpumask *mask; - union { - struct msr_addr msr; - struct io_addr io; - } addr; - u32 val; -}; /* Called via smp_call_function_single(), on the target CPU */ static void do_drv_read(void *_cmd) { - struct drv_cmd *cmd = _cmd; - u32 h; + struct drv_cmd *cmd = _cmd; + struct acpi_cpufreq_data *data = per_cpu(acfreq_data, +cpumask_first(cmd->mask)); - switch (cmd->type) { - case SYSTEM_INTEL_MSR_CAPABLE: - case SYSTEM_AMD_MSR_CAPABLE: - rdmsr(cmd->addr.msr.reg, cmd->val, h); - break; - case SYSTEM_IO_CAPABLE: - acpi_os_read_port((acpi_io_address)cmd->addr.io.port, - &cmd->val, - (u32)cmd->addr.io.bit_width); - break; - default: - break; - } + acpi->ops->drv_read(cmd, data); } /* Called via smp_call_function_many(), on the target CPUs */ static void do_drv_write(void *_cmd) { struct drv_cmd *cmd = _cmd; - u32 lo, hi; + struct acpi_cpufreq_data *data = per_cpu(acfreq_data, +cpumask_first(cmd->mask)); - switch (cmd->type) { - case SYSTEM_INTEL_MSR_CAPABLE: - rdmsr(cmd->addr.msr.reg, lo, hi); - lo = (lo & ~INTEL_MSR_RANGE) | (cmd->val & INTEL_MSR_RANGE); - wrmsr(cmd->addr.msr.reg, lo, hi); - break; - case SYSTEM_AMD_MSR_CAPABLE: - wrmsr(cmd->addr.msr.reg, cmd->val, 0); - break; - case SYSTEM_IO_CAPABLE: - acpi_os_write_port((acpi_io_address)cmd->addr.io.port, - cmd->val, - (u32)cmd->addr.io.bit_width); - break; - default: - break; - } + acpi->ops->drv_write(cmd, data); } static void drv_read(struct drv_cmd *cmd) @@ -330,32 +151,13 @@ static void drv_write(struct drv_cmd *cmd) static u32 get_cur_val(const struct cpumask *mask) { - struct acpi_processor_performance *perf; struct drv_cmd cmd; if (unlikely(cpumask_empty(mask))) return 0; - switch (per_cpu(acfreq_data, cpumask_first(mask))->cpu_feature) { - case SYSTEM_INTEL_MSR_CAPABLE: - cmd.type = SYSTEM_INTEL_MSR_CAPABLE; - cmd.addr.msr.reg = MSR_IA32_PERF_CTL; - break; - case SYSTEM_AMD_MSR_CAPABLE: - cmd.type = SYSTEM_AMD_MSR_CAPABLE; - cmd.addr.msr.reg = MSR_AMD_PERF_CTL; - break; - case SYSTEM_IO_CAPABLE: - cmd.type = SYSTEM_IO_CAPABLE; - perf = per_cpu(acfreq_data, cpumask_first(mask))->acpi_data; - cmd.addr.io.port = perf->control_register.address; - cmd.addr.io.bit_width = perf->control_register.bit_width; - break; - default: - return 0; - } - cmd.mask = mask; + drv_read(&cmd); pr_debug("get_cur_val = %u\n", cmd.val); @@ -377,7 +179,7 @@ static unsigned int get_cur_freq_on_cpu(unsigned int cpu) } cached_freq = data->freq_table[data->acpi_data->state].frequency; - freq = extract_freq(get_cur_val(cpumask_of(cpu)), data); + freq = acpi->ops->extract_freq(get_cur_val(cpumask_of(cpu)), data); if (freq != cached_freq) { /* * The dreaded BIOS frequency change behind our back. @@ -398,7 +200,7 @@ static unsigned int check_freqs(const struct cpumask *mask, unsigned int freq, unsigned int i; for (i = 0; i < 100; i++) { - cur_freq = extract_freq(get_cur_val(mask), data); + cur_freq = acpi->ops->extract_freq(get_cur_val(mask), data); if (cur_freq == freq) return 1; udelay(10); @@ -434,34 +236,14 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy, } } - switch (data->cpu_feature) { - case SYSTEM_INTEL_MSR_CAPABLE: - cmd.type = SYSTEM_INTEL_MSR_CAPABLE; - cmd.addr.msr.reg = MSR_IA32_PERF_CTL; - cmd.val = (u32) perf->states[next_perf_state].control; - break; - case SYSTEM_AMD_MSR_CAPABLE: - cmd.type = SYSTEM_AMD_MSR_CAPABLE; - cmd.addr.msr.reg = MSR_AMD_PERF_CTL; - cmd.val = (u32) perf->states[next_perf_state].control; - break; - case SYSTEM_IO_CAPABLE: - cmd.type = SYSTEM_IO_CAPABLE; - cmd.addr.io.port = perf->control_register.address; - cmd.addr.io.bit_width = perf->control_register.bit_width; - cmd.val = (u32) perf->states[next_perf_state].control; - break; - default: - result = -ENODEV; - goto out; - } - /* cpufreq holds the hotplug lock, so we are safe from here on */ if (policy->shared_type != CPUFREQ_SHARED_TYPE_ANY) cmd.mask = policy->cpus; else cmd.mask = cpumask_of(policy->cpu); + cmd.val = (u32) perf->states[next_perf_state].control; + drv_write(&cmd); if (acpi_pstate_strict) { @@ -484,7 +266,7 @@ static unsigned long acpi_cpufreq_guess_freq(struct acpi_cpufreq_data *data, unsigned int cpu) { struct acpi_processor_performance *perf = data->acpi_data; - +#ifdef CONFIG_X86 if (cpu_khz) { /* search the closest match to cpu_khz */ unsigned int i; @@ -501,11 +283,11 @@ acpi_cpufreq_guess_freq(struct acpi_cpufreq_data *data, unsigned int cpu) } perf->state = perf->state_count-1; return freqn; - } else { - /* assume CPU is at P0... */ - perf->state = 0; - return perf->states[0].core_frequency * 1000; } +#endif + /* assume CPU is at P0... */ + perf->state = 0; + return perf->states[0].core_frequency * 1000; } static void free_acpi_perf_data(void) @@ -519,44 +301,6 @@ static void free_acpi_perf_data(void) free_percpu(acpi_perf_data); } -static int boost_notify(struct notifier_block *nb, unsigned long action, - void *hcpu) -{ - unsigned cpu = (long)hcpu; - const struct cpumask *cpumask; - - cpumask = get_cpu_mask(cpu); - - /* - * Clear the boost-disable bit on the CPU_DOWN path so that - * this cpu cannot block the remaining ones from boosting. On - * the CPU_UP path we simply keep the boost-disable flag in - * sync with the current global state. - */ - - switch (action) { - case CPU_UP_PREPARE: - case CPU_UP_PREPARE_FROZEN: - boost_set_msrs(acpi_cpufreq_driver.boost_enabled, cpumask); - break; - - case CPU_DOWN_PREPARE: - case CPU_DOWN_PREPARE_FROZEN: - boost_set_msrs(1, cpumask); - break; - - default: - break; - } - - return NOTIFY_OK; -} - - -static struct notifier_block boost_nb = { - .notifier_call = boost_notify, -}; - /* * acpi_cpufreq_early_init - initialize ACPI P-States library * @@ -618,27 +362,6 @@ static const struct dmi_system_id sw_any_bug_dmi_table[] = { }, { } }; - -static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c) -{ - /* Intel Xeon Processor 7100 Series Specification Update - * http://www.intel.com/Assets/PDF/specupdate/314554.pdf - * AL30: A Machine Check Exception (MCE) Occurring during an - * Enhanced Intel SpeedStep Technology Ratio Change May Cause - * Both Processor Cores to Lock Up. */ - if (c->x86_vendor == X86_VENDOR_INTEL) { - if ((c->x86 == 15) && - (c->x86_model == 6) && - (c->x86_mask == 8)) { - printk(KERN_INFO "acpi-cpufreq: Intel(R) " - "Xeon(R) 7100 Errata AL30, processors may " - "lock up on frequency changes: disabling " - "acpi-cpufreq.\n"); - return -ENODEV; - } - } - return 0; -} #endif static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) @@ -648,7 +371,7 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) unsigned int cpu = policy->cpu; struct acpi_cpufreq_data *data; unsigned int result = 0; - struct cpuinfo_x86 *c = &cpu_data(policy->cpu); + void *c = &cpu_data(policy->cpu); struct acpi_processor_performance *perf; #ifdef CONFIG_SMP static int blacklisted; @@ -659,9 +382,11 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) #ifdef CONFIG_SMP if (blacklisted) return blacklisted; - blacklisted = acpi_cpufreq_blacklist(c); - if (blacklisted) - return blacklisted; + if (acpi->ops->arch_check) { + blacklisted = acpi->ops->arch_check(c); + if (blacklisted) + return blacklisted; + } #endif data = kzalloc(sizeof(*data), GFP_KERNEL); @@ -676,7 +401,7 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) data->acpi_data = per_cpu_ptr(acpi_perf_data, cpu); per_cpu(acfreq_data, cpu) = data; - if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) + if (acpi->const_loops) acpi_cpufreq_driver.flags |= CPUFREQ_CONST_LOOPS; result = acpi_processor_register_performance(data->acpi_data, cpu); @@ -700,13 +425,13 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) dmi_check_system(sw_any_bug_dmi_table); if (bios_with_sw_any_bug && !policy_is_shared(policy)) { policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; - cpumask_copy(policy->cpus, cpu_core_mask(cpu)); +//FIXME cpumask_copy(policy->cpus, cpu_core_mask(cpu)); } - if (check_amd_hwpstate_cpu(cpu) && !acpi_pstate_strict) { + if (acpi->feature_hw_pstate && !acpi_pstate_strict) { cpumask_clear(policy->cpus); cpumask_set_cpu(cpu, policy->cpus); - cpumask_copy(data->freqdomain_cpus, cpu_sibling_mask(cpu)); +//FIXME cpumask_copy(data->freqdomain_cpus, cpu_sibling_mask(cpu)); policy->shared_type = CPUFREQ_SHARED_TYPE_HW; pr_info_once(PFX "overriding BIOS provided _PSD data\n"); } @@ -724,32 +449,7 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) goto err_unreg; } - switch (perf->control_register.space_id) { - case ACPI_ADR_SPACE_SYSTEM_IO: - if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && - boot_cpu_data.x86 == 0xf) { - pr_debug("AMD K8 systems must use native drivers.\n"); - result = -ENODEV; - goto err_unreg; - } - pr_debug("SYSTEM IO addr space\n"); - data->cpu_feature = SYSTEM_IO_CAPABLE; - break; - case ACPI_ADR_SPACE_FIXED_HARDWARE: - pr_debug("HARDWARE addr space\n"); - if (check_est_cpu(cpu)) { - data->cpu_feature = SYSTEM_INTEL_MSR_CAPABLE; - break; - } - if (check_amd_hwpstate_cpu(cpu)) { - data->cpu_feature = SYSTEM_AMD_MSR_CAPABLE; - break; - } - result = -ENODEV; - goto err_unreg; - default: - pr_debug("Unknown addr space %d\n", - (u32) (perf->control_register.space_id)); + if (acpi->ops->arch_feature(data)) { result = -ENODEV; goto err_unreg; } @@ -899,34 +599,14 @@ static struct cpufreq_driver acpi_cpufreq_driver = { static void __init acpi_cpufreq_boost_init(void) { - if (boot_cpu_has(X86_FEATURE_CPB) || boot_cpu_has(X86_FEATURE_IDA)) { - msrs = msrs_alloc(); - - if (!msrs) - return; - - acpi_cpufreq_driver.boost_supported = true; - acpi_cpufreq_driver.boost_enabled = boost_state(0); - get_online_cpus(); - - /* Force all MSRs to the same value */ - boost_set_msrs(acpi_cpufreq_driver.boost_enabled, - cpu_online_mask); - - register_cpu_notifier(&boost_nb); - - put_online_cpus(); - } + if (acpi->ops->arch_boost_init) + acpi->ops->arch_boost_init(acpi); } static void acpi_cpufreq_boost_exit(void) { - if (msrs) { - unregister_cpu_notifier(&boost_nb); - - msrs_free(msrs); - msrs = NULL; - } + if (acpi->ops->arch_boost_exit) + acpi->ops->arch_boost_exit(); } static int __init acpi_cpufreq_init(void) @@ -946,14 +626,23 @@ static int __init acpi_cpufreq_init(void) if (ret) return ret; -#ifdef CONFIG_X86_ACPI_CPUFREQ_CPB + acpi = kzalloc(sizeof(*acpi), GFP_KERNEL); + if (!acpi) + return -ENOMEM; + + if (arch_acpi_cpufreq_init(acpi)) { //FIXME + kfree(acpi); + return -ENOMEM; + } + + /* this is a sysfs file with a strange name and an even stranger * semantic - per CPU instantiation, but system global effect. * Lets enable it only on AMD CPUs for compatibility reasons and * only if configured. This is considered legacy code, which * will probably be removed at some point in the future. */ - if (check_amd_hwpstate_cpu(0)) { + if (acpi->feature_hw_pstate) { struct freq_attr **iter; pr_debug("adding sysfs entry for cpb\n"); @@ -965,11 +654,12 @@ static int __init acpi_cpufreq_init(void) if (iter[1] == NULL) *iter = &cpb; } -#endif + acpi_cpufreq_boost_init(); ret = cpufreq_register_driver(&acpi_cpufreq_driver); if (ret) { + kfree(acpi); free_acpi_perf_data(); acpi_cpufreq_boost_exit(); } @@ -985,6 +675,8 @@ static void __exit acpi_cpufreq_exit(void) cpufreq_unregister_driver(&acpi_cpufreq_driver); free_acpi_perf_data(); + + kfree(acpi); } module_param(acpi_pstate_strict, uint, 0644); @@ -995,13 +687,6 @@ MODULE_PARM_DESC(acpi_pstate_strict, late_initcall(acpi_cpufreq_init); module_exit(acpi_cpufreq_exit); -static const struct x86_cpu_id acpi_cpufreq_ids[] = { - X86_FEATURE_MATCH(X86_FEATURE_ACPI), - X86_FEATURE_MATCH(X86_FEATURE_HW_PSTATE), - {} -}; -MODULE_DEVICE_TABLE(x86cpu, acpi_cpufreq_ids); - static const struct acpi_device_id processor_device_ids[] = { {ACPI_PROCESSOR_OBJECT_HID, }, {ACPI_PROCESSOR_DEVICE_HID, }, diff --git a/drivers/cpufreq/acpi-cpufreq.h b/drivers/cpufreq/acpi-cpufreq.h new file mode 100644 index 0000000..2e10c0e --- /dev/null +++ b/drivers/cpufreq/acpi-cpufreq.h @@ -0,0 +1,68 @@ +#ifndef _ACPI_CPUFREQ_H +#define _ACPI_CPUFREQ_H + +#define PFX "acpi-cpufreq: " + +enum { + UNDEFINED_CAPABLE = 0, + SYSTEM_INTEL_MSR_CAPABLE, + SYSTEM_AMD_MSR_CAPABLE, + SYSTEM_IO_CAPABLE, + SYSTEM_MEMORY_CAPABLE, +}; + +struct msr_addr { + u32 reg; +}; + +struct io_addr { + u16 port; + u32 bit_width; +}; + +struct mem_addr { + u64 addr; + u32 bit_width; +}; + +struct drv_cmd { + const struct cpumask *mask; + union { + struct msr_addr msr; + struct io_addr io; + struct mem_addr mem; + } addr; + u32 val; +}; + +struct acpi_cpufreq_data; +struct acpi_cpufreq_common; + +struct acpi_cpufreq_ops { + int (*arch_check)(void *info); + int (*arch_feature)(struct acpi_cpufreq_data *data); + void (*arch_boost_init)(struct acpi_cpufreq_common *acpi); + void (*arch_boost_exit)(void); + void (*drv_read)(void *cmd, struct acpi_cpufreq_data *data); + void (*drv_write)(void *cmd, struct acpi_cpufreq_data *data); + void (*update_boost)(bool enable, const struct cpumask *cpumask); + unsigned (*extract_freq)(u32 val, struct acpi_cpufreq_data *data); }; + +struct acpi_cpufreq_data { + struct acpi_processor_performance *acpi_data; + struct cpufreq_frequency_table *freq_table; + unsigned int resume; + unsigned int cpu_feature; + cpumask_var_t freqdomain_cpus; +}; + +struct acpi_cpufreq_common { + struct acpi_cpufreq_ops *ops; + bool boost_supported; + bool feature_hw_pstate; + bool const_loops; +}; + +int arch_acpi_cpufreq_init(struct acpi_cpufreq_common *common); +#endif /* _ACPI_CPUFREQ_H */ diff --git a/drivers/cpufreq/acpi-cpufreq_arm.c b/drivers/cpufreq/acpi-cpufreq_arm.c new file mode 100644 index 0000000..241c2a1 --- /dev/null +++ b/drivers/cpufreq/acpi-cpufreq_arm.c @@ -0,0 +1,88 @@ +#include <linux/acpi.h> +#include <linux/cpu.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/uaccess.h> + +#include <acpi/processor.h> + +#include <asm/cpu.h> +#include <asm/processor.h> + +#include "acpi-cpufreq.h" + +/* Called via smp_call_function_single(), on the target CPU */ static +void arm_do_drv_read(void *_cmd, struct acpi_cpufreq_data *data) { + struct drv_cmd *cmd = _cmd; + + if (data->cpu_feature != SYSTEM_MEMORY_CAPABLE) + return; + + acpi_os_read_memory((acpi_physical_address)cmd->addr.mem.addr, + (u64*)&cmd->val, + cmd->addr.mem.bit_width); +} + +/* Called via smp_call_function_many(), on the target CPUs */ static +void arm_do_drv_write(void *_cmd, struct acpi_cpufreq_data *data) { + struct drv_cmd *cmd = _cmd; + + if (data->cpu_feature != SYSTEM_MEMORY_CAPABLE) + return; + + acpi_os_write_memory((acpi_physical_address)cmd->addr.mem.addr, + (u64)cmd->val, + cmd->addr.mem.bit_width); +} + +static unsigned arm_extract_io(u32 value, struct acpi_cpufreq_data +*data) { + return 0; +} + +static unsigned arm_extract_freq(u32 val, struct acpi_cpufreq_data +*data) { + if (data->cpu_feature != SYSTEM_MEMORY_CAPABLE) + return 0; + + return arm_extract_io(val, data); +} + +static int arm_arch_feature(struct acpi_cpufreq_data *data) { + struct acpi_processor_performance *perf; + int result = 0; + + perf = data->acpi_data; + + switch (perf->control_register.space_id) { + case ACPI_ADR_SPACE_SYSTEM_MEMORY: + pr_debug("SYSTEM Memory addr space\n"); + data->cpu_feature = SYSTEM_MEMORY_CAPABLE; + break; + default: + pr_debug("Unknown addr space %d\n", + (u32) (perf->control_register.space_id)); + result = -ENODEV; + break; + } + + return result; +} + +static struct acpi_cpufreq_ops arm_ops = { + .arch_feature = arm_arch_feature, + .extract_freq = arm_extract_freq, + .drv_read = arm_do_drv_read, + .drv_write = arm_do_drv_write, +}; + +int arch_acpi_cpufreq_init(struct acpi_cpufreq_common *common) { + common->ops = &arm_ops; + + return 0; +} + diff --git a/drivers/cpufreq/acpi-cpufreq_x86.c b/drivers/cpufreq/acpi-cpufreq_x86.c new file mode 100644 index 0000000..82c9337 --- /dev/null +++ b/drivers/cpufreq/acpi-cpufreq_x86.c @@ -0,0 +1,334 @@ +#include <linux/module.h> +#include <linux/acpi.h> +#include <linux/cpu.h> +#include <linux/cpufreq.h> +#include <linux/io.h> + +#include <acpi/processor.h> + +#include <asm/msr.h> +#include <asm/cpufeature.h> +#include <asm/processor.h> + +#include "acpi-cpufreq.h" + +#define INTEL_MSR_RANGE (0xffff) +#define AMD_MSR_RANGE (0x7) + +#define MSR_K7_HWCR_CPB_DIS (1ULL << 25) + +static struct msr __percpu *msrs; + +static void x86_boost_set_msrs(bool enable, const struct cpumask +*cpumask) { + u32 cpu; + u32 msr_addr; + u64 msr_mask; + + switch (boot_cpu_data.x86_vendor) { + case X86_VENDOR_INTEL: + msr_addr = MSR_IA32_MISC_ENABLE; + msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE; + break; + case X86_VENDOR_AMD: + msr_addr = MSR_K7_HWCR; + msr_mask = MSR_K7_HWCR_CPB_DIS; + break; + default: + return; + } + + rdmsr_on_cpus(cpumask, msr_addr, msrs); + + for_each_cpu(cpu, cpumask) { + struct msr *reg = per_cpu_ptr(msrs, cpu); + if (enable) + reg->q &= ~msr_mask; + else + reg->q |= msr_mask; + } + + wrmsr_on_cpus(cpumask, msr_addr, msrs); } + +static bool boost_state(unsigned int cpu) { + u32 lo, hi; + u64 msr; + + switch (boot_cpu_data.x86_vendor) { + case X86_VENDOR_INTEL: + rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi); + msr = lo | ((u64)hi << 32); + return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); + case X86_VENDOR_AMD: + rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi); + msr = lo | ((u64)hi << 32); + return !(msr & MSR_K7_HWCR_CPB_DIS); + } + return false; +} + +#ifdef CONFIG_SMP +static int x86_arch_check(void *data) +{ + struct cpuinfo_x86 *c = data; + /* Intel Xeon Processor 7100 Series Specification Update + * http://www.intel.com/Assets/PDF/specupdate/314554.pdf + * AL30: A Machine Check Exception (MCE) Occurring during an + * Enhanced Intel SpeedStep Technology Ratio Change May Cause + * Both Processor Cores to Lock Up. */ + if (c->x86_vendor == X86_VENDOR_INTEL) { + if ((c->x86 == 15) && + (c->x86_model == 6) && + (c->x86_mask == 8)) { + printk(KERN_INFO "acpi-cpufreq: Intel(R) " + "Xeon(R) 7100 Errata AL30, processors may " + "lock up on frequency changes: disabling " + "acpi-cpufreq.\n"); + return -ENODEV; + } + } + return 0; +} +#else +#define x86_arch_check NULL +#endif + +/* Called via smp_call_function_single(), on the target CPU */ static +void x86_do_drv_read(void *_cmd, struct acpi_cpufreq_data *data) { + struct acpi_processor_performance *perf; + struct drv_cmd *cmd = _cmd; + u32 h; + + switch (data->cpu_feature) { + case SYSTEM_INTEL_MSR_CAPABLE: + cmd->addr.msr.reg = MSR_IA32_PERF_CTL; + rdmsr(cmd->addr.msr.reg, cmd->val, h); + break; + case SYSTEM_AMD_MSR_CAPABLE: + cmd->addr.msr.reg = MSR_AMD_PERF_CTL; + rdmsr(cmd->addr.msr.reg, cmd->val, h); + break; + case SYSTEM_IO_CAPABLE: + perf = data->acpi_data; + cmd->addr.io.port = perf->control_register.address; + cmd->addr.io.bit_width = perf->control_register.bit_width; + acpi_os_read_port((acpi_io_address)cmd->addr.io.port, + &cmd->val, + (u32)cmd->addr.io.bit_width); + break; + } +} + +/* Called via smp_call_function_many(), on the target CPUs */ static +void x86_do_drv_write(void *_cmd, struct acpi_cpufreq_data *data) { + struct acpi_processor_performance *perf; + struct drv_cmd *cmd = _cmd; + u32 lo, hi; + + perf = data->acpi_data; + + switch (data->cpu_feature) { + case SYSTEM_INTEL_MSR_CAPABLE: + cmd->addr.msr.reg = MSR_IA32_PERF_CTL; + rdmsr(cmd->addr.msr.reg, lo, hi); + lo = (lo & ~INTEL_MSR_RANGE) | (cmd->val & INTEL_MSR_RANGE); + wrmsr(cmd->addr.msr.reg, lo, hi); + break; + case SYSTEM_AMD_MSR_CAPABLE: + cmd->addr.msr.reg = MSR_AMD_PERF_CTL; + wrmsr(cmd->addr.msr.reg, cmd->val, 0); + break; + case SYSTEM_IO_CAPABLE: + cmd->addr.io.port = perf->control_register.address; + cmd->addr.io.bit_width = perf->control_register.bit_width; + acpi_os_write_port((acpi_io_address)cmd->addr.io.port, + cmd->val, + (u32)cmd->addr.io.bit_width); + break; + } +} + +static unsigned extract_io(u32 value, struct acpi_cpufreq_data *data) { + struct acpi_processor_performance *perf; + int i; + + perf = data->acpi_data; + + for (i = 0; i < perf->state_count; i++) { + if (value == perf->states[i].status) + return data->freq_table[i].frequency; + } + return 0; +} + +static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data) { + int i; + struct acpi_processor_performance *perf; + + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) + msr &= AMD_MSR_RANGE; + else + msr &= INTEL_MSR_RANGE; + + perf = data->acpi_data; + + for (i = 0; data->freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { + if (msr == perf->states[data->freq_table[i].driver_data].status) + return data->freq_table[i].frequency; + } + return data->freq_table[0].frequency; } + +unsigned x86_extract_freq(u32 val, struct acpi_cpufreq_data *data) { + switch (data->cpu_feature) { + case SYSTEM_INTEL_MSR_CAPABLE: + case SYSTEM_AMD_MSR_CAPABLE: + return extract_msr(val, data); + case SYSTEM_IO_CAPABLE: + return extract_io(val, data); + default: + return 0; + } +} + +static int boost_notify(struct notifier_block *nb, unsigned long action, + void *hcpu) +{ + unsigned cpu = (long)hcpu; + const struct cpumask *cpumask; + + cpumask = get_cpu_mask(cpu); + + /* + * Clear the boost-disable bit on the CPU_DOWN path so that + * this cpu cannot block the remaining ones from boosting. On + * the CPU_UP path we simply keep the boost-disable flag in + * sync with the current global state. + */ + + switch (action) { + case CPU_UP_PREPARE: + case CPU_UP_PREPARE_FROZEN: + x86_boost_set_msrs(boost_state(0), cpumask); + break; + + case CPU_DOWN_PREPARE: + case CPU_DOWN_PREPARE_FROZEN: + x86_boost_set_msrs(1, cpumask); + break; + + default: + break; + } + + return NOTIFY_OK; +} + +static struct notifier_block boost_nb = { + .notifier_call = boost_notify, +}; + +static void x86_arch_boost_init(struct acpi_cpufreq_common *acpi) { + if (boot_cpu_has(X86_FEATURE_CPB) || boot_cpu_has(X86_FEATURE_IDA)) { + msrs = msrs_alloc(); + + if (!msrs) + return; + + acpi->boost_supported = true; + + get_online_cpus(); + + x86_boost_set_msrs(boost_state(0), cpu_online_mask); + + register_cpu_notifier(&boost_nb); + + put_online_cpus(); + } +} + +static void x86_arch_boost_exit(void) +{ + if (msrs) { + unregister_cpu_notifier(&boost_nb); + + msrs_free(msrs); + msrs = NULL; + } +} + +static int x86_arch_feature(struct acpi_cpufreq_data *data) { + struct acpi_processor_performance *perf; + int result = 0; + + perf = data->acpi_data; + + switch (perf->control_register.space_id) { + case ACPI_ADR_SPACE_SYSTEM_IO: + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && + boot_cpu_data.x86 == 0xf) { + pr_debug("AMD K8 systems must use native drivers.\n"); + result = -ENODEV; + break; + } + pr_debug("SYSTEM IO addr space\n"); + data->cpu_feature = SYSTEM_IO_CAPABLE; + break; + case ACPI_ADR_SPACE_FIXED_HARDWARE: + pr_debug("HARDWARE addr space\n"); + if (boot_cpu_has(X86_FEATURE_EST)) { + data->cpu_feature = SYSTEM_INTEL_MSR_CAPABLE; + break; + } + if (boot_cpu_has(X86_FEATURE_HW_PSTATE)) { + data->cpu_feature = SYSTEM_AMD_MSR_CAPABLE; + break; + } + result = -ENODEV; + break; + default: + pr_debug("Unknown addr space %d\n", + (u32) (perf->control_register.space_id)); + result = -ENODEV; + break; + } + + return result; +} + +static struct acpi_cpufreq_ops x86_ops = { + .arch_check = x86_arch_check, + .arch_feature = x86_arch_feature, + .arch_boost_init = x86_arch_boost_init, + .arch_boost_exit = x86_arch_boost_exit, + .drv_read = x86_do_drv_read, + .drv_write = x86_do_drv_write, + .update_boost = x86_boost_set_msrs, + .extract_freq = x86_extract_freq, +}; + +int __init arch_acpi_cpufreq_init(struct acpi_cpufreq_common *acpi) { + acpi->ops = &x86_ops; + + acpi->feature_hw_pstate = boot_cpu_has(X86_FEATURE_HW_PSTATE); + acpi->const_loops = boot_cpu_has(X86_FEATURE_CONSTANT_TSC); + + return 0; +} + +static const struct x86_cpu_id acpi_cpufreq_ids[] = { + X86_FEATURE_MATCH(X86_FEATURE_ACPI), + X86_FEATURE_MATCH(X86_FEATURE_HW_PSTATE), + {} +}; +MODULE_DEVICE_TABLE(x86cpu, acpi_cpufreq_ids); diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 85c60f3..9630ccc 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -115,6 +115,7 @@ static inline void acpi_initrd_override(void *data, size_t size) char * __acpi_map_table (unsigned long phys_addr, unsigned long size); void __acpi_unmap_table(char *map, unsigned long size); +int early_acpi_boot_init(void); int acpi_boot_init (void); void acpi_boot_table_init (void); int acpi_mps_check (void); -- 1.7.10.4

11 years

2
2
0 0

[PATCH linaro-acpi] [RFC] ACPU / cpuidle: Add ACPI cpuidle support for ARM

by Jonghwan Choi

Hi all, I would like to support acpi cpuidle for ARM. For that I applied Lorenzo Pieralisi's patches on leg-kernel repository. [PATCH RFC v2 0/4] ARM generic idle states] [PATCH RFC v2 1/4] drivers: cpuidle: implement OF based idle states infrastructure [PATCH RFC v2 2/4] arm64: add PSCI CPU_SUSPEND based cpu_suspend support [PATCH RFC v2 3/4] drivers: cpuidle: CPU idle ARM64 driver [PATCH RFC v2 4/4] arm64: boot: dts: update rtsm aemv8 dts with PSCI and idle states Lorenzo Pieralisi's patches used PSCI method to enter the low power mode. (Over C2 State) I used that method in processor_idle.c This patch is based on "http://git.linaro.org/leg/acpi/leg-kernel.git" Last commit : Commit a493444ce7f1792b44897160454149dc31ca208b Author: Graeme Gregory <graeme.gregory(a)linaro.org> Date: Tue Feb 11 09:21:17 2014 +0000 linaro-configs: add enterprise-distro.conf Signed-off-by: Graeme Gregory graeme.gregory(a)linaro.org For applying this patch, leg-kernel + [RFC] cpufreq: Add ACPI cpufreq support for ARM(My patch) + Lorenzo Pieralisi's patches should be merged. Some point might require fixing. So i would like to get your reviews and comments. Thanks. Best Regards Signed-off-by: Jonghwan Choi <jhbird.choi(a)samsung.com> --- arch/arm64/include/asm/acpi.h | 9 +++++++ arch/arm64/include/asm/irqflags.h | 7 ++++++ drivers/acpi/processor_idle.c | 50 ++++++++++++++++++++++++++++--------- 3 files changed, 54 insertions(+), 12 deletions(-) diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h index dff95da..3b0ace4 100644 --- a/arch/arm64/include/asm/acpi.h +++ b/arch/arm64/include/asm/acpi.h @@ -85,6 +85,14 @@ void arch_fix_phys_package_id(int num, u32 slot); extern int (*acpi_suspend_lowlevel)(void); #define acpi_wakeup_address (0) +/* + * Check if the CPU can handle C2 and deeper + */ +static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate) +{ + return max_cstate; +} + /* map logic cpu id to physical GIC id */ extern int arm_cpu_to_apicid[NR_CPUS]; #define cpu_physical_id(cpu) arm_cpu_to_apicid[cpu] @@ -110,4 +118,5 @@ static inline int cpu_acpi_read_ops(int cpu) #endif +#define acpi_unlazy_tlb(x) do { } while(0) #endif /*_ASM_ARM64_ACPI_H*/ diff --git a/arch/arm64/include/asm/irqflags.h b/arch/arm64/include/asm/irqflags.h index b2fcfbc..758c4e9 100644 --- a/arch/arm64/include/asm/irqflags.h +++ b/arch/arm64/include/asm/irqflags.h @@ -19,6 +19,7 @@ #ifdef __KERNEL__ #include <asm/ptrace.h> +#include <asm/barrier.h> /* * CPU interrupt mask handling. @@ -90,5 +91,11 @@ static inline int arch_irqs_disabled_flags(unsigned long flags) return flags & PSR_I_BIT; } +static inline void arch_safe_halt(void) +{ + arch_local_irq_enable(); + wfi(); +} + #endif #endif diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index 0556a0a..c0e931f 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -34,8 +34,10 @@ #include <linux/sched.h> /* need_resched() */ #include <linux/clockchips.h> #include <linux/cpuidle.h> +#include <linux/cpu_pm.h> #include <linux/syscore_ops.h> #include <acpi/processor.h> +#include <asm/suspend.h> /* * Include the apic definitions for x86 to have the APIC timer related defines @@ -70,10 +72,8 @@ static DEFINE_PER_CPU(struct acpi_processor_cx * [CPUIDLE_STATE_MAX], static int disabled_by_idle_boot_param(void) { -#ifdef CONFIG_X86 return boot_option_idle_override == IDLE_POLL || boot_option_idle_override == IDLE_HALT; -#endif } /* @@ -120,9 +120,7 @@ static struct dmi_system_id processor_power_dmi_table[] = { static void acpi_safe_halt(void) { if (!tif_need_resched()) { -#ifdef CONFIG_X86 safe_halt(); -#endif local_irq_disable(); } } @@ -752,11 +750,7 @@ static int acpi_idle_play_dead(struct cpuidle_device *dev, int index) while (1) { if (cx->entry_method == ACPI_CSTATE_HALT) -#ifdef CONFIG_X86 safe_halt(); -#else - acpi_safe_halt(); -#endif else if (cx->entry_method == ACPI_CSTATE_SYSTEMIO) { inb(cx->address); /* See comment in acpi_idle_do_entry() */ @@ -769,6 +763,7 @@ static int acpi_idle_play_dead(struct cpuidle_device *dev, int index) return 0; } +#ifdef CONFIG_X86 /** * acpi_idle_enter_simple - enters an ACPI state without BM handling * @dev: the target CPU @@ -811,6 +806,41 @@ static int acpi_idle_enter_simple(struct cpuidle_device *dev, lapic_timer_state_broadcast(pr, cx, 0); return index; } +#else +/** + * acpi_idle_enter_state - enters an acpi state without bm handling + * @dev: the target cpu + * @drv: cpuidle driver with cpuidle state information + * @index: the index of suggested state + */ +static int acpi_idle_enter_simple(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) +{ + int ret; + + if (!index) { + cpu_do_idle(); + return index; + } + + cpu_pm_enter(); + /* + * Pass idle state index to cpu_suspend which in turn will call + * the CPU ops suspend protocol with idle index as a parameter. + * + * Some states would not require context to be saved and flushed + * to DRAM, so calling cpu_suspend would not be stricly necessary. + * When power domains specifications for ARM CPUs are finalized then + * this code can be optimized to prevent saving registers if not + * needed. + */ + ret = cpu_suspend(index); + + cpu_pm_exit(); + + return ret ? -1 : index; +} +#endif static int c3_cpu_count; static DEFINE_RAW_SPINLOCK(c3_lock); @@ -851,9 +881,7 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev, } } -#ifdef CONFIG_X86 acpi_unlazy_tlb(smp_processor_id()); -#endif /* Tell the scheduler that we are going deep-idle: */ sched_clock_idle_sleep_event(); @@ -1131,9 +1159,7 @@ int acpi_processor_power_init(struct acpi_processor *pr) if (!first_run) { dmi_check_system(processor_power_dmi_table); -#ifdef CONFIG_X86 max_cstate = acpi_processor_cstate_check(max_cstate); -#endif if (max_cstate < ACPI_C_STATES_MAX) printk(KERN_NOTICE "ACPI: processor limited to max C-state %d\n", -- 1.7.10.4 > -----Original Message----- > From: Jonghwan Choi [mailto:jhbird.choi@samsung.com] > Sent: Monday, April 14, 2014 2:54 PM > To: Jonghwan Choi (jhbird.choi(a)gmail.com); sbkim73(a)samsung.com > Cc: 'linaro-acpi(a)lists.linaro.org' > Subject: [PATCH linaro-acpi] [RFC] cpufreq: Add ACPI cpufreq support for > ARM > > Hi all, > > I would like to support acpi-cpufreq for ARM. > For that, Firstly, I made new file which is a apci-freq-arm.c. > But some people, such as Rafael, Sudeep and Hanjun Guo, worried about that. > What ther are worried about is there are too many duplicate code between > acpi-cpufreq.c and acpi-cpifre-arm.c So, I tried to separate this code > into 3 parts which are common, x86-specific and arm-specific code. > I tried to separate soc-specific code from acpi-cpufreq.c as much as > possible. > But as you know, there are too much x86-specific code in acpi-cpufreq.c > When I tried to implement acpi-cpufreq-arm, there were a lot of compile > error(due to x86-specific code). > So I used #ifdef CONFIG_X86 to solve those errors.(and some hack codes) In > this patch, I mostly focused on cpufreq. > Later I will remove #ifdef CONFIG_X86. > I would like your reviews and comments. > > This patch is based on > "http://git.linaro.org/leg/acpi/leg-kernel.git" > > Last commit : > commit a493444ce7f1792b44897160454149dc31ca208b > Author: Graeme Gregory <graeme.gregory(a)linaro.org> > Date: Tue Feb 11 09:21:17 2014 +0000 > linaro-configs: add enterprise-distro.conf > Signed-off-by: Graeme Gregory graeme.gregory(a)linaro.org > > > Thanks > Best Regards > > Signed-off-by: Jonghwan Choi <jhbird.choi(a)samsung.com> > --- > arch/arm64/Kconfig | 12 ++ > arch/arm64/include/asm/cpu.h | 3 +- > arch/arm64/include/asm/processor.h | 2 + > arch/arm64/kernel/process.c | 6 + > arch/arm64/kernel/setup.c | 5 +- > drivers/acpi/Kconfig | 3 +- > drivers/acpi/acpi_processor.c | 4 + > drivers/acpi/processor_idle.c | 12 ++ > drivers/cpufreq/Kconfig | 2 +- > drivers/cpufreq/Kconfig.arm | 16 ++ > drivers/cpufreq/Makefile | 3 +- > drivers/cpufreq/acpi-cpufreq.c | 419 +++++---------------------------- > --- > drivers/cpufreq/acpi-cpufreq.h | 68 ++++++ > drivers/cpufreq/acpi-cpufreq_arm.c | 88 ++++++++ > drivers/cpufreq/acpi-cpufreq_x86.c | 334 ++++++++++++++++++++++++++++ > include/linux/acpi.h | 1 + > 16 files changed, 604 insertions(+), 373 deletions(-) create mode 100644 > drivers/cpufreq/acpi-cpufreq.h create mode 100644 drivers/cpufreq/acpi- > cpufreq_arm.c > create mode 100644 drivers/cpufreq/acpi-cpufreq_x86.c > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index > 94cc542..e150e60 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -108,6 +108,13 @@ config IOMMU_HELPER config KERNEL_MODE_NEON > def_bool y > > +config ARCH_HAS_CPUFREQ > + bool > + help > + Internal node to signify that the ARCH has CPUFREQ support > + and that the relevant menu configurations are displayed for > + it. > + > source "init/Kconfig" > > source "kernel/Kconfig.freezer" > @@ -116,6 +123,7 @@ menu "Platform selection" > > config ARCH_VEXPRESS > bool "ARMv8 software model (Versatile Express)" > + select ARCH_HAS_CPUFREQ > select ARCH_REQUIRE_GPIOLIB > select COMMON_CLK_VERSATILE > select POWER_RESET_VEXPRESS > @@ -325,6 +333,10 @@ endmenu > > menu "CPU Power Management" > > +if ARCH_HAS_CPUFREQ > +source "drivers/cpufreq/Kconfig" > +endif > + > source "drivers/cpuidle/Kconfig" > > endmenu > diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h > index 8625eb1..69db3e7 100644 > --- a/arch/arm64/include/asm/cpu.h > +++ b/arch/arm64/include/asm/cpu.h > @@ -20,6 +20,7 @@ struct cpuinfo_arm { > #endif > }; > > -DECLARE_PER_CPU(struct cpuinfo_arm, cpu_data); > +DECLARE_PER_CPU(struct cpuinfo_arm, cpu_info); > +#define cpu_data(cpu) per_cpu(cpu_info, cpu) > > #endif > diff --git a/arch/arm64/include/asm/processor.h > b/arch/arm64/include/asm/processor.h > index 50ce951..7196873 100644 > --- a/arch/arm64/include/asm/processor.h > +++ b/arch/arm64/include/asm/processor.h > @@ -47,6 +47,8 @@ > #define ARCH_LOW_ADDRESS_LIMIT PHYS_MASK > #endif /* __KERNEL__ */ > > +enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, > + IDLE_POLL}; > struct debug_info { > /* Have we suspended stepping by a debugger? */ > int suspended_step; > diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c > index 1c0a9be..1c985a9 100644 > --- a/arch/arm64/kernel/process.c > +++ b/arch/arm64/kernel/process.c > @@ -86,6 +86,12 @@ void (*arm_pm_restart)(enum reboot_mode reboot_mode, > const char *cmd); EXPORT_SYMBOL_GPL(arm_pm_restart); > > /* > + * Idle related variables and functions */ unsigned long > +boot_option_idle_override = IDLE_NO_OVERRIDE; > +EXPORT_SYMBOL(boot_option_idle_override); > + > +/* > * This is our default idle handler. > */ > void arch_cpu_idle(void) > diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c index > fecf272..99b973b 100644 > --- a/arch/arm64/kernel/setup.c > +++ b/arch/arm64/kernel/setup.c > @@ -377,14 +377,15 @@ static int __init arm64_device_init(void) } > arch_initcall(arm64_device_init); > > -static DEFINE_PER_CPU(struct cpu, cpu_data); > +DEFINE_PER_CPU(struct cpu, cpu_info); > +EXPORT_PER_CPU_SYMBOL(cpu_info); > > static int __init topology_init(void) > { > int i; > > for_each_possible_cpu(i) { > - struct cpu *cpu = &per_cpu(cpu_data, i); > + struct cpu *cpu = &per_cpu(cpu_info, i); > cpu->hotpluggable = 1; > register_cpu(cpu, i); > } > diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index > cbc5dfc..961211f 100644 > --- a/drivers/acpi/Kconfig > +++ b/drivers/acpi/Kconfig > @@ -152,7 +152,7 @@ config ACPI_PROCESSOR > tristate "Processor" > select THERMAL > select CPU_IDLE > - depends on X86 || IA64 > + depends on X86 || IA64 || ARM64 > default y > help > This driver installs ACPI as the idle handler for Linux and uses > diff --git a/drivers/acpi/acpi_processor.c b/drivers/acpi/acpi_processor.c > index c29c2c3..6a89856 100644 > --- a/drivers/acpi/acpi_processor.c > +++ b/drivers/acpi/acpi_processor.c > @@ -177,6 +177,7 @@ static int acpi_processor_hotadd_init(struct > acpi_processor *pr) > cpu_maps_update_begin(); > cpu_ho\\12.36.155.51\jhbirdchoi\Kernel\leg-kerneltplug_begin(); > > +#ifdef CONFIG_X86 > ret = acpi_map_lsapic(pr->handle, pr->apic_id, &pr->id); > if (ret) > goto out; > @@ -186,6 +187,7 @@ static int acpi_processor_hotadd_init(struct > acpi_processor *pr) > acpi_unmap_lsapic(pr->id); > goto out; > } > +#endif > > /* > * CPU got hot-added, but cpu_data is not initialized yet. Set a > flag @@ -457,8 +459,10 @@ static void acpi_processor_remove(struct > acpi_device *device) > cpu_hotplug_begin(); > > /* Remove the CPU. */ > +#ifdef CONFIG_X86 > arch_unregister_cpu(pr->id); > acpi_unmap_lsapic(pr->id); > +#endif > > cpu_hotplug_done(); > cpu_maps_update_done(); > diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c > index 3dca36d..0556a0a 100644 > --- a/drivers/acpi/processor_idle.c > +++ b/drivers/acpi/processor_idle.c > @@ -70,8 +70,10 @@ static DEFINE_PER_CPU(struct acpi_processor_cx * > [CPUIDLE_STATE_MAX], > > static int disabled_by_idle_boot_param(void) { > +#ifdef CONFIG_X86 > return boot_option_idle_override == IDLE_POLL || > boot_option_idle_override == IDLE_HALT; > +#endif > } > > /* > @@ -118,7 +120,9 @@ static struct dmi_system_id processor_power_dmi_table[] > = { static void acpi_safe_halt(void) { > if (!tif_need_resched()) { > +#ifdef CONFIG_X86 > safe_halt(); > +#endif > local_irq_disable(); > } > } > @@ -748,7 +752,11 @@ static int acpi_idle_play_dead(struct cpuidle_device > *dev, int index) > while (1) { > > if (cx->entry_method == ACPI_CSTATE_HALT) > +#ifdef CONFIG_X86 > safe_halt(); > +#else > + acpi_safe_halt(); > +#endif > else if (cx->entry_method == ACPI_CSTATE_SYSTEMIO) { > inb(cx->address); > /* See comment in acpi_idle_do_entry() */ @@ -843,7 > +851,9 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev, > } > } > > +#ifdef CONFIG_X86 > acpi_unlazy_tlb(smp_processor_id()); > +#endif > > /* Tell the scheduler that we are going deep-idle: */ > sched_clock_idle_sleep_event(); > @@ -1121,7 +1131,9 @@ int acpi_processor_power_init(struct acpi_processor > *pr) > > if (!first_run) { > dmi_check_system(processor_power_dmi_table); > +#ifdef CONFIG_X86 > max_cstate = acpi_processor_cstate_check(max_cstate); > +#endif > if (max_cstate < ACPI_C_STATES_MAX) > printk(KERN_NOTICE > "ACPI: processor limited to max C-state %d\n", > diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig index > 3a7202d..6417406 100644 > --- a/drivers/cpufreq/Kconfig > +++ b/drivers/cpufreq/Kconfig > @@ -228,7 +228,7 @@ source "drivers/cpufreq/Kconfig.x86" > endmenu > > menu "ARM CPU frequency scaling drivers" > -depends on ARM > +depends on ARM64 > source "drivers/cpufreq/Kconfig.arm" > endmenu > > diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm > index 3129749..ef00a4c 100644 > --- a/drivers/cpufreq/Kconfig.arm > +++ b/drivers/cpufreq/Kconfig.arm > @@ -16,6 +16,21 @@ config ARM_DT_BL_CPUFREQ > This enables probing via DT for Generic CPUfreq driver for ARM > big.LITTLE platform. This gets frequency tables from DT. > > +config ARM_ACPI_CPUFREQ > + tristate "ACPI Processor P-States driver" > + depends on ACPI_PROCESSOR > + help > + This driver adds a CPUFreq driver which utilizes the ACPI > + Processor Performance States. > + This driver also supports ARM CPUs. > + > + To compile this driver as a module, choose M here: the > + module will be called acpi-cpufreq. > + > + For details, take a look at <file:Documentation/cpu-freq/>. > + > + If in doubt, say N. > + > config ARM_EXYNOS_CPUFREQ > bool > > @@ -249,3 +264,4 @@ config ARM_VEXPRESS_SPC_CPUFREQ > help > This add the CPUfreq driver support for Versatile Express > big.LITTLE platforms using SPC for power management. > + > diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index > 0fd80cb..83e44f6 100644 > --- a/drivers/cpufreq/Makefile > +++ b/drivers/cpufreq/Makefile > @@ -21,7 +21,8 @@ obj-$(CONFIG_GENERIC_CPUFREQ_CPU0) += cpufreq-cpu0.o > # powernow-k8 can load then. ACPI is preferred to all other hardware- > specific drivers. > # speedstep-* is preferred over p4-clockmod. > > -obj-$(CONFIG_X86_ACPI_CPUFREQ) += acpi-cpufreq.o > +obj-$(CONFIG_X86_ACPI_CPUFREQ) += acpi-cpufreq.o acpi- > cpufreq_x86.o > +obj-$(CONFIG_ARM_ACPI_CPUFREQ) += acpi-cpufreq.o acpi- > cpufreq_arm.o > obj-$(CONFIG_X86_POWERNOW_K8) += powernow-k8.o > obj-$(CONFIG_X86_PCC_CPUFREQ) += pcc-cpufreq.o > obj-$(CONFIG_X86_POWERNOW_K6) += powernow-k6.o > diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi- > cpufreq.c index 18448a7..26bf7112 100644 > --- a/drivers/cpufreq/acpi-cpufreq.c > +++ b/drivers/cpufreq/acpi-cpufreq.c > @@ -42,37 +42,17 @@ > > #include <acpi/processor.h> > > -#include <asm/msr.h> > +#include <asm/cpu.h> > #include <asm/processor.h> > -#include <asm/cpufeature.h> > + > +#include "acpi-cpufreq.h" > > MODULE_AUTHOR("Paul Diefenbaugh, Dominik Brodowski"); > MODULE_DESCRIPTION("ACPI Processor P-States Driver"); > MODULE_LICENSE("GPL"); > > -#define PFX "acpi-cpufreq: " > - > -enum { > - UNDEFINED_CAPABLE = 0, > - SYSTEM_INTEL_MSR_CAPABLE, > - SYSTEM_AMD_MSR_CAPABLE, > - SYSTEM_IO_CAPABLE, > -}; > - > -#define INTEL_MSR_RANGE (0xffff) > -#define AMD_MSR_RANGE (0x7) > - > -#define MSR_K7_HWCR_CPB_DIS (1ULL << 25) > - > -struct acpi_cpufreq_data { > - struct acpi_processor_performance *acpi_data; > - struct cpufreq_frequency_table *freq_table; > - unsigned int resume; > - unsigned int cpu_feature; > - cpumask_var_t freqdomain_cpus; > -}; > - > static DEFINE_PER_CPU(struct acpi_cpufreq_data *, acfreq_data); > +static struct acpi_cpufreq_common *acpi; > > /* acpi_perf_data is a pointer to percpu data. */ static struct > acpi_processor_performance __percpu *acpi_perf_data; @@ -80,62 +60,12 @@ > static struct acpi_processor_performance __percpu *acpi_perf_data; static > struct cpufreq_driver acpi_cpufreq_driver; > > static unsigned int acpi_pstate_strict; -static struct msr __percpu *msrs; > - > -static bool boost_state(unsigned int cpu) -{ > - u32 lo, hi; > - u64 msr; > - > - switch (boot_cpu_data.x86_vendor) { > - case X86_VENDOR_INTEL: > - rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi); > - msr = lo | ((u64)hi << 32); > - return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); > - case X86_VENDOR_AMD: > - rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi); > - msr = lo | ((u64)hi << 32); > - return !(msr & MSR_K7_HWCR_CPB_DIS); > - } > - return false; > -} > - > -static void boost_set_msrs(bool enable, const struct cpumask *cpumask) -{ > - u32 cpu; > - u32 msr_addr; > - u64 msr_mask; > - > - switch (boot_cpu_data.x86_vendor) { > - case X86_VENDOR_INTEL: > - msr_addr = MSR_IA32_MISC_ENABLE; > - msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE; > - break; > - case X86_VENDOR_AMD: > - msr_addr = MSR_K7_HWCR; > - msr_mask = MSR_K7_HWCR_CPB_DIS; > - break; > - default: > - return; > - } > - > - rdmsr_on_cpus(cpumask, msr_addr, msrs); > - > - for_each_cpu(cpu, cpumask) { > - struct msr *reg = per_cpu_ptr(msrs, cpu); > - if (enable) > - reg->q &= ~msr_mask; > - else > - reg->q |= msr_mask; > - } > - > - wrmsr_on_cpus(cpumask, msr_addr, msrs); > -} > > static int _store_boost(int val) > { > get_online_cpus(); > - boost_set_msrs(val, cpu_online_mask); > + if (acpi->ops->update_boost) > + acpi->ops->update_boost(val, cpu_online_mask); > put_online_cpus(); > pr_debug("Core Boosting %sabled.\n", val ? "en" : "dis"); > > @@ -151,13 +81,12 @@ static ssize_t show_freqdomain_cpus(struct > cpufreq_policy *policy, char *buf) > > cpufreq_freq_attr_ro(freqdomain_cpus); > > -#ifdef CONFIG_X86_ACPI_CPUFREQ_CPB > static ssize_t store_boost(const char *buf, size_t count) { > int ret; > unsigned long val = 0; > > - if (!acpi_cpufreq_driver.boost_supported) > + if (!acpi->boost_supported) > return -EINVAL; > > ret = kstrtoul(buf, 10, &val); > @@ -181,131 +110,23 @@ static ssize_t show_cpb(struct cpufreq_policy > *policy, char *buf) } > > cpufreq_freq_attr_rw(cpb); > -#endif > - > -static int check_est_cpu(unsigned int cpuid) -{ > - struct cpuinfo_x86 *cpu = &cpu_data(cpuid); > - > - return cpu_has(cpu, X86_FEATURE_EST); > -} > - > -static int check_amd_hwpstate_cpu(unsigned int cpuid) -{ > - struct cpuinfo_x86 *cpu = &cpu_data(cpuid); > - > - return cpu_has(cpu, X86_FEATURE_HW_PSTATE); > -} > - > -static unsigned extract_io(u32 value, struct acpi_cpufreq_data *data) -{ > - struct acpi_processor_performance *perf; > - int i; > - > - perf = data->acpi_data; > - > - for (i = 0; i < perf->state_count; i++) { > - if (value == perf->states[i].status) > - return data->freq_table[i].frequency; > - } > - return 0; > -} > - > -static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data) -{ > - int i; > - struct acpi_processor_performance *perf; > - > - if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) > - msr &= AMD_MSR_RANGE; > - else > - msr &= INTEL_MSR_RANGE; > - > - perf = data->acpi_data; > - > - for (i = 0; data->freq_table[i].frequency != CPUFREQ_TABLE_END; i++) > { > - if (msr == perf->states[data- > >freq_table[i].driver_data].status) > - return data->freq_table[i].frequency; > - } > - return data->freq_table[0].frequency; > -} > - > -static unsigned extract_freq(u32 val, struct acpi_cpufreq_data *data) -{ > - switch (data->cpu_feature) { > - case SYSTEM_INTEL_MSR_CAPABLE: > - case SYSTEM_AMD_MSR_CAPABLE: > - return extract_msr(val, data); > - case SYSTEM_IO_CAPABLE: > - return extract_io(val, data); > - default: > - return 0; > - } > -} > - > -struct msr_addr { > - u32 reg; > -}; > - > -struct io_addr { > - u16 port; > - u8 bit_width; > -}; > - > -struct drv_cmd { > - unsigned int type; > - const struct cpumask *mask; > - union { > - struct msr_addr msr; > - struct io_addr io; > - } addr; > - u32 val; > -}; > > /* Called via smp_call_function_single(), on the target CPU */ static > void do_drv_read(void *_cmd) { > - struct drv_cmd *cmd = _cmd; > - u32 h; > + struct drv_cmd *cmd = _cmd; > + struct acpi_cpufreq_data *data = per_cpu(acfreq_data, > +cpumask_first(cmd->mask)); > > - switch (cmd->type) { > - case SYSTEM_INTEL_MSR_CAPABLE: > - case SYSTEM_AMD_MSR_CAPABLE: > - rdmsr(cmd->addr.msr.reg, cmd->val, h); > - break; > - case SYSTEM_IO_CAPABLE: > - acpi_os_read_port((acpi_io_address)cmd->addr.io.port, > - &cmd->val, > - (u32)cmd->addr.io.bit_width); > - break; > - default: > - break; > - } > + acpi->ops->drv_read(cmd, data); > } > > /* Called via smp_call_function_many(), on the target CPUs */ static > void do_drv_write(void *_cmd) { > struct drv_cmd *cmd = _cmd; > - u32 lo, hi; > + struct acpi_cpufreq_data *data = per_cpu(acfreq_data, > +cpumask_first(cmd->mask)); > > - switch (cmd->type) { > - case SYSTEM_INTEL_MSR_CAPABLE: > - rdmsr(cmd->addr.msr.reg, lo, hi); > - lo = (lo & ~INTEL_MSR_RANGE) | (cmd->val & INTEL_MSR_RANGE); > - wrmsr(cmd->addr.msr.reg, lo, hi); > - break; > - case SYSTEM_AMD_MSR_CAPABLE: > - wrmsr(cmd->addr.msr.reg, cmd->val, 0); > - break; > - case SYSTEM_IO_CAPABLE: > - acpi_os_write_port((acpi_io_address)cmd->addr.io.port, > - cmd->val, > - (u32)cmd->addr.io.bit_width); > - break; > - default: > - break; > - } > + acpi->ops->drv_write(cmd, data); > } > > static void drv_read(struct drv_cmd *cmd) @@ -330,32 +151,13 @@ static > void drv_write(struct drv_cmd *cmd) > > static u32 get_cur_val(const struct cpumask *mask) { > - struct acpi_processor_performance *perf; > struct drv_cmd cmd; > > if (unlikely(cpumask_empty(mask))) > return 0; > > - switch (per_cpu(acfreq_data, cpumask_first(mask))->cpu_feature) { > - case SYSTEM_INTEL_MSR_CAPABLE: > - cmd.type = SYSTEM_INTEL_MSR_CAPABLE; > - cmd.addr.msr.reg = MSR_IA32_PERF_CTL; > - break; > - case SYSTEM_AMD_MSR_CAPABLE: > - cmd.type = SYSTEM_AMD_MSR_CAPABLE; > - cmd.addr.msr.reg = MSR_AMD_PERF_CTL; > - break; > - case SYSTEM_IO_CAPABLE: > - cmd.type = SYSTEM_IO_CAPABLE; > - perf = per_cpu(acfreq_data, cpumask_first(mask))->acpi_data; > - cmd.addr.io.port = perf->control_register.address; > - cmd.addr.io.bit_width = perf->control_register.bit_width; > - break; > - default: > - return 0; > - } > - > cmd.mask = mask; > + > drv_read(&cmd); > > pr_debug("get_cur_val = %u\n", cmd.val); @@ -377,7 +179,7 @@ static > unsigned int get_cur_freq_on_cpu(unsigned int cpu) > } > > cached_freq = data->freq_table[data->acpi_data->state].frequency; > - freq = extract_freq(get_cur_val(cpumask_of(cpu)), data); > + freq = acpi->ops->extract_freq(get_cur_val(cpumask_of(cpu)), data); > if (freq != cached_freq) { > /* > * The dreaded BIOS frequency change behind our back. > @@ -398,7 +200,7 @@ static unsigned int check_freqs(const struct cpumask > *mask, unsigned int freq, > unsigned int i; > > for (i = 0; i < 100; i++) { > - cur_freq = extract_freq(get_cur_val(mask), data); > + cur_freq = acpi->ops->extract_freq(get_cur_val(mask), data); > if (cur_freq == freq) > return 1; > udelay(10); > @@ -434,34 +236,14 @@ static int acpi_cpufreq_target(struct cpufreq_policy > *policy, > } > } > > - switch (data->cpu_feature) { > - case SYSTEM_INTEL_MSR_CAPABLE: > - cmd.type = SYSTEM_INTEL_MSR_CAPABLE; > - cmd.addr.msr.reg = MSR_IA32_PERF_CTL; > - cmd.val = (u32) perf->states[next_perf_state].control; > - break; > - case SYSTEM_AMD_MSR_CAPABLE: > - cmd.type = SYSTEM_AMD_MSR_CAPABLE; > - cmd.addr.msr.reg = MSR_AMD_PERF_CTL; > - cmd.val = (u32) perf->states[next_perf_state].control; > - break; > - case SYSTEM_IO_CAPABLE: > - cmd.type = SYSTEM_IO_CAPABLE; > - cmd.addr.io.port = perf->control_register.address; > - cmd.addr.io.bit_width = perf->control_register.bit_width; > - cmd.val = (u32) perf->states[next_perf_state].control; > - break; > - default: > - result = -ENODEV; > - goto out; > - } > - > /* cpufreq holds the hotplug lock, so we are safe from here on */ > if (policy->shared_type != CPUFREQ_SHARED_TYPE_ANY) > cmd.mask = policy->cpus; > else > cmd.mask = cpumask_of(policy->cpu); > > + cmd.val = (u32) perf->states[next_perf_state].control; > + > drv_write(&cmd); > > if (acpi_pstate_strict) { > @@ -484,7 +266,7 @@ static unsigned long acpi_cpufreq_guess_freq(struct > acpi_cpufreq_data *data, unsigned int cpu) { > struct acpi_processor_performance *perf = data->acpi_data; > - > +#ifdef CONFIG_X86 > if (cpu_khz) { > /* search the closest match to cpu_khz */ > unsigned int i; > @@ -501,11 +283,11 @@ acpi_cpufreq_guess_freq(struct acpi_cpufreq_data > *data, unsigned int cpu) > } > perf->state = perf->state_count-1; > return freqn; > - } else { > - /* assume CPU is at P0... */ > - perf->state = 0; > - return perf->states[0].core_frequency * 1000; > } > +#endif > + /* assume CPU is at P0... */ > + perf->state = 0; > + return perf->states[0].core_frequency * 1000; > } > > static void free_acpi_perf_data(void) > @@ -519,44 +301,6 @@ static void free_acpi_perf_data(void) > free_percpu(acpi_perf_data); > } > > -static int boost_notify(struct notifier_block *nb, unsigned long action, > - void *hcpu) > -{ > - unsigned cpu = (long)hcpu; > - const struct cpumask *cpumask; > - > - cpumask = get_cpu_mask(cpu); > - > - /* > - * Clear the boost-disable bit on the CPU_DOWN path so that > - * this cpu cannot block the remaining ones from boosting. On > - * the CPU_UP path we simply keep the boost-disable flag in > - * sync with the current global state. > - */ > - > - switch (action) { > - case CPU_UP_PREPARE: > - case CPU_UP_PREPARE_FROZEN: > - boost_set_msrs(acpi_cpufreq_driver.boost_enabled, cpumask); > - break; > - > - case CPU_DOWN_PREPARE: > - case CPU_DOWN_PREPARE_FROZEN: > - boost_set_msrs(1, cpumask); > - break; > - > - default: > - break; > - } > - > - return NOTIFY_OK; > -} > - > - > -static struct notifier_block boost_nb = { > - .notifier_call = boost_notify, > -}; > - > /* > * acpi_cpufreq_early_init - initialize ACPI P-States library > * > @@ -618,27 +362,6 @@ static const struct dmi_system_id > sw_any_bug_dmi_table[] = { > }, > { } > }; > - > -static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c) -{ > - /* Intel Xeon Processor 7100 Series Specification Update > - * http://www.intel.com/Assets/PDF/specupdate/314554.pdf > - * AL30: A Machine Check Exception (MCE) Occurring during an > - * Enhanced Intel SpeedStep Technology Ratio Change May Cause > - * Both Processor Cores to Lock Up. */ > - if (c->x86_vendor == X86_VENDOR_INTEL) { > - if ((c->x86 == 15) && > - (c->x86_model == 6) && > - (c->x86_mask == 8)) { > - printk(KERN_INFO "acpi-cpufreq: Intel(R) " > - "Xeon(R) 7100 Errata AL30, processors may " > - "lock up on frequency changes: disabling " > - "acpi-cpufreq.\n"); > - return -ENODEV; > - } > - } > - return 0; > -} > #endif > > static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) @@ -648,7 > +371,7 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) > unsigned int cpu = policy->cpu; > struct acpi_cpufreq_data *data; > unsigned int result = 0; > - struct cpuinfo_x86 *c = &cpu_data(policy->cpu); > + void *c = &cpu_data(policy->cpu); > struct acpi_processor_performance *perf; #ifdef CONFIG_SMP > static int blacklisted; > @@ -659,9 +382,11 @@ static int acpi_cpufreq_cpu_init(struct > cpufreq_policy *policy) #ifdef CONFIG_SMP > if (blacklisted) > return blacklisted; > - blacklisted = acpi_cpufreq_blacklist(c); > - if (blacklisted) > - return blacklisted; > + if (acpi->ops->arch_check) { > + blacklisted = acpi->ops->arch_check(c); > + if (blacklisted) > + return blacklisted; > + } > #endif > > data = kzalloc(sizeof(*data), GFP_KERNEL); @@ -676,7 +401,7 @@ > static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) > data->acpi_data = per_cpu_ptr(acpi_perf_data, cpu); > per_cpu(acfreq_data, cpu) = data; > > - if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) > + if (acpi->const_loops) > acpi_cpufreq_driver.flags |= CPUFREQ_CONST_LOOPS; > > result = acpi_processor_register_performance(data->acpi_data, cpu); > @@ -700,13 +425,13 @@ static int acpi_cpufreq_cpu_init(struct > cpufreq_policy *policy) > dmi_check_system(sw_any_bug_dmi_table); > if (bios_with_sw_any_bug && !policy_is_shared(policy)) { > policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; > - cpumask_copy(policy->cpus, cpu_core_mask(cpu)); > +//FIXME cpumask_copy(policy->cpus, cpu_core_mask(cpu)); > } > > - if (check_amd_hwpstate_cpu(cpu) && !acpi_pstate_strict) { > + if (acpi->feature_hw_pstate && !acpi_pstate_strict) { > cpumask_clear(policy->cpus); > cpumask_set_cpu(cpu, policy->cpus); > - cpumask_copy(data->freqdomain_cpus, cpu_sibling_mask(cpu)); > +//FIXME cpumask_copy(data->freqdomain_cpus, > cpu_sibling_mask(cpu)); > policy->shared_type = CPUFREQ_SHARED_TYPE_HW; > pr_info_once(PFX "overriding BIOS provided _PSD data\n"); > } > @@ -724,32 +449,7 @@ static int acpi_cpufreq_cpu_init(struct > cpufreq_policy *policy) > goto err_unreg; > } > > - switch (perf->control_register.space_id) { > - case ACPI_ADR_SPACE_SYSTEM_IO: > - if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && > - boot_cpu_data.x86 == 0xf) { > - pr_debug("AMD K8 systems must use native drivers.\n"); > - result = -ENODEV; > - goto err_unreg; > - } > - pr_debug("SYSTEM IO addr space\n"); > - data->cpu_feature = SYSTEM_IO_CAPABLE; > - break; > - case ACPI_ADR_SPACE_FIXED_HARDWARE: > - pr_debug("HARDWARE addr space\n"); > - if (check_est_cpu(cpu)) { > - data->cpu_feature = SYSTEM_INTEL_MSR_CAPABLE; > - break; > - } > - if (check_amd_hwpstate_cpu(cpu)) { > - data->cpu_feature = SYSTEM_AMD_MSR_CAPABLE; > - break; > - } > - result = -ENODEV; > - goto err_unreg; > - default: > - pr_debug("Unknown addr space %d\n", > - (u32) (perf->control_register.space_id)); > + if (acpi->ops->arch_feature(data)) { > result = -ENODEV; > goto err_unreg; > } > @@ -899,34 +599,14 @@ static struct cpufreq_driver acpi_cpufreq_driver = { > > static void __init acpi_cpufreq_boost_init(void) { > - if (boot_cpu_has(X86_FEATURE_CPB) || boot_cpu_has(X86_FEATURE_IDA)) > { > - msrs = msrs_alloc(); > - > - if (!msrs) > - return; > - > - acpi_cpufreq_driver.boost_supported = true; > - acpi_cpufreq_driver.boost_enabled = boost_state(0); > - get_online_cpus(); > - > - /* Force all MSRs to the same value */ > - boost_set_msrs(acpi_cpufreq_driver.boost_enabled, > - cpu_online_mask); > - > - register_cpu_notifier(&boost_nb); > - > - put_online_cpus(); > - } > + if (acpi->ops->arch_boost_init) > + acpi->ops->arch_boost_init(acpi); > } > > static void acpi_cpufreq_boost_exit(void) { > - if (msrs) { > - unregister_cpu_notifier(&boost_nb); > - > - msrs_free(msrs); > - msrs = NULL; > - } > + if (acpi->ops->arch_boost_exit) > + acpi->ops->arch_boost_exit(); > } > > static int __init acpi_cpufreq_init(void) @@ -946,14 +626,23 @@ static > int __init acpi_cpufreq_init(void) > if (ret) > return ret; > > -#ifdef CONFIG_X86_ACPI_CPUFREQ_CPB > + acpi = kzalloc(sizeof(*acpi), GFP_KERNEL); > + if (!acpi) > + return -ENOMEM; > + > + if (arch_acpi_cpufreq_init(acpi)) { //FIXME > + kfree(acpi); > + return -ENOMEM; > + } > + > + > /* this is a sysfs file with a strange name and an even stranger > * semantic - per CPU instantiation, but system global effect. > * Lets enable it only on AMD CPUs for compatibility reasons and > * only if configured. This is considered legacy code, which > * will probably be removed at some point in the future. > */ > - if (check_amd_hwpstate_cpu(0)) { > + if (acpi->feature_hw_pstate) { > struct freq_attr **iter; > > pr_debug("adding sysfs entry for cpb\n"); @@ -965,11 +654,12 > @@ static int __init acpi_cpufreq_init(void) > if (iter[1] == NULL) > *iter = &cpb; > } > -#endif > + > acpi_cpufreq_boost_init(); > > ret = cpufreq_register_driver(&acpi_cpufreq_driver); > if (ret) { > + kfree(acpi); > free_acpi_perf_data(); > acpi_cpufreq_boost_exit(); > } > @@ -985,6 +675,8 @@ static void __exit acpi_cpufreq_exit(void) > cpufreq_unregister_driver(&acpi_cpufreq_driver); > > free_acpi_perf_data(); > + > + kfree(acpi); > } > > module_param(acpi_pstate_strict, uint, 0644); @@ -995,13 +687,6 @@ > MODULE_PARM_DESC(acpi_pstate_strict, > late_initcall(acpi_cpufreq_init); > module_exit(acpi_cpufreq_exit); > > -static const struct x86_cpu_id acpi_cpufreq_ids[] = { > - X86_FEATURE_MATCH(X86_FEATURE_ACPI), > - X86_FEATURE_MATCH(X86_FEATURE_HW_PSTATE), > - {} > -}; > -MODULE_DEVICE_TABLE(x86cpu, acpi_cpufreq_ids); > - > static const struct acpi_device_id processor_device_ids[] = { > {ACPI_PROCESSOR_OBJECT_HID, }, > {ACPI_PROCESSOR_DEVICE_HID, }, > diff --git a/drivers/cpufreq/acpi-cpufreq.h b/drivers/cpufreq/acpi- > cpufreq.h new file mode 100644 index 0000000..2e10c0e > --- /dev/null > +++ b/drivers/cpufreq/acpi-cpufreq.h > @@ -0,0 +1,68 @@ > +#ifndef _ACPI_CPUFREQ_H > +#define _ACPI_CPUFREQ_H > + > +#define PFX "acpi-cpufreq: " > + > +enum { > + UNDEFINED_CAPABLE = 0, > + SYSTEM_INTEL_MSR_CAPABLE, > + SYSTEM_AMD_MSR_CAPABLE, > + SYSTEM_IO_CAPABLE, > + SYSTEM_MEMORY_CAPABLE, > +}; > + > +struct msr_addr { > + u32 reg; > +}; > + > +struct io_addr { > + u16 port; > + u32 bit_width; > +}; > + > +struct mem_addr { > + u64 addr; > + u32 bit_width; > +}; > + > +struct drv_cmd { > + const struct cpumask *mask; > + union { > + struct msr_addr msr; > + struct io_addr io; > + struct mem_addr mem; > + } addr; > + u32 val; > +}; > + > +struct acpi_cpufreq_data; > +struct acpi_cpufreq_common; > + > +struct acpi_cpufreq_ops { > + int (*arch_check)(void *info); > + int (*arch_feature)(struct acpi_cpufreq_data *data); > + void (*arch_boost_init)(struct acpi_cpufreq_common *acpi); > + void (*arch_boost_exit)(void); > + void (*drv_read)(void *cmd, struct acpi_cpufreq_data *data); > + void (*drv_write)(void *cmd, struct acpi_cpufreq_data *data); > + void (*update_boost)(bool enable, const struct cpumask *cpumask); > + unsigned (*extract_freq)(u32 val, struct acpi_cpufreq_data > *data); }; > + > +struct acpi_cpufreq_data { > + struct acpi_processor_performance *acpi_data; > + struct cpufreq_frequency_table *freq_table; > + unsigned int resume; > + unsigned int cpu_feature; > + cpumask_var_t freqdomain_cpus; > +}; > + > +struct acpi_cpufreq_common { > + struct acpi_cpufreq_ops *ops; > + bool boost_supported; > + bool feature_hw_pstate; > + bool const_loops; > +}; > + > +int arch_acpi_cpufreq_init(struct acpi_cpufreq_common *common); > +#endif /* _ACPI_CPUFREQ_H */ > diff --git a/drivers/cpufreq/acpi-cpufreq_arm.c b/drivers/cpufreq/acpi- > cpufreq_arm.c > new file mode 100644 > index 0000000..241c2a1 > --- /dev/null > +++ b/drivers/cpufreq/acpi-cpufreq_arm.c > @@ -0,0 +1,88 @@ > +#include <linux/acpi.h> > +#include <linux/cpu.h> > +#include <linux/io.h> > +#include <linux/delay.h> > +#include <linux/uaccess.h> > + > +#include <acpi/processor.h> > + > +#include <asm/cpu.h> > +#include <asm/processor.h> > + > +#include "acpi-cpufreq.h" > + > +/* Called via smp_call_function_single(), on the target CPU */ static > +void arm_do_drv_read(void *_cmd, struct acpi_cpufreq_data *data) { > + struct drv_cmd *cmd = _cmd; > + > + if (data->cpu_feature != SYSTEM_MEMORY_CAPABLE) > + return; > + > + acpi_os_read_memory((acpi_physical_address)cmd->addr.mem.addr, > + (u64*)&cmd->val, > + cmd->addr.mem.bit_width); > +} > + > +/* Called via smp_call_function_many(), on the target CPUs */ static > +void arm_do_drv_write(void *_cmd, struct acpi_cpufreq_data *data) { > + struct drv_cmd *cmd = _cmd; > + > + if (data->cpu_feature != SYSTEM_MEMORY_CAPABLE) > + return; > + > + acpi_os_write_memory((acpi_physical_address)cmd->addr.mem.addr, > + (u64)cmd->val, > + cmd->addr.mem.bit_width); > +} > + > +static unsigned arm_extract_io(u32 value, struct acpi_cpufreq_data > +*data) { > + return 0; > +} > + > +static unsigned arm_extract_freq(u32 val, struct acpi_cpufreq_data > +*data) { > + if (data->cpu_feature != SYSTEM_MEMORY_CAPABLE) > + return 0; > + > + return arm_extract_io(val, data); > +} > + > +static int arm_arch_feature(struct acpi_cpufreq_data *data) { > + struct acpi_processor_performance *perf; > + int result = 0; > + > + perf = data->acpi_data; > + > + switch (perf->control_register.space_id) { > + case ACPI_ADR_SPACE_SYSTEM_MEMORY: > + pr_debug("SYSTEM Memory addr space\n"); > + data->cpu_feature = SYSTEM_MEMORY_CAPABLE; > + break; > + default: > + pr_debug("Unknown addr space %d\n", > + (u32) (perf->control_register.space_id)); > + result = -ENODEV; > + break; > + } > + > + return result; > +} > + > +static struct acpi_cpufreq_ops arm_ops = { > + .arch_feature = arm_arch_feature, > + .extract_freq = arm_extract_freq, > + .drv_read = arm_do_drv_read, > + .drv_write = arm_do_drv_write, > +}; > + > +int arch_acpi_cpufreq_init(struct acpi_cpufreq_common *common) { > + common->ops = &arm_ops; > + > + return 0; > +} > + > diff --git a/drivers/cpufreq/acpi-cpufreq_x86.c b/drivers/cpufreq/acpi- > cpufreq_x86.c > new file mode 100644 > index 0000000..82c9337 > --- /dev/null > +++ b/drivers/cpufreq/acpi-cpufreq_x86.c > @@ -0,0 +1,334 @@ > +#include <linux/module.h> > +#include <linux/acpi.h> > +#include <linux/cpu.h> > +#include <linux/cpufreq.h> > +#include <linux/io.h> > + > +#include <acpi/processor.h> > + > +#include <asm/msr.h> > +#include <asm/cpufeature.h> > +#include <asm/processor.h> > + > +#include "acpi-cpufreq.h" > + > +#define INTEL_MSR_RANGE (0xffff) > +#define AMD_MSR_RANGE (0x7) > + > +#define MSR_K7_HWCR_CPB_DIS (1ULL << 25) > + > +static struct msr __percpu *msrs; > + > +static void x86_boost_set_msrs(bool enable, const struct cpumask > +*cpumask) { > + u32 cpu; > + u32 msr_addr; > + u64 msr_mask; > + > + switch (boot_cpu_data.x86_vendor) { > + case X86_VENDOR_INTEL: > + msr_addr = MSR_IA32_MISC_ENABLE; > + msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE; > + break; > + case X86_VENDOR_AMD: > + msr_addr = MSR_K7_HWCR; > + msr_mask = MSR_K7_HWCR_CPB_DIS; > + break; > + default: > + return; > + } > + > + rdmsr_on_cpus(cpumask, msr_addr, msrs); > + > + for_each_cpu(cpu, cpumask) { > + struct msr *reg = per_cpu_ptr(msrs, cpu); > + if (enable) > + reg->q &= ~msr_mask; > + else > + reg->q |= msr_mask; > + } > + > + wrmsr_on_cpus(cpumask, msr_addr, msrs); } > + > +static bool boost_state(unsigned int cpu) { > + u32 lo, hi; > + u64 msr; > + > + switch (boot_cpu_data.x86_vendor) { > + case X86_VENDOR_INTEL: > + rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi); > + msr = lo | ((u64)hi << 32); > + return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); > + case X86_VENDOR_AMD: > + rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi); > + msr = lo | ((u64)hi << 32); > + return !(msr & MSR_K7_HWCR_CPB_DIS); > + } > + return false; > +} > + > +#ifdef CONFIG_SMP > +static int x86_arch_check(void *data) > +{ > + struct cpuinfo_x86 *c = data; > + /* Intel Xeon Processor 7100 Series Specification Update > + * http://www.intel.com/Assets/PDF/specupdate/314554.pdf > + * AL30: A Machine Check Exception (MCE) Occurring during an > + * Enhanced Intel SpeedStep Technology Ratio Change May Cause > + * Both Processor Cores to Lock Up. */ > + if (c->x86_vendor == X86_VENDOR_INTEL) { > + if ((c->x86 == 15) && > + (c->x86_model == 6) && > + (c->x86_mask == 8)) { > + printk(KERN_INFO "acpi-cpufreq: Intel(R) " > + "Xeon(R) 7100 Errata AL30, processors may " > + "lock up on frequency changes: disabling " > + "acpi-cpufreq.\n"); > + return -ENODEV; > + } > + } > + return 0; > +} > +#else > +#define x86_arch_check NULL > +#endif > + > +/* Called via smp_call_function_single(), on the target CPU */ static > +void x86_do_drv_read(void *_cmd, struct acpi_cpufreq_data *data) { > + struct acpi_processor_performance *perf; > + struct drv_cmd *cmd = _cmd; > + u32 h; > + > + switch (data->cpu_feature) { > + case SYSTEM_INTEL_MSR_CAPABLE: > + cmd->addr.msr.reg = MSR_IA32_PERF_CTL; > + rdmsr(cmd->addr.msr.reg, cmd->val, h); > + break; > + case SYSTEM_AMD_MSR_CAPABLE: > + cmd->addr.msr.reg = MSR_AMD_PERF_CTL; > + rdmsr(cmd->addr.msr.reg, cmd->val, h); > + break; > + case SYSTEM_IO_CAPABLE: > + perf = data->acpi_data; > + cmd->addr.io.port = perf->control_register.address; > + cmd->addr.io.bit_width = perf->control_register.bit_width; > + acpi_os_read_port((acpi_io_address)cmd->addr.io.port, > + &cmd->val, > + (u32)cmd->addr.io.bit_width); > + break; > + } > +} > + > +/* Called via smp_call_function_many(), on the target CPUs */ static > +void x86_do_drv_write(void *_cmd, struct acpi_cpufreq_data *data) { > + struct acpi_processor_performance *perf; > + struct drv_cmd *cmd = _cmd; > + u32 lo, hi; > + > + perf = data->acpi_data; > + > + switch (data->cpu_feature) { > + case SYSTEM_INTEL_MSR_CAPABLE: > + cmd->addr.msr.reg = MSR_IA32_PERF_CTL; > + rdmsr(cmd->addr.msr.reg, lo, hi); > + lo = (lo & ~INTEL_MSR_RANGE) | (cmd->val & INTEL_MSR_RANGE); > + wrmsr(cmd->addr.msr.reg, lo, hi); > + break; > + case SYSTEM_AMD_MSR_CAPABLE: > + cmd->addr.msr.reg = MSR_AMD_PERF_CTL; > + wrmsr(cmd->addr.msr.reg, cmd->val, 0); > + break; > + case SYSTEM_IO_CAPABLE: > + cmd->addr.io.port = perf->control_register.address; > + cmd->addr.io.bit_width = perf->control_register.bit_width; > + acpi_os_write_port((acpi_io_address)cmd->addr.io.port, > + cmd->val, > + (u32)cmd->addr.io.bit_width); > + break; > + } > +} > + > +static unsigned extract_io(u32 value, struct acpi_cpufreq_data *data) { > + struct acpi_processor_performance *perf; > + int i; > + > + perf = data->acpi_data; > + > + for (i = 0; i < perf->state_count; i++) { > + if (value == perf->states[i].status) > + return data->freq_table[i].frequency; > + } > + return 0; > +} > + > +static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data) { > + int i; > + struct acpi_processor_performance *perf; > + > + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) > + msr &= AMD_MSR_RANGE; > + else > + msr &= INTEL_MSR_RANGE; > + > + perf = data->acpi_data; > + > + for (i = 0; data->freq_table[i].frequency != CPUFREQ_TABLE_END; i++) > { > + if (msr == perf->states[data- > >freq_table[i].driver_data].status) > + return data->freq_table[i].frequency; > + } > + return data->freq_table[0].frequency; } > + > +unsigned x86_extract_freq(u32 val, struct acpi_cpufreq_data *data) { > + switch (data->cpu_feature) { > + case SYSTEM_INTEL_MSR_CAPABLE: > + case SYSTEM_AMD_MSR_CAPABLE: > + return extract_msr(val, data); > + case SYSTEM_IO_CAPABLE: > + return extract_io(val, data); > + default: > + return 0; > + } > +} > + > +static int boost_notify(struct notifier_block *nb, unsigned long action, > + void *hcpu) > +{ > + unsigned cpu = (long)hcpu; > + const struct cpumask *cpumask; > + > + cpumask = get_cpu_mask(cpu); > + > + /* > + * Clear the boost-disable bit on the CPU_DOWN path so that > + * this cpu cannot block the remaining ones from boosting. On > + * the CPU_UP path we simply keep the boost-disable flag in > + * sync with the current global state. > + */ > + > + switch (action) { > + case CPU_UP_PREPARE: > + case CPU_UP_PREPARE_FROZEN: > + x86_boost_set_msrs(boost_state(0), cpumask); > + break; > + > + case CPU_DOWN_PREPARE: > + case CPU_DOWN_PREPARE_FROZEN: > + x86_boost_set_msrs(1, cpumask); > + break; > + > + default: > + break; > + } > + > + return NOTIFY_OK; > +} > + > +static struct notifier_block boost_nb = { > + .notifier_call = boost_notify, > +}; > + > +static void x86_arch_boost_init(struct acpi_cpufreq_common *acpi) { > + if (boot_cpu_has(X86_FEATURE_CPB) || boot_cpu_has(X86_FEATURE_IDA)) > { > + msrs = msrs_alloc(); > + > + if (!msrs) > + return; > + > + acpi->boost_supported = true; > + > + get_online_cpus(); > + > + x86_boost_set_msrs(boost_state(0), cpu_online_mask); > + > + register_cpu_notifier(&boost_nb); > + > + put_online_cpus(); > + } > +} > + > +static void x86_arch_boost_exit(void) > +{ > + if (msrs) { > + unregister_cpu_notifier(&boost_nb); > + > + msrs_free(msrs); > + msrs = NULL; > + } > +} > + > +static int x86_arch_feature(struct acpi_cpufreq_data *data) { > + struct acpi_processor_performance *perf; > + int result = 0; > + > + perf = data->acpi_data; > + > + switch (perf->control_register.space_id) { > + case ACPI_ADR_SPACE_SYSTEM_IO: > + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && > + boot_cpu_data.x86 == 0xf) { > + pr_debug("AMD K8 systems must use native drivers.\n"); > + result = -ENODEV; > + break; > + } > + pr_debug("SYSTEM IO addr space\n"); > + data->cpu_feature = SYSTEM_IO_CAPABLE; > + break; > + case ACPI_ADR_SPACE_FIXED_HARDWARE: > + pr_debug("HARDWARE addr space\n"); > + if (boot_cpu_has(X86_FEATURE_EST)) { > + data->cpu_feature = SYSTEM_INTEL_MSR_CAPABLE; > + break; > + } > + if (boot_cpu_has(X86_FEATURE_HW_PSTATE)) { > + data->cpu_feature = SYSTEM_AMD_MSR_CAPABLE; > + break; > + } > + result = -ENODEV; > + break; > + default: > + pr_debug("Unknown addr space %d\n", > + (u32) (perf->control_register.space_id)); > + result = -ENODEV; > + break; > + } > + > + return result; > +} > + > +static struct acpi_cpufreq_ops x86_ops = { > + .arch_check = x86_arch_check, > + .arch_feature = x86_arch_feature, > + .arch_boost_init = x86_arch_boost_init, > + .arch_boost_exit = x86_arch_boost_exit, > + .drv_read = x86_do_drv_read, > + .drv_write = x86_do_drv_write, > + .update_boost = x86_boost_set_msrs, > + .extract_freq = x86_extract_freq, > +}; > + > +int __init arch_acpi_cpufreq_init(struct acpi_cpufreq_common *acpi) { > + acpi->ops = &x86_ops; > + > + acpi->feature_hw_pstate = boot_cpu_has(X86_FEATURE_HW_PSTATE); > + acpi->const_loops = boot_cpu_has(X86_FEATURE_CONSTANT_TSC); > + > + return 0; > +} > + > +static const struct x86_cpu_id acpi_cpufreq_ids[] = { > + X86_FEATURE_MATCH(X86_FEATURE_ACPI), > + X86_FEATURE_MATCH(X86_FEATURE_HW_PSTATE), > + {} > +}; > +MODULE_DEVICE_TABLE(x86cpu, acpi_cpufreq_ids); > diff --git a/include/linux/acpi.h b/include/linux/acpi.h index > 85c60f3..9630ccc 100644 > --- a/include/linux/acpi.h > +++ b/include/linux/acpi.h > @@ -115,6 +115,7 @@ static inline void acpi_initrd_override(void *data, > size_t size) > > char * __acpi_map_table (unsigned long phys_addr, unsigned long size); > void __acpi_unmap_table(char *map, unsigned long size); > +int early_acpi_boot_init(void); > int acpi_boot_init (void); > void acpi_boot_table_init (void); > int acpi_mps_check (void); > -- > 1.7.10.4

11 years

2
2
0 0

[PATCH V3] ACPI: Update the ownership and developers for ACPI in Kconfig

by Hanjun Guo

The UEFI Forum included the ACPI spec in its portfolio in October 2013 and will host future spec iterations, following the ACPI v5.0a release. A UEFI Forum working group named ACPI Specification Working Group (ASWG) has been established to handle future ACPI developments, any UEFI member can join the group and contribute to ACPI specification. So update the ownership and developers for ACPI in Kconfig accordingly, and add another website link to ACPI specification too. Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org> --- drivers/acpi/Kconfig | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index c205653..ab686b3 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -31,10 +31,14 @@ menuconfig ACPI ACPI CA, see: <http://acpica.org/> - ACPI is an open industry specification co-developed by - Hewlett-Packard, Intel, Microsoft, Phoenix, and Toshiba. + ACPI is an open industry specification originally co-developed by + Hewlett-Packard, Intel, Microsoft, Phoenix, and Toshiba. Currently, + it is developed by the ACPI Specification Working Group (ASWG) under + the UEFI Forum and any UEFI member can join the ASWG and contribute + to the ACPI specification. The specification is available at: <http://www.acpi.info> + <http://www.uefi.org/acpi/specs> if ACPI -- 1.7.9.5

11 years, 1 month

2
1
0 0

[PATCH V2] ACPI: Update the ownership and developers for ACPI in Kconfig

by Hanjun Guo

The UEFI Forum included the ACPI spec in its portfolio in October 2013 and will host future spec iterations, following the ACPI v5.0a release. A UEFI Forum working group named ACPI Specification Working Group (ASWG) has been established to handle future ACPI developments, any UEFI member can join the group and contribute to ACPI specification. So update the ownership and developers for ACPI in Kconfig accordingly, and add another website link to ACPI specification too. Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org> --- drivers/acpi/Kconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index c205653..6bbf36e 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -32,9 +32,11 @@ menuconfig ACPI <http://acpica.org/> ACPI is an open industry specification co-developed by - Hewlett-Packard, Intel, Microsoft, Phoenix, and Toshiba. + ACPI Specification Working Group (ASWG) under UEFI Forum, any + UEFI member can join ASWG and contribute to ACPI specification. The specification is available at: <http://www.acpi.info> + <http://www.uefi.org/acpi/specs> if ACPI -- 1.7.9.5

11 years, 1 month

2
2
0 0

[PATCH] ACPI: Update the ownership and developers for ACPI in Kconfig

by Hanjun Guo

The UEFI Forum included the ACPI spec in its portfolio in October 2013 and will host future spec iterations, following the ACPI v5.0a release. A UEFI Forum working group named ACPI Specification Working Group (ASWG) has been established to handle future ACPI developments, any UEFI member can join the group and contribute to ACPI specification. So update the ownership and developers for ACPI in Kconfig accordingly, and update the website link to ACPI specification too. Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org> --- drivers/acpi/Kconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index c205653..831e541 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -32,9 +32,10 @@ menuconfig ACPI <http://acpica.org/> ACPI is an open industry specification co-developed by - Hewlett-Packard, Intel, Microsoft, Phoenix, and Toshiba. + ACPI Specification Working Group (ASWG) under UEFI Forum, any + UEFI member can join ASWG and contribute to ACPI specification. The specification is available at: - <http://www.acpi.info> + <http://www.uefi.org/acpi/specs> if ACPI -- 1.7.9.5

11 years, 1 month

2
4
0 0

[PATCH] ARM64: Remove duplicated Kconfig entry for "kernel/power/Kconfig"

by Hanjun Guo

There is a duplicated Kconfig entry for "kernel/power/Kconfig" in menu "Power management options" and "CPU Power Management", remove the one from menu "CPU Power Management" suggested by Viresh. Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org> --- arch/arm64/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index e6e4d37..e759af5 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -323,8 +323,6 @@ menu "CPU Power Management" source "drivers/cpuidle/Kconfig" -source "kernel/power/Kconfig" - source "drivers/cpufreq/Kconfig" endmenu -- 1.7.9.5

11 years, 1 month

3
2
0 0

How to pass I2C platform_data under ACPI

by Pallala, Ramakrishna

Hi All, I am trying to enable a i2c client driver under ACPI. The device is being enumerated behind adapter device and I am getting IRQ resource as well. The problem I have now is, how do I pass the platform data to driver? struct i2c_board_info { char type[I2C_NAME_SIZE]; unsigned short flags; unsigned short addr; void *platform_data; ===========> how can I initialize this filed. struct dev_archdata *archdata; struct device_node *of_node; struct acpi_dev_node acpi_node; int irq; }; In non ACPI environment I used to initialize the platform_data under board or platforms files. Under ACPI how do I do that? Thanks, Ram

11 years, 1 month

3
7
0 0

[PATCH] arm64: Fix duplicated Kconfig entries again

by Hanjun Guo

After commit 74397174989e5 (arm64: Fix duplicated Kconfig entries), I still get a duplicate Power management options section in linux-next git repo, may be due to some merge conflicts, anyway, fix that in this patch. Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org> --- Based on linux-next repo, weird, did I miss something? --- arch/arm64/Kconfig | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index d9f23ad..6085dca 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -317,24 +317,12 @@ config ARCH_SUSPEND_POSSIBLE config ARM64_CPU_SUSPEND def_bool PM_SLEEP -endmenu - -menu "CPU Power Management" - source "drivers/cpuidle/Kconfig" source "drivers/cpufreq/Kconfig" endmenu -menu "Power management options" - -source "kernel/power/Kconfig" - -source "drivers/cpufreq/Kconfig" - -endmenu - source "net/Kconfig" source "drivers/Kconfig" -- 1.7.9.5

11 years, 1 month

5
12
0 0

How to i2c pass platform_data under ACPI

by Pallala, Ramakrishna

Hi All, I am trying to enable a i2c client driver under ACPI. The device is being enumerated behind adapter device and I am getting IRQ resource as well. The problem I have now is, how do I pass the platform data to driver? struct i2c_board_info { char type[I2C_NAME_SIZE]; unsigned short flags; unsigned short addr; void *platform_data; ===========> how can I initialize this filed. struct dev_archdata *archdata; struct device_node *of_node; struct acpi_dev_node acpi_node; int irq; }; In non ACPI environment I used to initialize the platform_data under board or platforms files. Under ACPI how do I do that? Thanks, Ram

11 years, 1 month

1
0
0 0

leg-kernel tag leg-20140401.0 released

by Graeme Gregory

The leg-kernel release has been made and tagged as leg-20140401.0 This is based on mainline kernel v3.14 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: https://git.linaro.org/leg/acpi/leg-kernel.git/commit/a493444ce7f1792b44897… Notes :- 1) starting from this release, a FDT is not used to describe the platform. The kernel uses ACPI tables only. This release contains prototype code to boot the CPUs from information held in the MADT. It is hard coded to PSCI control method for the FVP base model

11 years, 1 month

1
0
0 0

[PATCH v5 0/3] PSCI v0.2 support and DT bindings

by Ashwin Chaugule

Changes in v5: - Add uapi/linux/psci.h to kbuild - ret with err if PSCI_ID_VERSION is not implemented. Changes in v4: - Correct copyright banner format. - Check if PSCI Version ID is supported. - Add all PSCI RET codes in uapi header. - Explicitely ret 1 from psci_cpu_kill() Changes in v3: - Roll up common functionality for getting conduit method. - Remove #defines for ARM32 and ARM64 in uapi/linux/psci.h - Remove functions not supported by PSCI v0.1 - Misc cleanups. - Add PSCI_AFFINITY_INFO return types in uapi header. - Changed function names for PSCI v0.1 and PSCI v0.2 - Added copyright info to uapi header. - Fixed args to affinity_info call. - Fix typo in psci_init definition when PSCI is not defined. Changes in v2: - Add AFFINITY_INFO and MIGRATE_INFO_TYPE functions. - Add binding Documentation. - Add function to get PSCI version. - Add common #defines in uapi/linux/psci.h - Implement cpu_kill and check if CPU is dead via AFFINITY_INFO. - Misc cleanups. Changes in v1: - Add new binding "arm, psci-0.2" - Separate conduit and PSCI function assignment methods. Ashwin Chaugule (3): PSCI: Add initial support for PSCIv0.2 functions Documentation: devicetree: Add new binding for PSCIv0.2 ARM: Check if a CPU has gone offline Documentation/devicetree/bindings/arm/psci.txt | 35 +++++- arch/arm/include/asm/psci.h | 7 +- arch/arm/kernel/psci.c | 158 +++++++++++++++++++----- arch/arm/kernel/psci_smp.c | 21 ++++ arch/arm64/kernel/psci.c | 163 ++++++++++++++++++++----- include/uapi/linux/Kbuild | 1 + include/uapi/linux/psci.h | 66 ++++++++++ 7 files changed, 390 insertions(+), 61 deletions(-) create mode 100644 include/uapi/linux/psci.h -- 1.8.3.2

11 years, 1 month

1
3
0 0

[PATCH v4 0/3] PSCI v0.2 support and DT bindings

by Ashwin Chaugule

Changes in v4: - Correct copyright banner format. - Check if PSCI Version ID is supported. - Add all PSCI RET codes in uapi header. - Explicitely ret 1 from psci_cpu_kill() Changes in v3: - Roll up common functionality for getting conduit method. - Remove #defines for ARM32 and ARM64 in uapi/linux/psci.h - Remove functions not supported by PSCI v0.1 - Misc cleanups. - Add PSCI_AFFINITY_INFO return types in uapi header. - Changed function names for PSCI v0.1 and PSCI v0.2 - Added copyright info to uapi header. - Fixed args to affinity_info call. - Fix typo in psci_init definition when PSCI is not defined. Changes in v2: - Add AFFINITY_INFO and MIGRATE_INFO_TYPE functions. - Add binding Documentation. - Add function to get PSCI version. - Add common #defines in uapi/linux/psci.h - Implement cpu_kill and check if CPU is dead via AFFINITY_INFO. - Misc cleanups. Changes in v1: - Add new binding "arm, psci-0.2" - Separate conduit and PSCI function assignment methods. Ashwin Chaugule (3): PSCI: Add initial support for PSCIv0.2 functions Documentation: devicetree: Add new binding for PSCIv0.2 ARM: Check if a CPU has gone offline Documentation/devicetree/bindings/arm/psci.txt | 35 +++++- arch/arm/include/asm/psci.h | 7 +- arch/arm/kernel/psci.c | 155 +++++++++++++++++++----- arch/arm/kernel/psci_smp.c | 21 ++++ arch/arm64/kernel/psci.c | 160 ++++++++++++++++++++----- include/uapi/linux/psci.h | 66 ++++++++++ 6 files changed, 383 insertions(+), 61 deletions(-) create mode 100644 include/uapi/linux/psci.h -- 1.8.3.2

11 years, 1 month

2
7
0 0

Replaced Tomasz Hardcoded PSCI

by Graeme Gregory

Hi Guys, I pulled Aschwin's updated PSCI cleanup for upstream into acpi-mainline-core this morning. This invalidated the previous patch from Tomasz to hardcard PSCI booting method so I replaced it with this simpler patch until we have ASWG compliant method. We can of course improve this within acpi-core until that time. Graeme

11 years, 1 month

2
3
0 0

[RFC PATCH 0/5] Introducing the Grand Unified Firmware Interface

by al.stone＠linaro.org

From: Al Stone <al.stone(a)linaro.org> These patches are purely experimental; they just barely compile and they do not run just yet. The reason for posting them is really just to stir some discussion and see if this is a truly crazy idea or if it has some potential for easing the ACPI transition. These patches introduce GUFI: the Grand Unified Firmware Interface. Okay, yes, it is a silly name. I didn't spend a lot of time on it. What I'm most interested in is the idea and whether it is worth pursuing further, and whether or not there are better ways to do this if it does make sense. The idea is very simple: introduce a shim layer that looks like a merge of some sort between ACPI and FDT functionality in the kernel. In that shim layer, make it possible for a driver to make a single call to a function, and with that call, retrieve configuration information stored in either ACPI tables or a DT. Further, allow the kernel to specify which has priority -- i.e., search through ACPI tables, and then through FDT if data is not found, or vice versa -- or which is exclusive, either ACPI or FDT only. Why would I do this? As a kernel developer, this allows me to make changes in the direction of either FDT or ACPI as quickly or as slowly as I want to. Most of my config can be in FDT and I can then piecemeal convert to ACPI as I figure out ASL and/or any driver changes that may be needed. Secondly, if I do this well, the changes to convert from FDT to ACPI *should* be very small; from ACPI to FDT may be much more difficult but over time that can likely be improved as well. Third, in the really, really long term, maybe someone comes up with yet another hardware configuration description format that is so cool it provides sharks with laser beams on their heads and *everyone* wants to convert to it. With this layer in place, perhaps we can smooth even that transition by abstracting out the config info that's needed and the API to retrieve it. So, what do you think? Al Stone (5): ACPI: GUFI: add kernel config options for GUFI ACPI: GUFI: add build commands for drivers/gufi ACPI: GUFI: add in early prototype code for some GUFI functions ACPI: GUFI: add in simple test driver placeholders ACPI: GUFI: start modifying the vexpress-sysreg driver to use the GUFI arch/arm64/Kconfig | 6 - drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/acpi/acpi_platform.c | 1 + drivers/gufi/Kconfig | 54 ++++++++ drivers/gufi/Makefile | 11 ++ drivers/gufi/gufi.c | 309 ++++++++++++++++++++++++++++++++++++++++++ drivers/gufi/gufi_acpi_test.c | 84 ++++++++++++ drivers/gufi/gufi_of_test.c | 83 ++++++++++++ drivers/mfd/vexpress-sysreg.c | 14 +- include/linux/gufi.h | 83 ++++++++++++ 11 files changed, 636 insertions(+), 12 deletions(-) create mode 100644 drivers/gufi/Kconfig create mode 100644 drivers/gufi/Makefile create mode 100644 drivers/gufi/gufi.c create mode 100644 drivers/gufi/gufi_acpi_test.c create mode 100644 drivers/gufi/gufi_of_test.c create mode 100644 include/linux/gufi.h -- 1.8.3.1

11 years, 1 month

6
13
0 0

[PATCH v3 0/3] PSCI v0.2 support and DT bindings

by Ashwin Chaugule

This patchset adds some new functions introduced by the PSCI v0.2 spec. It also adds DT bindings to differentiate between PSCI v0.1 and v0.2 and appropriately selects the Function IDs. The third patch makes use of a new function, AFFINITY_INFO, added by PSCI v0.2 to ensure that CPU's killed after CPU_OFF are actually offlined. Changes in v3: - Roll up common functionality for getting conduit method. - Remove #defines for ARM32 and ARM64 in uapi/linux/psci.h - Remove functions not supported by PSCI v0.1 - Misc cleanups. - Add PSCI_AFFINITY_INFO return types in uapi header. - Changed function names for PSCI v0.1 and PSCI v0.2 - Added copyright info to uapi header. - Fixed args to affinity_info call. - Fix typo in psci_init definition when PSCI is not defined. Changes in v2: - Add AFFINITY_INFO and MIGRATE_INFO_TYPE functions. - Add binding Documentation. - Add function to get PSCI version. - Add common #defines in uapi/linux/psci.h - Implement cpu_kill and check if CPU is dead via AFFINITY_INFO. - Misc cleanups. Changes in v1: - Add new binding "arm, psci-0.2" - Separate conduit and PSCI function assignment methods. Ashwin Chaugule (3): PSCI: Add initial support for PSCIv0.2 functions Documentation: devicetree: Add new binding for PSCIv0.2 ARM: Check if a CPU has gone offline Documentation/devicetree/bindings/arm/psci.txt | 35 +++++- arch/arm/include/asm/psci.h | 7 +- arch/arm/kernel/psci.c | 151 ++++++++++++++++++++---- arch/arm/kernel/psci_smp.c | 21 ++++ arch/arm64/kernel/psci.c | 154 +++++++++++++++++++++---- include/uapi/linux/psci.h | 45 ++++++++ 6 files changed, 367 insertions(+), 46 deletions(-) create mode 100644 include/uapi/linux/psci.h -- 1.8.3.2

11 years, 1 month

3
7
0 0

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

Linaro-acpi