[PATCH] acpi: arm: remove unused code paths and features
by Graeme Gregory
Tidy the file a bit by removing unused paths. Also removed unused kernel
options that do not currently make sense on arm/arm64
Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org>
---
drivers/acpi/plat/arm/boot.c | 115 ++-----------------------------------------
1 file changed, 5 insertions(+), 110 deletions(-)
diff --git a/drivers/acpi/plat/arm/boot.c b/drivers/acpi/plat/arm/boot.c
index 8600cd0..881478d 100644
--- a/drivers/acpi/plat/arm/boot.c
+++ b/drivers/acpi/plat/arm/boot.c
@@ -24,9 +24,6 @@
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/
-/*
- * BOZO: this needs to be done right....
- */
#include <linux/init.h>
#include <linux/acpi.h>
#include <linux/acpi_pmtmr.h>
@@ -46,8 +43,12 @@
#include <asm/smp.h>
#include <asm/acpi.h>
-static int __initdata acpi_force;
+/*
+ * We never plad to use RSDT on arm/arm64 as its deprecated in spec but this
+ * variable is still required by the ACPI core
+ */
u32 acpi_rsdt_forced;
+
int acpi_disabled;
EXPORT_SYMBOL(acpi_disabled);
@@ -223,56 +224,6 @@ acpi_parse_gic_distributor(struct acpi_subtable_header *header,
return 0;
}
-/*
- * acpi_pic_sci_set_trigger()
- *
- * use ELCR to set PIC-mode trigger type for SCI
- *
- * If a PIC-mode SCI is not recognized or gives spurious IRQ7's
- * it may require Edge Trigger -- use "acpi_sci=edge"
- *
- * Port 0x4d0-4d1 are ECLR1 and ECLR2, the Edge/Level Control Registers
- * for the 8259 PIC. bit[n] = 1 means irq[n] is Level, otherwise Edge.
- * ECLR1 is IRQs 0-7 (IRQ 0, 1, 2 must be 0)
- * ECLR2 is IRQs 8-15 (IRQ 8, 13 must be 0)
- */
-
-void __init acpi_pic_sci_set_trigger(unsigned int irq, u16 trigger)
-{
- unsigned int mask = 1 << irq;
- unsigned int old, new;
-
- /* Real old ELCR mask */
- old = inb(0x4d0) | (inb(0x4d1) << 8);
-
- /*
- * If we use ACPI to set PCI IRQs, then we should clear ELCR
- * since we will set it correctly as we enable the PCI irq
- * routing.
- */
- new = acpi_noirq ? old : 0;
-
- /*
- * Update SCI information in the ELCR, it isn't in the PCI
- * routing tables..
- */
- switch (trigger) {
- case 1: /* Edge - clear */
- new &= ~mask;
- break;
- case 3: /* Level - set */
- new |= mask;
- break;
- }
-
- if (old == new)
- return;
-
- printk(PREFIX "setting ELCR to %04x (from %04x)\n", new, old);
- outb(new, 0x4d0);
- outb(new >> 8, 0x4d1);
-}
-
int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
{
*irq = gsi_to_irq(gsi);
@@ -812,70 +763,14 @@ static int __init parse_acpi(char *arg)
if (strcmp(arg, "off") == 0) {
disable_acpi();
}
- /* acpi=force to over-ride black-list */
- else if (strcmp(arg, "force") == 0) {
- acpi_force = 1;
- acpi_disabled = 0;
- }
/* acpi=strict disables out-of-spec workarounds */
else if (strcmp(arg, "strict") == 0) {
acpi_strict = 1;
}
- /* acpi=rsdt use RSDT instead of XSDT */
- else if (strcmp(arg, "rsdt") == 0) {
- acpi_rsdt_forced = 1;
- }
- /* "acpi=noirq" disables ACPI interrupt routing */
- else if (strcmp(arg, "noirq") == 0) {
- acpi_noirq_set();
- }
- /* "acpi=copy_dsdt" copys DSDT */
- else if (strcmp(arg, "copy_dsdt") == 0) {
- acpi_gbl_copy_dsdt_locally = 1;
- } else {
- /* Core will printk when we return error. */
- return -EINVAL;
- }
return 0;
}
early_param("acpi", parse_acpi);
-/* FIXME: Using pci= for an ACPI parameter is a travesty. */
-static int __init parse_pci(char *arg)
-{
- if (arg && strcmp(arg, "noacpi") == 0)
- acpi_disable_pci();
- return 0;
-}
-early_param("pci", parse_pci);
-
-int __init acpi_mps_check(void)
-{
- return 0;
-}
-
-static int __init setup_acpi_sci(char *s)
-{
- if (!s)
- return -EINVAL;
- if (!strcmp(s, "edge"))
- acpi_sci_flags = ACPI_MADT_TRIGGER_EDGE |
- (acpi_sci_flags & ~ACPI_MADT_TRIGGER_MASK);
- else if (!strcmp(s, "level"))
- acpi_sci_flags = ACPI_MADT_TRIGGER_LEVEL |
- (acpi_sci_flags & ~ACPI_MADT_TRIGGER_MASK);
- else if (!strcmp(s, "high"))
- acpi_sci_flags = ACPI_MADT_POLARITY_ACTIVE_HIGH |
- (acpi_sci_flags & ~ACPI_MADT_POLARITY_MASK);
- else if (!strcmp(s, "low"))
- acpi_sci_flags = ACPI_MADT_POLARITY_ACTIVE_LOW |
- (acpi_sci_flags & ~ACPI_MADT_POLARITY_MASK);
- else
- return -EINVAL;
- return 0;
-}
-early_param("acpi_sci", setup_acpi_sci);
-
int __acpi_acquire_global_lock(unsigned int *lock)
{
unsigned int old, new, val;
--
1.8.3.1
11 years, 8 months
- 4
- 6
[PATCH 1/2] Remove __cpuinit and fix __init attribute location
by Hanjun Guo
__cpuinit is gone in kernel now, remove them.
__init belongs after the return type on functions,
not before, correct them too.
Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org>
---
drivers/acpi/plat/arm/boot.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/acpi/plat/arm/boot.c b/drivers/acpi/plat/arm/boot.c
index 8600cd0..928f6c9 100644
--- a/drivers/acpi/plat/arm/boot.c
+++ b/drivers/acpi/plat/arm/boot.c
@@ -147,7 +147,7 @@ static int __init acpi_parse_madt(struct acpi_table_header *table)
}
/* Local APIC = GIC cpu interface on ARM */
-static void __cpuinit acpi_register_lapic(int id, u8 enabled)
+static void acpi_register_lapic(int id, u8 enabled)
{
int cpu;
@@ -365,7 +365,7 @@ early_param("possible_cpus", _setup_possible_cpus);
* We do this because additional CPUs waste a lot of memory.
* -AK
*/
-__init void prefill_possible_map(void)
+void __init prefill_possible_map(void)
{
int i;
int possible, disabled_cpus;
@@ -405,7 +405,7 @@ __init void prefill_possible_map(void)
#ifdef CONFIG_ACPI_HOTPLUG_CPU
#include <acpi/processor.h>
-static void __cpuinit acpi_map_cpu2node(acpi_handle handle, int cpu, int physid)
+static void acpi_map_cpu2node(acpi_handle handle, int cpu, int physid)
{
#ifdef CONFIG_ACPI_NUMA
int nid;
@@ -418,7 +418,7 @@ static void __cpuinit acpi_map_cpu2node(acpi_handle handle, int cpu, int physid)
#endif
}
-static int __cpuinit _acpi_map_lsapic(acpi_handle handle, int *pcpu)
+static int _acpi_map_lsapic(acpi_handle handle, int *pcpu)
{
struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
union acpi_object *obj;
@@ -582,7 +582,7 @@ static int __init acpi_parse_hpet(struct acpi_table_header *table)
* hpet_insert_resource inserts the HPET resources used into the resource
* tree.
*/
-static __init int hpet_insert_resource(void)
+static int __init hpet_insert_resource(void)
{
if (!hpet_res)
return 1;
--
1.7.9.5
11 years, 8 months
- 1
- 1
[PATCH] ARMv8 foudation model: Fix cpu hot add failure on ARM64
by Hanjun Guo
All values in the ACPI blob are little-endian, but I creat the
DSDT table with values in big-endian format, so when I evaluate
_MAT object I will get values unexperted, this leads to cpu
hot add failure, fix it.
Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org>
---
platforms/foundation-v8.acpi/dsdt.asl | 27 ++++++++++++++-------------
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/platforms/foundation-v8.acpi/dsdt.asl b/platforms/foundation-v8.acpi/dsdt.asl
index d1a9716..9c128d3 100644
--- a/platforms/foundation-v8.acpi/dsdt.asl
+++ b/platforms/foundation-v8.acpi/dsdt.asl
@@ -38,8 +38,9 @@ DefinitionBlock (
Name (MAT0, Buffer (0x28)
{
+ /* Be careful, little-endian here */
/* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* type, len, reserved, gic_id */
- /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, /* uid, flags */
+ /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* uid, flags */
/* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* parking_version, performance_interrupt */
/* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* parked_address */
/* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* base_address */
@@ -88,8 +89,8 @@ DefinitionBlock (
Name (MAT0, Buffer (0x28)
{
- /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
- /* 0008 */ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01,
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
/* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
@@ -97,8 +98,8 @@ DefinitionBlock (
Name (MAT1, Buffer (0x28)
{
- /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
- /* 0008 */ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
@@ -138,8 +139,8 @@ DefinitionBlock (
Name (MAT0, Buffer (0x28)
{
- /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
- /* 0008 */ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00,
+ /* 0008 */ 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
/* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
@@ -147,8 +148,8 @@ DefinitionBlock (
Name (MAT1, Buffer (0x28)
{
- /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
- /* 0008 */ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00,
+ /* 0008 */ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
@@ -188,8 +189,8 @@ DefinitionBlock (
Name (MAT0, Buffer (0x28)
{
- /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
- /* 0008 */ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01,
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
+ /* 0008 */ 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
/* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
@@ -197,8 +198,8 @@ DefinitionBlock (
Name (MAT1, Buffer (0x28)
{
- /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
- /* 0008 */ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00,
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
+ /* 0008 */ 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
--
1.7.9.5
11 years, 8 months
- 1
- 0
[PATCH][acpi-asl] ACPI: ARM: arndale: convert GPIO controller 3 of 4 to ACPI
by al.stone＠linaro.org
From: Al Stone <ahs3(a)redhat.com>
This builds on the prior Arndale GPIO patch by adding another controller
to the ACPI configuration.
Signed-off-by: Al Stone <al.stone(a)linaro.org>
---
platforms/exynos5250-arndale.acpi/ssdt0.asl | 156 +++++++++++++++++++++++++++-
1 file changed, 154 insertions(+), 2 deletions(-)
diff --git a/platforms/exynos5250-arndale.acpi/ssdt0.asl b/platforms/exynos5250-arndale.acpi/ssdt0.asl
index 8b8efc7..48fa409 100644
--- a/platforms/exynos5250-arndale.acpi/ssdt0.asl
+++ b/platforms/exynos5250-arndale.acpi/ssdt0.asl
@@ -12,10 +12,162 @@ DefinitionBlock (
2, // SSDT compliance revision
"LINARO", // OEM ID
"ARNDALE ", // table ID
- 0x00000003) // OEM revision
+ 0x00000004) // OEM revision
{
Scope (\_SB)
{
+ // Base Address: 0x10d10000
+ Device (SPC2) // Samsung pin controller
+ {
+ Name (_HID, "LINA0002")
+ Name (_UID, 0x2)
+
+ Name (BNKS, 0x5) // number of pin banks
+ Name (NGRP, 0x2) // number of pin groups
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ // Base address for the pin controller
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0x10d10000,
+ 0x20)
+ })
+ Return (RBUF)
+ }
+
+ Device (GPV0) // GPIO chip GPV0 -- first bank
+ {
+ Name (TAG, "gpv0") // human-readable name
+ Name (BASE, 0x0) // base pin number
+ Name (NPIN, 0x8) // number of pins
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0x10d10000,
+ 0x20)
+ })
+ Return (RBUF)
+ }
+ }
+
+ Device (GPV1) // GPIO chip GPV1
+ {
+ Name (TAG, "gpv1") // human-readable name
+ Name (BASE, 0x0) // base pin number
+ Name (NPIN, 0x8) // number of pins
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0x10d10020,
+ 0x20)
+ })
+ Return (RBUF)
+ }
+ }
+
+ Device (GPV2) // GPIO chip GPV2
+ {
+ Name (TAG, "gpv2") // human-readable name
+ Name (BASE, 0x0) // base pin number
+ Name (NPIN, 0x8) // number of pins
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0x10d10060,
+ 0x20)
+ })
+ Return (RBUF)
+ }
+ }
+
+ Device (GPV3) // GPIO chip GPV3
+ {
+ Name (TAG, "gpv3") // human-readable name
+ Name (BASE, 0x0) // base pin number
+ Name (NPIN, 0x8) // number of pins
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0x10d10080,
+ 0x20)
+ })
+ Return (RBUF)
+ }
+ }
+
+ Device (GPV4) // GPIO chip GPV4
+ {
+ Name (TAG, "gpv4") // human-readable name
+ Name (BASE, 0x0) // base pin number
+ Name (NPIN, 0x8) // number of pins
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0x10d100c0,
+ 0x20)
+ })
+ Return (RBUF)
+ }
+ }
+
+ Device (C2RX) // First pin group
+ {
+ Name (NPIN, 0x10) // number of pins
+ Name (FUNC, 0x2) // function number
+ Name (PUD, 0x0) // direction
+ Name (DRV, 0x0) // drive
+
+ Method (PINS, 0x0, NotSerialized)
+ {
+ Return (Package () {
+ "gpv0-0", "gpv0-1", "gpv0-2",
+ "gpv0-3", "gpv0-4", "gpv0-5",
+ "gpv0-6", "gpv0-7",
+ "gpv1-0", "gpv1-1", "gpv1-2",
+ "gpv1-3", "gpv1-4", "gpv1-5",
+ "gpv1-6", "gpv1-7",
+ })
+ }
+ }
+
+ Device (C2TX) // second pin group
+ {
+ Name (NPIN, 0x10) // number of pins
+ Name (FUNC, 0x2) // function number
+ Name (PUD, 0x0) // direction
+ Name (DRV, 0x0) // drive
+
+ Method (PINS, 0x0, NotSerialized)
+ {
+ Return (Package () {
+ "gpv2-0", "gpv2-1", "gpv2-2",
+ "gpv2-3", "gpv2-4", "gpv2-5",
+ "gpv2-6", "gpv2-7",
+ "gpv3-0", "gpv3-1", "gpv3-2",
+ "gpv3-3", "gpv3-4", "gpv3-5",
+ "gpv3-6", "gpv3-7",
+ })
+ }
+ }
+ }
+
// Base Address: 0x03860000
Device (SPC3) // Samsung pin controller
{
@@ -24,7 +176,6 @@ DefinitionBlock (
Name (BNKS, 0x1) // number of pin banks
Name (NGRP, 0x1) // number of pin groups
- Name (NFUN, 0x1) // number of pinmux functions
Method (_CRS, 0x0, Serialized)
{
@@ -65,6 +216,7 @@ DefinitionBlock (
Name (FUNC, 0x2) // function number
Name (PUD, 0x0) // direction
Name (DRV, 0x0) // drive
+
Method (PINS, 0x0, NotSerialized)
{
Return (Package () {
--
1.8.3.1
11 years, 8 months
- 1
- 0
of: fix fdt parsing of acpi blob addr/size for arm64
by Mark Salter
The early_init_dt_scan_acpi() function currently uses be32_to_cpu()
helpers to read the "linux,acpi-start" and "linux,acpi-len" properties.
This may not be safe for arm64. This patch uses of_read_ulong to read
the property values which should be safe for both arm and arm64.
Signed-off-by: Mark Salter <msalter(a)redhat.com>
---
drivers/of/fdt.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
index 875a4c1..d48ab6a 100644
--- a/drivers/of/fdt.c
+++ b/drivers/of/fdt.c
@@ -720,13 +720,13 @@ int __init early_init_dt_scan_acpi(unsigned long node, const char *uname,
/* Retrieve acpi,address line */
pinfo = (struct acpi_arm_root *)data;
p = of_get_flat_dt_prop(node, "linux,acpi-start", &l);
- if (p != NULL && l > 0)
- pinfo->phys_address = be32_to_cpu(*p);
+ if (p)
+ pinfo->phys_address = of_read_ulong(p, l/4);
/* Retrieve acpi,size line */
p = of_get_flat_dt_prop(node, "linux,acpi-len", &l);
- if (p != NULL && l > 0)
- pinfo->size = be32_to_cpu(*p);
+ if (p)
+ pinfo->size = of_read_ulong(p, l/4);
return 1;
}
--
1.8.3.1
11 years, 8 months
- 2
- 1
[PATCH 0/5] First of the Arndale GPIO/pinctrl patches
by al.stone＠linaro.org
From: Al Stone <ahs3(a)redhat.com>
I should have sent these out for comment much sooner. Once these are
in good shape, the next steps are to send patches for verifying that
the pinconf code is working properly, connecting up the GPIO interrupts
using ACPI, and then conversion of all of the pin controllers for
Arndale (this patch converts one of four).
This patch puts most of the infrastructure in place so that in the
3.11 kernel the Arndale pin controllers can be converted from FDT to
ACPI. The changes in ASL are included in a separate patch. What this
allows is for the pin controllers to be described in either FDT or ACPI
for Arndale and -- in conjunction with the ASL changes -- shows how to
describe a Samsung controller in ACPI.
Al Stone (5):
ACPI: ARM: arndale: remove GPZ GPIO definition from DT so it can be in
ACPI
ACPI: ARM: arndale: whitelist the samsung-pinctrl driver for ACPI
ACPI: make an error message a little clearer
ACPI: improve acpi_extract_package() utility
ACPI: ARM: arndale: enable ACPI in the Samsung pinctrl driver
arch/arm/boot/dts/exynos5250-pinctrl.dtsi | 2 +
arch/arm/boot/dts/exynos5250.dtsi | 6 +-
drivers/acpi/acpi_platform.c | 3 +
drivers/acpi/osl.c | 2 +-
drivers/acpi/utils.c | 17 +-
drivers/pinctrl/pinctrl-samsung.c | 507 +++++++++++++++++++++++++++++-
drivers/pinctrl/pinctrl-samsung.h | 3 +
7 files changed, 526 insertions(+), 14 deletions(-)
--
1.8.3.1
11 years, 8 months
- 3
- 7
[PATCH] Fix build errors when CONFIG_ACPI not defined
by Mark Salter
The kernel fails to build when CONFIG_ACPI is not defined:
drivers/virtio/virtio_mmio.c:657:3: error: implicit declaration of function 'ACPI_PTR'
.acpi_match_table = ACPI_PTR(virtio_mmio_acpi_match),
^
...
drivers/net/ethernet/smsc/smc91x.c:2412:3: error: implicit declaration of function 'ACPI_PTR'
.acpi_match_table = ACPI_PTR(smc91x_acpi_match),
^
^
This patch adds some needed ifdefs to allow !CONFIG_ACPI builds.
Signed-off-by: Mark Salter <msalter(a)redhat.com>
---
drivers/net/ethernet/smsc/smc91x.c | 2 ++
drivers/virtio/virtio_mmio.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/net/ethernet/smsc/smc91x.c b/drivers/net/ethernet/smsc/smc91x.c
index b181377..3561147 100644
--- a/drivers/net/ethernet/smsc/smc91x.c
+++ b/drivers/net/ethernet/smsc/smc91x.c
@@ -2409,7 +2409,9 @@ static struct platform_driver smc_driver = {
.owner = THIS_MODULE,
.pm = &smc_drv_pm_ops,
.of_match_table = of_match_ptr(smc91x_match),
+#ifdef CONFIG_ACPI
.acpi_match_table = ACPI_PTR(smc91x_acpi_match),
+#endif
},
};
diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c
index 1bf6bad..e7c4db6 100644
--- a/drivers/virtio/virtio_mmio.c
+++ b/drivers/virtio/virtio_mmio.c
@@ -654,7 +654,9 @@ static struct platform_driver virtio_mmio_driver = {
.name = "virtio-mmio",
.owner = THIS_MODULE,
.of_match_table = virtio_mmio_match,
+#ifdef CONFIG_ACPI
.acpi_match_table = ACPI_PTR(virtio_mmio_acpi_match),
+#endif
},
};
--
1.8.3.1
11 years, 8 months
- 2
- 1
[PATCHv2] platforms: add rtsm_ve-aemv8a.acpi
by Graeme Gregory
There are enough differences between this model and foundation model I think
it is ok to be a different platform.
Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org>
---
platforms/rtsm_ve-aemv8a.acpi/.gitignore | 3 +
platforms/rtsm_ve-aemv8a.acpi/apic.asl | 126 ++++++++++
platforms/rtsm_ve-aemv8a.acpi/bert.asl | 21 ++
platforms/rtsm_ve-aemv8a.acpi/cpep.asl | 26 ++
platforms/rtsm_ve-aemv8a.acpi/dsdt.asl | 234 +++++++++++++++++
platforms/rtsm_ve-aemv8a.acpi/ecdt.asl | 37 +++
platforms/rtsm_ve-aemv8a.acpi/einj.asl | 151 +++++++++++
platforms/rtsm_ve-aemv8a.acpi/erst.asl | 278 +++++++++++++++++++++
platforms/rtsm_ve-aemv8a.acpi/facp.asl | 167 +++++++++++++
platforms/rtsm_ve-aemv8a.acpi/facs.asl | 21 ++
platforms/rtsm_ve-aemv8a.acpi/fpdt.asl | 35 +++
platforms/rtsm_ve-aemv8a.acpi/gtdt.asl | 42 ++++
platforms/rtsm_ve-aemv8a.acpi/hest.asl | 193 ++++++++++++++
platforms/rtsm_ve-aemv8a.acpi/mcfg.asl | 26 ++
platforms/rtsm_ve-aemv8a.acpi/mchi.asl | 38 +++
platforms/rtsm_ve-aemv8a.acpi/mpst.asl | 87 +++++++
platforms/rtsm_ve-aemv8a.acpi/msct.asl | 51 ++++
platforms/rtsm_ve-aemv8a.acpi/oem0.asl | 18 ++
platforms/rtsm_ve-aemv8a.acpi/pmtt.asl | 105 ++++++++
platforms/rtsm_ve-aemv8a.acpi/rsdp.asl | 17 ++
.../rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest | 34 +++
platforms/rtsm_ve-aemv8a.acpi/slit.asl | 60 +++++
platforms/rtsm_ve-aemv8a.acpi/spmi.asl | 40 +++
platforms/rtsm_ve-aemv8a.acpi/srat.asl | 57 +++++
platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl | 17 ++
platforms/rtsm_ve-aemv8a.acpi/tpm2.asl | 22 ++
platforms/rtsm_ve-aemv8a.acpi/uefi.asl | 21 ++
platforms/rtsm_ve-aemv8a.acpi/xsdt.asl | 39 +++
28 files changed, 1966 insertions(+)
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/.gitignore
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/apic.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/bert.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/cpep.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/dsdt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/ecdt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/einj.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/erst.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/facp.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/facs.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/fpdt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/gtdt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/hest.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/mcfg.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/mchi.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/mpst.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/msct.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/oem0.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/pmtt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/rsdp.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/slit.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/spmi.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/srat.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/tpm2.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/uefi.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/xsdt.asl
diff --git a/platforms/rtsm_ve-aemv8a.acpi/.gitignore b/platforms/rtsm_ve-aemv8a.acpi/.gitignore
new file mode 100644
index 0000000..9585b50
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/.gitignore
@@ -0,0 +1,3 @@
+*.aml
+*.lst
+*.acpi
diff --git a/platforms/rtsm_ve-aemv8a.acpi/apic.asl b/platforms/rtsm_ve-aemv8a.acpi/apic.asl
new file mode 100644
index 0000000..6f1158e
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/apic.asl
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [APIC] Multiple APIC Description Table (MADT)
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "APIC"
+[0004] Table Length : 000000F6
+[0001] Revision : 03
+[0001] Checksum : B0
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20110623
+
+[0004] Local Apic Address : 2C002000
+[0004] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 0
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 28
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000000 /* Should be equal to FDT provided or CPU hardware ID */
+[0004] Processor UID : 00000000
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C002000 /* this is the foundation model's GIC address */
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 28
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000001
+[0004] Processor UID : 00000001
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C002000
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 28
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000002
+[0004] Processor UID : 00000002
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C002000
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 28
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000003
+[0004] Processor UID : 00000003
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C002000
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 28
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000004
+[0004] Processor UID : 00000004
+[0004] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C002000
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 28
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000005
+[0004] Processor UID : 00000005
+[0004] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C002000
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 28
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000006
+[0004] Processor UID : 00000006
+[0004] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C002000
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 28
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000007
+[0004] Processor UID : 00000007
+[0004] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C002000
+
+[0001] Subtable Type : 0C [Generic Interrupt Distributor]
+[0001] Length : 18
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000000
+[0008] Base Address : 000000002C001000 /* armv8 foundation model's GIC distributor base addr */
+[0004] Interrupt Base : 00000000
+[0004] Reserved : 00000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/bert.asl b/platforms/rtsm_ve-aemv8a.acpi/bert.asl
new file mode 100644
index 0000000..60a147f
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/bert.asl
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [BERT] Boot Error Record Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "BERT"
+[0004] Table Length : 00000030
+[0001] Revision : 01
+[0001] Checksum : 15
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Boot Error Region Length : 00000000
+[0008] Boot Error Region Address : 0000000000000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/cpep.asl b/platforms/rtsm_ve-aemv8a.acpi/cpep.asl
new file mode 100644
index 0000000..332b6fd
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/cpep.asl
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [CPEP] Corrected Platform Error Polling Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "CPEP"
+[0004] Table Length : 00000034
+[0001] Revision : 01
+[0001] Checksum : 0F
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0008] Reserved : 0000000000000000
+
+[0001] Subtable Type : 00
+[0001] Length : 08
+[0001] Processor ID : 00
+[0001] Processor EID : 00
+[0004] Polling Interval : 00000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/dsdt.asl b/platforms/rtsm_ve-aemv8a.acpi/dsdt.asl
new file mode 100644
index 0000000..ed13b1f
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/dsdt.asl
@@ -0,0 +1,234 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [DSDT] Description of the armv8 VE Model
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+DefinitionBlock (
+ "dsdt.aml", // output filename
+ "DSDT", // table signature
+ 2, // DSDT compliance revision
+ "LINARO", // OEM ID
+ "RTSMVEV8", // table ID
+ 0x00000002) // OEM revision
+{
+ Scope (\_SB)
+ {
+ Device (SCK0)
+ {
+ Name (_HID, "ACPI0004")
+ Name (_UID, 0x00)
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Device (PRC0)
+ {
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0x00)
+
+ /* CPU0 will be always present */
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Name (MAT0, Buffer (0x28)
+ {
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* type, len, reserved, gic_id */
+ /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, /* uid, flags */
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* parking_version, performance_interrupt */
+ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* parked_address */
+ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* base_address */
+ })
+
+ Name (MAT1, Buffer (0x28)
+ {
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+
+ Method (_MAT, 0, NotSerialized)
+ {
+ If (_STA())
+ {
+ Return (MAT0)
+ }
+ Else
+ {
+ Return (MAT1)
+ }
+ }
+ }
+
+ Device (PRC1)
+ {
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0x01)
+
+ Name (STA1, 0x0F)
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (STA1)
+ }
+
+ Method (_EJ0, 1, NotSerialized)
+ {
+ If (LEqual (STA1, 0x0F))
+ {
+ Store (0x00, STA1)
+ }
+ }
+
+ Name (MAT0, Buffer (0x28)
+ {
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+ /* 0008 */ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01,
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+
+ Name (MAT1, Buffer (0x28)
+ {
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+ /* 0008 */ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+
+ Method (_MAT, 0, NotSerialized)
+ {
+ If (_STA())
+ {
+ Return (MAT0)
+ }
+ Else
+ {
+ Return (MAT1)
+ }
+ }
+ }
+
+ Device (PRC2)
+ {
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0x02)
+
+ Name (STA2, 0x0F)
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (STA2)
+ }
+
+ Method (_EJ0, 1, NotSerialized)
+ {
+ If (LEqual (STA2, 0x0F))
+ {
+ Store (0x00, STA2)
+ }
+ }
+
+ Name (MAT0, Buffer (0x28)
+ {
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+ /* 0008 */ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+
+ Name (MAT1, Buffer (0x28)
+ {
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+ /* 0008 */ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+
+ Method (_MAT, 0, NotSerialized)
+ {
+ If (_STA())
+ {
+ Return (MAT0)
+ }
+ Else
+ {
+ Return (MAT1)
+ }
+ }
+ }
+
+ Device (PRC3)
+ {
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0x03)
+
+ Name (STA3, 0x0F)
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (STA3)
+ }
+
+ Method (_EJ0, 1, NotSerialized)
+ {
+ If (LEqual (STA3, 0x0F))
+ {
+ Store (0x00, STA3)
+ }
+ }
+
+ Name (MAT0, Buffer (0x28)
+ {
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+ /* 0008 */ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01,
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+
+ Name (MAT1, Buffer (0x28)
+ {
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+ /* 0008 */ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00,
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+
+ Method (_MAT, 0, NotSerialized)
+ {
+ If (_STA())
+ {
+ Return (MAT0)
+ }
+ Else
+ {
+ Return (MAT1)
+ }
+ }
+ }
+ }
+
+ Device (NET0) {
+ Name (_HID, "LINA0003")
+ Name (_UID, 0)
+
+ Method (_CRS, 0x0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0x1a000000, 0x00010000)
+ Interrupt (ResourceConsumer, Edge, ActiveBoth, Exclusive, , , ) {0x2F}
+ })
+ Return (RBUF)
+ }
+ }
+ }
+}
diff --git a/platforms/rtsm_ve-aemv8a.acpi/ecdt.asl b/platforms/rtsm_ve-aemv8a.acpi/ecdt.asl
new file mode 100644
index 0000000..a7e1442
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/ecdt.asl
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [ECDT] Embedded Controller Boot Resources Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "ECDT"
+[0004] Table Length : 00000042
+[0001] Revision : 01
+[0001] Checksum : 2D
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+
+[0012] Command/Status Register : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000066
+
+[0012] Data Register : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000062
+
+[0004] UID : 00000000
+[0001] GPE Number : 09
+[0001] Namepath : ""
diff --git a/platforms/rtsm_ve-aemv8a.acpi/einj.asl b/platforms/rtsm_ve-aemv8a.acpi/einj.asl
new file mode 100644
index 0000000..e12c75b
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/einj.asl
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [EINJ] Error Injection Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "EINJ"
+[0004] Table Length : 00000130
+[0001] Revision : 01
+[0001] Checksum : 09
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Injection Header Length : 00000030
+[0001] Flags : 00
+[0003] Reserved : 000000
+[0004] Injection Entry Count : 0000000A
+
+[0001] Action : 00 [Begin Operation]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 01 [Get Trigger Table]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 02 [Set Error Type]
+[0001] Instruction : 02 [Write Register]
+[0001] Flags (decoded below) : 01
+ Preserve Register Bits : 1
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 03 [Get Error Type]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 04 [End Operation]
+[0001] Instruction : 03 [Write Register Value]
+[0001] Flags (decoded below) : 01
+ Preserve Register Bits : 1
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 05 [Execute Operation]
+[0001] Instruction : 03 [Write Register Value]
+[0001] Flags (decoded below) : 01
+ Preserve Register Bits : 1
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 10
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 02 [Word Access:16]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 06 [Check Busy Status]
+[0001] Instruction : 01 [Read Register Value]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 07 [Get Command Status]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 01
+ Preserve Register Bits : 1
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
diff --git a/platforms/rtsm_ve-aemv8a.acpi/erst.asl b/platforms/rtsm_ve-aemv8a.acpi/erst.asl
new file mode 100644
index 0000000..817845f
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/erst.asl
@@ -0,0 +1,278 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [ERST] Error Record Serialization Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "ERST"
+[0004] Table Length : 00000230
+[0001] Revision : 01
+[0001] Checksum : AB
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Serialization Header Length : 00000030
+[0004] Reserved : 00000000
+[0004] Instruction Entry Count : 00000010
+
+[0001] Action : 00 [Begin Write Operation]
+[0001] Instruction : 03 [Write Register Value]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 01 [Begin Read Operation]
+[0001] Instruction : 03 [Write Register Value]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 02 [Begin Clear Operation]
+[0001] Instruction : 03 [Write Register Value]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 03 [End Operation]
+[0001] Instruction : 04 [Noop]
+[0001] Flags (decoded below) : 01
+ Preserve Register Bits : 1
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 04 [Set Record Offset]
+[0001] Instruction : 02 [Write Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 05 [Execute Operation]
+[0001] Instruction : 03 [Write Register Value]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 01 [Byte Access:8]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 06 [Check Busy Status]
+[0001] Instruction : 01 [Read Register Value]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 07 [Get Command Status]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 08 [Get Record Identifier]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 09 [Set Record Identifier]
+[0001] Instruction : 02 [Write Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 0A [Get Record Count]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 0B [Begin Dummy Write]
+[0001] Instruction : 03 [Write Register Value]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 0C [Unused/Unknown Action]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 0D [Get Error Address Range]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 0E [Get Error Address Length]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 0F [Get Error Attributes]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
diff --git a/platforms/rtsm_ve-aemv8a.acpi/facp.asl b/platforms/rtsm_ve-aemv8a.acpi/facp.asl
new file mode 100644
index 0000000..14ed9f2
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/facp.asl
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [FACP] ACPI Table
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "FACP"
+[0004] Table Length : 0000010C
+[0001] Revision : 05
+[0001] Checksum : 18
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20111123
+
+[0004] FACS Address : 00000000
+[0004] DSDT Address : 00000010
+[0001] Model : 00
+[0001] PM Profile : 04 /* Enterprise Server */
+[0002] SCI Interrupt : 0000
+[0004] SMI Command Port : 00000000
+[0001] ACPI Enable Value : 00
+[0001] ACPI Disable Value : 00
+[0001] S4BIOS Command : 00
+[0001] P-State Control : 00
+[0004] PM1A Event Block Address : 00000001
+[0004] PM1B Event Block Address : 00000000
+[0004] PM1A Control Block Address : 00000001
+[0004] PM1B Control Block Address : 00000000
+[0004] PM2 Control Block Address : 00000001
+[0004] PM Timer Block Address : 00000001
+[0004] GPE0 Block Address : 00000001
+[0004] GPE1 Block Address : 00000000
+[0001] PM1 Event Block Length : 04
+[0001] PM1 Control Block Length : 02
+[0001] PM2 Control Block Length : 01
+[0001] PM Timer Block Length : 04
+[0001] GPE0 Block Length : 08
+[0001] GPE1 Block Length : 00
+[0001] GPE1 Base Offset : 00
+[0001] _CST Support : 00
+[0002] C2 Latency : 0000
+[0002] C3 Latency : 0000
+[0002] CPU Cache Size : 0000
+[0002] Cache Flush Stride : 0000
+[0001] Duty Cycle Offset : 00
+[0001] Duty Cycle Width : 00
+[0001] RTC Day Alarm Index : 00
+[0001] RTC Month Alarm Index : 00
+[0001] RTC Century Index : 00
+[0002] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[0001] Reserved : 00
+[0004] Flags (decoded below) : 00000000
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 1
+ All CPUs support C1 (V1) : 0
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 1
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 0
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 0
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 1
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 0
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 1
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 1
+ Low Power S0 Idle (V5) : 1
+
+[0012] Reset Register : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 01 [Byte Access:8]
+[0008] Address : 0000000000000001
+
+[0001] Value to cause reset : 00
+[0003] Reserved : 000000
+[0008] FACS Address : 0000000000000000
+[0008] DSDT Address : 0000000000000010
+[0012] PM1A Event Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 20
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 02 [Word Access:16]
+[0008] Address : 0000000000000001
+
+[0012] PM1B Event Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 00
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+[0012] PM1A Control Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 10
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 02 [Word Access:16]
+[0008] Address : 0000000000000001
+
+[0012] PM1B Control Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 00
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+[0012] PM2 Control Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000001
+
+[0012] PM Timer Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 20
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 03 [DWord Access:32]
+[0008] Address : 0000000000000001
+
+[0012] GPE0 Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 80
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 01 [Byte Access:8]
+[0008] Address : 0000000000000001
+
+[0012] GPE1 Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 00
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+
+[0012] Sleep Control Register : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 01 [Byte Access:8]
+[0008] Address : 0000000000000000
+
+[0012] Sleep Status Register : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 01 [Byte Access:8]
+[0008] Address : 0000000000000000
+
diff --git a/platforms/rtsm_ve-aemv8a.acpi/facs.asl b/platforms/rtsm_ve-aemv8a.acpi/facs.asl
new file mode 100644
index 0000000..9695e05
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/facs.asl
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [FACS] ACPI Table
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "FACS"
+[0004] Length : 00000040
+[0004] Hardware Signature : 00000000
+[0004] 32 Firmware Waking Vector : 00000000
+[0004] Global Lock : 00000000
+[0004] Flags (decoded below) : 00000000
+ S4BIOS Support Present : 0
+ 64-bit Wake Supported (V2) : 0
+[0008] 64 Firmware Waking Vector : 0000000000000000
+[0001] Version : 02
+[0003] Reserved : 000000
+[0004] OspmFlags (decoded below) : 00000000
+ 64-bit Wake Env Required (V2) : 0
diff --git a/platforms/rtsm_ve-aemv8a.acpi/fpdt.asl b/platforms/rtsm_ve-aemv8a.acpi/fpdt.asl
new file mode 100644
index 0000000..bb03f47
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/fpdt.asl
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [FPDT] Firmware Performance Data Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "FPDT"
+[0004] Table Length : 00000064
+[0001] Revision : 01
+[0001] Checksum : BD
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20110804
+
+
+[0002] Subtable Type : 0000
+[0001] Length : 30
+[0001] Revision : 01
+[0004] Reserved : 00000000
+[0008] Reset End : 0000000000000000
+[0008] Load Image Start : 0000000000000000
+[0008] Start Image Start : 0000000000000000
+[0008] Exit Services Entry : 0000000000000000
+[0008] Exit Services Exit : 0000000000000000
+
+[0002] Subtable Type : 0001
+[0001] Length : 10
+[0001] Revision : 01
+[0004] Reserved : 00000000
+[0008] S3PT Address : 0000000000000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl b/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl
new file mode 100644
index 0000000..068ad4a
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [GTDT] Generic Timer Description Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "GTDT"
+[0004] Table Length : 00000050
+[0001] Revision : 01
+[0001] Checksum : F1
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20110623
+
+[0008] Timer Address : 0000000000000000
+[0004] Flags (decoded below) : 00000001
+ Memory Present : 1
+
+[0004] Secure PL1 Interrupt : 00000000
+[0004] SPL1 Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
+
+[0004] Non-Secure PL1 Interrupt : 00000000
+[0004] NSPL1 Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
+
+[0004] Virtual Timer Interrupt : 00000000
+[0004] VT Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
+
+[0004] Non-Secure PL2 Interrupt : 00000000
+[0004] NSPL2 Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
diff --git a/platforms/rtsm_ve-aemv8a.acpi/hest.asl b/platforms/rtsm_ve-aemv8a.acpi/hest.asl
new file mode 100644
index 0000000..b143bbb
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/hest.asl
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org
+ *
+ * [HEST] Hardware Error Source Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "HEST"
+[0004] Table Length : 000001D4
+[0001] Revision : 01
+[0001] Checksum : 20
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Error Source Count : 00000004
+
+[0002] Subtable Type : 0000 [IA-32 Machine Check Exception]
+[0002] Source Id : 0000
+[0002] Reserved1 : 0000
+[0001] Flags (decoded below) : 00
+ Firmware First : 0
+[0001] Enabled : 01
+[0004] Records To Preallocate : 00000001
+[0004] Max Sections Per Record : 00000001
+[0008] Global Capability Data : 0000000000000000
+[0008] Global Control Data : 0000000000000000
+[0001] Num Hardware Banks : 02
+[0007] Reserved2 : 00000000000000
+
+[0001] Bank Number : 00
+[0001] Clear Status On Init : 00
+[0001] Status Format : 00
+[0001] Reserved : 00
+[0004] Control Register : 00000000
+[0008] Control Data : 0000000000000000
+[0004] Status Register : 00000000
+[0004] Address Register : 00000000
+[0004] Misc Register : 00000000
+
+[0001] Bank Number : 01
+[0001] Clear Status On Init : 00
+[0001] Status Format : 00
+[0001] Reserved : 00
+[0004] Control Register : 00000000
+[0008] Control Data : 0000000000000000
+[0004] Status Register : 00000000
+[0004] Address Register : 00000000
+[0004] Misc Register : 00000000
+
+[0002] Subtable Type : 0001 [IA-32 Corrected Machine Check]
+[0002] Source Id : 0001
+[0002] Reserved1 : 0000
+[0001] Flags (decoded below) : 00
+ Firmware First : 0
+[0001] Enabled : 01
+[0004] Records To Preallocate : 00000001
+[0004] Max Sections Per Record : 00000001
+
+[0028] Notify : [Hardware Error Notification Structure]
+[0001] Notify Type : 00 [Polled]
+[0001] Notify Length : 00
+[0002] Configuration Write Enable : 0000
+[0004] PollInterval : 00000000
+[0004] Vector : 00000000
+[0004] Polling Threshold Value : 00000000
+[0004] Polling Threshold Window : 00000000
+[0004] Error Threshold Value : 00000000
+[0004] Error Threshold Window : 00000000
+
+[0001] Num Hardware Banks : 02
+[0003] Reserved2 : 000000
+
+[0001] Bank Number : 00
+[0001] Clear Status On Init : 00
+[0001] Status Format : 00
+[0001] Reserved : 00
+[0004] Control Register : 00000000
+[0008] Control Data : 0000000000000000
+[0004] Status Register : 00000000
+[0004] Address Register : 00000000
+[0004] Misc Register : 00000000
+
+[0001] Bank Number : 01
+[0001] Clear Status On Init : 00
+[0001] Status Format : 00
+[0001] Reserved : 00
+[0004] Control Register : 00000000
+[0008] Control Data : 0000000000000000
+[0004] Status Register : 00000000
+[0004] Address Register : 00000000
+[0004] Misc Register : 00000000
+
+[0002] Subtable Type : 0007 [PCI Express AER (AER Endpoint)]
+[0002] Source Id : 0000
+[0002] Reserved : 0000
+[0001] Flags (decoded below) : 00
+ Firmware First : 0
+[0001] Enabled : 01
+[0004] Records To Preallocate : 00000001
+[0004] Max Sections Per Record : 00000001
+[0004] Bus : 00000000
+[0002] Device : 0000
+[0002] Function : 0000
+[0002] DeviceControl : 0000
+[0002] Reserved : 0000
+[0004] Uncorrectable Mask : 00000000
+[0004] Uncorrectable Severity : 00000000
+[0004] Correctable Mask : 00000000
+[0004] Advanced Capabilities : 00000000
+
+[0002] Subtable Type : 0008 [PCI Express/PCI-X Bridge AER]
+[0002] Source Id : 0000
+[0002] Reserved : 0000
+[0001] Flags (decoded below) : 00
+ Firmware First : 0
+[0001] Enabled : 01
+[0004] Records To Preallocate : 00000001
+[0004] Max Sections Per Record : 00000001
+[0004] Bus : 00000000
+[0002] Device : 0000
+[0002] Function : 0000
+[0002] DeviceControl : 0000
+[0002] Reserved : 0000
+[0004] Uncorrectable Mask : 00000000
+[0004] Uncorrectable Severity : 00000000
+[0004] Correctable Mask : 00000000
+[0004] Advanced Capabilities : 00000000
+[0004] 2nd Uncorrectable Mask : 00000000
+[0004] 2nd Uncorrectable Severity : 00000000
+[0004] 2nd Advanced Capabilities : 00000000
+
+[0002] Subtable Type : 0009 [Generic Hardware Error Source]
+[0002] Source Id : 0002
+[0002] Related Source Id : FFFF
+[0001] Reserved : 00
+[0001] Enabled : 01
+[0004] Records To Preallocate : 00000001
+[0004] Max Sections Per Record : 00000001
+[0004] Max Raw Data Length : 00001000
+
+[0012] Error Status Address : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0028] Notify : [Hardware Error Notification Structure]
+[0001] Notify Type : 03 [SCI]
+[0001] Notify Length : 1C
+[0002] Configuration Write Enable : 0000
+[0004] PollInterval : 00000000
+[0004] Vector : 00000000
+[0004] Polling Threshold Value : 00000000
+[0004] Polling Threshold Window : 00000000
+[0004] Error Threshold Value : 00000000
+[0004] Error Threshold Window : 00000000
+
+[0004] Error Status Block Length : 00001000
+
+[0002] Subtable Type : 0009 [Generic Hardware Error Source]
+[0002] Source Id : 0003
+[0002] Related Source Id : 0000
+[0001] Reserved : 00
+[0001] Enabled : 01
+[0004] Records To Preallocate : 00000001
+[0004] Max Sections Per Record : 00000001
+[0004] Max Raw Data Length : 00001000
+
+[0012] Error Status Address : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0028] Notify : [Hardware Error Notification Structure]
+[0001] Notify Type : 04 [NMI]
+[0001] Notify Length : 1C
+[0002] Configuration Write Enable : 0000
+[0004] PollInterval : 00000000
+[0004] Vector : 00000000
+[0004] Polling Threshold Value : 00000000
+[0004] Polling Threshold Window : 00000000
+[0004] Error Threshold Value : 00000000
+[0004] Error Threshold Window : 00000000
+
+[0004] Error Status Block Length : 00001000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/mcfg.asl b/platforms/rtsm_ve-aemv8a.acpi/mcfg.asl
new file mode 100644
index 0000000..aa56900
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/mcfg.asl
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [MCFG] PCIe Memory Mapped Configuration Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "MCFG"
+[0004] Table Length : 0000003C
+[0001] Revision : 01
+[0001] Checksum : 19
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0008] Reserved : 0000000000000000
+
+[0008] Base Address : 0000000000000000
+[0002] Segment Group Number : 0000
+[0001] Start Bus Number : 00
+[0001] End Bus Number : 00
+[0004] Reserved : 00000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/mchi.asl b/platforms/rtsm_ve-aemv8a.acpi/mchi.asl
new file mode 100644
index 0000000..33b5ea2
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/mchi.asl
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [MCHI] Management Controller Host Interface Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "MCHI"
+[0004] Table Length : 00000045
+[0001] Revision : 01
+[0001] Checksum : E4
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 02000715
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0001] Interface Type : 01
+[0001] Protocol : 00
+[0008] Protocol Data : 0000000000000000
+[0001] Interrupt Type : 00
+[0001] Gpe : 00
+[0001] Pci Device Flag : 00
+[0004] Global Interrupt : 00000000
+
+[0012] Control Register : [Generic Address Structure]
+[0001] Space ID : 02 [PCI_Config]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+[0001] Pci Segment : 00
+[0001] Pci Bus : 00
+[0001] Pci Device : 00
+[0001] Pci Function : 00
diff --git a/platforms/rtsm_ve-aemv8a.acpi/mpst.asl b/platforms/rtsm_ve-aemv8a.acpi/mpst.asl
new file mode 100644
index 0000000..8fe524f
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/mpst.asl
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [MPST] Memory Power State Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "MPST"
+[0004] Table Length : 000000B6
+[0001] Revision : 01
+[0001] Checksum : 77
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20120913
+
+[0001] Channel ID : 00
+[0003] Reserved : 000000
+[0002] Power Node Count : 0002
+[0002] Reserved : 0000
+
+[0001] Flags (decoded below) : 00
+ Node Enabled : 0
+ Power Managed : 0
+ Hot Plug Capable : 0
+[0001] Reserved : 00
+[0002] Node ID : 0000
+[0004] Length : 00000000
+[0008] Range Address : 0000000000000000
+[0008] Range Length : 0000000000000000
+[0004] Num Power States : 00000002
+[0004] Num Physical Components : 00000003
+
+[0001] Power State : 00
+[0001] InfoIndex : 00
+
+[0001] Power State : 00
+[0001] InfoIndex : 00
+
+[0002] Component Id : 0000
+[0002] Component Id : 0001
+[0002] Component Id : 0002
+
+[0001] Flags (decoded below) : 00
+ Node Enabled : 0
+ Power Managed : 0
+ Hot Plug Capable : 0
+[0001] Reserved : 00
+[0002] Node ID : 0000
+[0004] Length : 00000000
+[0008] Range Address : 0000000000000000
+[0008] Range Length : 0000000000000000
+[0004] Num Power States : 00000001
+[0004] Num Physical Components : 00000001
+
+[0001] Power State : 00
+[0001] InfoIndex : 00
+
+[0002] Component Id : 0000
+
+[0002] Characteristics Count : 0002
+[0002] Reserved : 0000
+
+[0001] Structure ID : 01
+[0001] Flags (decoded below) : 00
+ Memory Preserved : 0
+ Auto Entry : 0
+ Auto Exit : 0
+[0002] Reserved : 0000
+[0004] Average Power : 00000000
+[0004] Power Saving : 00000000
+[0008] Exit Latency : 0000000000000000
+[0008] Reserved : 0000000000000000
+
+[0001] Structure ID : 01
+[0001] Flags (decoded below) : 00
+ Memory Preserved : 0
+ Auto Entry : 0
+ Auto Exit : 0
+[0002] Reserved : 0000
+[0004] Average Power : 00000000
+[0004] Power Saving : 00000000
+[0008] Exit Latency : 0000000000000000
+[0008] Reserved : 0000000000000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/msct.asl b/platforms/rtsm_ve-aemv8a.acpi/msct.asl
new file mode 100644
index 0000000..39dd49a
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/msct.asl
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [MSCT] Maximum System Characteristics Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "MSCT"
+[0004] Table Length : 00000090
+[0001] Revision : 01
+[0001] Checksum : B7
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Proximity Offset : 00000038
+[0004] Max Proximity Domains : 00000003
+[0004] Max Clock Domains : 00000000
+[0008] Max Physical Address : 00000FFFFFFFFFFF
+
+[0001] Revision : 01
+[0001] Length : 16
+[0004] Domain Range Start : 00000000
+[0004] Domain Range End : 00000003
+[0004] Processor Capacity : 00000010
+[0008] Memory Capacity : 0000004000000000
+
+[0001] Revision : 01
+[0001] Length : 16
+[0004] Domain Range Start : 00000000
+[0004] Domain Range End : 00000000
+[0004] Processor Capacity : 00000000
+[0008] Memory Capacity : 0000000000000000
+
+[0001] Revision : 01
+[0001] Length : 16
+[0004] Domain Range Start : 00000000
+[0004] Domain Range End : 00000000
+[0004] Processor Capacity : 00000000
+[0008] Memory Capacity : 0000000000000000
+
+[0001] Revision : 01
+[0001] Length : 16
+[0004] Domain Range Start : 00000000
+[0004] Domain Range End : 00000000
+[0004] Processor Capacity : 00000000
+[0008] Memory Capacity : 0000000000000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/oem0.asl b/platforms/rtsm_ve-aemv8a.acpi/oem0.asl
new file mode 100644
index 0000000..570ea27
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/oem0.asl
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [OEMx] OEM Specific Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "OEM0"
+[0004] Table Length : 00000024
+[0001] Revision : 01
+[0001] Checksum : 8B
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 0000000A
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
diff --git a/platforms/rtsm_ve-aemv8a.acpi/pmtt.asl b/platforms/rtsm_ve-aemv8a.acpi/pmtt.asl
new file mode 100644
index 0000000..ce4fcba
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/pmtt.asl
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [PMTT] Platform Memory Topology Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "PMTT"
+[0004] Table Length : 000000B4
+[0001] Revision : 01
+[0001] Checksum : 3A
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20110826
+
+[0004] Reserved : 00000000
+
+[0001] Subtable Type : 00 [Socket]
+[0001] Reserved : 00
+[0002] Length : 0080
+[0002] Flags (decoded below) : 0001
+ Top-level Device : 1
+ Physical Element : 0
+ Memory Type : 0
+[0002] Reserved : 0000
+[0002] Socket ID : 0000
+[0002] Reserved : 0000
+
+[0001] Subtable Type : 01 [Memory Controller]
+[0001] Reserved : 00
+[0002] Length : 0054
+[0002] Flags (decoded below) : 0005
+ Top-level Device : 1
+ Physical Element : 0
+ Memory Type : 1
+[0002] Reserved : 0000
+[0004] Read Latency : 00000000
+[0004] Write Latency : 00000000
+[0004] Read Bandwidth : 00000000
+[0004] Write Bandwidth : 00000000
+[0002] Access Width : 0000
+[0002] Alignment : 0000
+[0002] Reserved : 0000
+[0002] Domain Count : 0003
+[0004] Proximity Domain : 00000000
+[0004] Proximity Domain : 00000000
+[0004] Proximity Domain : 00000000
+
+[0001] Subtable Type : 02 [Physical Component (DIMM)]
+[0001] Reserved : 00
+[0002] Length : 0014
+[0002] Flags (decoded below) : 0002
+ Top-level Device : 0
+ Physical Element : 1
+ Memory Type : 0
+[0002] Reserved : 0000
+[0002] Component ID : 0000
+[0002] Reserved : 0000
+[0004] Memory Size : 00000000
+[0004] Bios Handle : 00000000
+
+[0001] Subtable Type : 02 [Physical Component (DIMM)]
+[0001] Reserved : 00
+[0002] Length : 0014
+[0002] Flags (decoded below) : 0002
+ Top-level Device : 0
+ Physical Element : 1
+ Memory Type : 0
+[0002] Reserved : 0000
+[0002] Component ID : 0000
+[0002] Reserved : 0000
+[0004] Memory Size : 00000000
+[0004] Bios Handle : 00000000
+
+[0001] Subtable Type : 01 [Memory Controller]
+[0001] Reserved : 00
+[0002] Length : 0020
+[0002] Flags (decoded below) : 0001
+ Top-level Device : 1
+ Physical Element : 0
+ Memory Type : 0
+[0002] Reserved : 0000
+[0004] Read Latency : 00000000
+[0004] Write Latency : 00000000
+[0004] Read Bandwidth : 00000000
+[0004] Write Bandwidth : 00000000
+[0002] Access Width : 0000
+[0002] Alignment : 0000
+[0002] Reserved : 0000
+[0002] Domain Count : 0000
+
+[0001] Subtable Type : 00 [Socket]
+[0001] Reserved : 00
+[0002] Length : 000C
+[0002] Flags (decoded below) : 0001
+ Top-level Device : 1
+ Physical Element : 0
+ Memory Type : 0
+[0002] Reserved : 0000
+[0002] Socket ID : 0000
+[0002] Reserved : 0000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/rsdp.asl b/platforms/rtsm_ve-aemv8a.acpi/rsdp.asl
new file mode 100644
index 0000000..329ffe5
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/rsdp.asl
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [RSDP] ACPI Table
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0008] Signature : "RSD PTR "
+[0001] Checksum : 43
+[0006] Oem ID : "LINARO"
+[0001] Revision : 02
+[0004] RSDT Address : 00000000
+[0004] Length : 00000024
+[0008] XSDT Address : 0000000000000000
+[0001] Extended Checksum : DC
+[0003] Reserved : 000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest b/platforms/rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest
new file mode 100644
index 0000000..6b3a743
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest
@@ -0,0 +1,34 @@
+#
+# Each line is either a comment, white space, or two fields:
+#
+# <signature> : <ASL file name>
+#
+# NB: for each file x.asl, an AML file called x.aml will be created
+#
+
+rsdp: rsdp.asl
+xsdt: xsdt.asl
+facp: facp.asl
+dsdt: dsdt.asl
+ssdt: ssdt0.asl
+bert: bert.asl
+ecdt: ecdt.asl
+facs: facs.asl
+gtdt: gtdt.asl
+hest: hest.asl
+apic: apic.asl
+mcfg: mcfg.asl
+mpst: mpst.asl
+oem: oem0.asl
+pmmt: pmmt.asl
+slit: slit.asl
+spmi: spmi.asl
+srat: srat.asl
+uefi: uefi.asl
+cpep: cpep.asl
+einj: einj.asl
+erst: erst.asl
+fpdt: fpdt.asl
+mchi: mchi.asl
+msct: msct.asl
+
diff --git a/platforms/rtsm_ve-aemv8a.acpi/slit.asl b/platforms/rtsm_ve-aemv8a.acpi/slit.asl
new file mode 100644
index 0000000..96305c8
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/slit.asl
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [SLIT] System Locality Information Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "SLIT"
+[0004] Table Length : 000001BC
+[0001] Revision : 01
+[0001] Checksum : 00
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20110316
+
+[0008] Localities : 0000000000000014
+[0020] Locality 0 : 0A 10 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 \
+ 24 25 26 27
+[0020] Locality 1 : 10 0A 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 \
+ 23 24 25 26
+[0020] Locality 2 : 16 15 0A 10 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 \
+ 22 23 24 25
+[0020] Locality 3 : 17 16 10 0A 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 \
+ 21 22 23 24
+[0020] Locality 4 : 18 17 16 15 0A 10 16 17 18 19 1A 1B 1C 1D 1E 1F \
+ 20 21 22 23
+[0020] Locality 5 : 19 18 17 16 10 0A 15 16 17 18 19 1A 1B 1C 1D 1E \
+ 1F 20 21 22
+[0020] Locality 6 : 1A 19 18 17 16 15 0A 10 16 17 18 19 1A 1B 1C 1D \
+ 1E 1F 20 21
+[0020] Locality 7 : 1B 1A 19 18 17 16 10 0A 15 16 17 18 19 1A 1B 1C \
+ 1D 1E 1F 20
+[0020] Locality 8 : 1C 1B 1A 19 18 17 16 15 0A 10 16 17 18 19 1A 1B \
+ 1C 1D 1E 1F
+[0020] Locality 9 : 1D 1C 1B 1A 19 18 17 16 10 0A 15 16 17 18 19 1A \
+ 1B 1C 1D 1E
+[0020] Locality 10 : 1E 1D 1C 1B 1A 19 18 17 16 15 0A 10 16 17 18 19 \
+ 1A 1B 1C 1D
+[0020] Locality 11 : 1F 1E 1D 1C 1B 1A 19 18 17 16 10 0A 15 16 17 18 \
+ 19 1A 1B 1C
+[0020] Locality 12 : 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 0A 10 16 17 \
+ 18 19 1A 1B
+[0020] Locality 13 : 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 10 0A 15 16 \
+ 17 18 19 1A
+[0020] Locality 14 : 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 0A 10 \
+ 16 17 18 19
+[0020] Locality 15 : 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 10 0A \
+ 15 16 17 18
+[0020] Locality 16 : 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 \
+ 0A 10 16 17
+[0020] Locality 17 : 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 \
+ 10 0A 15 16
+[0020] Locality 18 : 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 \
+ 16 15 0A 10
+[0020] Locality 19 : 27 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 \
+ 17 16 10 0A
diff --git a/platforms/rtsm_ve-aemv8a.acpi/spmi.asl b/platforms/rtsm_ve-aemv8a.acpi/spmi.asl
new file mode 100644
index 0000000..8793979
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/spmi.asl
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org
+ *
+ * [SPMI] Server Platform Management Interface Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "SPMI"
+[0004] Table Length : 00000041
+[0001] Revision : 04
+[0001] Checksum : ED
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0001] Interface Type : 00
+[0001] Reserved : 00
+[0002] IPMI Spec Version : 0000
+[0001] Interrupt Type : 00
+[0001] GPE Number : 00
+[0001] Reserved : 00
+[0001] PCI Device Flag : 00
+[0004] Interrupt : 00000000
+
+[0012] IPMI Register : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 01 [Byte Access:8]
+[0008] Address : 0000000000000000
+
+[0001] PCI Segment : 00
+[0001] PCI Bus : 00
+[0001] PCI Device : 00
+[0001] PCI Function : 00
+[0001] Reserved : 00
diff --git a/platforms/rtsm_ve-aemv8a.acpi/srat.asl b/platforms/rtsm_ve-aemv8a.acpi/srat.asl
new file mode 100644
index 0000000..c525c89
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/srat.asl
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [SRAT] System Resource Affinity Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "SRAT"
+[0004] Table Length : 00000080
+[0001] Revision : 03
+[0001] Checksum : 5A
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Table Revision : 00000001
+[0008] Reserved : 0000000000000000
+
+[0001] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[0001] Length : 10
+
+[0001] Proximity Domain Low(8) : 00
+[0001] Apic ID : 00
+[0004] Flags (decoded below) : 00000001
+ Enabled : 1
+[0001] Local Sapic EID : 00
+[0003] Proximity Domain High(24) : 000000
+[0004] Reserved : 00000000
+
+[0001] Subtable Type : 01 [Memory Affinity]
+[0001] Length : 28
+
+[0004] Proximity Domain : 00000000
+[0002] Reserved1 : 0000
+[0008] Base Address : 0000000000000000
+[0008] Address Length : 000000000009FC00
+[0004] Reserved2 : 00000000
+[0004] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0008] Reserved3 : 0000000000000000
+
+[0001] Subtable Type : 02 [Processor Local x2APIC Affinity]
+[0001] Length : 18
+
+[0002] Reserved1 : 0000
+[0004] Proximity Domain : 00000000
+[0004] Apic ID : 00000000
+[0004] Flags (decoded below) : 00000001
+ Enabled : 1
+[0004] Clock Domain : 00000000
+[0004] Reserved2 : 00000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl b/platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl
new file mode 100644
index 0000000..c13ceef
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [SSDT] Description of the armv8 VE Model
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+DefinitionBlock (
+ "ssdt0.aml", // output filename
+ "SSDT", // table signature
+ 2, // SSDT compliance revision
+ "LINARO", // OEM ID
+ "RTSMVEV8", // table ID
+ 0x00000001) // OEM revision
+{
+}
diff --git a/platforms/rtsm_ve-aemv8a.acpi/tpm2.asl b/platforms/rtsm_ve-aemv8a.acpi/tpm2.asl
new file mode 100644
index 0000000..c88eb2c
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/tpm2.asl
@@ -0,0 +1,22 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [TPM2] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "TPM2" [Trusted Platform Module hardware interface table]
+[0004] Table Length : 00000034
+[0001] Revision : 03
+[0001] Checksum : 42
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20121114
+
+[0004] Flags : 00000000
+[0008] Control Address : 0011223344556677
+[0004] Start Method : 00000001
diff --git a/platforms/rtsm_ve-aemv8a.acpi/uefi.asl b/platforms/rtsm_ve-aemv8a.acpi/uefi.asl
new file mode 100644
index 0000000..2b927d7
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/uefi.asl
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [UEFI] UEFI Boot Optimization Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "UEFI"
+[0004] Table Length : 00000036
+[0001] Revision : 01
+[0001] Checksum : 9B
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0016] UUID Identifier : 03020100-0504-0706-0809-0A0B0C0D0E0F
+[0002] Data Offset : 0000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/xsdt.asl b/platforms/rtsm_ve-aemv8a.acpi/xsdt.asl
new file mode 100644
index 0000000..d935006
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/xsdt.asl
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [XSDT] Extended System Description Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "XSDT"
+[0004] Table Length : 00000064
+[0001] Revision : 01
+[0001] Checksum : 8B
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000014
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0008] ACPI Table Address 0 : 0000000000000010
+[0008] ACPI Table Address 0 : 0000000000000020
+[0008] ACPI Table Address 0 : 0000000000000030
+[0008] ACPI Table Address 0 : 0000000000000040
+[0008] ACPI Table Address 0 : 0000000000000050
+[0008] ACPI Table Address 0 : 0000000000000060
+[0008] ACPI Table Address 0 : 0000000000000070
+[0008] ACPI Table Address 0 : 0000000000000080
+[0008] ACPI Table Address 0 : 0000000000000090
+[0008] ACPI Table Address 0 : 00000000000000A0
+[0008] ACPI Table Address 0 : 00000000000000B0
+[0008] ACPI Table Address 0 : 00000000000000C0
+[0008] ACPI Table Address 0 : 00000000000000D0
+[0008] ACPI Table Address 0 : 00000000000000E0
+[0008] ACPI Table Address 0 : 00000000000000F0
+[0008] ACPI Table Address 0 : 0000000000000100
+[0008] ACPI Table Address 0 : 0000000000000110
+[0008] ACPI Table Address 0 : 0000000000000120
+[0008] ACPI Table Address 0 : 0000000000000130
+[0008] ACPI Table Address 0 : 0000000000000140
--
1.8.3.1
11 years, 8 months
- 2
- 1
[PATCH 0/3] Interrupt priority patch set
by Tomasz Nowicki
ACPI spec is x86 oriented thus it use NMI for error reporting as low latency
error signalling way. Fast response to error occurrence is what ARM trying to
satisfy using interrupt prioritization since there is no NMI direct equivalent
for ARM architecture.
Patch set are divided into three step:
1. Create generic code responsible for setting interrupt priority.
2. Use it in interrupt setup.
3. Example of interrupt controller priority mapping for GIC platform dependent
code.
Patch set tries to meet requirements like:
- not breaking existing code
- easy to expand to new priority levels
- easy to map generic priority levels to platform dependent priority values
See commit logs for more detailed explanation.
11 years, 8 months
- 3
- 9
[PATCH] cab: add a gitignore for binary result
by Graeme Gregory
Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org>
---
tools/cab/.gitignore | 2 ++
1 file changed, 2 insertions(+)
create mode 100644 tools/cab/.gitignore
diff --git a/tools/cab/.gitignore b/tools/cab/.gitignore
new file mode 100644
index 0000000..ead9b1c
--- /dev/null
+++ b/tools/cab/.gitignore
@@ -0,0 +1,2 @@
+cab
+
--
1.8.3.1
11 years, 8 months
- 2
- 1
[PATCH 0/3] Interrupt priority patch set
by Tomasz Nowicki
ACPI spec is x86 oriented thus it use NMI for error reporting as low latency
error signalling way. Fast response to error occurrance is what ARM trying to
satisfy using interrupt prioritization since there is no NMI direct equivalent
for ARM architecture.
Patch set are divided into three step:
1. Create generic code responsible for setting interrupt priority.
2. Use it in interrupt setup.
3. Example of interrupt controller priority mapping for GIC platform dependent
code.
Patch set tries to meet requirements like:
- not breaking existing code
- easy to expand to new priority levels
- easy to map generic priority levels to platform dependent priority values
See commit logs for more detailed explanation.
11 years, 8 months
- 3
- 6
[PATCH v2][acpi-asl] cab (check-ACPI-blob): new tool that looks for errors in an ACPI blob.
by al.stone＠linaro.org
From: Al Stone <ahs3(a)redhat.com>
While trying to hunt down what appeared to be structural errors in
an ACPI blob, I got tired of double checking pointers and load addresses
by hand (and having to double check my lousy arithmetic). So, cab
will search a blob for tables using brute force to determine where
tables actually are, and then compare those locations with where all
the table pointers say they should be, reporting any discrepancies
found. Cab will also double check all table headers looking for
invalid checksums, and table revision levels older than current
ACPI 5.0 spec dictates.
If you can think of additional checks on tables, please add them.
Changes from v1:
-- Clean up whitespace issues found by checkpatch
Signed-off-by: Al Stone <al.stone(a)linaro.org>
---
Makefile | 7 +-
tools/cab/Makefile | 8 +
tools/cab/cab.c | 650 +++++++++++++++++++++++++++++++++++++++++++++++++++++
tools/cab/cab.h | 169 ++++++++++++++
4 files changed, 833 insertions(+), 1 deletion(-)
create mode 100644 tools/cab/Makefile
create mode 100644 tools/cab/cab.c
create mode 100644 tools/cab/cab.h
diff --git a/Makefile b/Makefile
index e82376d..ef63965 100644
--- a/Makefile
+++ b/Makefile
@@ -1,14 +1,19 @@
MABDIR := tools/mab/
+CABDIR := tools/cab/
PLATDIR := platforms/
-%.acpi : $(MABDIR)/mab
+%.acpi : $(MABDIR)/mab $(CABDIR)/cab
make MAB=$(CURDIR)/$(MABDIR)/mab PADDR=$(PADDR) -C $(PLATDIR) $@
$(MABDIR)/mab : FORCE
make -C $(MABDIR)
+$(CABDIR)/cab : FORCE
+ make -C $(CABDIR)
+
clean :
make -C $(MABDIR) clean
+ make -C $(CABDIR) clean
make -C $(PLATDIR) clean
FORCE :
diff --git a/tools/cab/Makefile b/tools/cab/Makefile
new file mode 100644
index 0000000..7d86b59
--- /dev/null
+++ b/tools/cab/Makefile
@@ -0,0 +1,8 @@
+CFLAGS := -g
+
+cab : cab.h cab.c
+ $(CC) $(CFLAGS) -o cab cab.c
+
+clean :
+ -rm -f cab cab.o
+
diff --git a/tools/cab/cab.c b/tools/cab/cab.c
new file mode 100644
index 0000000..ebf5a83
--- /dev/null
+++ b/tools/cab/cab.c
@@ -0,0 +1,652 @@
+/*
+ * cab.c: main program for the tool to Check A Blob of ACPI tables
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file "COPYING" in the main directory of this
+ * archive for more details.
+ *
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * NB: all values are assumed to be little-endian in the blob.
+ *
+ */
+
+#include "cab.h"
+
+#include <sys/queue.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/mman.h>
+
+#include <ctype.h>
+#include <endian.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <libgen.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+int passed;
+int failed;
+
+void usage(void)
+{
+ printf("%s %s\n", PROGNAME, VERSION);
+ printf("usage: %s -b <blob> -p <paddr> [-q]\n", PROGNAME);
+ printf("\n");
+ printf(" -b <blob> => file name of input ACPI blob\n");
+ printf(" -p <paddr> => physical address used in relocation\n");
+ printf(" -q => if given, supress output\n");
+}
+
+int get_file_size(char *fname)
+{
+ struct stat buf;
+ int err;
+
+ err = stat(fname, &buf);
+ if (err)
+ printf("? cannot stat %s (%d)\n", fname, err);
+ return (err == 0 ? buf.st_size : 0);
+}
+
+int valid_sig(char *sig)
+{
+ char **p;
+
+ p = known_sigs;
+ while (*p != NULL) {
+ if (strncmp(*p, sig, strlen(*p)) == 0)
+ return 1;
+ p++;
+ }
+ return 0;
+}
+
+struct table *build_table_entry(unsigned char *buf)
+{
+ struct table *tmp;
+ const int RSDP_NUDGE = 3;
+ int len;
+
+ tmp = (struct table *)malloc(sizeof(struct table));
+ if (tmp != NULL) {
+ memset(tmp, 0, sizeof(struct table));
+
+ /* fill in the struct */
+ len = SIG_LENGTH + 1;
+ if (strncmp(buf, SIG_RSDP, SIG_LENGTH + RSDP_NUDGE) == 0)
+ len += RSDP_NUDGE;
+ tmp->signature = (char *)malloc(len);
+ memset(tmp->signature, 0, len);
+ memcpy(tmp->signature, buf, len - 1);
+
+ LIST_INSERT_HEAD(&thead, tmp, tables);
+ }
+
+ return tmp;
+}
+
+struct table *find_table(char *sig)
+{
+ struct table *np;
+
+ LIST_FOREACH(np, &thead, tables) {
+ if (strncmp(np->signature, sig, strlen(np->signature)) == 0)
+ return np;
+ }
+ return NULL;
+}
+
+struct known_table_info *find_known_table_info(char *sig)
+{
+ struct known_table_info *np;
+
+ for (np = known_info; np->signature != NULL; np++) {
+ if (strncmp(np->signature, sig, strlen(np->signature)) == 0)
+ return np;
+ }
+ return NULL;
+}
+
+int verify_checksum(unsigned char *start, int offset, int len)
+{
+ uint8_t newsum, oldsum;
+ uint8_t *p;
+ uint8_t old_cksum, cksum;
+
+ old_cksum = start[offset];
+ cksum = old_cksum;
+ newsum = 0;
+ for (p = (uint8_t *)start; p < (uint8_t *)(start + len); p++)
+ newsum += *p;
+
+ oldsum = cksum;
+ newsum = (uint8_t)(newsum - oldsum);
+
+ cksum = (uint8_t)(0 - newsum);
+
+ return (old_cksum == cksum ? PASS : FAIL);
+}
+
+int verify_revision(unsigned char *r, int min)
+{
+ return (*(uint8_t *)r >= min ? PASS : FAIL);
+}
+
+void presult(int res, char *topic)
+{
+ if (res != 0)
+ passed++;
+ else
+ failed++;
+ if (res >= 0)
+ printf("[%4s] %s\n", (res != 0) ? "PASS" : "FAIL", topic);
+ else
+ printf("[%4s] %s\n", "INFO", topic);
+}
+
+void check_blob_header(unsigned char *blob)
+{
+ int res;
+
+ printf("\nchecking blob header...\n");
+ res = strncmp(blob, BLOB_MAGIC, BLOB_MAGIC_SIZE);
+ res = (res == 0 ? PASS : FAIL);
+ presult(res, "blob magic number is correct");
+}
+
+void check_table_header(char *name, unsigned char *loc)
+{
+ const int CHECKSUM_OFFSET = 9;
+ const int CREATOR_ID_OFFSET = 28;
+ const int CREATOR_ID_LEN = 4;
+ const int CREATOR_REV_OFFSET = 32;
+ const int CREATOR_REV_LEN = 4;
+ const int OEMID_OFFSET = 10;
+ const int OEMID_LEN = 6;
+ const int REVISION_OFFSET = 8;
+
+ struct known_table_info *kp;
+ char buf[MAX_LINE];
+ int res;
+ int offset;
+ uint32_t len;
+ int min;
+
+ /* valid signature? */
+ kp = find_known_table_info(name);
+ res = (kp ? PASS : FAIL);
+ memset(buf, 0, MAX_LINE);
+ sprintf(buf, "%s: signature is correct", name);
+ presult(res, buf);
+
+ if (!kp) {
+ printf("? %s is an unknown table\n", name);
+ return;
+ }
+
+ /* possibly usable length? */
+ len = *(uint32_t *)(loc + TABLE_LEN_OFFSET);
+ res = PASS;
+ if ((len <= 0) || (len < MIN_TABLE_LENGTH))
+ res = FAIL;
+ memset(buf, 0, MAX_LINE);
+ sprintf(buf, "%s: table length is reasonable (%d)", name, len);
+ presult(res, buf);
+
+ /* valid checksum? */
+ res = verify_checksum(loc, CHECKSUM_OFFSET, len);
+ memset(buf, 0, MAX_LINE);
+ sprintf(buf, "%s: checksum is correct", name);
+ presult(res, buf);
+
+ /* valid revision number? */
+ res = verify_revision(loc + REVISION_OFFSET, kp->min_revision);
+ memset(buf, 0, MAX_LINE);
+ sprintf(buf, "%s: minimum revision is correct", name);
+ presult(res, buf);
+
+ /* non-empty OEMID field? */
+ res = (loc[OEMID_OFFSET] != 0 ? PASS : FAIL);
+ memset(buf, 0, MAX_LINE);
+ sprintf(buf, "%s: there is an OEMID (", name);
+ strncat(buf, (unsigned char *)(loc + OEMID_OFFSET), OEMID_LEN);
+ strncat(buf, ")", 1);
+ presult(res, buf);
+
+ /* non-empty CreatorID field? */
+ res = (loc[CREATOR_ID_OFFSET] != 0 ? PASS : FAIL);
+ memset(buf, 0, MAX_LINE);
+ sprintf(buf, "%s: there is a CreatorID", name);
+ presult(res, buf);
+
+ /* non-empty CreatorRevision field? */
+ res = (loc[CREATOR_REV_OFFSET] != 0 ? PASS : FAIL);
+ memset(buf, 0, MAX_LINE);
+ sprintf(buf, "%s: there is a CreatorRevision", name);
+ presult(res, buf);
+}
+
+void check_first_table_is_rsdp(unsigned char *blob)
+{
+ int res;
+
+ res = strncmp(blob + BLOB_HEADER_SIZE, SIG_RSDP, strlen(SIG_RSDP));
+ res = (res == 0 ? PASS : FAIL);
+ presult(res, "first table has RSDP signature");
+}
+
+void check_rsdp(unsigned char *blob)
+{
+ const int RSDP_FIRST_CKSUM_OFFSET = 8;
+ const int RSDP_FIRST_CKSUM_LEN = 20;
+ const int RSDP_SECOND_CKSUM_OFFSET = 32;
+ const int RSDP_SECOND_CKSUM_LEN = 36;
+ const int RSDP_RSDT_ADDR_OFFSET = 16;
+
+ unsigned char *ptr;
+ int res;
+ uint32_t rsdt_addr;
+
+ ptr = blob + BLOB_HEADER_SIZE;
+ printf("\nchecking RSDP...\n");
+ check_first_table_is_rsdp(blob);
+
+ res = verify_checksum(ptr, RSDP_FIRST_CKSUM_OFFSET,
+ RSDP_FIRST_CKSUM_LEN);
+ presult(res, "first RSDP checksum verified");
+
+ res = verify_checksum(ptr, RSDP_SECOND_CKSUM_OFFSET,
+ RSDP_SECOND_CKSUM_LEN);
+ presult(res, "second RSDP checksum verified");
+
+ rsdt_addr = *(uint32_t *)(ptr + RSDP_RSDT_ADDR_OFFSET);
+ res = (rsdt_addr == 0) ? PASS : FAIL;
+ presult(res, "RSDT address is null");
+}
+
+void find_all_tables(unsigned char *blob, int size, int base_addr)
+{
+ struct table *tp;
+ unsigned char *p;
+ int offset;
+ int delta;
+
+ /* this assumes that all signatures and lengths are correct */
+ printf("\nscanning for tables...\n");
+
+ p = blob + BLOB_HEADER_SIZE;
+ offset = (int)(p - blob);
+
+ while (offset + SIG_LENGTH < size) {
+ if (valid_sig(p)) {
+ tp = build_table_entry(p);
+ if (tp) {
+ delta = TABLE_LEN_OFFSET;
+ if (strcmp(tp->signature, SIG_RSDP) == 0)
+ delta = RSDP_LEN_OFFSET;
+ tp->len = *(uint32_t *)(p + delta);
+ tp->offset = offset;
+ tp->paddr = base_addr + offset;
+
+ offset += *(uint32_t *)(p + delta);
+ p += tp->len;
+ } else {
+ printf("? no room for building a table\n");
+ exit(1);
+ }
+ } else {
+ /* skip forward until we find something; a table
+ * could have been moved to the next page boundary */
+ while (offset + SIG_LENGTH < size) {
+ p++;
+ offset++;
+ if (isalpha(*p) && valid_sig(p))
+ break;
+ }
+ }
+ }
+}
+
+void check_rsdp_relocs(unsigned char *blob, int size, uint64_t paddr)
+{
+ const int RSDT_ADDR_OFFSET = 16;
+ const int XSDT_ADDR_OFFSET = 24;
+
+ struct table *np, *xp;
+ int res;
+ uint32_t rsdt_addr;
+ uint64_t xsdt_addr;
+
+ printf("\nchecking RSDP relocations...\n");
+
+ res = FAIL;
+ np = find_table(SIG_RSDP);
+ if (np) {
+ np->ref_cnt++;
+
+ rsdt_addr = *(uint32_t *)(blob + np->offset + RSDT_ADDR_OFFSET);
+ res = (rsdt_addr == 0) ? PASS : FAIL;
+ presult(res, "RSDP has null RSDT pointer");
+
+ xsdt_addr = *(uint32_t *)(blob + np->offset + XSDT_ADDR_OFFSET);
+ xp = find_table(SIG_XSDT);
+ if (xp) {
+ xp->ref_cnt++;
+ if ((xsdt_addr == xp->paddr) &&
+ (strncmp(blob + xp->offset, SIG_XSDT,
+ strlen(xp->signature)) == 0))
+ res = PASS;
+ }
+ presult(res, "RSDP has correct XSDT pointer");
+ } else {
+ res = FAIL;
+ presult(res, "RSDP has null RSDT pointer");
+ presult(res, "RSDP has correct XSDT pointer");
+ }
+}
+
+void check_xsdt_relocs(unsigned char *blob, int size, uint64_t paddr)
+{
+ const int XSDT_ENTRY_START = 36;
+ const int XSDT_ENTRY_SIZE = 8;
+
+ struct table *np, *xp;
+ int res;
+ int cnt;
+ int ii;
+ int offset;
+ uint32_t len;
+ uint64_t *tpaddr;
+ char buf[MAX_LINE];
+
+ printf("\nchecking XSDT relocations...\n");
+
+ res = FAIL;
+ np = find_table(SIG_XSDT);
+ if (np) {
+ len = *(uint32_t *)(blob + np->offset + TABLE_LEN_OFFSET);
+ cnt = (len - XSDT_ENTRY_START) / XSDT_ENTRY_SIZE;
+ tpaddr = (uint64_t *)(blob + np->offset + XSDT_ENTRY_START);
+ if (len < 1) {
+ printf("? XSDT can not have an empty list\n");
+ exit(1);
+ }
+
+ /* first entry needs to be the FACP (aka FADT) */
+ offset = (*tpaddr - paddr);
+ if (strncmp(blob + offset, SIG_FACP, strlen(SIG_FACP)) == 0)
+ res = PASS;
+ presult(res, "first XSDT entry points to the FADT (aka FACP)");
+
+ /* verify all the relocations, best we can */
+ for (ii = 0; ii < cnt; ii++, tpaddr++) {
+ offset = (*tpaddr - paddr);
+ res = FAIL;
+ if (valid_sig(blob + offset)) {
+ xp = find_table(blob + offset);
+ if (xp) {
+ xp->ref_cnt++;
+ if ((*tpaddr == xp->paddr) &&
+ (strncmp(blob + xp->offset,
+ blob + offset,
+ strlen(xp->signature)) == 0))
+ res = PASS;
+ memset(buf, 0, MAX_LINE);
+ sprintf(buf,
+ "XSDT has correct %s pointer",
+ xp->signature);
+ presult(res, buf);
+ } else {
+ memset(buf, 0, MAX_LINE);
+ sprintf(buf,
+ "XSDT entry %d does not point to a valid table",
+ ii);
+ presult(res, buf);
+ }
+ }
+ }
+ } else {
+ printf("? XSDT can not be found in table list\n");
+ exit(1);
+ }
+}
+
+void check_fadt_relocs(unsigned char *blob, int size, uint64_t paddr)
+{
+ const int FWCTL_OFFSET = 36;
+ const int DSDT_OFFSET = 40;
+ const int XFWCTL_OFFSET = 132;
+ const int XDSDT_OFFSET = 140;
+
+ struct table *np, *xp;
+ uint32_t fwctl, dsdt;
+ uint64_t xfwctl, xdsdt;
+ uint64_t tpaddr;
+ int res;
+ int offset;
+
+ printf("\nchecking FADT relocations...\n");
+ np = find_table(SIG_FACP);
+ if (np) {
+ fwctl = *(uint32_t *)(blob + np->offset + FWCTL_OFFSET);
+ xfwctl = *(uint64_t *)(blob + np->offset + XFWCTL_OFFSET);
+ res = FAIL;
+ if ((fwctl == 0 && xfwctl == 0) || /* no FACS is okay */
+ (fwctl == 0 && xfwctl != 0) ||
+ (fwctl != 0 && xfwctl == 0))
+ res = PASS;
+ presult(res, "FADT has a proper 32-bit FACS pointer");
+ presult(res, "FADT has a proper 64-bit FACS pointer");
+ if (fwctl != 0 && xfwctl != 0)
+ presult(INFO,
+ "both fields have been set, not just one");
+
+ if (fwctl != 0 || xfwctl != 0) {
+ tpaddr = (fwctl == 0) ? xfwctl : fwctl;
+ offset = tpaddr - paddr;
+
+ xp = find_table(SIG_FACS);
+ if (xp) {
+ xp->ref_cnt++;
+ res = FAIL;
+ if ((tpaddr == xp->paddr) &&
+ (strncmp(blob + xp->offset,
+ blob + offset,
+ strlen(xp->signature)) == 0))
+ res = PASS;
+ presult(res, "FADT has correct FACS pointer");
+
+ } else {
+ printf("? FADT refers to an FACS but ");
+ printf("there is no such table\n");
+ exit(1);
+ }
+ }
+
+ dsdt = *(uint32_t *)(blob + np->offset + DSDT_OFFSET);
+ xdsdt = *(uint64_t *)(blob + np->offset + XDSDT_OFFSET);
+ res = FAIL;
+ if ((dsdt == 0 && xdsdt != 0) || /* must have a DSDT */
+ (dsdt != 0 && xdsdt == 0))
+ res = PASS;
+ presult(res, "FADT has a proper 32-bit DSDT pointer");
+ presult(res, "FADT has a proper 64-bit DSDT pointer");
+ if (dsdt != 0 && xdsdt != 0)
+ presult(INFO,
+ "both fields have been set, not just one");
+
+ if (dsdt != 0 || xdsdt != 0) {
+ tpaddr = (dsdt == 0) ? xdsdt : dsdt;
+ offset = tpaddr - paddr;
+
+ xp = find_table(SIG_DSDT);
+ if (xp) {
+ xp->ref_cnt++;
+ res = FAIL;
+ if ((tpaddr == xp->paddr) &&
+ (strncmp(blob + xp->offset,
+ blob + offset,
+ strlen(xp->signature)) == 0))
+ res = PASS;
+ presult(res, "FADT has correct DSDT pointer");
+
+ } else {
+ printf("? FADT refers to a DSDT but ");
+ printf("there is no such table\n");
+ exit(1);
+ }
+ }
+
+ } else {
+ printf("? FADT (aka FACP) can not be found in table list\n");
+ exit(1);
+ }
+}
+
+void check_ref_cnts(void)
+{
+ struct table *np;
+ int res;
+ char buf[MAX_LINE];
+
+ printf("\nchecking references to tables...\n");
+ LIST_FOREACH(np, &thead, tables) {
+ memset(buf, 0, MAX_LINE);
+ sprintf(buf, "%s referenced only once", np->signature);
+ res = (np->ref_cnt == 1) ? PASS : FAIL;
+ presult(res, buf);
+ }
+
+}
+
+void check_relocations(unsigned char *blob, int size, uint64_t paddr)
+{
+ check_rsdp_relocs(blob, size, paddr);
+ check_xsdt_relocs(blob, size, paddr);
+ check_fadt_relocs(blob, size, paddr);
+ check_ref_cnts();
+}
+
+int main(int argc, char *argv[])
+{
+ int ii, jj;
+ int offset;
+ int delta;
+ int size;
+ int fd;
+ unsigned char *blob;
+ char *acpi_blob_name;
+ char *paddr_cmd;
+ uint64_t paddr = 0;
+ char sig[SIG_LENGTH];
+ struct table *np;
+ int opt;
+ int quiet;
+
+ /* parameter handling */
+ acpi_blob_name = NULL;
+ paddr_cmd = NULL;
+ quiet = 0;
+ passed = 0;
+ failed = 0;
+
+ while ((opt = getopt(argc, argv, "b:p:q")) != EOF) {
+ switch (opt) {
+ case 'b':
+ acpi_blob_name = optarg;
+ break;
+ case 'p':
+ paddr_cmd = optarg;
+ break;
+ case 'q':
+ quiet = 1;
+ break;
+ default:
+ usage();
+ return 1;
+ }
+ }
+
+ if (!quiet)
+ printf("%s %s\n", PROGNAME, VERSION);
+
+ if ((argc > (optind + 1)) || (acpi_blob_name == NULL)) {
+ printf("? missing a parameter value\n");
+ usage();
+ return 1;
+ }
+ if (paddr_cmd) {
+ errno = 0;
+ paddr = strtoull(paddr_cmd, NULL, 0);
+ if (errno) {
+ printf("invalid physical address given\n");
+ return 1;
+ } else {
+ printf("assume blob was relocated to 0x%llx\n", paddr);
+ }
+ } else {
+ printf("? missing required physical address parameter\n");
+ usage();
+ return 1;
+ }
+
+ size = get_file_size(acpi_blob_name);
+ if (!size) {
+ printf("? blob cannot be zero length\n");
+ exit(1);
+ }
+
+ fd = open(acpi_blob_name, O_RDONLY);
+ if (fd < 0) {
+ perror(PROGNAME);
+ exit(1);
+ }
+ blob = mmap(NULL, size, PROT_READ, MAP_PRIVATE, fd , 0);
+ if (blob == MAP_FAILED) {
+ perror(PROGNAME);
+ exit(1);
+ }
+
+ LIST_INIT(&thead);
+
+ check_blob_header(blob);
+ check_rsdp(blob);
+
+ find_all_tables(blob, size, paddr);
+ if (!quiet) {
+ printf("found the following tables....\n");
+ ii = 0;
+ LIST_FOREACH(np, &thead, tables) {
+ printf(
+ "[%03d] %4s: %d bytes @ 0x%08x, loads @ 0x%016x\n",
+ ii, np->signature, np->len, np->offset, np->paddr);
+ ii++;
+ }
+ }
+ LIST_FOREACH(np, &thead, tables) {
+ if ((strncmp(np->signature, SIG_RSDP,
+ strlen(np->signature) != 0)) &&
+ (strncmp(np->signature, SIG_FACS,
+ strlen(np->signature) != 0))) {
+ printf("\nchecking header of %s...\n", np->signature);
+ check_table_header(np->signature, blob + np->offset);
+ }
+ }
+
+ check_relocations(blob, size, paddr);
+
+ printf("\nTotal tests: %d\n", passed + failed);
+ printf("Passed: %d\n", passed);
+ printf("Failed: %d\n", failed);
+ printf("Success rate: %0.1f%\n",
+ (100.0 * (float)passed) / (float)(passed + failed));
+
+ munmap(blob, size);
+
+ return (failed > 0) ? 1 : 0;
+}
diff --git a/tools/cab/cab.h b/tools/cab/cab.h
new file mode 100644
index 0000000..4512757
--- /dev/null
+++ b/tools/cab/cab.h
@@ -0,0 +1,169 @@
+#ifndef _CAB_H
+#define _CAB_H
+/*
+ * cab.h: tool to Check A Blob of ACPI tables
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file "COPYING" in the main directory of this
+ * archive for more details.
+ *
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * NB: all values are assumed to be little-endian in the blob.
+ *
+ */
+
+#include <stdint.h>
+#include <string.h>
+
+#include <sys/queue.h>
+
+/* VERSION a.b.c = <ACPI standard>.<functionality changes>.<bug fixes> */
+const char VERSION[] = { "5.0~3.1" };
+const char PROGNAME[] = { "cab" };
+
+#define PASS 1
+#define FAIL 0
+#define INFO (-1)
+
+#define BLOB_HEADER_SIZE 8
+#define BLOB_MAGIC "ACPI"
+#define BLOB_MAGIC_SIZE 4
+#define MAX_LINE 1024
+#define MIN_TABLE_LENGTH 36
+#define NOT_REQUIRED 0
+#define REQUIRED 1
+#define RSDP_LEN_OFFSET 20
+#define SIG_LENGTH 4
+#define TABLE_LEN_OFFSET 4
+
+#define SIG_APIC "APIC"
+#define SIG_BERT "BERT"
+#define SIG_CPEP "CPEP"
+#define SIG_DSDT "DSDT"
+#define SIG_ECDT "ECDT"
+#define SIG_EINJ "EINJ"
+#define SIG_ERST "ERST"
+#define SIG_FACP "FACP"
+#define SIG_FACS "FACS"
+#define SIG_FPDT "FPDT"
+#define SIG_GTDT "GTDT"
+#define SIG_HEST "HEST"
+#define SIG_MCFG "MCFG"
+#define SIG_MCHI "MCHI"
+#define SIG_MPST "MPST"
+#define SIG_MSCT "MSCT"
+#define SIG_OEM "OEM"
+#define SIG_PCCT "PCCT"
+#define SIG_PMTT "PMTT"
+#define SIG_RASF "RASF"
+#define SIG_RSDP "RSD PTR"
+#define SIG_RSDT "RSDT"
+#define SIG_SLIT "SLIT"
+#define SIG_SPMI "SPMI"
+#define SIG_SRAT "SRAT"
+#define SIG_SSDT "SSDT"
+#define SIG_UEFI "UEFI"
+#define SIG_XSDT "XSDT"
+
+struct known_table_info {
+ char *signature; /* table signature */
+ int min_revision; /* minimum allowed revision */
+};
+
+struct known_table_info known_info[] = {
+ { SIG_APIC, 3 },
+ { SIG_BERT, 1 },
+ { SIG_CPEP, 1 },
+ { SIG_DSDT, 2 },
+ { SIG_ECDT, 1 },
+ { SIG_EINJ, 1 },
+ { SIG_ERST, 1 },
+ { SIG_FACP, 5 },
+ { SIG_FACS, 5 },
+ { SIG_FPDT, 1 },
+ { SIG_GTDT, 1 },
+ { SIG_HEST, 1 },
+ { SIG_MCFG, 1 },
+ { SIG_MCHI, 1 },
+ { SIG_MPST, 1 },
+ { SIG_MSCT, 1 },
+ { SIG_OEM, 1 },
+ { SIG_PMTT, 1 },
+ { SIG_RASF, 1 },
+ { SIG_RSDP, 2 },
+ { SIG_RSDT, 1 },
+ { SIG_SLIT, 1 },
+ { SIG_SPMI, 1 },
+ { SIG_SRAT, 3 },
+ { SIG_SSDT, 2 },
+ { SIG_UEFI, 1 },
+ { SIG_XSDT, 1 },
+ { NULL, 0 }
+};
+
+char *known_sigs[] = {
+ "APIC",
+ "BERT",
+ "CPEP",
+ "DSDT",
+ "ECDT",
+ "EINJ",
+ "ERST",
+ "FACP",
+ "FACS",
+ "FPDT",
+ "GTDT",
+ "HEST",
+ "MCFG",
+ "MCHI",
+ "MPST",
+ "MSCT",
+ "OEM",
+ "PCCT",
+ "PMTT",
+ "RASF",
+ "RSD PTR",
+ "SLIT",
+ "SPMI",
+ "SRAT",
+ "SSDT",
+ "UEFI",
+ "XSDT",
+ NULL
+};
+
+LIST_HEAD(table_head, table) thead;
+struct table_head *theadp;
+
+struct table {
+ char *signature; /* an ACPI table name/signature */
+ int len; /* reported table length */
+ int offset; /* location in the blob */
+ uint64_t paddr; /* where it should live in RAM */
+ int ref_cnt; /* reference count */
+ LIST_ENTRY(table) tables;
+};
+
+
+struct table *build_table_entry(unsigned char *buf);
+void check_blob_header(unsigned char *blob);
+void check_fadt_relocs(unsigned char *blob, int size, uint64_t paddr);
+void check_first_table_is_rsdp(unsigned char *blob);
+void check_rsdp(unsigned char *blob);
+void check_ref_cnts(void);
+void check_relocations(unsigned char *blob, int size, uint64_t paddr);
+void check_rsdp_relocs(unsigned char *blob, int size, uint64_t paddr);
+void check_table_header(char *name, unsigned char *loc);
+void check_xsdt_relocs(unsigned char *blob, int size, uint64_t paddr);
+void find_all_tables(unsigned char *blob, int size, int base_addr);
+struct known_table_info *find_known_table_info(char *sig);
+struct table *find_table(char *sig);
+int get_file_size(char *fname);
+void usage(void);
+int valid_sig(char *sig);
+int verify_checksum(unsigned char *start, int offset, int len);
+int verify_revision(unsigned char *r, int min);
+void presult(int res, char *topic);
+
+#endif
--
1.8.3.1
11 years, 8 months
- 4
- 4
[PATCH][acpi-asl] ACPI: ARM: arndale: move definition of GPZ GPIO from DT to ACPI
by al.stone＠linaro.org
From: Al Stone <ahs3(a)redhat.com>
This is the first in a series to eventually convert all of the Arndale
GPIO controllers to ACPI. This is the proposed ACPI description meant
to match what is done in DT, but is very specific to the Samsung driver.
Signed-off-by: Al Stone <al.stone(a)linaro.org>
---
platforms/exynos5250-arndale.acpi/ssdt0.asl | 64 ++++++++++++++++++++++++++++-
1 file changed, 63 insertions(+), 1 deletion(-)
diff --git a/platforms/exynos5250-arndale.acpi/ssdt0.asl b/platforms/exynos5250-arndale.acpi/ssdt0.asl
index 69dce10..8b8efc7 100644
--- a/platforms/exynos5250-arndale.acpi/ssdt0.asl
+++ b/platforms/exynos5250-arndale.acpi/ssdt0.asl
@@ -12,6 +12,68 @@ DefinitionBlock (
2, // SSDT compliance revision
"LINARO", // OEM ID
"ARNDALE ", // table ID
- 0x00000001) // OEM revision
+ 0x00000003) // OEM revision
{
+ Scope (\_SB)
+ {
+ // Base Address: 0x03860000
+ Device (SPC3) // Samsung pin controller
+ {
+ Name (_HID, "LINA0002")
+ Name (_UID, 0x3)
+
+ Name (BNKS, 0x1) // number of pin banks
+ Name (NGRP, 0x1) // number of pin groups
+ Name (NFUN, 0x1) // number of pinmux functions
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ // Base address for the pin controller
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0x03860000,
+ 0x20)
+ })
+ Return (RBUF)
+ }
+
+ Device (GPZ) // GPIO chip GPZ -- first bank
+ {
+ Name (TAG, "gpz") // human-readable name
+ Name (BASE, 0x0) // base pin number
+ Name (NPIN, 0x7) // number of pins
+
+ // We need _CRS here in order to provide
+ // the actual registers for this part of
+ // the controller
+ Method (_CRS, 0x0, Serialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0x03860000,
+ 0x20)
+ })
+ Return (RBUF)
+ }
+ }
+
+ Device (I2S0) // First Pin Group
+ {
+ Name (NPIN, 0x7) // number of pins
+ Name (FUNC, 0x2) // function number
+ Name (PUD, 0x0) // direction
+ Name (DRV, 0x0) // drive
+ Method (PINS, 0x0, NotSerialized)
+ {
+ Return (Package () {
+ "gpz-0", "gpz-1", "gpz-2",
+ "gpz-3", "gpz-4", "gpz-5",
+ "gpz-6"
+ })
+ }
+ }
+ }
+ }
}
--
1.8.3.1
11 years, 8 months
- 1
- 0
[PATCH] ACPICA:enable 64bit build for aarch64 architecture
by naresh.bhat＠linaro.org
From: Naresh Bhat <naresh.bhat(a)linaro.org>
Signed-off-by: Naresh Bhat <naresh.bhat(a)linaro.org>
Enable 64 bit build for aarch64 architecture in ACPICA Linux
platform specific defines.
---
src/acpica/source/include/platform/aclinux.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/acpica/source/include/platform/aclinux.h b/src/acpica/source/include/platform/aclinux.h
index e561292..6b8b1ab 100644
--- a/src/acpica/source/include/platform/aclinux.h
+++ b/src/acpica/source/include/platform/aclinux.h
@@ -159,7 +159,7 @@
#define ACPI_FLUSH_CPU_CACHE()
#define ACPI_CAST_PTHREAD_T(pthread) ((ACPI_THREAD_ID) (pthread))
-#if defined(__ia64__) || defined(__x86_64__)
+#if defined(__ia64__) || defined(__x86_64__) || defined(__aarch64__)
#define ACPI_MACHINE_WIDTH 64
#define COMPILER_DEPENDENT_INT64 long
#define COMPILER_DEPENDENT_UINT64 unsigned long
--
1.7.9.5
11 years, 8 months
- 2
- 1
[PATCH 0/7 v2][acpi-asl] mab 0.28.1: fixes and new features
by al.stone＠linaro.org
From: Al Stone <ahs3(a)redhat.com>
While trying to figure out some problems I was having with my ACPI
blobs, I ran into several things that needed fixing in mab. Some of
these are innocuous, but some -- like using both 32- and 64-bit addresses
in the FACS, and the RSDP checksums -- are actually in violation of the
spec.
While I was there, I added a little more info in the verbose output,
and corrected what was being printed out.
The new feature is that one can now use -H to produce a blob that does
not have the header we've been using so far.
Changes from v1:
-- This time, I actually _remembered_ to run checkpatch, so cleaned
up the extra whitespace in patch 7/7.
Al Stone (7):
mab: Makefile needs to rebuild if .h changes and use CFLAGS properly
mab: use 32- or 64-bit FACS addresses in the FADT, not both
mab: set both checksums in the RSDP, not just one
mab: print out the correct offset in the blob
mab: add option to NOT use a blob header, if needed
mab: print out physical address when being verbose
mab: update Changelog and version number for this patch series
tools/mab/Changelog | 19 +++++++++
tools/mab/Makefile | 6 +--
tools/mab/mab.c | 109 +++++++++++++++++++++++++++++++---------------------
tools/mab/mab.h | 5 ++-
4 files changed, 91 insertions(+), 48 deletions(-)
--
1.8.3.1
11 years, 8 months
- 2
- 8
FYI //Fwd: ACPI vs Device Tree - moving forward
by Hanjun Guo
Hi,
Lots of people from different companies are concerned about ACPI vs FDT, not only Linaro,
This is a good news for us.
They will discuss it in person in New Orleans at Linux Plumber (September, 2013)
Al, Graeme, will you attend Linux Plumber next month？
Thanks
Hanjun
-------- Original Message --------
Subject: ACPI vs Device Tree - moving forward
Date: Tue, 20 Aug 2013 20:26:50 +0100
From: Matthew Garrett <mjg59(a)srcf.ucam.org>
To: <linux-kernel(a)vger.kernel.org>, <linux-acpi(a)vger.kernel.org>
CC: <linux(a)roeck-us.net>, <dvhart(a)linux.intel.com>, <hpa(a)zytor.com>, <linus.walleij(a)linaro.org>, <rjw(a)sisk.pl>
This conversation seems to have pretty much entirely ended up happening
on ksummit-discuss, which doesn't seem that useful. So let's have
another go with a wider audience (and where I don't have to sign up for
yet another mailing list...)
ACPI and DT overlap in that they both provide a mechanism for
enumerating non-enumerable devices, and both also provide a mechanism
for attaching additional configuration data to devices (which may or may
not be otherwise enumerable). There's a sufficient overlap in
functionality that at least one platform that's traditionally been
Device Tree (arm) is also adding support for ACPI - there's even
ACPI-based arm hardware on the market already.
Right now that's a problem for us. The same hardware may end up shipped
with either ACPI or DT-based firmware, and at the moment we'd need to
either write two drivers or one driver with two glue layers. This is
somewhat suboptimal.
The biggest difference between DT and ACPI is that DT is effectively a
somewhat structured mechanism for passing arbitrary data, while ACPI
tends (with exceptions) to provide standardised data. For instance, in
DT we might have:
sdhci@c8000000 {
status = "okay";
power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
keep-power-in-suspend;
};
In ACPI the normal way to handle this would be to have a GPIO operation
region that listed the GPIOs:
OperationRegion(GPO1, GeneralPurposeIO, 0, 1)
Field(GP01, ByteAcc, NoLock, Preserve)
{
Connection (GpioIo(Exclusive, PullUp,,,,,)
TG06, 1
}
And then an ACPI device:
Device (\_SB.SDHC)
{
Method (_PS0, 0, NotSerialized)
{
Store (1, TG06)
}
Method (_PS3, 0, NotSerialized)
{
Store (0, TG06)
}
}
with the ACPI core then executing these methods whenever a device is
powered up or down.
How can we unify these two different representations? The only terribly
plausible way of doing so seems to be to push that out to a helper
function and then have it handled as part of device runtime power
management, and just have the driver make pm_runtime_get() and _put()
calls.
So we can theoretically handle cases like power lines without /too/ much
trouble, while representing the same thing in either ACPI or DT. But we
have plenty of other data - in the case of SDHCI alone, there's the bus
width and potentially card detect and write protect gpio lines. These
can easily be represented in ACPI, but not in a terribly generic way. We
could easily add new functions to retrieve this information, but doing
this through the standards body is likely to prove tedious, especially
when new hardware types appear and we want to be able to ship support
pretty much immediately.
The other choice is to ignore most of the existing ACPI functionality
and just use it as a mechanism for providing additional metadata. Apple
already do this using the _DSM methods:
Method (_DSM, 4, NotSerialized)
{
Store (Package (0x07)
{
"refnum",
0x00,
"address",
0x39,
"device-id",
0x0cc8,
Buffer (0x01)
{
0x00
}
}, Local0)
DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
Return (Local0)
}
where the DTGP() method verifies that the caller passed in an
appropriate UUID and then hands back this buffer.
Putting all our existing DT metadata in there would be straightforward,
but we would then effectively just be using ACPI to repackage DT -
drivers would continue to make DT-specific calls in order to obtain the
information they need.
This seems like the least-effort approach, but it doesn't really solve
much. Any other OS on the same hardware is unlikely to use the DT data,
and if someone wants to run Linux on hardware that was intended for
another OS they're unlikely to have any DT data to use.
So while unifying this seems hugely desirable, right now it's not
incredibly obvious how we can actually achieve that. In some cases it's
easy to take DT information and rewrite it the ACPI way, but in others
we just don't seem to have the primitives we need for that. One approach
would be to work through the existing DT bindings documentation and see
what's missing from ACPI and work on adding it, but we'll still then
need helper functions that are able to obtain the same information from
either source.
In any case, it seems like this is something that should be discussed. A
bunch of people in the earlier discussion mentioned that they were going
to be in New Orleans, so I'd suggest that we arrange a time for
in-person discussion there. That should give us a solid basis for
further mailing list discussion, and then there'll be another
opportunity for discussion in Edinburgh.
--
Matthew Garrett | mjg59(a)srcf.ucam.org
--
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.
11 years, 8 months
- 2
- 1
[PATCH] Fix comments ARMv8 foundation acpi platform
by naresh.bhat＠linaro.org
From: Naresh Bhat <naresh.bhat(a)linaro.org>
Signed-off-by: Naresh Bhat <naresh.bhat(a)linaro.org>
Fix comments ARMv8 foundation acpi platform
---
platforms/foundation-v8.acpi/dsdt.asl | 2 +-
platforms/foundation-v8.acpi/ssdt0.asl | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/platforms/foundation-v8.acpi/dsdt.asl b/platforms/foundation-v8.acpi/dsdt.asl
index d1a9716..69f5884 100644
--- a/platforms/foundation-v8.acpi/dsdt.asl
+++ b/platforms/foundation-v8.acpi/dsdt.asl
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
*
- * [DSDT] Description of the Arndale board (exynos5250)
+ * [DSDT] Description of the ARMv8 foundation model
*
* This source is released under the terms of the GPLv2.
*/
diff --git a/platforms/foundation-v8.acpi/ssdt0.asl b/platforms/foundation-v8.acpi/ssdt0.asl
index 165c1ae..9796ebd 100644
--- a/platforms/foundation-v8.acpi/ssdt0.asl
+++ b/platforms/foundation-v8.acpi/ssdt0.asl
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
*
- * [SSDT] Description of the Arndale board (exynos5250) GPIO structure
+ * [SSDT] Description of the ARMv8 foundation model GPIO structure
*
* This source is released under the terms of the GPLv2.
*/
--
1.7.9.5
11 years, 8 months
- 2
- 1
[PATCH] Update comments under foundation-v8.acpi
by naresh.bhat＠linaro.org
From: Naresh Bhat <naresh.bhat(a)linaro.org>
Signed-off-by: Naresh Bhat <naresh.bhat(a)linaro.org>
Fix all the comments under foundation-v8.acpi platforms
---
platforms/foundation-v8.acpi/dsdt.asl | 2 +-
platforms/foundation-v8.acpi/ssdt0.asl | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/platforms/foundation-v8.acpi/dsdt.asl b/platforms/foundation-v8.acpi/dsdt.asl
index 6a5d1be..c5c692b 100644
--- a/platforms/foundation-v8.acpi/dsdt.asl
+++ b/platforms/foundation-v8.acpi/dsdt.asl
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
*
- * [DSDT] Description of the Arndale board (exynos5250)
+ * [DSDT] Description of the foundation-v8
*
* This source is released under the terms of the GPLv2.
*/
diff --git a/platforms/foundation-v8.acpi/ssdt0.asl b/platforms/foundation-v8.acpi/ssdt0.asl
index 165c1ae..11328f9 100644
--- a/platforms/foundation-v8.acpi/ssdt0.asl
+++ b/platforms/foundation-v8.acpi/ssdt0.asl
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
*
- * [SSDT] Description of the Arndale board (exynos5250) GPIO structure
+ * [SSDT] Description of the foundation-v8 GPIO structure
*
* This source is released under the terms of the GPLv2.
*/
--
1.7.9.5
11 years, 8 months
- 3
- 2
[PATCH] arm: setup: remove BOZO pfn_mapped handling
by Graeme Gregory
This is only required if we are doing initrd table overiding. This is
currently disabled for arm/arm64. Remove this as allowing initrd
overiding needs fuller re-work on these platforms anyway.
Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org>
---
arch/arm/kernel/setup.c | 13 -------------
1 file changed, 13 deletions(-)
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 168f7c5..da3d8df 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -62,19 +62,6 @@
#include "atags.h"
-/* BOZO: clears up the missing symbol during compile, but is this
- * the right way to handle it?
- */
-/*
- * end_pfn only includes RAM, while max_pfn_mapped includes all e820 entries.
- * The direct mapping extends to max_pfn_mapped, so that we can directly access
- * apertures, ACPI and other tables without having to play with fixmaps.
- */
-unsigned long max_low_pfn_mapped;
-unsigned long max_pfn_mapped;
-
-/* END BOZO */
-
#if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE)
char fpe_type[8];
--
1.7.10.4
11 years, 8 months
- 2
- 1
[PATCH] acpi: remove last trace of MAB from Kconfig
by Graeme Gregory
MAB is now moved to acpi-asl so remove it from Kconfig here.
Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org>
---
drivers/acpi/Kconfig | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig
index bd08033..85f774a 100644
--- a/drivers/acpi/Kconfig
+++ b/drivers/acpi/Kconfig
@@ -2,9 +2,6 @@
# ACPI Configuration
#
-config MAB
- bool
-
config ACPI_ARM
bool
@@ -13,7 +10,6 @@ menuconfig ACPI
depends on !IA64_HP_SIM
depends on ((IA64 || X86) && PCI) || (ARM || ARM64)
select PNP
- select MAB if (ARM || ARM64)
select ACPI_ARM if (ARM || ARM64)
default y if !(ARM || ARM64)
help
--
1.7.10.4
11 years, 8 months
- 2
- 1
[PATCH 1/3] x86 / ACPI: modify the stale comment for __acpi_map_table()
by Hanjun Guo
The comment for __acpi_map_table() is obvious wrong. In fact, after
commit 1c14fa49 (x86: use early_ioremap in __acpi_map_table), the
comment became stale, so remove it and add a new one.
Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org>
---
arch/x86/kernel/acpi/boot.c | 12 ++----------
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index 2627a81..665f857 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -141,16 +141,8 @@ static u32 irq_to_gsi(int irq)
}
/*
- * Temporarily use the virtual area starting from FIX_IO_APIC_BASE_END,
- * to map the target physical address. The problem is that set_fixmap()
- * provides a single page, and it is possible that the page is not
- * sufficient.
- * By using this area, we can map up to MAX_IO_APICS pages temporarily,
- * i.e. until the next __va_range() call.
- *
- * Important Safety Note: The fixed I/O APIC page numbers are *subtracted*
- * from the fixed base. That's why we start at FIX_IO_APIC_BASE_END and
- * count idx down while incrementing the phys address.
+ * __acpi_map_table() will be called before the memory allocation
+ * is ready, so call early_ioremap() to map tables.
*/
char *__init __acpi_map_table(unsigned long phys, unsigned long size)
{
--
1.7.9.5
11 years, 8 months
- 1
- 2
[PATCH][acpi-asl] cab (check-ACPI-blob): new tool that looks for errors in an ACPI blob.
by al.stone＠linaro.org
From: Al Stone <ahs3(a)redhat.com>
While trying to hunt down what appeared to be structural errors in
an ACPI blob, I got tired of double checking pointers and load addresses
by hand (and having to double check my lousy arithmetic). So, cab
will search a blob for tables using brute force to determine where
tables actually are, and then compare those locations with where all
the table pointers say they should be, reporting any discrepancies
found. Cab will also double check all table headers looking for
invalid checksums, and table revision levels older than current
ACPI 5.0 spec dictates.
If you can think of additional checks on tables, please add them.
Signed-off-by: Al Stone <al.stone(a)linaro.org>
---
Makefile | 7 +-
tools/cab/Makefile | 8 +
tools/cab/cab.c | 650 +++++++++++++++++++++++++++++++++++++++++++++++++++++
tools/cab/cab.h | 169 ++++++++++++++
4 files changed, 833 insertions(+), 1 deletion(-)
create mode 100644 tools/cab/Makefile
create mode 100644 tools/cab/cab.c
create mode 100644 tools/cab/cab.h
diff --git a/Makefile b/Makefile
index e82376d..ef63965 100644
--- a/Makefile
+++ b/Makefile
@@ -1,14 +1,19 @@
MABDIR := tools/mab/
+CABDIR := tools/cab/
PLATDIR := platforms/
-%.acpi : $(MABDIR)/mab
+%.acpi : $(MABDIR)/mab $(CABDIR)/cab
make MAB=$(CURDIR)/$(MABDIR)/mab PADDR=$(PADDR) -C $(PLATDIR) $@
$(MABDIR)/mab : FORCE
make -C $(MABDIR)
+$(CABDIR)/cab : FORCE
+ make -C $(CABDIR)
+
clean :
make -C $(MABDIR) clean
+ make -C $(CABDIR) clean
make -C $(PLATDIR) clean
FORCE :
diff --git a/tools/cab/Makefile b/tools/cab/Makefile
new file mode 100644
index 0000000..7d86b59
--- /dev/null
+++ b/tools/cab/Makefile
@@ -0,0 +1,8 @@
+CFLAGS := -g
+
+cab : cab.h cab.c
+ $(CC) $(CFLAGS) -o cab cab.c
+
+clean :
+ -rm -f cab cab.o
+
diff --git a/tools/cab/cab.c b/tools/cab/cab.c
new file mode 100644
index 0000000..ebf5a83
--- /dev/null
+++ b/tools/cab/cab.c
@@ -0,0 +1,650 @@
+/*
+ * cab.c: main program for the tool to Check A Blob of ACPI tables
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file "COPYING" in the main directory of this
+ * archive for more details.
+ *
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * NB: all values are assumed to be little-endian in the blob.
+ *
+ */
+
+#include "cab.h"
+
+#include <sys/queue.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/mman.h>
+
+#include <ctype.h>
+#include <endian.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <libgen.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+int passed = 0;
+int failed = 0;
+
+void usage(void)
+{
+ printf("%s %s\n", PROGNAME, VERSION);
+ printf("usage: %s -b <blob> -p <paddr> [-q]\n", PROGNAME);
+ printf("\n");
+ printf(" -b <blob> => file name of input ACPI blob\n");
+ printf(" -p <paddr> => physical address used in relocation\n");
+ printf(" -q => if given, supress output\n");
+}
+
+int get_file_size(char *fname)
+{
+ struct stat buf;
+ int err;
+
+ err = stat(fname, &buf);
+ if (err)
+ printf("? cannot stat %s (%d)\n", fname, err);
+ return (err == 0 ? buf.st_size : 0);
+}
+
+int valid_sig(char *sig)
+{
+ char **p;
+
+ p = known_sigs;
+ while (*p != NULL) {
+ if (strncmp(*p, sig, strlen(*p)) == 0)
+ return 1;
+ p++;
+ }
+ return 0;
+}
+
+struct table *build_table_entry(unsigned char *buf)
+{
+ struct table *tmp;
+ const int RSDP_NUDGE = 3;
+ int len;
+
+ tmp = (struct table *)malloc(sizeof(struct table));
+ if (tmp != NULL) {
+ memset(tmp, 0, sizeof(struct table));
+
+ /* fill in the struct */
+ len = SIG_LENGTH + 1;
+ if (strncmp(buf, SIG_RSDP, SIG_LENGTH + RSDP_NUDGE) == 0)
+ len += RSDP_NUDGE;
+ tmp->signature = (char *)malloc(len);
+ memset(tmp->signature, 0, len);
+ memcpy(tmp->signature, buf, len - 1);
+
+ LIST_INSERT_HEAD(&thead, tmp, tables);
+ }
+
+ return tmp;
+}
+
+struct table *find_table(char *sig)
+{
+ struct table *np;
+
+ LIST_FOREACH(np, &thead, tables) {
+ if (strncmp(np->signature, sig, strlen(np->signature)) == 0)
+ return np;
+ }
+ return NULL;
+}
+
+struct known_table_info *find_known_table_info(char *sig)
+{
+ struct known_table_info *np;
+
+ for (np = known_info; np->signature != NULL; np++) {
+ if (strncmp(np->signature, sig, strlen(np->signature)) == 0)
+ return np;
+ }
+ return NULL;
+}
+
+int verify_checksum(unsigned char *start, int offset, int len)
+{
+ uint8_t newsum, oldsum;
+ uint8_t *p;
+ uint8_t old_cksum, cksum;
+
+ old_cksum = start[offset];
+ cksum = old_cksum;
+ newsum = 0;
+ for (p = (uint8_t *)start; p < (uint8_t *)(start + len); p++)
+ newsum += *p;
+
+ oldsum = cksum;
+ newsum = (uint8_t)(newsum - oldsum);
+
+ cksum = (uint8_t)(0 - newsum);
+
+ return (old_cksum == cksum ? PASS : FAIL);
+}
+
+int verify_revision(unsigned char *r, int min)
+{
+ return (*(uint8_t *)r >= min ? PASS : FAIL);
+}
+
+void presult(int res, char *topic)
+{
+ if (res != 0)
+ passed++;
+ else
+ failed++;
+ if (res >= 0)
+ printf("[%4s] %s\n", (res != 0) ? "PASS" : "FAIL", topic);
+ else
+ printf("[%4s] %s\n", "INFO", topic);
+}
+
+void check_blob_header(unsigned char *blob)
+{
+ int res;
+
+ printf ("\nchecking blob header...\n");
+ res = strncmp(blob, BLOB_MAGIC, BLOB_MAGIC_SIZE);
+ res = (res == 0 ? PASS : FAIL);
+ presult(res, "blob magic number is correct");
+}
+
+void check_table_header(char *name, unsigned char *loc)
+{
+ const int CHECKSUM_OFFSET = 9;
+ const int CREATOR_ID_OFFSET = 28;
+ const int CREATOR_ID_LEN = 4;
+ const int CREATOR_REV_OFFSET = 32;
+ const int CREATOR_REV_LEN = 4;
+ const int OEMID_OFFSET = 10;
+ const int OEMID_LEN = 6;
+ const int REVISION_OFFSET = 8;
+
+ struct known_table_info *kp;
+ char buf[MAX_LINE];
+ int res;
+ int offset;
+ uint32_t len;
+ int min;
+
+ /* valid signature? */
+ kp = find_known_table_info(name);
+ res = (kp ? PASS : FAIL);
+ memset(buf, 0, MAX_LINE);
+ sprintf(buf, "%s: signature is correct", name);
+ presult(res, buf);
+
+ if (!kp) {
+ printf("? %s is an unknown table\n", name);
+ return;
+ }
+
+ /* possibly usable length? */
+ len = *(uint32_t *)(loc + TABLE_LEN_OFFSET);
+ res = PASS;
+ if ((len <= 0) || (len < MIN_TABLE_LENGTH))
+ res = FAIL;
+ memset(buf, 0, MAX_LINE);
+ sprintf(buf, "%s: table length is reasonable (%d)", name, len);
+ presult(res, buf);
+
+ /* valid checksum? */
+ res = verify_checksum(loc, CHECKSUM_OFFSET, len);
+ memset(buf, 0, MAX_LINE);
+ sprintf(buf, "%s: checksum is correct", name);
+ presult(res, buf);
+
+ /* valid revision number? */
+ res = verify_revision(loc + REVISION_OFFSET, kp->min_revision);
+ memset(buf, 0, MAX_LINE);
+ sprintf(buf, "%s: minimum revision is correct", name);
+ presult(res, buf);
+
+ /* non-empty OEMID field? */
+ res = (loc[OEMID_OFFSET] != 0 ? PASS : FAIL);
+ memset(buf, 0, MAX_LINE);
+ sprintf(buf, "%s: there is an OEMID (", name);
+ strncat(buf, (unsigned char *)(loc + OEMID_OFFSET), OEMID_LEN);
+ strncat(buf, ")", 1);
+ presult(res, buf);
+
+ /* non-empty CreatorID field? */
+ res = (loc[CREATOR_ID_OFFSET] != 0 ? PASS : FAIL);
+ memset(buf, 0, MAX_LINE);
+ sprintf(buf, "%s: there is a CreatorID", name);
+ presult(res, buf);
+
+ /* non-empty CreatorRevision field? */
+ res = (loc[CREATOR_REV_OFFSET] != 0 ? PASS : FAIL);
+ memset(buf, 0, MAX_LINE);
+ sprintf(buf, "%s: there is a CreatorRevision", name);
+ presult(res, buf);
+}
+
+void check_first_table_is_rsdp(unsigned char *blob)
+{
+ int res;
+
+ res = strncmp(blob + BLOB_HEADER_SIZE, SIG_RSDP, strlen(SIG_RSDP));
+ res = (res == 0 ? PASS : FAIL);
+ presult(res, "first table has RSDP signature");
+}
+
+void check_rsdp(unsigned char *blob)
+{
+ const int RSDP_FIRST_CKSUM_OFFSET = 8;
+ const int RSDP_FIRST_CKSUM_LEN = 20;
+ const int RSDP_SECOND_CKSUM_OFFSET = 32;
+ const int RSDP_SECOND_CKSUM_LEN = 36;
+ const int RSDP_RSDT_ADDR_OFFSET = 16;
+
+ unsigned char *ptr;
+ int res;
+ uint32_t rsdt_addr;
+
+ ptr = blob + BLOB_HEADER_SIZE;
+ printf ("\nchecking RSDP...\n");
+ check_first_table_is_rsdp(blob);
+
+ res = verify_checksum(ptr, RSDP_FIRST_CKSUM_OFFSET,
+ RSDP_FIRST_CKSUM_LEN);
+ presult(res, "first RSDP checksum verified");
+
+ res = verify_checksum(ptr, RSDP_SECOND_CKSUM_OFFSET,
+ RSDP_SECOND_CKSUM_LEN);
+ presult(res, "second RSDP checksum verified");
+
+ rsdt_addr = *(uint32_t *)(ptr + RSDP_RSDT_ADDR_OFFSET);
+ res = (rsdt_addr == 0) ? PASS : FAIL;
+ presult(res, "RSDT address is null");
+}
+
+void find_all_tables(unsigned char *blob, int size, int base_addr)
+{
+ struct table *tp;
+ unsigned char *p;
+ int offset;
+ int delta;
+
+ /* this assumes that all signatures and lengths are correct */
+ printf("\nscanning for tables...\n");
+
+ p = blob + BLOB_HEADER_SIZE;
+ offset = (int)(p - blob);
+
+ while (offset + SIG_LENGTH < size) {
+ if (valid_sig(p)) {
+ tp = build_table_entry(p);
+ if (tp) {
+ delta = TABLE_LEN_OFFSET;
+ if (strcmp(tp->signature, SIG_RSDP) == 0)
+ delta = RSDP_LEN_OFFSET;
+ tp->len = *(uint32_t *)(p + delta);
+ tp->offset = offset;
+ tp->paddr = base_addr + offset;
+
+ offset += *(uint32_t *)(p + delta);
+ p += tp->len;
+ } else {
+ printf("? no room for building a table\n");
+ exit(1);
+ }
+ } else {
+ /* skip forward until we find something; a table
+ * could have been moved to the next page boundary */
+ while (offset + SIG_LENGTH < size) {
+ p++;
+ offset++;
+ if (isalpha(*p) && valid_sig(p))
+ break;
+ }
+ }
+ }
+}
+
+void check_rsdp_relocs(unsigned char *blob, int size, uint64_t paddr)
+{
+ const int RSDT_ADDR_OFFSET = 16;
+ const int XSDT_ADDR_OFFSET = 24;
+
+ struct table *np, *xp;
+ int res;
+ uint32_t rsdt_addr;
+ uint64_t xsdt_addr;
+
+ printf("\nchecking RSDP relocations...\n");
+
+ res = FAIL;
+ np = find_table(SIG_RSDP);
+ if (np) {
+ np->ref_cnt++;
+
+ rsdt_addr = *(uint32_t *)(blob + np->offset + RSDT_ADDR_OFFSET);
+ res = (rsdt_addr == 0) ? PASS : FAIL;
+ presult(res, "RSDP has null RSDT pointer");
+
+ xsdt_addr = *(uint32_t *)(blob + np->offset + XSDT_ADDR_OFFSET);
+ xp = find_table(SIG_XSDT);
+ if (xp) {
+ xp->ref_cnt++;
+ if ((xsdt_addr == xp->paddr) &&
+ (strncmp(blob + xp->offset, SIG_XSDT,
+ strlen(xp->signature)) == 0))
+ res = PASS;
+ }
+ presult(res, "RSDP has correct XSDT pointer");
+ } else {
+ res = FAIL;
+ presult(res, "RSDP has null RSDT pointer");
+ presult(res, "RSDP has correct XSDT pointer");
+ }
+}
+
+void check_xsdt_relocs(unsigned char *blob, int size, uint64_t paddr)
+{
+ const int XSDT_ENTRY_START = 36;
+ const int XSDT_ENTRY_SIZE = 8;
+
+ struct table *np, *xp;
+ int res;
+ int cnt;
+ int ii;
+ int offset;
+ uint32_t len;
+ uint64_t *tpaddr;
+ char buf[MAX_LINE];
+
+ printf("\nchecking XSDT relocations...\n");
+
+ res = FAIL;
+ np = find_table(SIG_XSDT);
+ if (np) {
+ len = *(uint32_t *)(blob + np->offset + TABLE_LEN_OFFSET);
+ cnt = (len - XSDT_ENTRY_START) / XSDT_ENTRY_SIZE;
+ tpaddr = (uint64_t *)(blob + np->offset + XSDT_ENTRY_START);
+ if (len < 1) {
+ printf("? XSDT can not have an empty list\n");
+ exit(1);
+ }
+
+ /* first entry needs to be the FACP (aka FADT) */
+ offset = (*tpaddr - paddr);
+ if (strncmp(blob + offset, SIG_FACP, strlen(SIG_FACP)) == 0)
+ res = PASS;
+ presult(res, "first XSDT entry points to the FADT (aka FACP)");
+
+ /* verify all the relocations, best we can */
+ for (ii = 0; ii < cnt; ii++, tpaddr++) {
+ offset = (*tpaddr - paddr);
+ res = FAIL;
+ if (valid_sig(blob + offset)) {
+ xp = find_table(blob + offset);
+ if (xp) {
+ xp->ref_cnt++;
+ if ((*tpaddr == xp->paddr) &&
+ (strncmp(blob + xp->offset,
+ blob + offset,
+ strlen(xp->signature)) == 0))
+ res = PASS;
+ memset(buf, 0, MAX_LINE);
+ sprintf(buf,
+ "XSDT has correct %s pointer",
+ xp->signature);
+ presult(res, buf);
+ } else {
+ memset(buf, 0, MAX_LINE);
+ sprintf(buf,
+ "XSDT entry %d does not point to a valid table",
+ ii);
+ presult(res, buf);
+ }
+ }
+ }
+ } else {
+ printf("? XSDT can not be found in table list\n");
+ exit(1);
+ }
+}
+
+void check_fadt_relocs(unsigned char *blob, int size, uint64_t paddr)
+{
+ const int FWCTL_OFFSET = 36;
+ const int DSDT_OFFSET = 40;
+ const int XFWCTL_OFFSET = 132;
+ const int XDSDT_OFFSET = 140;
+
+ struct table *np, *xp;
+ uint32_t fwctl, dsdt;
+ uint64_t xfwctl, xdsdt;
+ uint64_t tpaddr;
+ int res;
+ int offset;
+
+ printf("\nchecking FADT relocations...\n");
+ np = find_table(SIG_FACP);
+ if (np) {
+ fwctl = *(uint32_t *)(blob + np->offset + FWCTL_OFFSET);
+ xfwctl = *(uint64_t *)(blob + np->offset + XFWCTL_OFFSET);
+ res = FAIL;
+ if ((fwctl == 0 && xfwctl == 0) || /* no FACS is okay */
+ (fwctl == 0 && xfwctl != 0) ||
+ (fwctl != 0 && xfwctl == 0))
+ res = PASS;
+ presult(res, "FADT has a proper 32-bit FACS pointer");
+ presult(res, "FADT has a proper 64-bit FACS pointer");
+ if (fwctl != 0 && xfwctl != 0)
+ presult(INFO,
+ "both fields have been set, not just one");
+
+ if (fwctl != 0 || xfwctl != 0) {
+ tpaddr = (fwctl == 0) ? xfwctl : fwctl;
+ offset = tpaddr - paddr;
+
+ xp = find_table(SIG_FACS);
+ if (xp) {
+ xp->ref_cnt++;
+ res = FAIL;
+ if ((tpaddr == xp->paddr) &&
+ (strncmp(blob + xp->offset,
+ blob + offset,
+ strlen(xp->signature)) == 0))
+ res = PASS;
+ presult(res, "FADT has correct FACS pointer");
+
+ } else {
+ printf("? FADT refers to an FACS but ");
+ printf("there is no such table\n");
+ exit(1);
+ }
+ }
+
+ dsdt = *(uint32_t *)(blob + np->offset + DSDT_OFFSET);
+ xdsdt = *(uint64_t *)(blob + np->offset + XDSDT_OFFSET);
+ res = FAIL;
+ if ((dsdt == 0 && xdsdt != 0) || /* must have a DSDT */
+ (dsdt != 0 && xdsdt == 0))
+ res = PASS;
+ presult(res, "FADT has a proper 32-bit DSDT pointer");
+ presult(res, "FADT has a proper 64-bit DSDT pointer");
+ if (dsdt != 0 && xdsdt != 0)
+ presult(INFO,
+ "both fields have been set, not just one");
+
+ if (dsdt != 0 || xdsdt != 0) {
+ tpaddr = (dsdt == 0) ? xdsdt : dsdt;
+ offset = tpaddr - paddr;
+
+ xp = find_table(SIG_DSDT);
+ if (xp) {
+ xp->ref_cnt++;
+ res = FAIL;
+ if ((tpaddr == xp->paddr) &&
+ (strncmp(blob + xp->offset,
+ blob + offset,
+ strlen(xp->signature)) == 0))
+ res = PASS;
+ presult(res, "FADT has correct DSDT pointer");
+
+ } else {
+ printf("? FADT refers to a DSDT but ");
+ printf("there is no such table\n");
+ exit(1);
+ }
+ }
+
+ } else {
+ printf("? FADT (aka FACP) can not be found in table list\n");
+ exit(1);
+ }
+}
+
+void check_ref_cnts(void)
+{
+ struct table *np;
+ int res;
+ char buf[MAX_LINE];
+
+ printf("\nchecking references to tables...\n");
+ LIST_FOREACH(np, &thead, tables) {
+ memset(buf, 0, MAX_LINE);
+ sprintf(buf, "%s referenced only once", np->signature);
+ res = (np->ref_cnt == 1) ? PASS : FAIL;
+ presult(res, buf);
+ }
+
+}
+
+void check_relocations(unsigned char *blob, int size, uint64_t paddr)
+{
+ check_rsdp_relocs(blob, size, paddr);
+ check_xsdt_relocs(blob, size, paddr);
+ check_fadt_relocs(blob, size, paddr);
+ check_ref_cnts();
+}
+
+int main(int argc, char *argv[])
+{
+ int ii, jj;
+ int offset;
+ int delta;
+ int size;
+ int fd;
+ unsigned char *blob;
+ char *acpi_blob_name;
+ char *paddr_cmd;
+ uint64_t paddr = 0;
+ char sig[SIG_LENGTH];
+ struct table *np;
+ int opt;
+ int quiet;
+
+ /* parameter handling */
+ acpi_blob_name = NULL;
+ paddr_cmd = NULL;
+ quiet = 0;
+
+ while ((opt = getopt(argc, argv, "b:p:q")) != EOF) {
+ switch (opt) {
+ case 'b':
+ acpi_blob_name = optarg;
+ break;
+ case 'p':
+ paddr_cmd = optarg;
+ break;
+ case 'q':
+ quiet = 1;
+ break;
+ default:
+ usage();
+ return 1;
+ }
+ }
+
+ if (!quiet)
+ printf("%s %s\n", PROGNAME, VERSION);
+
+ if ((argc > (optind + 1)) || (acpi_blob_name == NULL)) {
+ printf("? missing a parameter value\n");
+ usage();
+ return 1;
+ }
+ if (paddr_cmd) {
+ errno = 0;
+ paddr = strtoull(paddr_cmd, NULL, 0);
+ if (errno) {
+ printf("invalid physical address given\n");
+ return 1;
+ } else {
+ printf("assume blob was relocated to 0x%llx\n", paddr);
+ }
+ } else {
+ printf("? missing required physical address parameter\n");
+ usage();
+ return 1;
+ }
+
+ size = get_file_size(acpi_blob_name);
+ if (!size) {
+ printf("? blob cannot be zero length\n");
+ exit(1);
+ }
+
+ fd = open(acpi_blob_name, O_RDONLY);
+ if (fd < 0) {
+ perror(PROGNAME);
+ exit(1);
+ }
+ blob = mmap(NULL, size, PROT_READ, MAP_PRIVATE, fd , 0);
+ if (blob == MAP_FAILED) {
+ perror(PROGNAME);
+ exit(1);
+ }
+
+ LIST_INIT(&thead);
+
+ check_blob_header(blob);
+ check_rsdp(blob);
+
+ find_all_tables(blob, size, paddr);
+ if (!quiet) {
+ printf("found the following tables....\n");
+ ii = 0;
+ LIST_FOREACH(np, &thead, tables) {
+ printf(
+ "[%03d] %4s: %d bytes @ 0x%08x, loads @ 0x%016x\n",
+ ii, np->signature, np->len, np->offset, np->paddr);
+ ii++;
+ }
+ }
+ LIST_FOREACH(np, &thead, tables) {
+ if ((strncmp(np->signature, SIG_RSDP,
+ strlen(np->signature) != 0)) &&
+ (strncmp(np->signature, SIG_FACS,
+ strlen(np->signature) != 0))) {
+ printf("\nchecking header of %s...\n", np->signature);
+ check_table_header(np->signature, blob + np->offset);
+ }
+ }
+
+ check_relocations(blob, size, paddr);
+
+ printf("\nTotal tests: %d\n", passed + failed);
+ printf("Passed: %d\n", passed);
+ printf("Failed: %d\n", failed);
+ printf("Success rate: %0.1f%\n",
+ (100.0 * (float)passed) / (float)(passed + failed));
+
+ munmap(blob, size);
+
+ return (failed > 0) ? 1 : 0;
+}
diff --git a/tools/cab/cab.h b/tools/cab/cab.h
new file mode 100644
index 0000000..4512757
--- /dev/null
+++ b/tools/cab/cab.h
@@ -0,0 +1,169 @@
+#ifndef _CAB_H
+#define _CAB_H
+/*
+ * cab.h: tool to Check A Blob of ACPI tables
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file "COPYING" in the main directory of this
+ * archive for more details.
+ *
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * NB: all values are assumed to be little-endian in the blob.
+ *
+ */
+
+#include <stdint.h>
+#include <string.h>
+
+#include <sys/queue.h>
+
+/* VERSION a.b.c = <ACPI standard>.<functionality changes>.<bug fixes> */
+const char VERSION[] = { "5.0~3.1" };
+const char PROGNAME[] = { "cab" };
+
+#define PASS 1
+#define FAIL 0
+#define INFO (-1)
+
+#define BLOB_HEADER_SIZE 8
+#define BLOB_MAGIC "ACPI"
+#define BLOB_MAGIC_SIZE 4
+#define MAX_LINE 1024
+#define MIN_TABLE_LENGTH 36
+#define NOT_REQUIRED 0
+#define REQUIRED 1
+#define RSDP_LEN_OFFSET 20
+#define SIG_LENGTH 4
+#define TABLE_LEN_OFFSET 4
+
+#define SIG_APIC "APIC"
+#define SIG_BERT "BERT"
+#define SIG_CPEP "CPEP"
+#define SIG_DSDT "DSDT"
+#define SIG_ECDT "ECDT"
+#define SIG_EINJ "EINJ"
+#define SIG_ERST "ERST"
+#define SIG_FACP "FACP"
+#define SIG_FACS "FACS"
+#define SIG_FPDT "FPDT"
+#define SIG_GTDT "GTDT"
+#define SIG_HEST "HEST"
+#define SIG_MCFG "MCFG"
+#define SIG_MCHI "MCHI"
+#define SIG_MPST "MPST"
+#define SIG_MSCT "MSCT"
+#define SIG_OEM "OEM"
+#define SIG_PCCT "PCCT"
+#define SIG_PMTT "PMTT"
+#define SIG_RASF "RASF"
+#define SIG_RSDP "RSD PTR"
+#define SIG_RSDT "RSDT"
+#define SIG_SLIT "SLIT"
+#define SIG_SPMI "SPMI"
+#define SIG_SRAT "SRAT"
+#define SIG_SSDT "SSDT"
+#define SIG_UEFI "UEFI"
+#define SIG_XSDT "XSDT"
+
+struct known_table_info {
+ char *signature; /* table signature */
+ int min_revision; /* minimum allowed revision */
+};
+
+struct known_table_info known_info[] = {
+ { SIG_APIC, 3 },
+ { SIG_BERT, 1 },
+ { SIG_CPEP, 1 },
+ { SIG_DSDT, 2 },
+ { SIG_ECDT, 1 },
+ { SIG_EINJ, 1 },
+ { SIG_ERST, 1 },
+ { SIG_FACP, 5 },
+ { SIG_FACS, 5 },
+ { SIG_FPDT, 1 },
+ { SIG_GTDT, 1 },
+ { SIG_HEST, 1 },
+ { SIG_MCFG, 1 },
+ { SIG_MCHI, 1 },
+ { SIG_MPST, 1 },
+ { SIG_MSCT, 1 },
+ { SIG_OEM, 1 },
+ { SIG_PMTT, 1 },
+ { SIG_RASF, 1 },
+ { SIG_RSDP, 2 },
+ { SIG_RSDT, 1 },
+ { SIG_SLIT, 1 },
+ { SIG_SPMI, 1 },
+ { SIG_SRAT, 3 },
+ { SIG_SSDT, 2 },
+ { SIG_UEFI, 1 },
+ { SIG_XSDT, 1 },
+ { NULL, 0 }
+};
+
+char *known_sigs[] = {
+ "APIC",
+ "BERT",
+ "CPEP",
+ "DSDT",
+ "ECDT",
+ "EINJ",
+ "ERST",
+ "FACP",
+ "FACS",
+ "FPDT",
+ "GTDT",
+ "HEST",
+ "MCFG",
+ "MCHI",
+ "MPST",
+ "MSCT",
+ "OEM",
+ "PCCT",
+ "PMTT",
+ "RASF",
+ "RSD PTR",
+ "SLIT",
+ "SPMI",
+ "SRAT",
+ "SSDT",
+ "UEFI",
+ "XSDT",
+ NULL
+};
+
+LIST_HEAD(table_head, table) thead;
+struct table_head *theadp;
+
+struct table {
+ char *signature; /* an ACPI table name/signature */
+ int len; /* reported table length */
+ int offset; /* location in the blob */
+ uint64_t paddr; /* where it should live in RAM */
+ int ref_cnt; /* reference count */
+ LIST_ENTRY(table) tables;
+};
+
+
+struct table *build_table_entry(unsigned char *buf);
+void check_blob_header(unsigned char *blob);
+void check_fadt_relocs(unsigned char *blob, int size, uint64_t paddr);
+void check_first_table_is_rsdp(unsigned char *blob);
+void check_rsdp(unsigned char *blob);
+void check_ref_cnts(void);
+void check_relocations(unsigned char *blob, int size, uint64_t paddr);
+void check_rsdp_relocs(unsigned char *blob, int size, uint64_t paddr);
+void check_table_header(char *name, unsigned char *loc);
+void check_xsdt_relocs(unsigned char *blob, int size, uint64_t paddr);
+void find_all_tables(unsigned char *blob, int size, int base_addr);
+struct known_table_info *find_known_table_info(char *sig);
+struct table *find_table(char *sig);
+int get_file_size(char *fname);
+void usage(void);
+int valid_sig(char *sig);
+int verify_checksum(unsigned char *start, int offset, int len);
+int verify_revision(unsigned char *r, int min);
+void presult(int res, char *topic);
+
+#endif
--
1.8.3.1
11 years, 8 months
- 2
- 1
[PATCH][acpi-asl] ASL: set proper revision level in tables
by al.stone＠linaro.org
From: Al Stone <ahs3(a)redhat.com>
Checking for some other errors in tables, I stumbled across several
tables where the ASL had an old revision number in them (pre-5.0
spec). These have now been set to at least the 5.0 revision level
that they should be at.
Signed-off-by: Al Stone <al.stone(a)linaro.org>
---
platforms/exynos5250-arndale.acpi/apic.asl | 2 +-
platforms/exynos5250-arndale.acpi/dsdt.asl | 2 +-
platforms/foundation-v8.acpi/dsdt.asl | 2 +-
platforms/loadtest.acpi/dsdt.asl | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/platforms/exynos5250-arndale.acpi/apic.asl b/platforms/exynos5250-arndale.acpi/apic.asl
index 69f0dc1..c93a3a4 100644
--- a/platforms/exynos5250-arndale.acpi/apic.asl
+++ b/platforms/exynos5250-arndale.acpi/apic.asl
@@ -9,7 +9,7 @@
[0004] Signature : "APIC"
[0004] Table Length : 000000F6
-[0001] Revision : 01
+[0001] Revision : 03
[0001] Checksum : B0
[0006] Oem ID : "LINARO"
[0008] Oem Table ID : "ARNDALE "
diff --git a/platforms/exynos5250-arndale.acpi/dsdt.asl b/platforms/exynos5250-arndale.acpi/dsdt.asl
index 7f05c6b..aa01757 100644
--- a/platforms/exynos5250-arndale.acpi/dsdt.asl
+++ b/platforms/exynos5250-arndale.acpi/dsdt.asl
@@ -9,7 +9,7 @@
DefinitionBlock (
"dsdt.aml", // output filename
"DSDT", // table signature
- 1, // DSDT compliance revision
+ 2, // DSDT compliance revision
"LINARO", // OEM ID
"ARNDALE ", // table ID
0x00000002) // OEM revision
diff --git a/platforms/foundation-v8.acpi/dsdt.asl b/platforms/foundation-v8.acpi/dsdt.asl
index d1a9716..6a5d1be 100644
--- a/platforms/foundation-v8.acpi/dsdt.asl
+++ b/platforms/foundation-v8.acpi/dsdt.asl
@@ -9,7 +9,7 @@
DefinitionBlock (
"dsdt.aml", // output filename
"DSDT", // table signature
- 1, // DSDT compliance revision
+ 2, // DSDT compliance revision
"LINARO", // OEM ID
"FOUNDATI", // table ID
0x00000002) // OEM revision
diff --git a/platforms/loadtest.acpi/dsdt.asl b/platforms/loadtest.acpi/dsdt.asl
index 394bca6..d0d7178 100644
--- a/platforms/loadtest.acpi/dsdt.asl
+++ b/platforms/loadtest.acpi/dsdt.asl
@@ -9,7 +9,7 @@
DefinitionBlock (
"dsdt.aml", // output filename
"DSDT", // table signature
- 1, // DSDT compliance revision
+ 2, // DSDT compliance revision
"LINARO", // OEM ID
"LOADTEST", // table ID
0x00000001) // OEM revision
--
1.8.3.1
11 years, 8 months
- 2
- 1
[PATCH 0/7][acpi-asl] mab 0.28.1: fixes and new features
by al.stone＠linaro.org
From: Al Stone <ahs3(a)redhat.com>
While trying to figure out some problems I was having with my ACPI
blobs, I ran into several things that needed fixing in mab. Some of
these are innocuous, but some -- like using both 32- and 64-bit addresses
in the FACS, and the RSDP checksums -- are actually in violation of the
spec.
While I was there, I added a little more info in the verbose output,
and corrected what was being printed out.
The new feature is that one can now use -H to produce a blob that does
not have the header we've been using so far.
Al Stone (7):
mab: Makefile needs to rebuild if .h changes and use CFLAGS properly
mab: use 32- or 64-bit FACS addresses in the FADT, not both
mab: set both checksums in the RSDP, not just one
mab: print out the correct offset in the blob
mab: add option to NOT use a blob header, if needed
mab: print out physical address when being verbose
mab: update Changelog and version number for this patch series
tools/mab/Changelog | 19 +++++++++
tools/mab/Makefile | 6 +--
tools/mab/mab.c | 109 +++++++++++++++++++++++++++++++---------------------
tools/mab/mab.h | 5 ++-
4 files changed, 91 insertions(+), 48 deletions(-)
--
1.8.3.1
11 years, 8 months
- 2
- 8
Simple ACPI Boot Tests
by Graeme Gregory
For card LEG-583 I needed some simple ACPI tests to check that we have
booted with ACPI support and have probably not corrupted the tables.
I think the attached script should do it if anyone has any comments.
Next I need to see how to get this into a LAVA test.
Tests:-
1) Check presence of /sys/firmware/acpi
2) Check presence of /sys/firmware/acpi/tables/DSDT
3) If iasl is installed test decompile of /sys/firmware/acpi/tables/DSDT
I think this is simple enough to be a boot test but enough confidence
that the bootloader correctly passed us some tables?
iasl should thanks to Naresh be part of released OE images soon.
Thanks
Graeme
11 years, 8 months
- 2
- 1
[PATCH] exynos5250-arndale: DSDT requires _CRS to be serialized
by al.stone＠linaro.org
From: Al Stone <ahs3(a)redhat.com>
Signed-off-by: Al Stone <al.stone(a)linaro.org>
---
platforms/exynos5250-arndale.acpi/dsdt.asl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/platforms/exynos5250-arndale.acpi/dsdt.asl b/platforms/exynos5250-arndale.acpi/dsdt.asl
index 2cca765..7f05c6b 100644
--- a/platforms/exynos5250-arndale.acpi/dsdt.asl
+++ b/platforms/exynos5250-arndale.acpi/dsdt.asl
@@ -23,7 +23,7 @@ DefinitionBlock (
Name (_HID, "LINA0001")
Name (_UID, 0)
- Method (_CRS, 0x0, NotSerialized) {
+ Method (_CRS, 0x0, Serialized) {
Name (RBUF, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0x12C60000, 0x00000100)
--
1.8.3.1
11 years, 8 months
- 2
- 1
[PATCH] mab: prevent tables crossing 4K boundaries
by Graeme Gregory
Tables crossing pages is currently causing issues on armv7 devices, for
now get mab to fixup addresses so we do not cross a page boundary with a
table.
Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org>
---
tools/mab/mab.c | 32 ++++++++++++++++++++++++++++++--
tools/mab/mab.h | 3 +++
2 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/tools/mab/mab.c b/tools/mab/mab.c
index 74ed0e9..c9c8c7c 100644
--- a/tools/mab/mab.c
+++ b/tools/mab/mab.c
@@ -237,8 +237,25 @@ void set_checksum(unsigned char *start, int len, uint8_t *cksum)
int add_table(unsigned char *blob, char *table_name, int offset, int reqd)
{
struct table *p;
+ int new_offset;
p = find_table(table_name);
+ new_offset = offset + p->file_size;
+
+ /*
+ * Handle crossing of page boundaries to prevent problems
+ * on armv7 with small page sizes
+ */
+ if ((new_offset / PAGE_SIZE) != (offset / PAGE_SIZE)) {
+ offset += (PAGE_SIZE - (offset % PAGE_SIZE));
+ /*
+ * If this is the first page crossing remove the
+ * blob header from calculations
+ */
+ if ((offset / PAGE_SIZE) == 1)
+ offset -= BLOB_HEADER_SIZE;
+ }
+
if (p) {
write_table(blob, p, offset);
} else {
@@ -519,8 +536,19 @@ int main(int argc, char *argv[])
/* build up the contents of the blob, table by table */
blob_size = 0;
- LIST_FOREACH(np, &thead, tables)
- blob_size += np->file_size;
+ LIST_FOREACH(np, &thead, tables) {
+ int new_size, adjustment = 0;
+
+ new_size = blob_size + np->file_size;
+
+ if ((new_size / PAGE_SIZE) != (blob_size / PAGE_SIZE)) {
+ adjustment = PAGE_SIZE - (blob_size % PAGE_SIZE);
+ if (!(blob_size / PAGE_SIZE))
+ adjustment -= BLOB_HEADER_SIZE;
+ }
+
+ blob_size += np->file_size + adjustment;
+ }
blob = (unsigned char *)malloc(blob_size + BLOB_HEADER_SIZE);
memset(blob, 0, blob_size + BLOB_HEADER_SIZE);
diff --git a/tools/mab/mab.h b/tools/mab/mab.h
index 366caef..37cd850 100644
--- a/tools/mab/mab.h
+++ b/tools/mab/mab.h
@@ -89,4 +89,7 @@ void fixup_facp(unsigned char *blob, int *offset, unsigned long paddr);
void fixup_rsdp(unsigned char *blob, unsigned long paddr);
void fixup_xsdt(unsigned char *blob, int *offset, unsigned long paddr);
+/* Currently a hack to avoid issues on 4k pages on armv7 */
+#define PAGE_SIZE 0x1000
+
#endif
--
1.7.10.4
11 years, 8 months
- 3
- 3
[PATCH] platforms: add rtsm_ve-aemv8a.acpi
by Graeme Gregory
There are enough differences between this model and foundation model I think
it is ok to be a different platform.
Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org>
---
platforms/rtsm_ve-aemv8a.acpi/.gitignore | 3 +
platforms/rtsm_ve-aemv8a.acpi/apic.asl | 126 +++++++++
platforms/rtsm_ve-aemv8a.acpi/asf!.asl | 80 ++++++
platforms/rtsm_ve-aemv8a.acpi/bert.asl | 21 ++
platforms/rtsm_ve-aemv8a.acpi/bgrt.asl | 25 ++
platforms/rtsm_ve-aemv8a.acpi/boot.asl | 21 ++
platforms/rtsm_ve-aemv8a.acpi/cpep.asl | 26 ++
platforms/rtsm_ve-aemv8a.acpi/csrt.asl | 143 ++++++++++
platforms/rtsm_ve-aemv8a.acpi/dbgp.asl | 29 ++
platforms/rtsm_ve-aemv8a.acpi/dmar.asl | 68 +++++
platforms/rtsm_ve-aemv8a.acpi/dsdt.asl | 234 ++++++++++++++++
platforms/rtsm_ve-aemv8a.acpi/ecdt.asl | 37 +++
platforms/rtsm_ve-aemv8a.acpi/einj.asl | 151 +++++++++++
platforms/rtsm_ve-aemv8a.acpi/erst.asl | 278 ++++++++++++++++++++
platforms/rtsm_ve-aemv8a.acpi/facp.asl | 167 ++++++++++++
platforms/rtsm_ve-aemv8a.acpi/facs.asl | 21 ++
platforms/rtsm_ve-aemv8a.acpi/fpdt.asl | 35 +++
platforms/rtsm_ve-aemv8a.acpi/gtdt.asl | 42 +++
platforms/rtsm_ve-aemv8a.acpi/hest.asl | 193 ++++++++++++++
platforms/rtsm_ve-aemv8a.acpi/hpet.asl | 33 +++
platforms/rtsm_ve-aemv8a.acpi/ivrs.asl | 86 ++++++
platforms/rtsm_ve-aemv8a.acpi/mcfg.asl | 26 ++
platforms/rtsm_ve-aemv8a.acpi/mchi.asl | 38 +++
platforms/rtsm_ve-aemv8a.acpi/mpst.asl | 87 ++++++
platforms/rtsm_ve-aemv8a.acpi/msct.asl | 51 ++++
platforms/rtsm_ve-aemv8a.acpi/oem0.asl | 18 ++
platforms/rtsm_ve-aemv8a.acpi/pmtt.asl | 105 ++++++++
platforms/rtsm_ve-aemv8a.acpi/rsdp.asl | 17 ++
.../rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest | 34 +++
platforms/rtsm_ve-aemv8a.acpi/s3pt.asl | 26 ++
platforms/rtsm_ve-aemv8a.acpi/sbst.asl | 22 ++
platforms/rtsm_ve-aemv8a.acpi/slic.asl | 56 ++++
platforms/rtsm_ve-aemv8a.acpi/slit.asl | 60 +++++
platforms/rtsm_ve-aemv8a.acpi/spcr.asl | 46 ++++
platforms/rtsm_ve-aemv8a.acpi/spmi.asl | 40 +++
platforms/rtsm_ve-aemv8a.acpi/srat.asl | 57 ++++
platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl | 17 ++
platforms/rtsm_ve-aemv8a.acpi/tcpa.asl | 22 ++
platforms/rtsm_ve-aemv8a.acpi/tpm2.asl | 22 ++
platforms/rtsm_ve-aemv8a.acpi/uefi.asl | 21 ++
platforms/rtsm_ve-aemv8a.acpi/waet.asl | 22 ++
platforms/rtsm_ve-aemv8a.acpi/wdat.asl | 47 ++++
platforms/rtsm_ve-aemv8a.acpi/wddt.asl | 44 ++++
platforms/rtsm_ve-aemv8a.acpi/wdrt.asl | 42 +++
platforms/rtsm_ve-aemv8a.acpi/xsdt.asl | 39 +++
45 files changed, 2778 insertions(+)
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/.gitignore
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/apic.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/asf!.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/bert.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/bgrt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/boot.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/cpep.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/csrt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/dbgp.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/dmar.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/dsdt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/ecdt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/einj.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/erst.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/facp.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/facs.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/fpdt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/gtdt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/hest.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/hpet.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/ivrs.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/mcfg.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/mchi.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/mpst.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/msct.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/oem0.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/pmtt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/rsdp.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/s3pt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/sbst.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/slic.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/slit.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/spcr.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/spmi.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/srat.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/tcpa.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/tpm2.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/uefi.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/waet.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/wdat.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/wddt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/wdrt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/xsdt.asl
diff --git a/platforms/rtsm_ve-aemv8a.acpi/.gitignore b/platforms/rtsm_ve-aemv8a.acpi/.gitignore
new file mode 100644
index 0000000..9585b50
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/.gitignore
@@ -0,0 +1,3 @@
+*.aml
+*.lst
+*.acpi
diff --git a/platforms/rtsm_ve-aemv8a.acpi/apic.asl b/platforms/rtsm_ve-aemv8a.acpi/apic.asl
new file mode 100644
index 0000000..0df308d
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/apic.asl
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [APIC] Multiple APIC Description Table (MADT)
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "APIC"
+[0004] Table Length : 000000F6
+[0001] Revision : 03
+[0001] Checksum : B0
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20110623
+
+[0004] Local Apic Address : 2C002000
+[0004] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 0
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 28
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000000 /* Should be equal to FDT provided or CPU hardware ID */
+[0004] Processor UID : 00000000
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C002000 /* this is the foundation model's GIC address */
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 28
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000001
+[0004] Processor UID : 00000001
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C002000
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 28
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000002
+[0004] Processor UID : 00000002
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C002000
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 28
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000003
+[0004] Processor UID : 00000003
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C002000
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 28
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000004
+[0004] Processor UID : 00000004
+[0004] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C002000
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 28
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000005
+[0004] Processor UID : 00000005
+[0004] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C002000
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 28
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000006
+[0004] Processor UID : 00000006
+[0004] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C002000
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 28
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000007
+[0004] Processor UID : 00000007
+[0004] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C002000
+
+[0001] Subtable Type : 0C [Generic Interrupt Distributor]
+[0001] Length : 18
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000000
+[0008] Base Address : 000000002C001000 /* armv8 foundation model's GIC distributor base addr */
+[0004] Interrupt Base : 00000000
+[0004] Reserved : 00000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/asf!.asl b/platforms/rtsm_ve-aemv8a.acpi/asf!.asl
new file mode 100644
index 0000000..a05f924
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/asf!.asl
@@ -0,0 +1,80 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [ASF!] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "ASF!" [Alert Standard Format table]
+[0004] Table Length : 00000072
+[0001] Revision : 10
+[0001] Checksum : 0B
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0001] Subtable Type : 00 [ASF Information]
+[0001] Reserved : 00
+[0002] Length : 0010
+[0001] Minimum Reset Value : 00
+[0001] Minimum Polling Interval : 00
+[0002] System ID : 0000
+[0004] Manufacturer ID : 00000000
+[0001] Flags : 00
+[0003] Reserved : 000000
+
+[0001] Subtable Type : 01 [ASF Alerts]
+[0001] Reserved : 00
+[0002] Length : 0014
+[0001] AssertMask : 00
+[0001] DeassertMask : 00
+[0001] Alert Count : 01
+[0001] Alert Data Length : 0C
+
+[0001] Address : 00
+[0001] Command : 00
+[0001] Mask : 00
+[0001] Value : 00
+[0001] SensorType : 00
+[0001] Type : 00
+[0001] Offset : 00
+[0001] SourceType : 00
+[0001] Severity : 00
+[0001] SensorNumber : 00
+[0001] Entity : 00
+[0001] Instance : 00
+
+[0001] Subtable Type : 02 [ASF Remote Control]
+[0001] Reserved : 00
+[0002] Length : 000C
+[0001] Control Count : 01
+[0001] Control Data Length : 04
+[0002] Reserved : 0000
+
+[0001] Function : 00
+[0001] Address : 00
+[0001] Command : 00
+[0001] Value : 00
+
+[0001] Subtable Type : 03 [ASF RMCP Boot Options]
+[0001] Reserved : 00
+[0002] Length : 0017
+[0007] Capabilities : 00 00 00 00 00 00 00
+[0001] Completion Code : 00
+[0004] Enterprise ID : 00000000
+[0001] Command : 00
+[0002] Parameter : 0000
+[0002] Boot Options : 0000
+[0002] Oem Parameters : 0000
+
+[0001] Subtable Type : 84 [ASF Address]
+[0001] Reserved : 00
+[0002] Length : 0007
+[0001] Eprom Address : 00
+[0001] Device Count : 01
+[0001] Addresses : 00
+
diff --git a/platforms/rtsm_ve-aemv8a.acpi/bert.asl b/platforms/rtsm_ve-aemv8a.acpi/bert.asl
new file mode 100644
index 0000000..6cb628c
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/bert.asl
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [BERT] Boot Error Record Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "BERT"
+[0004] Table Length : 00000030
+[0001] Revision : 01
+[0001] Checksum : 15
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Boot Error Region Length : 00000000
+[0008] Boot Error Region Address : 0000000000000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/bgrt.asl b/platforms/rtsm_ve-aemv8a.acpi/bgrt.asl
new file mode 100644
index 0000000..c8af10e
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/bgrt.asl
@@ -0,0 +1,25 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [BGRT] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "BGRT" [Boot Graphics Resource Table]
+[0004] Table Length : 00000038
+[0001] Revision : 01
+[0001] Checksum : 0D
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20110623
+
+[0002] Version : 0001
+[0001] Status : 00
+[0001] Image Type : 00
+[0008] Image Address : 0000000000000000
+[0004] Image OffsetX : 00000000
+[0004] Image OffsetY : 00000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/boot.asl b/platforms/rtsm_ve-aemv8a.acpi/boot.asl
new file mode 100644
index 0000000..5a567fb
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/boot.asl
@@ -0,0 +1,21 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [BOOT] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "BOOT" [Simple Boot Flag Table]
+[0004] Table Length : 00000028
+[0001] Revision : 01
+[0001] Checksum : 0D
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 06040000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0001] Boot Register Index : 00
+[0003] Reserved : 000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/cpep.asl b/platforms/rtsm_ve-aemv8a.acpi/cpep.asl
new file mode 100644
index 0000000..8f6b3b2
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/cpep.asl
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [CPEP] Corrected Platform Error Polling Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "CPEP"
+[0004] Table Length : 00000034
+[0001] Revision : 01
+[0001] Checksum : 0F
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0008] Reserved : 0000000000000000
+
+[0001] Subtable Type : 00
+[0001] Length : 08
+[0001] Processor ID : 00
+[0001] Processor EID : 00
+[0004] Polling Interval : 00000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/csrt.asl b/platforms/rtsm_ve-aemv8a.acpi/csrt.asl
new file mode 100644
index 0000000..ab43ea5
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/csrt.asl
@@ -0,0 +1,143 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [CSRT] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "CSRT" [Core System Resource Table]
+[0004] Table Length : 0000014C
+[0001] Revision : 01
+[0001] Checksum : 0D
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20121114
+
+
+[0004] Length : 00000088
+[0004] Vendor ID : 4C544E49
+[0004] Subvendor ID : 00000000
+[0002] Device ID : 9C60
+[0002] Subdevice ID : 0000
+[0002] Revision : 0002
+[0002] Reserved : 0000
+[0004] Shared Info Length : 0000001C
+
+[0002] Major Version : 0001
+[0002] Minor Version : 0000
+[0004] MMIO Base Address Low : B3A00000
+[0004] MMIO Base Address High : 00000000
+[0004] GSI Interrupt : 0000002A
+[0001] Interrupt Polarity : 02
+[0001] Interrupt Mode : 00
+[0001] Num Channels : 06
+[0001] DMA Address Width : 20
+[0002] Base Request Line : 0000
+[0002] Num Handshake Signals : 0010
+[0004] Max Block Size : 00000FFF
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0001
+[0004] UID : 20495053
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 30414843
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 31414843
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 32414843
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 33414843
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 34414843
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 35414843
+
+[0004] Length : 000000A0
+[0004] Vendor ID : 4C544E49
+[0004] Subvendor ID : 00000000
+[0002] Device ID : 9C60
+[0002] Subdevice ID : 0000
+[0002] Revision : 0003
+[0002] Reserved : 0000
+[0004] Shared Info Length : 0000001C
+
+[0002] Major Version : 0001
+[0002] Minor Version : 0000
+[0004] MMIO Base Address Low : 00000000
+[0004] MMIO Base Address High : 00000000
+[0004] GSI Interrupt : 0000002B
+[0001] Interrupt Polarity : 02
+[0001] Interrupt Mode : 00
+[0001] Num Channels : 08
+[0001] DMA Address Width : 20
+[0002] Base Request Line : 0010
+[0002] Num Handshake Signals : 0010
+[0004] Max Block Size : 00000FFF
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0001
+[0004] UID : 20433249
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 30414843
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 31414843
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 32414843
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 33414843
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 34414843
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 35414843
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 36414843
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 37414843
diff --git a/platforms/rtsm_ve-aemv8a.acpi/dbgp.asl b/platforms/rtsm_ve-aemv8a.acpi/dbgp.asl
new file mode 100644
index 0000000..d1a826f
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/dbgp.asl
@@ -0,0 +1,29 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [DBGP] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "DBGP" [Debug Port table]
+[0004] Table Length : 00000034
+[0001] Revision : 01
+[0001] Checksum : 1A
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0001] Interface Type : 00
+[0003] Reserved : 000000
+
+[0012] Debug Port Register : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
diff --git a/platforms/rtsm_ve-aemv8a.acpi/dmar.asl b/platforms/rtsm_ve-aemv8a.acpi/dmar.asl
new file mode 100644
index 0000000..e10c8c3
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/dmar.asl
@@ -0,0 +1,68 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [DMAR] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "DMAR" [DMA Remapping table]
+[0004] Table Length : 0000008C
+[0001] Revision : 01
+[0001] Checksum : 15
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0001] Host Address Width : 2F
+[0001] Flags : 01
+
+[0002] Subtable Type : 0000 [Hardware Unit Definition]
+[0002] Length : 0018
+[0001] Flags : 01
+[0001] Reserved : 00
+[0002] PCI Segment Number : 0000
+[0008] Register Base Address : 00000000FD020000
+
+[0001] Device Scope Entry Type : 03
+[0001] Entry Length : 08
+[0002] Reserved : 0000
+[0001] Enumeration ID : 08
+[0001] PCI Bus Number : F0
+[0002] PCI Path : 1F,07
+
+[0002] Subtable Type : 0001 [Reserved Memory Region]
+[0002] Length : 0020
+[0002] Reserved : 0000
+[0002] PCI Segment Number : 0000
+[0008] Base Address : 0000000078C21000
+[0008] End Address (limit) : 0000000078C23FFF
+
+[0001] Device Scope Entry Type : 01
+[0001] Entry Length : 08
+[0002] Reserved : 0000
+[0001] Enumeration ID : 00
+[0001] PCI Bus Number : 00
+[0002] PCI Path : 1D,00
+
+[0002] Subtable Type : 0002 [Root Port ATS Capability]
+[0002] Length : 0010
+[0001] Flags : 00
+[0001] Reserved : 00
+[0002] PCI Segment Number : 0000
+
+[0001] Device Scope Entry Type : 02
+[0001] Entry Length : 08
+[0002] Reserved : 0000
+[0001] Enumeration ID : 00
+[0001] PCI Bus Number : 00
+[0002] PCI Path : 01,00
+
+[0002] Subtable Type : 0003 [Remapping Hardware Static Affinity]
+[0002] Length : 0014
+[0004] Reserved : 00000000
+[0008] Base Address : 00000000FD020000
+[0004] Proximity Domain : 00000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/dsdt.asl b/platforms/rtsm_ve-aemv8a.acpi/dsdt.asl
new file mode 100644
index 0000000..daefcd8
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/dsdt.asl
@@ -0,0 +1,234 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [DSDT] Description of the Arndale board (exynos5250)
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+DefinitionBlock (
+ "dsdt.aml", // output filename
+ "DSDT", // table signature
+ 1, // DSDT compliance revision
+ "LINARO", // OEM ID
+ "RTSMVEV8", // table ID
+ 0x00000002) // OEM revision
+{
+ Scope (\_SB)
+ {
+ Device (SCK0)
+ {
+ Name (_HID, "ACPI0004")
+ Name (_UID, 0x00)
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Device (PRC0)
+ {
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0x00)
+
+ /* CPU0 will be always present */
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Name (MAT0, Buffer (0x28)
+ {
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* type, len, reserved, gic_id */
+ /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, /* uid, flags */
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* parking_version, performance_interrupt */
+ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* parked_address */
+ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* base_address */
+ })
+
+ Name (MAT1, Buffer (0x28)
+ {
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+
+ Method (_MAT, 0, NotSerialized)
+ {
+ If (_STA())
+ {
+ Return (MAT0)
+ }
+ Else
+ {
+ Return (MAT1)
+ }
+ }
+ }
+
+ Device (PRC1)
+ {
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0x01)
+
+ Name (STA1, 0x0F)
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (STA1)
+ }
+
+ Method (_EJ0, 1, NotSerialized)
+ {
+ If (LEqual (STA1, 0x0F))
+ {
+ Store (0x00, STA1)
+ }
+ }
+
+ Name (MAT0, Buffer (0x28)
+ {
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+ /* 0008 */ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01,
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+
+ Name (MAT1, Buffer (0x28)
+ {
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+ /* 0008 */ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+
+ Method (_MAT, 0, NotSerialized)
+ {
+ If (_STA())
+ {
+ Return (MAT0)
+ }
+ Else
+ {
+ Return (MAT1)
+ }
+ }
+ }
+
+ Device (PRC2)
+ {
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0x02)
+
+ Name (STA2, 0x0F)
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (STA2)
+ }
+
+ Method (_EJ0, 1, NotSerialized)
+ {
+ If (LEqual (STA2, 0x0F))
+ {
+ Store (0x00, STA2)
+ }
+ }
+
+ Name (MAT0, Buffer (0x28)
+ {
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+ /* 0008 */ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+
+ Name (MAT1, Buffer (0x28)
+ {
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+ /* 0008 */ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+
+ Method (_MAT, 0, NotSerialized)
+ {
+ If (_STA())
+ {
+ Return (MAT0)
+ }
+ Else
+ {
+ Return (MAT1)
+ }
+ }
+ }
+
+ Device (PRC3)
+ {
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0x03)
+
+ Name (STA3, 0x0F)
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (STA3)
+ }
+
+ Method (_EJ0, 1, NotSerialized)
+ {
+ If (LEqual (STA3, 0x0F))
+ {
+ Store (0x00, STA3)
+ }
+ }
+
+ Name (MAT0, Buffer (0x28)
+ {
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+ /* 0008 */ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01,
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+
+ Name (MAT1, Buffer (0x28)
+ {
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+ /* 0008 */ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00,
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+
+ Method (_MAT, 0, NotSerialized)
+ {
+ If (_STA())
+ {
+ Return (MAT0)
+ }
+ Else
+ {
+ Return (MAT1)
+ }
+ }
+ }
+ }
+
+ Device (NET0) {
+ Name (_HID, "LINA0003")
+ Name (_UID, 0)
+
+ Method (_CRS, 0x0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0x1a000000, 0x00010000)
+ Interrupt (ResourceConsumer, Edge, ActiveBoth, Exclusive, , , ) {0x2F}
+ })
+ Return (RBUF)
+ }
+ }
+ }
+}
diff --git a/platforms/rtsm_ve-aemv8a.acpi/ecdt.asl b/platforms/rtsm_ve-aemv8a.acpi/ecdt.asl
new file mode 100644
index 0000000..75ffdc4
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/ecdt.asl
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [ECDT] Embedded Controller Boot Resources Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "ECDT"
+[0004] Table Length : 00000042
+[0001] Revision : 01
+[0001] Checksum : 2D
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+
+[0012] Command/Status Register : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000066
+
+[0012] Data Register : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000062
+
+[0004] UID : 00000000
+[0001] GPE Number : 09
+[0001] Namepath : ""
diff --git a/platforms/rtsm_ve-aemv8a.acpi/einj.asl b/platforms/rtsm_ve-aemv8a.acpi/einj.asl
new file mode 100644
index 0000000..e2d3f5e
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/einj.asl
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [EINJ] Error Injection Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "EINJ"
+[0004] Table Length : 00000130
+[0001] Revision : 01
+[0001] Checksum : 09
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Injection Header Length : 00000030
+[0001] Flags : 00
+[0003] Reserved : 000000
+[0004] Injection Entry Count : 0000000A
+
+[0001] Action : 00 [Begin Operation]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 01 [Get Trigger Table]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 02 [Set Error Type]
+[0001] Instruction : 02 [Write Register]
+[0001] Flags (decoded below) : 01
+ Preserve Register Bits : 1
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 03 [Get Error Type]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 04 [End Operation]
+[0001] Instruction : 03 [Write Register Value]
+[0001] Flags (decoded below) : 01
+ Preserve Register Bits : 1
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 05 [Execute Operation]
+[0001] Instruction : 03 [Write Register Value]
+[0001] Flags (decoded below) : 01
+ Preserve Register Bits : 1
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 10
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 02 [Word Access:16]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 06 [Check Busy Status]
+[0001] Instruction : 01 [Read Register Value]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 07 [Get Command Status]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 01
+ Preserve Register Bits : 1
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
diff --git a/platforms/rtsm_ve-aemv8a.acpi/erst.asl b/platforms/rtsm_ve-aemv8a.acpi/erst.asl
new file mode 100644
index 0000000..a453eab
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/erst.asl
@@ -0,0 +1,278 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [ERST] Error Record Serialization Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "ERST"
+[0004] Table Length : 00000230
+[0001] Revision : 01
+[0001] Checksum : AB
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Serialization Header Length : 00000030
+[0004] Reserved : 00000000
+[0004] Instruction Entry Count : 00000010
+
+[0001] Action : 00 [Begin Write Operation]
+[0001] Instruction : 03 [Write Register Value]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 01 [Begin Read Operation]
+[0001] Instruction : 03 [Write Register Value]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 02 [Begin Clear Operation]
+[0001] Instruction : 03 [Write Register Value]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 03 [End Operation]
+[0001] Instruction : 04 [Noop]
+[0001] Flags (decoded below) : 01
+ Preserve Register Bits : 1
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 04 [Set Record Offset]
+[0001] Instruction : 02 [Write Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 05 [Execute Operation]
+[0001] Instruction : 03 [Write Register Value]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 01 [Byte Access:8]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 06 [Check Busy Status]
+[0001] Instruction : 01 [Read Register Value]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 07 [Get Command Status]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 08 [Get Record Identifier]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 09 [Set Record Identifier]
+[0001] Instruction : 02 [Write Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 0A [Get Record Count]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 0B [Begin Dummy Write]
+[0001] Instruction : 03 [Write Register Value]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 0C [Unused/Unknown Action]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 0D [Get Error Address Range]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 0E [Get Error Address Length]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 0F [Get Error Attributes]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
diff --git a/platforms/rtsm_ve-aemv8a.acpi/facp.asl b/platforms/rtsm_ve-aemv8a.acpi/facp.asl
new file mode 100644
index 0000000..c4713fe
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/facp.asl
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [FACP] ACPI Table
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "FACP"
+[0004] Table Length : 0000010C
+[0001] Revision : 05
+[0001] Checksum : 18
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20111123
+
+[0004] FACS Address : 00000000
+[0004] DSDT Address : 00000010
+[0001] Model : 00
+[0001] PM Profile : 04 /* Enterprise Server */
+[0002] SCI Interrupt : 0000
+[0004] SMI Command Port : 00000000
+[0001] ACPI Enable Value : 00
+[0001] ACPI Disable Value : 00
+[0001] S4BIOS Command : 00
+[0001] P-State Control : 00
+[0004] PM1A Event Block Address : 00000001
+[0004] PM1B Event Block Address : 00000000
+[0004] PM1A Control Block Address : 00000001
+[0004] PM1B Control Block Address : 00000000
+[0004] PM2 Control Block Address : 00000001
+[0004] PM Timer Block Address : 00000001
+[0004] GPE0 Block Address : 00000001
+[0004] GPE1 Block Address : 00000000
+[0001] PM1 Event Block Length : 04
+[0001] PM1 Control Block Length : 02
+[0001] PM2 Control Block Length : 01
+[0001] PM Timer Block Length : 04
+[0001] GPE0 Block Length : 08
+[0001] GPE1 Block Length : 00
+[0001] GPE1 Base Offset : 00
+[0001] _CST Support : 00
+[0002] C2 Latency : 0000
+[0002] C3 Latency : 0000
+[0002] CPU Cache Size : 0000
+[0002] Cache Flush Stride : 0000
+[0001] Duty Cycle Offset : 00
+[0001] Duty Cycle Width : 00
+[0001] RTC Day Alarm Index : 00
+[0001] RTC Month Alarm Index : 00
+[0001] RTC Century Index : 00
+[0002] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[0001] Reserved : 00
+[0004] Flags (decoded below) : 00000000
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 1
+ All CPUs support C1 (V1) : 0
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 1
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 0
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 0
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 1
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 0
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 1
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 1
+ Low Power S0 Idle (V5) : 1
+
+[0012] Reset Register : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 01 [Byte Access:8]
+[0008] Address : 0000000000000001
+
+[0001] Value to cause reset : 00
+[0003] Reserved : 000000
+[0008] FACS Address : 0000000000000000
+[0008] DSDT Address : 0000000000000010
+[0012] PM1A Event Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 20
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 02 [Word Access:16]
+[0008] Address : 0000000000000001
+
+[0012] PM1B Event Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 00
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+[0012] PM1A Control Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 10
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 02 [Word Access:16]
+[0008] Address : 0000000000000001
+
+[0012] PM1B Control Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 00
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+[0012] PM2 Control Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000001
+
+[0012] PM Timer Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 20
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 03 [DWord Access:32]
+[0008] Address : 0000000000000001
+
+[0012] GPE0 Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 80
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 01 [Byte Access:8]
+[0008] Address : 0000000000000001
+
+[0012] GPE1 Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 00
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+
+[0012] Sleep Control Register : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 01 [Byte Access:8]
+[0008] Address : 0000000000000000
+
+[0012] Sleep Status Register : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 01 [Byte Access:8]
+[0008] Address : 0000000000000000
+
diff --git a/platforms/rtsm_ve-aemv8a.acpi/facs.asl b/platforms/rtsm_ve-aemv8a.acpi/facs.asl
new file mode 100644
index 0000000..8d12b41
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/facs.asl
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [FACS] ACPI Table
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "FACS"
+[0004] Length : 00000040
+[0004] Hardware Signature : 00000000
+[0004] 32 Firmware Waking Vector : 00000000
+[0004] Global Lock : 00000000
+[0004] Flags (decoded below) : 00000000
+ S4BIOS Support Present : 0
+ 64-bit Wake Supported (V2) : 0
+[0008] 64 Firmware Waking Vector : 0000000000000000
+[0001] Version : 02
+[0003] Reserved : 000000
+[0004] OspmFlags (decoded below) : 00000000
+ 64-bit Wake Env Required (V2) : 0
diff --git a/platforms/rtsm_ve-aemv8a.acpi/fpdt.asl b/platforms/rtsm_ve-aemv8a.acpi/fpdt.asl
new file mode 100644
index 0000000..2b691b6
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/fpdt.asl
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [FPDT] Firmware Performance Data Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "FPDT"
+[0004] Table Length : 00000064
+[0001] Revision : 01
+[0001] Checksum : BD
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20110804
+
+
+[0002] Subtable Type : 0000
+[0001] Length : 30
+[0001] Revision : 01
+[0004] Reserved : 00000000
+[0008] Reset End : 0000000000000000
+[0008] Load Image Start : 0000000000000000
+[0008] Start Image Start : 0000000000000000
+[0008] Exit Services Entry : 0000000000000000
+[0008] Exit Services Exit : 0000000000000000
+
+[0002] Subtable Type : 0001
+[0001] Length : 10
+[0001] Revision : 01
+[0004] Reserved : 00000000
+[0008] S3PT Address : 0000000000000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl b/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl
new file mode 100644
index 0000000..ff2c08a
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [GTDT] Generic Timer Description Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "GTDT"
+[0004] Table Length : 00000050
+[0001] Revision : 01
+[0001] Checksum : F1
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20110623
+
+[0008] Timer Address : 0000000000000000
+[0004] Flags (decoded below) : 00000001
+ Memory Present : 1
+
+[0004] Secure PL1 Interrupt : 00000000
+[0004] SPL1 Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
+
+[0004] Non-Secure PL1 Interrupt : 00000000
+[0004] NSPL1 Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
+
+[0004] Virtual Timer Interrupt : 00000000
+[0004] VT Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
+
+[0004] Non-Secure PL2 Interrupt : 00000000
+[0004] NSPL2 Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
diff --git a/platforms/rtsm_ve-aemv8a.acpi/hest.asl b/platforms/rtsm_ve-aemv8a.acpi/hest.asl
new file mode 100644
index 0000000..05ddb24
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/hest.asl
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org
+ *
+ * [HEST] Hardware Error Source Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "HEST"
+[0004] Table Length : 000001D4
+[0001] Revision : 01
+[0001] Checksum : 20
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Error Source Count : 00000004
+
+[0002] Subtable Type : 0000 [IA-32 Machine Check Exception]
+[0002] Source Id : 0000
+[0002] Reserved1 : 0000
+[0001] Flags (decoded below) : 00
+ Firmware First : 0
+[0001] Enabled : 01
+[0004] Records To Preallocate : 00000001
+[0004] Max Sections Per Record : 00000001
+[0008] Global Capability Data : 0000000000000000
+[0008] Global Control Data : 0000000000000000
+[0001] Num Hardware Banks : 02
+[0007] Reserved2 : 00000000000000
+
+[0001] Bank Number : 00
+[0001] Clear Status On Init : 00
+[0001] Status Format : 00
+[0001] Reserved : 00
+[0004] Control Register : 00000000
+[0008] Control Data : 0000000000000000
+[0004] Status Register : 00000000
+[0004] Address Register : 00000000
+[0004] Misc Register : 00000000
+
+[0001] Bank Number : 01
+[0001] Clear Status On Init : 00
+[0001] Status Format : 00
+[0001] Reserved : 00
+[0004] Control Register : 00000000
+[0008] Control Data : 0000000000000000
+[0004] Status Register : 00000000
+[0004] Address Register : 00000000
+[0004] Misc Register : 00000000
+
+[0002] Subtable Type : 0001 [IA-32 Corrected Machine Check]
+[0002] Source Id : 0001
+[0002] Reserved1 : 0000
+[0001] Flags (decoded below) : 00
+ Firmware First : 0
+[0001] Enabled : 01
+[0004] Records To Preallocate : 00000001
+[0004] Max Sections Per Record : 00000001
+
+[0028] Notify : [Hardware Error Notification Structure]
+[0001] Notify Type : 00 [Polled]
+[0001] Notify Length : 00
+[0002] Configuration Write Enable : 0000
+[0004] PollInterval : 00000000
+[0004] Vector : 00000000
+[0004] Polling Threshold Value : 00000000
+[0004] Polling Threshold Window : 00000000
+[0004] Error Threshold Value : 00000000
+[0004] Error Threshold Window : 00000000
+
+[0001] Num Hardware Banks : 02
+[0003] Reserved2 : 000000
+
+[0001] Bank Number : 00
+[0001] Clear Status On Init : 00
+[0001] Status Format : 00
+[0001] Reserved : 00
+[0004] Control Register : 00000000
+[0008] Control Data : 0000000000000000
+[0004] Status Register : 00000000
+[0004] Address Register : 00000000
+[0004] Misc Register : 00000000
+
+[0001] Bank Number : 01
+[0001] Clear Status On Init : 00
+[0001] Status Format : 00
+[0001] Reserved : 00
+[0004] Control Register : 00000000
+[0008] Control Data : 0000000000000000
+[0004] Status Register : 00000000
+[0004] Address Register : 00000000
+[0004] Misc Register : 00000000
+
+[0002] Subtable Type : 0007 [PCI Express AER (AER Endpoint)]
+[0002] Source Id : 0000
+[0002] Reserved : 0000
+[0001] Flags (decoded below) : 00
+ Firmware First : 0
+[0001] Enabled : 01
+[0004] Records To Preallocate : 00000001
+[0004] Max Sections Per Record : 00000001
+[0004] Bus : 00000000
+[0002] Device : 0000
+[0002] Function : 0000
+[0002] DeviceControl : 0000
+[0002] Reserved : 0000
+[0004] Uncorrectable Mask : 00000000
+[0004] Uncorrectable Severity : 00000000
+[0004] Correctable Mask : 00000000
+[0004] Advanced Capabilities : 00000000
+
+[0002] Subtable Type : 0008 [PCI Express/PCI-X Bridge AER]
+[0002] Source Id : 0000
+[0002] Reserved : 0000
+[0001] Flags (decoded below) : 00
+ Firmware First : 0
+[0001] Enabled : 01
+[0004] Records To Preallocate : 00000001
+[0004] Max Sections Per Record : 00000001
+[0004] Bus : 00000000
+[0002] Device : 0000
+[0002] Function : 0000
+[0002] DeviceControl : 0000
+[0002] Reserved : 0000
+[0004] Uncorrectable Mask : 00000000
+[0004] Uncorrectable Severity : 00000000
+[0004] Correctable Mask : 00000000
+[0004] Advanced Capabilities : 00000000
+[0004] 2nd Uncorrectable Mask : 00000000
+[0004] 2nd Uncorrectable Severity : 00000000
+[0004] 2nd Advanced Capabilities : 00000000
+
+[0002] Subtable Type : 0009 [Generic Hardware Error Source]
+[0002] Source Id : 0002
+[0002] Related Source Id : FFFF
+[0001] Reserved : 00
+[0001] Enabled : 01
+[0004] Records To Preallocate : 00000001
+[0004] Max Sections Per Record : 00000001
+[0004] Max Raw Data Length : 00001000
+
+[0012] Error Status Address : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0028] Notify : [Hardware Error Notification Structure]
+[0001] Notify Type : 03 [SCI]
+[0001] Notify Length : 1C
+[0002] Configuration Write Enable : 0000
+[0004] PollInterval : 00000000
+[0004] Vector : 00000000
+[0004] Polling Threshold Value : 00000000
+[0004] Polling Threshold Window : 00000000
+[0004] Error Threshold Value : 00000000
+[0004] Error Threshold Window : 00000000
+
+[0004] Error Status Block Length : 00001000
+
+[0002] Subtable Type : 0009 [Generic Hardware Error Source]
+[0002] Source Id : 0003
+[0002] Related Source Id : 0000
+[0001] Reserved : 00
+[0001] Enabled : 01
+[0004] Records To Preallocate : 00000001
+[0004] Max Sections Per Record : 00000001
+[0004] Max Raw Data Length : 00001000
+
+[0012] Error Status Address : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0028] Notify : [Hardware Error Notification Structure]
+[0001] Notify Type : 04 [NMI]
+[0001] Notify Length : 1C
+[0002] Configuration Write Enable : 0000
+[0004] PollInterval : 00000000
+[0004] Vector : 00000000
+[0004] Polling Threshold Value : 00000000
+[0004] Polling Threshold Window : 00000000
+[0004] Error Threshold Value : 00000000
+[0004] Error Threshold Window : 00000000
+
+[0004] Error Status Block Length : 00001000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/hpet.asl b/platforms/rtsm_ve-aemv8a.acpi/hpet.asl
new file mode 100644
index 0000000..c150282
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/hpet.asl
@@ -0,0 +1,33 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [HPET] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "HPET" [High Precision Event Timer table]
+[0004] Table Length : 00000038
+[0001] Revision : 01
+[0001] Checksum : 09
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Hardware Block ID : 00000000
+
+[0012] Timer Block Register : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 00
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+[0001] Sequence Number : 00
+[0002] Minimum Clock Ticks : 0000
+[0001] Flags (decoded below) : 00
+ 4K Page Protect : 0
+ 64K Page Protect : 0
diff --git a/platforms/rtsm_ve-aemv8a.acpi/ivrs.asl b/platforms/rtsm_ve-aemv8a.acpi/ivrs.asl
new file mode 100644
index 0000000..9f64314
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/ivrs.asl
@@ -0,0 +1,86 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [IVRS] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "IVRS" [I/O Virtualization Reporting Structure]
+[0004] Table Length : 000000BC
+[0001] Revision : 01
+[0001] Checksum : 87
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Virtualization Info : 00000000
+[0008] Reserved : 0000000000000000
+
+[0001] Subtable Type : 10 [Hardware Definition Block]
+[0001] Flags : 14
+[0002] Length : 0034
+[0002] DeviceId : 0000
+
+[0002] Capability Offset : 0000
+[0008] Base Address : 0000000000000000
+[0002] PCI Segment Group : 0000
+[0002] Virtualization Info : 0000
+[0004] Reserved : 00000000
+
+[0001] Entry Type : 00
+[0002] Device ID : 0000
+[0001] Data Setting : 00
+
+[0001] Entry Type : 40
+[0002] Device ID : 0000
+[0001] Data Setting : 00
+[0004] Extended Data : 00000000
+
+[0001] Entry Type : 42
+[0002] Device ID : 0000
+[0001] Data Setting : 00
+[0001] Reserved : 00
+[0002] Source Used Device ID : 0000
+[0001] Reserved : 00
+
+[0001] Entry Type : 48
+[0002] Device ID : 0000
+[0001] Data Setting : 00
+[0001] Handle : 00
+[0002] Source Used Device ID : 0000
+[0001] Variety : 00
+
+[0001] Subtable Type : 20 [Memory Definition Block]
+[0001] Flags : 08
+[0002] Length : 0020
+[0002] DeviceId : 0000
+
+[0002] Auxiliary Data : 0000
+[0008] Reserved : 0000000000000000
+[0008] Start Address : 0000000000000000
+[0008] Memory Length : 0000000000000000
+
+[0001] Subtable Type : 21 [Memory Definition Block]
+[0001] Flags : 04
+[0002] Length : 0020
+[0002] DeviceId : 0000
+
+[0002] Auxiliary Data : 0000
+[0008] Reserved : 0000000000000000
+[0008] Start Address : 0000000000000000
+[0008] Memory Length : 0000000000000000
+
+[0001] Subtable Type : 10 [Hardware Definition Block]
+[0001] Flags : 14
+[0002] Length : 0018
+[0002] DeviceId : 0000
+
+[0002] Capability Offset : 0000
+[0008] Base Address : 0000000000000000
+[0002] PCI Segment Group : 0000
+[0002] Virtualization Info : 0000
+[0004] Reserved : 00000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/mcfg.asl b/platforms/rtsm_ve-aemv8a.acpi/mcfg.asl
new file mode 100644
index 0000000..cee9d6f
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/mcfg.asl
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [MCFG] PCIe Memory Mapped Configuration Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "MCFG"
+[0004] Table Length : 0000003C
+[0001] Revision : 01
+[0001] Checksum : 19
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0008] Reserved : 0000000000000000
+
+[0008] Base Address : 0000000000000000
+[0002] Segment Group Number : 0000
+[0001] Start Bus Number : 00
+[0001] End Bus Number : 00
+[0004] Reserved : 00000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/mchi.asl b/platforms/rtsm_ve-aemv8a.acpi/mchi.asl
new file mode 100644
index 0000000..2154c51
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/mchi.asl
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [MCHI] Management Controller Host Interface Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "MCHI"
+[0004] Table Length : 00000045
+[0001] Revision : 01
+[0001] Checksum : E4
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 02000715
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0001] Interface Type : 01
+[0001] Protocol : 00
+[0008] Protocol Data : 0000000000000000
+[0001] Interrupt Type : 00
+[0001] Gpe : 00
+[0001] Pci Device Flag : 00
+[0004] Global Interrupt : 00000000
+
+[0012] Control Register : [Generic Address Structure]
+[0001] Space ID : 02 [PCI_Config]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+[0001] Pci Segment : 00
+[0001] Pci Bus : 00
+[0001] Pci Device : 00
+[0001] Pci Function : 00
diff --git a/platforms/rtsm_ve-aemv8a.acpi/mpst.asl b/platforms/rtsm_ve-aemv8a.acpi/mpst.asl
new file mode 100644
index 0000000..1c6933b
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/mpst.asl
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [MPST] Memory Power State Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "MPST"
+[0004] Table Length : 000000B6
+[0001] Revision : 01
+[0001] Checksum : 77
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20120913
+
+[0001] Channel ID : 00
+[0003] Reserved : 000000
+[0002] Power Node Count : 0002
+[0002] Reserved : 0000
+
+[0001] Flags (decoded below) : 00
+ Node Enabled : 0
+ Power Managed : 0
+ Hot Plug Capable : 0
+[0001] Reserved : 00
+[0002] Node ID : 0000
+[0004] Length : 00000000
+[0008] Range Address : 0000000000000000
+[0008] Range Length : 0000000000000000
+[0004] Num Power States : 00000002
+[0004] Num Physical Components : 00000003
+
+[0001] Power State : 00
+[0001] InfoIndex : 00
+
+[0001] Power State : 00
+[0001] InfoIndex : 00
+
+[0002] Component Id : 0000
+[0002] Component Id : 0001
+[0002] Component Id : 0002
+
+[0001] Flags (decoded below) : 00
+ Node Enabled : 0
+ Power Managed : 0
+ Hot Plug Capable : 0
+[0001] Reserved : 00
+[0002] Node ID : 0000
+[0004] Length : 00000000
+[0008] Range Address : 0000000000000000
+[0008] Range Length : 0000000000000000
+[0004] Num Power States : 00000001
+[0004] Num Physical Components : 00000001
+
+[0001] Power State : 00
+[0001] InfoIndex : 00
+
+[0002] Component Id : 0000
+
+[0002] Characteristics Count : 0002
+[0002] Reserved : 0000
+
+[0001] Structure ID : 01
+[0001] Flags (decoded below) : 00
+ Memory Preserved : 0
+ Auto Entry : 0
+ Auto Exit : 0
+[0002] Reserved : 0000
+[0004] Average Power : 00000000
+[0004] Power Saving : 00000000
+[0008] Exit Latency : 0000000000000000
+[0008] Reserved : 0000000000000000
+
+[0001] Structure ID : 01
+[0001] Flags (decoded below) : 00
+ Memory Preserved : 0
+ Auto Entry : 0
+ Auto Exit : 0
+[0002] Reserved : 0000
+[0004] Average Power : 00000000
+[0004] Power Saving : 00000000
+[0008] Exit Latency : 0000000000000000
+[0008] Reserved : 0000000000000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/msct.asl b/platforms/rtsm_ve-aemv8a.acpi/msct.asl
new file mode 100644
index 0000000..dcaf33f
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/msct.asl
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [MSCT] Maximum System Characteristics Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "MSCT"
+[0004] Table Length : 00000090
+[0001] Revision : 01
+[0001] Checksum : B7
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Proximity Offset : 00000038
+[0004] Max Proximity Domains : 00000003
+[0004] Max Clock Domains : 00000000
+[0008] Max Physical Address : 00000FFFFFFFFFFF
+
+[0001] Revision : 01
+[0001] Length : 16
+[0004] Domain Range Start : 00000000
+[0004] Domain Range End : 00000003
+[0004] Processor Capacity : 00000010
+[0008] Memory Capacity : 0000004000000000
+
+[0001] Revision : 01
+[0001] Length : 16
+[0004] Domain Range Start : 00000000
+[0004] Domain Range End : 00000000
+[0004] Processor Capacity : 00000000
+[0008] Memory Capacity : 0000000000000000
+
+[0001] Revision : 01
+[0001] Length : 16
+[0004] Domain Range Start : 00000000
+[0004] Domain Range End : 00000000
+[0004] Processor Capacity : 00000000
+[0008] Memory Capacity : 0000000000000000
+
+[0001] Revision : 01
+[0001] Length : 16
+[0004] Domain Range Start : 00000000
+[0004] Domain Range End : 00000000
+[0004] Processor Capacity : 00000000
+[0008] Memory Capacity : 0000000000000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/oem0.asl b/platforms/rtsm_ve-aemv8a.acpi/oem0.asl
new file mode 100644
index 0000000..570ea27
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/oem0.asl
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [OEMx] OEM Specific Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "OEM0"
+[0004] Table Length : 00000024
+[0001] Revision : 01
+[0001] Checksum : 8B
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 0000000A
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
diff --git a/platforms/rtsm_ve-aemv8a.acpi/pmtt.asl b/platforms/rtsm_ve-aemv8a.acpi/pmtt.asl
new file mode 100644
index 0000000..a9c5c93
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/pmtt.asl
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [PMTT] Platform Memory Topology Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "PMTT"
+[0004] Table Length : 000000B4
+[0001] Revision : 01
+[0001] Checksum : 3A
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20110826
+
+[0004] Reserved : 00000000
+
+[0001] Subtable Type : 00 [Socket]
+[0001] Reserved : 00
+[0002] Length : 0080
+[0002] Flags (decoded below) : 0001
+ Top-level Device : 1
+ Physical Element : 0
+ Memory Type : 0
+[0002] Reserved : 0000
+[0002] Socket ID : 0000
+[0002] Reserved : 0000
+
+[0001] Subtable Type : 01 [Memory Controller]
+[0001] Reserved : 00
+[0002] Length : 0054
+[0002] Flags (decoded below) : 0005
+ Top-level Device : 1
+ Physical Element : 0
+ Memory Type : 1
+[0002] Reserved : 0000
+[0004] Read Latency : 00000000
+[0004] Write Latency : 00000000
+[0004] Read Bandwidth : 00000000
+[0004] Write Bandwidth : 00000000
+[0002] Access Width : 0000
+[0002] Alignment : 0000
+[0002] Reserved : 0000
+[0002] Domain Count : 0003
+[0004] Proximity Domain : 00000000
+[0004] Proximity Domain : 00000000
+[0004] Proximity Domain : 00000000
+
+[0001] Subtable Type : 02 [Physical Component (DIMM)]
+[0001] Reserved : 00
+[0002] Length : 0014
+[0002] Flags (decoded below) : 0002
+ Top-level Device : 0
+ Physical Element : 1
+ Memory Type : 0
+[0002] Reserved : 0000
+[0002] Component ID : 0000
+[0002] Reserved : 0000
+[0004] Memory Size : 00000000
+[0004] Bios Handle : 00000000
+
+[0001] Subtable Type : 02 [Physical Component (DIMM)]
+[0001] Reserved : 00
+[0002] Length : 0014
+[0002] Flags (decoded below) : 0002
+ Top-level Device : 0
+ Physical Element : 1
+ Memory Type : 0
+[0002] Reserved : 0000
+[0002] Component ID : 0000
+[0002] Reserved : 0000
+[0004] Memory Size : 00000000
+[0004] Bios Handle : 00000000
+
+[0001] Subtable Type : 01 [Memory Controller]
+[0001] Reserved : 00
+[0002] Length : 0020
+[0002] Flags (decoded below) : 0001
+ Top-level Device : 1
+ Physical Element : 0
+ Memory Type : 0
+[0002] Reserved : 0000
+[0004] Read Latency : 00000000
+[0004] Write Latency : 00000000
+[0004] Read Bandwidth : 00000000
+[0004] Write Bandwidth : 00000000
+[0002] Access Width : 0000
+[0002] Alignment : 0000
+[0002] Reserved : 0000
+[0002] Domain Count : 0000
+
+[0001] Subtable Type : 00 [Socket]
+[0001] Reserved : 00
+[0002] Length : 000C
+[0002] Flags (decoded below) : 0001
+ Top-level Device : 1
+ Physical Element : 0
+ Memory Type : 0
+[0002] Reserved : 0000
+[0002] Socket ID : 0000
+[0002] Reserved : 0000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/rsdp.asl b/platforms/rtsm_ve-aemv8a.acpi/rsdp.asl
new file mode 100644
index 0000000..3460a77
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/rsdp.asl
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [RSDP] ACPI Table
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0008] Signature : "RSD PTR "
+[0001] Checksum : 43
+[0006] Oem ID : "LINARO"
+[0001] Revision : 02
+[0004] RSDT Address : 00000000
+[0004] Length : 00000024
+[0008] XSDT Address : 0000000000000000
+[0001] Extended Checksum : DC
+[0003] Reserved : 000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest b/platforms/rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest
new file mode 100644
index 0000000..6b3a743
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest
@@ -0,0 +1,34 @@
+#
+# Each line is either a comment, white space, or two fields:
+#
+# <signature> : <ASL file name>
+#
+# NB: for each file x.asl, an AML file called x.aml will be created
+#
+
+rsdp: rsdp.asl
+xsdt: xsdt.asl
+facp: facp.asl
+dsdt: dsdt.asl
+ssdt: ssdt0.asl
+bert: bert.asl
+ecdt: ecdt.asl
+facs: facs.asl
+gtdt: gtdt.asl
+hest: hest.asl
+apic: apic.asl
+mcfg: mcfg.asl
+mpst: mpst.asl
+oem: oem0.asl
+pmmt: pmmt.asl
+slit: slit.asl
+spmi: spmi.asl
+srat: srat.asl
+uefi: uefi.asl
+cpep: cpep.asl
+einj: einj.asl
+erst: erst.asl
+fpdt: fpdt.asl
+mchi: mchi.asl
+msct: msct.asl
+
diff --git a/platforms/rtsm_ve-aemv8a.acpi/s3pt.asl b/platforms/rtsm_ve-aemv8a.acpi/s3pt.asl
new file mode 100644
index 0000000..694caf7
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/s3pt.asl
@@ -0,0 +1,26 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [S3PT] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "S3PT" [S3 Performance Table]
+[0004] Length : 00000034
+
+[0002] Type : 0000
+[0001] Length : 18
+[0001] Revision : 01
+
+[0004] Resume Count : 00000000
+[0008] Full Resume : 0000000000000000
+[0008] Average Resume : 0000000000000000
+
+[0002] Type : 0001
+[0001] Length : 14
+[0001] Revision : 01
+
+[0008] Suspend Start : 0000000000000000
+[0008] Suspend End : 0000000000000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/sbst.asl b/platforms/rtsm_ve-aemv8a.acpi/sbst.asl
new file mode 100644
index 0000000..714b15f
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/sbst.asl
@@ -0,0 +1,22 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [SBST] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "SBST" [Smart Battery Specification Table]
+[0004] Table Length : 00000030
+[0001] Revision : 01
+[0001] Checksum : 06
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Warning Level : 00000000
+[0004] Low Level : 00000000
+[0004] Critical Level : 00000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/slic.asl b/platforms/rtsm_ve-aemv8a.acpi/slic.asl
new file mode 100644
index 0000000..df77bf2
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/slic.asl
@@ -0,0 +1,56 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [SLIC] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "SLIC" [Software Licensing Description Table]
+[0004] Table Length : 00000176
+[0001] Revision : 01
+[0001] Checksum : 07
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20110211
+
+
+[0004] Subtable Type : 00000000 [Public Key Structure]
+[0004] Length : 0000009C
+
+[0001] Key Type : 06
+[0001] Version : 02
+[0002] Reserved : 0000
+[0004] Algorithm : 00002400
+[0004] Magic : "RSA1"
+[0004] BitLength : 00000400
+[0004] Exponent : 00000000
+[0128] Modulus : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+[0004] Subtable Type : 00000001 [Windows Marker Structure]
+[0004] Length : 000000B6
+
+[0004] Version : 00020000
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0008] Windows Flag : "WINDOWS "
+[0004] SLIC Version : 00020001
+[0016] Reserved : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+[0128] Signature : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/platforms/rtsm_ve-aemv8a.acpi/slit.asl b/platforms/rtsm_ve-aemv8a.acpi/slit.asl
new file mode 100644
index 0000000..c34e4bb
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/slit.asl
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [SLIT] System Locality Information Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "SLIT"
+[0004] Table Length : 000001BC
+[0001] Revision : 01
+[0001] Checksum : 00
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20110316
+
+[0008] Localities : 0000000000000014
+[0020] Locality 0 : 0A 10 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 \
+ 24 25 26 27
+[0020] Locality 1 : 10 0A 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 \
+ 23 24 25 26
+[0020] Locality 2 : 16 15 0A 10 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 \
+ 22 23 24 25
+[0020] Locality 3 : 17 16 10 0A 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 \
+ 21 22 23 24
+[0020] Locality 4 : 18 17 16 15 0A 10 16 17 18 19 1A 1B 1C 1D 1E 1F \
+ 20 21 22 23
+[0020] Locality 5 : 19 18 17 16 10 0A 15 16 17 18 19 1A 1B 1C 1D 1E \
+ 1F 20 21 22
+[0020] Locality 6 : 1A 19 18 17 16 15 0A 10 16 17 18 19 1A 1B 1C 1D \
+ 1E 1F 20 21
+[0020] Locality 7 : 1B 1A 19 18 17 16 10 0A 15 16 17 18 19 1A 1B 1C \
+ 1D 1E 1F 20
+[0020] Locality 8 : 1C 1B 1A 19 18 17 16 15 0A 10 16 17 18 19 1A 1B \
+ 1C 1D 1E 1F
+[0020] Locality 9 : 1D 1C 1B 1A 19 18 17 16 10 0A 15 16 17 18 19 1A \
+ 1B 1C 1D 1E
+[0020] Locality 10 : 1E 1D 1C 1B 1A 19 18 17 16 15 0A 10 16 17 18 19 \
+ 1A 1B 1C 1D
+[0020] Locality 11 : 1F 1E 1D 1C 1B 1A 19 18 17 16 10 0A 15 16 17 18 \
+ 19 1A 1B 1C
+[0020] Locality 12 : 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 0A 10 16 17 \
+ 18 19 1A 1B
+[0020] Locality 13 : 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 10 0A 15 16 \
+ 17 18 19 1A
+[0020] Locality 14 : 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 0A 10 \
+ 16 17 18 19
+[0020] Locality 15 : 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 10 0A \
+ 15 16 17 18
+[0020] Locality 16 : 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 \
+ 0A 10 16 17
+[0020] Locality 17 : 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 \
+ 10 0A 15 16
+[0020] Locality 18 : 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 \
+ 16 15 0A 10
+[0020] Locality 19 : 27 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 \
+ 17 16 10 0A
diff --git a/platforms/rtsm_ve-aemv8a.acpi/spcr.asl b/platforms/rtsm_ve-aemv8a.acpi/spcr.asl
new file mode 100644
index 0000000..7998ba8
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/spcr.asl
@@ -0,0 +1,46 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [SPCR] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "SPCR" [Serial Port Console Redirection table]
+[0004] Table Length : 00000050
+[0001] Revision : 01
+[0001] Checksum : E3
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0001] Interface Type : 00
+[0003] Reserved : 000000
+
+[0012] Serial Port Register : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+[0001] Interrupt Type : 00
+[0001] PCAT-compatible IRQ : 00
+[0004] Interrupt : 00000000
+[0001] Baud Rate : 00
+[0001] Parity : 00
+[0001] Stop Bits : 00
+[0001] Flow Control : 00
+[0001] Terminal Type : 00
+[0001] Reserved : 00
+[0002] PCI Device ID : 0000
+[0002] PCI Vendor ID : 0000
+[0001] PCI Bus : 00
+[0001] PCI Device : 00
+[0001] PCI Function : 00
+[0004] PCI Flags : 00000000
+[0001] PCI Segment : 00
+[0004] Reserved : 00000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/spmi.asl b/platforms/rtsm_ve-aemv8a.acpi/spmi.asl
new file mode 100644
index 0000000..a9f244d
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/spmi.asl
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org
+ *
+ * [SPMI] Server Platform Management Interface Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "SPMI"
+[0004] Table Length : 00000041
+[0001] Revision : 04
+[0001] Checksum : ED
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0001] Interface Type : 00
+[0001] Reserved : 00
+[0002] IPMI Spec Version : 0000
+[0001] Interrupt Type : 00
+[0001] GPE Number : 00
+[0001] Reserved : 00
+[0001] PCI Device Flag : 00
+[0004] Interrupt : 00000000
+
+[0012] IPMI Register : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 01 [Byte Access:8]
+[0008] Address : 0000000000000000
+
+[0001] PCI Segment : 00
+[0001] PCI Bus : 00
+[0001] PCI Device : 00
+[0001] PCI Function : 00
+[0001] Reserved : 00
diff --git a/platforms/rtsm_ve-aemv8a.acpi/srat.asl b/platforms/rtsm_ve-aemv8a.acpi/srat.asl
new file mode 100644
index 0000000..6d549c3
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/srat.asl
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [SRAT] System Resource Affinity Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "SRAT"
+[0004] Table Length : 00000080
+[0001] Revision : 03
+[0001] Checksum : 5A
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Table Revision : 00000001
+[0008] Reserved : 0000000000000000
+
+[0001] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[0001] Length : 10
+
+[0001] Proximity Domain Low(8) : 00
+[0001] Apic ID : 00
+[0004] Flags (decoded below) : 00000001
+ Enabled : 1
+[0001] Local Sapic EID : 00
+[0003] Proximity Domain High(24) : 000000
+[0004] Reserved : 00000000
+
+[0001] Subtable Type : 01 [Memory Affinity]
+[0001] Length : 28
+
+[0004] Proximity Domain : 00000000
+[0002] Reserved1 : 0000
+[0008] Base Address : 0000000000000000
+[0008] Address Length : 000000000009FC00
+[0004] Reserved2 : 00000000
+[0004] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0008] Reserved3 : 0000000000000000
+
+[0001] Subtable Type : 02 [Processor Local x2APIC Affinity]
+[0001] Length : 18
+
+[0002] Reserved1 : 0000
+[0004] Proximity Domain : 00000000
+[0004] Apic ID : 00000000
+[0004] Flags (decoded below) : 00000001
+ Enabled : 1
+[0004] Clock Domain : 00000000
+[0004] Reserved2 : 00000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl b/platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl
new file mode 100644
index 0000000..8975977
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [SSDT] Description of the Arndale board (exynos5250) GPIO structure
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+DefinitionBlock (
+ "ssdt0.aml", // output filename
+ "SSDT", // table signature
+ 2, // SSDT compliance revision
+ "LINARO", // OEM ID
+ "RTSMVEV8", // table ID
+ 0x00000001) // OEM revision
+{
+}
diff --git a/platforms/rtsm_ve-aemv8a.acpi/tcpa.asl b/platforms/rtsm_ve-aemv8a.acpi/tcpa.asl
new file mode 100644
index 0000000..cfdfa39
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/tcpa.asl
@@ -0,0 +1,22 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [TCPA] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "TCPA" [Trusted Computing Platform Alliance table]
+[0004] Table Length : 00000032
+[0001] Revision : 01
+[0001] Checksum : 67
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00003180
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0002] Reserved : 0000
+[0004] Max Event Log Length : 00000000
+[0008] Event Log Address : 0000000000000001
diff --git a/platforms/rtsm_ve-aemv8a.acpi/tpm2.asl b/platforms/rtsm_ve-aemv8a.acpi/tpm2.asl
new file mode 100644
index 0000000..38cc502
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/tpm2.asl
@@ -0,0 +1,22 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [TPM2] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "TPM2" [Trusted Platform Module hardware interface table]
+[0004] Table Length : 00000034
+[0001] Revision : 03
+[0001] Checksum : 42
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20121114
+
+[0004] Flags : 00000000
+[0008] Control Address : 0011223344556677
+[0004] Start Method : 00000001
diff --git a/platforms/rtsm_ve-aemv8a.acpi/uefi.asl b/platforms/rtsm_ve-aemv8a.acpi/uefi.asl
new file mode 100644
index 0000000..855e330
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/uefi.asl
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [UEFI] UEFI Boot Optimization Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "UEFI"
+[0004] Table Length : 00000036
+[0001] Revision : 01
+[0001] Checksum : 9B
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0016] UUID Identifier : 03020100-0504-0706-0809-0A0B0C0D0E0F
+[0002] Data Offset : 0000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/waet.asl b/platforms/rtsm_ve-aemv8a.acpi/waet.asl
new file mode 100644
index 0000000..b459110
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/waet.asl
@@ -0,0 +1,22 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [WAET] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "WAET" [Windows ACPI Emulated Devices Table]
+[0004] Table Length : 00000028
+[0001] Revision : 01
+[0001] Checksum : 19
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Flags (decoded below) : 00000000
+ RTC needs no INT ack : 0
+ PM timer, one read only : 0
diff --git a/platforms/rtsm_ve-aemv8a.acpi/wdat.asl b/platforms/rtsm_ve-aemv8a.acpi/wdat.asl
new file mode 100644
index 0000000..e49205a
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/wdat.asl
@@ -0,0 +1,47 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [WDAT] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "WDAT" [Watchdog Action Table]
+[0004] Table Length : 0000005C
+[0001] Revision : 01
+[0001] Checksum : E3
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Header Length : 00000020
+[0002] PCI Segment : 00FF
+[0001] PCI Bus : FF
+[0001] PCI Device : FF
+[0001] PCI Function : FF
+[0003] Reserved : 000000
+[0004] Timer Period : 00000258
+[0004] Max Count : 000003FF
+[0004] Min Count : 00000002
+[0001] Flags (decoded below) : 00
+ Enabled : 0
+ Stopped When Asleep : 0
+[0003] Reserved : 000000
+[0004] Watchdog Entry Count : 0000000E
+
+[0001] Watchdog Action : 01
+[0001] Instruction : 02
+[0002] Reserved : 0000
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 10
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 02 [Word Access:16]
+[0008] Address : 0000000000000460
+
+[0004] Value : 00000001
+[0004] Register Mask : 00000001
diff --git a/platforms/rtsm_ve-aemv8a.acpi/wddt.asl b/platforms/rtsm_ve-aemv8a.acpi/wddt.asl
new file mode 100644
index 0000000..a0b039e
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/wddt.asl
@@ -0,0 +1,44 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [WDDT] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "WDDT" [Watchdog Description Table]
+[0004] Table Length : 00000040
+[0001] Revision : 01
+[0001] Checksum : 00
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0002] Specification Version : 0000
+[0002] Table Version : 0000
+[0002] PCI Vendor ID : 0000
+
+[0012] Timer Register : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : FF
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+[0002] Max Count : 0000
+[0002] Min Count : 0000
+[0002] Period : 0000
+[0002] Status (decoded below) : 0000
+ Available : 0
+ Active : 0
+ OS Owns : 0
+ User Reset : 0
+ Timeout Reset : 0
+ Power Fail Reset : 0
+ Unknown Reset : 0
+[0002] Capability (decoded below) : 0000
+ Auto Reset : 0
+ Timeout Alert : 0
diff --git a/platforms/rtsm_ve-aemv8a.acpi/wdrt.asl b/platforms/rtsm_ve-aemv8a.acpi/wdrt.asl
new file mode 100644
index 0000000..14453c7
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/wdrt.asl
@@ -0,0 +1,42 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [WDRT] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "WDRT" [Watchdog Resource Table]
+[0004] Table Length : 00000047
+[0001] Revision : 01
+[0001] Checksum : B0
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+
+[0012] Control Register : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 20
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+[0012] Count Register : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 20
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+[0002] PCI Device ID : FFFF
+[0002] PCI Vendor ID : FFFF
+[0001] PCI Bus : 00
+[0001] PCI Device : 00
+[0001] PCI Function : 00
+[0001] PCI Segment : 00
+[0002] Max Count : FFFF
+[0001] Counter Units : 00
diff --git a/platforms/rtsm_ve-aemv8a.acpi/xsdt.asl b/platforms/rtsm_ve-aemv8a.acpi/xsdt.asl
new file mode 100644
index 0000000..74f0c70
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/xsdt.asl
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [XSDT] Extended System Description Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "XSDT"
+[0004] Table Length : 00000064
+[0001] Revision : 01
+[0001] Checksum : 8B
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000014
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0008] ACPI Table Address 0 : 0000000000000010
+[0008] ACPI Table Address 0 : 0000000000000020
+[0008] ACPI Table Address 0 : 0000000000000030
+[0008] ACPI Table Address 0 : 0000000000000040
+[0008] ACPI Table Address 0 : 0000000000000050
+[0008] ACPI Table Address 0 : 0000000000000060
+[0008] ACPI Table Address 0 : 0000000000000070
+[0008] ACPI Table Address 0 : 0000000000000080
+[0008] ACPI Table Address 0 : 0000000000000090
+[0008] ACPI Table Address 0 : 00000000000000A0
+[0008] ACPI Table Address 0 : 00000000000000B0
+[0008] ACPI Table Address 0 : 00000000000000C0
+[0008] ACPI Table Address 0 : 00000000000000D0
+[0008] ACPI Table Address 0 : 00000000000000E0
+[0008] ACPI Table Address 0 : 00000000000000F0
+[0008] ACPI Table Address 0 : 0000000000000100
+[0008] ACPI Table Address 0 : 0000000000000110
+[0008] ACPI Table Address 0 : 0000000000000120
+[0008] ACPI Table Address 0 : 0000000000000130
+[0008] ACPI Table Address 0 : 0000000000000140
--
1.7.10.4
11 years, 8 months
- 2
- 1
[PATCH] arm64: configs: acpi add missing devices for booting RTSM VE model.
by Graeme Gregory
As well as devices for foundation model VE model also reguires
regulator, and MMC drivers.
Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org>
---
arch/arm64/configs/acpi_defconfig | 32 ++++++++++++++++++++++++++++++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/configs/acpi_defconfig b/arch/arm64/configs/acpi_defconfig
index 222e051..d2804a5 100644
--- a/arch/arm64/configs/acpi_defconfig
+++ b/arch/arm64/configs/acpi_defconfig
@@ -389,6 +389,7 @@ CONFIG_NET_FLOW_LIMIT=y
# CONFIG_WIRELESS is not set
# CONFIG_WIMAX is not set
# CONFIG_RFKILL is not set
+# CONFIG_RFKILL_REGULATOR is not set
# CONFIG_NET_9P is not set
# CONFIG_CAIF is not set
# CONFIG_CEPH_LIB is not set
@@ -824,7 +825,14 @@ CONFIG_BCMA_POSSIBLE=y
# CONFIG_MFD_TPS65912 is not set
# CONFIG_MFD_TMIO is not set
CONFIG_VEXPRESS_CONFIG=y
-# CONFIG_REGULATOR is not set
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_DUMMY is not set
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_GPIO is not set
+CONFIG_REGULATOR_VEXPRESS=y
# CONFIG_MEDIA_SUPPORT is not set
#
@@ -941,7 +949,27 @@ CONFIG_HID_MONTEREY=y
# CONFIG_HID_ZYDACRON is not set
# CONFIG_HID_SENSOR_HUB is not set
# CONFIG_USB_SUPPORT is not set
-# CONFIG_MMC is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+# CONFIG_MMC_CLKGATE is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_ARMMMCI=y
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_SDHCI_PXAV3 is not set
+# CONFIG_MMC_SDHCI_PXAV2 is not set
# CONFIG_MEMSTICK is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_ACCESSIBILITY is not set
--
1.7.10.4
11 years, 8 months
- 1
- 0
[PATCH] arm64: configs: add acpi_defconfig
by Graeme Gregory
This contains the config required to boot kernel with acpi enabled for
arm64
Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org>
---
arch/arm64/configs/acpi_defconfig | 1445 +++++++++++++++++++++++++++++++++++++
1 file changed, 1445 insertions(+)
create mode 100644 arch/arm64/configs/acpi_defconfig
diff --git a/arch/arm64/configs/acpi_defconfig b/arch/arm64/configs/acpi_defconfig
new file mode 100644
index 0000000..222e051
--- /dev/null
+++ b/arch/arm64/configs/acpi_defconfig
@@ -0,0 +1,1445 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/arm64 3.11.0-rc5 Kernel Configuration
+#
+CONFIG_ARM64=y
+CONFIG_64BIT=y
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
+CONFIG_MMU=y
+CONFIG_NO_IOPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA32=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_SWIOTLB=y
+CONFIG_IOMMU_HELPER=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_IRQ_WORK=y
+CONFIG_BUILDTIME_EXTABLE_SORT=y
+
+#
+# General setup
+#
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+# CONFIG_COMPILE_TEST is not set
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_DEFAULT_HOSTNAME="(none)"
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_FHANDLE is not set
+# CONFIG_AUDIT is not set
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_IRQ_DOMAIN=y
+# CONFIG_IRQ_DOMAIN_DEBUG is not set
+CONFIG_SPARSE_IRQ=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+
+#
+# Timers subsystem
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ_COMMON=y
+# CONFIG_HZ_PERIODIC is not set
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+
+#
+# CPU/Task time and stats accounting
+#
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_RCU_FANOUT=64
+CONFIG_RCU_FANOUT_LEAF=16
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_RCU_FAST_NO_HZ is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_RCU_NOCB_CPU is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+# CONFIG_CGROUP_FREEZER is not set
+# CONFIG_CGROUP_DEVICE is not set
+# CONFIG_CPUSETS is not set
+# CONFIG_CGROUP_CPUACCT is not set
+# CONFIG_RESOURCE_COUNTERS is not set
+# CONFIG_CGROUP_PERF is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_CFS_BANDWIDTH is not set
+# CONFIG_RT_GROUP_SCHED is not set
+# CONFIG_BLK_CGROUP is not set
+# CONFIG_CHECKPOINT_RESTORE is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+CONFIG_UIDGID_CONVERTED=y
+# CONFIG_UIDGID_STRICT_TYPE_CHECKS is not set
+CONFIG_SCHED_AUTOGROUP=y
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+CONFIG_RD_LZ4=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_HAVE_UID16=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+# CONFIG_EXPERT is not set
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+# CONFIG_EMBEDDED is not set
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_PERF_EVENTS=y
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+CONFIG_SLUB_CPU_PARTIAL=y
+CONFIG_PROFILING=y
+CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
+CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_COMPAT_OLD_SIGACTION=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_MODULE_SIG is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_BLOCK_COMPAT=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+CONFIG_INLINE_READ_UNLOCK=y
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+CONFIG_INLINE_WRITE_UNLOCK=y
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+# CONFIG_FREEZER is not set
+
+#
+# Platform selection
+#
+CONFIG_ARCH_VEXPRESS=y
+# CONFIG_ARCH_XGENE is not set
+
+#
+# Bus support
+#
+CONFIG_ARM_AMBA=y
+
+#
+# Kernel Features
+#
+# CONFIG_ARM64_64K_PAGES is not set
+CONFIG_SMP=y
+CONFIG_ARM64_CPU_TOPOLOGY=y
+# CONFIG_SCHED_MC is not set
+# CONFIG_SCHED_SMT is not set
+CONFIG_NR_CPUS=4
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HW_PERF_EVENTS=y
+CONFIG_SYS_SUPPORTS_HUGETLBFS=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM=y
+CONFIG_HAVE_MEMORY_PRESENT=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_NO_BOOTMEM=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_COMPACTION=y
+CONFIG_MIGRATION=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_TRANSPARENT_HUGEPAGE is not set
+CONFIG_CROSS_MEMORY_ATTACH=y
+# CONFIG_CLEANCACHE is not set
+# CONFIG_ZBUD is not set
+# CONFIG_XEN is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+
+#
+# Boot options
+#
+CONFIG_CMDLINE="console=ttyAMA0"
+# CONFIG_CMDLINE_FORCE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_COMPAT_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_BINFMT_SCRIPT=y
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_COREDUMP=y
+CONFIG_COMPAT=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_DIAG is not set
+CONFIG_UNIX=y
+# CONFIG_UNIX_DIAG is not set
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+# CONFIG_NET_IP_TUNNEL is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_NET_IPVTI is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_INET_UDP_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+# CONFIG_BRIDGE is not set
+CONFIG_HAVE_NET_DSA=y
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_OPENVSWITCH is not set
+# CONFIG_VSOCKETS is not set
+# CONFIG_NETLINK_MMAP is not set
+# CONFIG_NETLINK_DIAG is not set
+# CONFIG_NET_MPLS_GSO is not set
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_XPS=y
+# CONFIG_NETPRIO_CGROUP is not set
+CONFIG_NET_RX_BUSY_POLL=y
+CONFIG_BQL=y
+CONFIG_NET_FLOW_LIMIT=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+# CONFIG_NFC is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+CONFIG_FW_LOADER_USER_HELPER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_GENERIC_CPU_DEVICES is not set
+# CONFIG_DMA_SHARED_BUFFER is not set
+
+#
+# Bus devices
+#
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+CONFIG_DTC=y
+CONFIG_OF=y
+
+#
+# Device Tree and Open Firmware support
+#
+# CONFIG_PROC_DEVICETREE is not set
+# CONFIG_OF_SELFTEST is not set
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_NET=y
+# CONFIG_PARPORT is not set
+CONFIG_PNP=y
+CONFIG_PNP_DEBUG_MESSAGES=y
+
+#
+# Protocols
+#
+CONFIG_PNPACPI=y
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_DRBD is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_VIRTIO_BLK=y
+# CONFIG_BLK_DEV_RBD is not set
+
+#
+# Misc devices
+#
+# CONFIG_SENSORS_LIS3LV02D is not set
+# CONFIG_ATMEL_PWM is not set
+# CONFIG_DUMMY_IRQ is not set
+# CONFIG_ATMEL_SSC is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_SRAM is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_93CX6 is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_TI_ST is not set
+
+#
+# Altera FPGA firmware download module
+#
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_TARGET_CORE is not set
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_NET_CORE=y
+# CONFIG_BONDING is not set
+# CONFIG_DUMMY is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_NET_TEAM is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_VXLAN is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_VIRTIO_NET is not set
+# CONFIG_NLMON is not set
+
+#
+# CAIF transport drivers
+#
+
+#
+# Distributed Switch Architecture drivers
+#
+# CONFIG_NET_DSA_MV88E6XXX is not set
+# CONFIG_NET_DSA_MV88E6060 is not set
+# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set
+# CONFIG_NET_DSA_MV88E6131 is not set
+# CONFIG_NET_DSA_MV88E6123_61_65 is not set
+CONFIG_ETHERNET=y
+CONFIG_NET_VENDOR_ARC=y
+# CONFIG_ARC_EMAC is not set
+CONFIG_NET_CADENCE=y
+# CONFIG_ARM_AT91_ETHER is not set
+# CONFIG_MACB is not set
+CONFIG_NET_VENDOR_BROADCOM=y
+# CONFIG_B44 is not set
+# CONFIG_NET_CALXEDA_XGMAC is not set
+# CONFIG_DNET is not set
+CONFIG_NET_VENDOR_INTEL=y
+CONFIG_NET_VENDOR_I825XX=y
+CONFIG_NET_VENDOR_MARVELL=y
+# CONFIG_MVMDIO is not set
+CONFIG_NET_VENDOR_MICREL=y
+# CONFIG_KS8851_MLL is not set
+CONFIG_NET_VENDOR_NATSEMI=y
+CONFIG_NET_VENDOR_8390=y
+# CONFIG_ETHOC is not set
+# CONFIG_SH_ETH is not set
+CONFIG_NET_VENDOR_SEEQ=y
+CONFIG_NET_VENDOR_SMSC=y
+CONFIG_SMC91X=y
+# CONFIG_SMSC911X is not set
+CONFIG_NET_VENDOR_STMICRO=y
+# CONFIG_STMMAC_ETH is not set
+CONFIG_NET_VENDOR_VIA=y
+CONFIG_NET_VENDOR_WIZNET=y
+# CONFIG_WIZNET_W5100 is not set
+# CONFIG_WIZNET_W5300 is not set
+# CONFIG_NET_SB1000 is not set
+# CONFIG_PHYLIB is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+# CONFIG_INPUT_MATRIXKMAP is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_GPIO_POLLED is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_SAMSUNG is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_SENTELIC is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_AMBAKMI is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
+# CONFIG_SERIO_PS2MULT is not set
+# CONFIG_SERIO_ARC_PS2 is not set
+# CONFIG_SERIO_APBPS2 is not set
+# CONFIG_SERIO_OLPC_APSP is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_TTY=y
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
+# CONFIG_TRACE_SINK is not set
+CONFIG_DEVKMEM=y
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_AMBA_PL010 is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_SCCNXP is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_SERIAL_ARC is not set
+# CONFIG_SERIAL_FSL_LPUART is not set
+# CONFIG_VIRTIO_CONSOLE is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_HPET is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_HSI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+# CONFIG_PTP_1588_CLOCK is not set
+
+#
+# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
+#
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_GPIOLIB=y
+CONFIG_OF_GPIO=y
+CONFIG_GPIO_ACPI=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO drivers:
+#
+# CONFIG_GPIO_GENERIC_PLATFORM is not set
+# CONFIG_GPIO_TS5500 is not set
+# CONFIG_GPIO_GRGPIO is not set
+
+#
+# I2C GPIO expanders:
+#
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+
+#
+# AC97 GPIO expanders:
+#
+
+#
+# MODULbus GPIO expanders:
+#
+
+#
+# USB GPIO expanders:
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2781 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_GPIO is not set
+# CONFIG_BATTERY_GOLDFISH is not set
+CONFIG_POWER_RESET=y
+# CONFIG_POWER_RESET_GPIO is not set
+CONFIG_POWER_RESET_VEXPRESS=y
+# CONFIG_POWER_AVS is not set
+# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
+# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
+# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
+CONFIG_THERMAL_GOV_STEP_WISE=y
+# CONFIG_THERMAL_GOV_USER_SPACE is not set
+# CONFIG_THERMAL_EMULATION is not set
+
+#
+# Texas Instruments thermal drivers
+#
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+
+#
+# Broadcom specific AMBA
+#
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_CROS_EC is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_KEMPLD is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_MFD_SYSCON is not set
+# CONFIG_MFD_TI_AM335X_TSCADC is not set
+# CONFIG_MFD_TPS65912 is not set
+# CONFIG_MFD_TMIO is not set
+CONFIG_VEXPRESS_CONFIG=y
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_GOLDFISH is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_FB_AUO_K190X is not set
+# CONFIG_FB_SIMPLE is not set
+# CONFIG_EXYNOS_VIDEO is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+# CONFIG_SOUND is not set
+
+#
+# HID support
+#
+CONFIG_HID=y
+# CONFIG_HID_BATTERY_STRENGTH is not set
+# CONFIG_HIDRAW is not set
+# CONFIG_UHID is not set
+CONFIG_HID_GENERIC=y
+
+#
+# Special HID drivers
+#
+CONFIG_HID_A4TECH=y
+# CONFIG_HID_ACRUX is not set
+CONFIG_HID_APPLE=y
+# CONFIG_HID_AUREAL is not set
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EMS_FF is not set
+# CONFIG_HID_ELECOM is not set
+CONFIG_HID_EZKEY=y
+# CONFIG_HID_KEYTOUCH is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_WALTOP is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_ICADE is not set
+# CONFIG_HID_TWINHAN is not set
+CONFIG_HID_KENSINGTON=y
+# CONFIG_HID_LCPOWER is not set
+CONFIG_HID_LOGITECH=y
+# CONFIG_HID_LOGITECH_DJ is not set
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+# CONFIG_LOGIG940_FF is not set
+# CONFIG_LOGIWHEELS_FF is not set
+# CONFIG_HID_MAGICMOUSE is not set
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+# CONFIG_HID_MULTITOUCH is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_PRIMAX is not set
+# CONFIG_HID_SAITEK is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SPEEDLINK is not set
+# CONFIG_HID_STEELSERIES is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TIVO is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+# CONFIG_HID_SENSOR_HUB is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+# CONFIG_VIRT_DRIVERS is not set
+CONFIG_VIRTIO=y
+
+#
+# Virtio drivers
+#
+# CONFIG_VIRTIO_BALLOON is not set
+CONFIG_VIRTIO_MMIO=y
+# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+# CONFIG_STAGING is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_COMMON_CLK=y
+
+#
+# Common Clock Framework
+#
+# CONFIG_COMMON_CLK_DEBUG is not set
+CONFIG_COMMON_CLK_VERSATILE=y
+
+#
+# Hardware Spinlock drivers
+#
+CONFIG_CLKSRC_OF=y
+CONFIG_ARM_ARCH_TIMER=y
+# CONFIG_MAILBOX is not set
+# CONFIG_IOMMU_SUPPORT is not set
+
+#
+# Remoteproc drivers
+#
+# CONFIG_STE_MODEM_RPROC is not set
+
+#
+# Rpmsg drivers
+#
+# CONFIG_PM_DEVFREQ is not set
+# CONFIG_EXTCON is not set
+# CONFIG_MEMORY is not set
+# CONFIG_IIO is not set
+# CONFIG_PWM is not set
+CONFIG_IRQCHIP=y
+CONFIG_ARM_GIC=y
+# CONFIG_IPACK_BUS is not set
+# CONFIG_RESET_CONTROLLER is not set
+# CONFIG_FMC is not set
+
+#
+# Power management and ACPI options
+#
+CONFIG_MAB=y
+CONFIG_ACPI_ARM=y
+CONFIG_ACPI=y
+CONFIG_ACPI_EC_DEBUGFS=y
+CONFIG_ACPI_AC=y
+CONFIG_ACPI_BATTERY=y
+CONFIG_ACPI_BUTTON=y
+CONFIG_ACPI_FAN=y
+CONFIG_ACPI_DOCK=y
+CONFIG_ACPI_PROCESSOR=y
+CONFIG_ACPI_PROCESSOR_AGGREGATOR=y
+CONFIG_ACPI_THERMAL=y
+# CONFIG_ACPI_CUSTOM_DSDT is not set
+CONFIG_ACPI_BLACKLIST_YEAR=0
+# CONFIG_ACPI_DEBUG is not set
+CONFIG_ACPI_CONTAINER=y
+CONFIG_ACPI_SBS=y
+CONFIG_ACPI_HED=y
+CONFIG_ACPI_CUSTOM_METHOD=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_FANOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=y
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_TMPFS_XATTR is not set
+# CONFIG_HUGETLBFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V2=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_SWAP is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_DEBUG is not set
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_MAC_ROMAN is not set
+# CONFIG_NLS_MAC_CELTIC is not set
+# CONFIG_NLS_MAC_CENTEURO is not set
+# CONFIG_NLS_MAC_CROATIAN is not set
+# CONFIG_NLS_MAC_CYRILLIC is not set
+# CONFIG_NLS_MAC_GAELIC is not set
+# CONFIG_NLS_MAC_GREEK is not set
+# CONFIG_NLS_MAC_ICELAND is not set
+# CONFIG_NLS_MAC_INUIT is not set
+# CONFIG_NLS_MAC_ROMANIAN is not set
+# CONFIG_NLS_MAC_TURKISH is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_VIRTUALIZATION is not set
+
+#
+# Kernel hacking
+#
+
+#
+# printk and dmesg options
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+
+#
+# Compile-time checks and compiler options
+#
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_INFO_REDUCED is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=2048
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_READABLE_ASM is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_ARCH_WANT_FRAME_POINTERS=y
+CONFIG_FRAME_POINTER=y
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_KERNEL=y
+
+#
+# Memory Debugging
+#
+# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_VM is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+# CONFIG_DEBUG_SHIRQ is not set
+
+#
+# Debug Lockups and Hangs
+#
+# CONFIG_LOCKUP_DETECTOR is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+
+#
+# Lock Debugging (spinlocks, mutexes, etc...)
+#
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_HAVE_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+
+#
+# RCU Debugging
+#
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+# CONFIG_RCU_CPU_STALL_INFO is not set
+# CONFIG_RCU_TRACE is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_NOTIFIER_ERROR_INJECTION is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+
+#
+# Runtime Testing
+#
+# CONFIG_LKDTM is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_RBTREE_TEST is not set
+# CONFIG_INTERVAL_TREE_TEST is not set
+CONFIG_ATOMIC64_SELFTEST=y
+# CONFIG_TEST_STRING_HELPERS is not set
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_EARLY_PRINTK=y
+# CONFIG_PID_IN_CONTEXTIDR is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=m
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_USER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_PCRYPT is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_CMAC is not set
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_CRC32 is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+# CONFIG_CRYPTO_LZ4 is not set
+# CONFIG_CRYPTO_LZ4HC is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_NET_UTILS=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IO=y
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC32_SELFTEST is not set
+CONFIG_CRC32_SLICEBY8=y
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SARWATE is not set
+# CONFIG_CRC32_BIT is not set
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+# CONFIG_CRC8 is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_ARM is not set
+# CONFIG_XZ_DEC_ARMTHUMB is not set
+# CONFIG_XZ_DEC_SPARC is not set
+# CONFIG_XZ_DEC_BCJ is not set
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_LZ4=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
+CONFIG_CPU_RMAP=y
+CONFIG_DQL=y
+CONFIG_NLATTR=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+# CONFIG_AVERAGE is not set
+# CONFIG_CORDIC is not set
+# CONFIG_DDR is not set
+CONFIG_FONT_SUPPORT=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
--
1.7.10.4
11 years, 8 months
- 1
- 0
[PATCH] arm64: dts: add acpi version of ve-aemv8a model dts
by Graeme Gregory
This performs the same function but we shall remove devices as probing
is converted to ACPI.
Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org>
---
arch/arm64/boot/dts/rtsm_ve-aemv8a-acpi.dts | 159 ++++++++++++++
arch/arm64/boot/dts/rtsm_ve-motherboard-acpi.dtsi | 238 +++++++++++++++++++++
2 files changed, 397 insertions(+)
create mode 100644 arch/arm64/boot/dts/rtsm_ve-aemv8a-acpi.dts
create mode 100644 arch/arm64/boot/dts/rtsm_ve-motherboard-acpi.dtsi
diff --git a/arch/arm64/boot/dts/rtsm_ve-aemv8a-acpi.dts b/arch/arm64/boot/dts/rtsm_ve-aemv8a-acpi.dts
new file mode 100644
index 0000000..aa68353
--- /dev/null
+++ b/arch/arm64/boot/dts/rtsm_ve-aemv8a-acpi.dts
@@ -0,0 +1,159 @@
+/*
+ * ARM Ltd. Fast Models
+ *
+ * Architecture Envelope Model (AEM) ARMv8-A
+ * ARMAEMv8AMPCT
+ *
+ * RTSM_VE_AEMv8A.lisa
+ */
+
+/dts-v1/;
+
+/memreserve/ 0x80000000 0x00010000;
+
+/ {
+ model = "RTSM_VE_AEMv8A";
+ compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ aliases {
+ serial0 = &v2m_serial0;
+ serial1 = &v2m_serial1;
+ serial2 = &v2m_serial2;
+ serial3 = &v2m_serial3;
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x8000fff8>;
+ };
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x8000fff8>;
+ };
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x2>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x8000fff8>;
+ };
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x3>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x8000fff8>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0 0x80000000>,
+ <0x00000008 0x80000000 0 0x80000000>;
+ };
+
+ gic: interrupt-controller@2c001000 {
+ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0x2c001000 0 0x1000>,
+ <0x0 0x2c002000 0 0x1000>,
+ <0x0 0x2c004000 0 0x2000>,
+ <0x0 0x2c006000 0 0x2000>;
+ interrupts = <1 9 0xf04>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 0xff01>,
+ <1 14 0xff01>,
+ <1 11 0xff01>,
+ <1 10 0xff01>;
+ clock-frequency = <100000000>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <0 60 4>,
+ <0 61 4>,
+ <0 62 4>,
+ <0 63 4>;
+ };
+
+ smb {
+ compatible = "simple-bus";
+
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0x08000000 0x04000000>,
+ <1 0 0 0x14000000 0x04000000>,
+ <2 0 0 0x18000000 0x04000000>,
+ <3 0 0 0x1c000000 0x04000000>,
+ <4 0 0 0x0c000000 0x04000000>,
+ <5 0 0 0x10000000 0x04000000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 63>;
+ interrupt-map = <0 0 0 &gic 0 0 4>,
+ <0 0 1 &gic 0 1 4>,
+ <0 0 2 &gic 0 2 4>,
+ <0 0 3 &gic 0 3 4>,
+ <0 0 4 &gic 0 4 4>,
+ <0 0 5 &gic 0 5 4>,
+ <0 0 6 &gic 0 6 4>,
+ <0 0 7 &gic 0 7 4>,
+ <0 0 8 &gic 0 8 4>,
+ <0 0 9 &gic 0 9 4>,
+ <0 0 10 &gic 0 10 4>,
+ <0 0 11 &gic 0 11 4>,
+ <0 0 12 &gic 0 12 4>,
+ <0 0 13 &gic 0 13 4>,
+ <0 0 14 &gic 0 14 4>,
+ <0 0 15 &gic 0 15 4>,
+ <0 0 16 &gic 0 16 4>,
+ <0 0 17 &gic 0 17 4>,
+ <0 0 18 &gic 0 18 4>,
+ <0 0 19 &gic 0 19 4>,
+ <0 0 20 &gic 0 20 4>,
+ <0 0 21 &gic 0 21 4>,
+ <0 0 22 &gic 0 22 4>,
+ <0 0 23 &gic 0 23 4>,
+ <0 0 24 &gic 0 24 4>,
+ <0 0 25 &gic 0 25 4>,
+ <0 0 26 &gic 0 26 4>,
+ <0 0 27 &gic 0 27 4>,
+ <0 0 28 &gic 0 28 4>,
+ <0 0 29 &gic 0 29 4>,
+ <0 0 30 &gic 0 30 4>,
+ <0 0 31 &gic 0 31 4>,
+ <0 0 32 &gic 0 32 4>,
+ <0 0 33 &gic 0 33 4>,
+ <0 0 34 &gic 0 34 4>,
+ <0 0 35 &gic 0 35 4>,
+ <0 0 36 &gic 0 36 4>,
+ <0 0 37 &gic 0 37 4>,
+ <0 0 38 &gic 0 38 4>,
+ <0 0 39 &gic 0 39 4>,
+ <0 0 40 &gic 0 40 4>,
+ <0 0 41 &gic 0 41 4>,
+ <0 0 42 &gic 0 42 4>;
+
+ /include/ "rtsm_ve-motherboard-acpi.dtsi"
+ };
+};
diff --git a/arch/arm64/boot/dts/rtsm_ve-motherboard-acpi.dtsi b/arch/arm64/boot/dts/rtsm_ve-motherboard-acpi.dtsi
new file mode 100644
index 0000000..bbaaa8e
--- /dev/null
+++ b/arch/arm64/boot/dts/rtsm_ve-motherboard-acpi.dtsi
@@ -0,0 +1,238 @@
+/*
+ * ARM Ltd. Fast Models
+ *
+ * Versatile Express (VE) system model
+ * Motherboard component
+ *
+ * VEMotherBoard.lisa
+ */
+
+ motherboard {
+ arm,v2m-memory-map = "rs1";
+ compatible = "arm,vexpress,v2m-p1", "simple-bus";
+ #address-cells = <2>; /* SMB chipselect number and offset */
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+ ranges;
+
+ flash@0,00000000 {
+ compatible = "arm,vexpress-flash", "cfi-flash";
+ reg = <0 0x00000000 0x04000000>,
+ <4 0x00000000 0x04000000>;
+ bank-width = <4>;
+ };
+
+ vram@2,00000000 {
+ compatible = "arm,vexpress-vram";
+ reg = <2 0x00000000 0x00800000>;
+ };
+
+ /*
+ * Removed for ACPI
+ *
+ ethernet@2,02000000 {
+ compatible = "smsc,lan91c111";
+ reg = <2 0x02000000 0x10000>;
+ interrupts = <15>;
+ };
+ */
+
+ v2m_clk24mhz: clk24mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "v2m:clk24mhz";
+ };
+
+ v2m_refclk1mhz: refclk1mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000000>;
+ clock-output-names = "v2m:refclk1mhz";
+ };
+
+ v2m_refclk32khz: refclk32khz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "v2m:refclk32khz";
+ };
+
+ iofpga@3,00000000 {
+ compatible = "arm,amba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 3 0 0x200000>;
+
+ v2m_sysreg: sysreg@010000 {
+ compatible = "arm,vexpress-sysreg";
+ reg = <0x010000 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ v2m_sysctl: sysctl@020000 {
+ compatible = "arm,sp810", "arm,primecell";
+ reg = <0x020000 0x1000>;
+ clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
+ clock-names = "refclk", "timclk", "apb_pclk";
+ #clock-cells = <1>;
+ clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
+ };
+
+ aaci@040000 {
+ compatible = "arm,pl041", "arm,primecell";
+ reg = <0x040000 0x1000>;
+ interrupts = <11>;
+ clocks = <&v2m_clk24mhz>;
+ clock-names = "apb_pclk";
+ };
+
+ mmci@050000 {
+ compatible = "arm,pl180", "arm,primecell";
+ reg = <0x050000 0x1000>;
+ interrupts = <9 10>;
+ cd-gpios = <&v2m_sysreg 0 0>;
+ wp-gpios = <&v2m_sysreg 1 0>;
+ max-frequency = <12000000>;
+ vmmc-supply = <&v2m_fixed_3v3>;
+ clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+ clock-names = "mclk", "apb_pclk";
+ };
+
+ kmi@060000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x060000 0x1000>;
+ interrupts = <12>;
+ clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+ clock-names = "KMIREFCLK", "apb_pclk";
+ };
+
+ kmi@070000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x070000 0x1000>;
+ interrupts = <13>;
+ clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+ clock-names = "KMIREFCLK", "apb_pclk";
+ };
+
+ v2m_serial0: uart@090000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x090000 0x1000>;
+ interrupts = <5>;
+ clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ v2m_serial1: uart@0a0000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0a0000 0x1000>;
+ interrupts = <6>;
+ clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ v2m_serial2: uart@0b0000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0b0000 0x1000>;
+ interrupts = <7>;
+ clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ v2m_serial3: uart@0c0000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0c0000 0x1000>;
+ interrupts = <8>;
+ clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ wdt@0f0000 {
+ compatible = "arm,sp805", "arm,primecell";
+ reg = <0x0f0000 0x1000>;
+ interrupts = <0>;
+ clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
+ clock-names = "wdogclk", "apb_pclk";
+ };
+
+ v2m_timer01: timer@110000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x110000 0x1000>;
+ interrupts = <2>;
+ clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
+ clock-names = "timclken1", "timclken2", "apb_pclk";
+ };
+
+ v2m_timer23: timer@120000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x120000 0x1000>;
+ interrupts = <3>;
+ clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
+ clock-names = "timclken1", "timclken2", "apb_pclk";
+ };
+
+ rtc@170000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x170000 0x1000>;
+ interrupts = <4>;
+ clocks = <&v2m_clk24mhz>;
+ clock-names = "apb_pclk";
+ };
+
+ clcd@1f0000 {
+ compatible = "arm,pl111", "arm,primecell";
+ reg = <0x1f0000 0x1000>;
+ interrupts = <14>;
+ clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
+ clock-names = "clcdclk", "apb_pclk";
+ };
+ };
+
+ v2m_fixed_3v3: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ mcc {
+ compatible = "arm,vexpress,config-bus", "simple-bus";
+ arm,vexpress,config-bridge = <&v2m_sysreg>;
+
+ v2m_oscclk1: osc@1 {
+ /* CLCD clock */
+ compatible = "arm,vexpress-osc";
+ arm,vexpress-sysreg,func = <1 1>;
+ freq-range = <23750000 63500000>;
+ #clock-cells = <0>;
+ clock-output-names = "v2m:oscclk1";
+ };
+
+ reset@0 {
+ compatible = "arm,vexpress-reset";
+ arm,vexpress-sysreg,func = <5 0>;
+ };
+
+ muxfpga@0 {
+ compatible = "arm,vexpress-muxfpga";
+ arm,vexpress-sysreg,func = <7 0>;
+ };
+
+ shutdown@0 {
+ compatible = "arm,vexpress-shutdown";
+ arm,vexpress-sysreg,func = <8 0>;
+ };
+
+ reboot@0 {
+ compatible = "arm,vexpress-reboot";
+ arm,vexpress-sysreg,func = <9 0>;
+ };
+
+ dvimode@0 {
+ compatible = "arm,vexpress-dvimode";
+ arm,vexpress-sysreg,func = <11 0>;
+ };
+ };
+ };
--
1.7.10.4
11 years, 8 months
- 1
- 0
[PATCH] platforms: add rtsm_ve-aemv8a.acpi
by Graeme Gregory
There are enough differences between this model and foundation model I think
it is ok to be a different platform.
Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org>
---
platforms/rtsm_ve-aemv8a.acpi/.gitignore | 3 +
platforms/rtsm_ve-aemv8a.acpi/apic.asl | 126 +++++++++
platforms/rtsm_ve-aemv8a.acpi/asf!.asl | 80 ++++++
platforms/rtsm_ve-aemv8a.acpi/bert.asl | 21 ++
platforms/rtsm_ve-aemv8a.acpi/bgrt.asl | 25 ++
platforms/rtsm_ve-aemv8a.acpi/boot.asl | 21 ++
platforms/rtsm_ve-aemv8a.acpi/cpep.asl | 26 ++
platforms/rtsm_ve-aemv8a.acpi/csrt.asl | 143 ++++++++++
platforms/rtsm_ve-aemv8a.acpi/dbgp.asl | 29 ++
platforms/rtsm_ve-aemv8a.acpi/dmar.asl | 68 +++++
platforms/rtsm_ve-aemv8a.acpi/dsdt.asl | 234 ++++++++++++++++
platforms/rtsm_ve-aemv8a.acpi/ecdt.asl | 37 +++
platforms/rtsm_ve-aemv8a.acpi/einj.asl | 151 +++++++++++
platforms/rtsm_ve-aemv8a.acpi/erst.asl | 278 ++++++++++++++++++++
platforms/rtsm_ve-aemv8a.acpi/facp.asl | 167 ++++++++++++
platforms/rtsm_ve-aemv8a.acpi/facs.asl | 21 ++
platforms/rtsm_ve-aemv8a.acpi/fpdt.asl | 35 +++
platforms/rtsm_ve-aemv8a.acpi/gtdt.asl | 42 +++
platforms/rtsm_ve-aemv8a.acpi/hest.asl | 193 ++++++++++++++
platforms/rtsm_ve-aemv8a.acpi/hpet.asl | 33 +++
platforms/rtsm_ve-aemv8a.acpi/ivrs.asl | 86 ++++++
platforms/rtsm_ve-aemv8a.acpi/mcfg.asl | 26 ++
platforms/rtsm_ve-aemv8a.acpi/mchi.asl | 38 +++
platforms/rtsm_ve-aemv8a.acpi/mpst.asl | 87 ++++++
platforms/rtsm_ve-aemv8a.acpi/msct.asl | 51 ++++
platforms/rtsm_ve-aemv8a.acpi/oem0.asl | 18 ++
platforms/rtsm_ve-aemv8a.acpi/pmtt.asl | 105 ++++++++
platforms/rtsm_ve-aemv8a.acpi/rsdp.asl | 17 ++
.../rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest | 34 +++
platforms/rtsm_ve-aemv8a.acpi/s3pt.asl | 26 ++
platforms/rtsm_ve-aemv8a.acpi/sbst.asl | 22 ++
platforms/rtsm_ve-aemv8a.acpi/slic.asl | 56 ++++
platforms/rtsm_ve-aemv8a.acpi/slit.asl | 60 +++++
platforms/rtsm_ve-aemv8a.acpi/spcr.asl | 46 ++++
platforms/rtsm_ve-aemv8a.acpi/spmi.asl | 40 +++
platforms/rtsm_ve-aemv8a.acpi/srat.asl | 57 ++++
platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl | 17 ++
platforms/rtsm_ve-aemv8a.acpi/tcpa.asl | 22 ++
platforms/rtsm_ve-aemv8a.acpi/tpm2.asl | 22 ++
platforms/rtsm_ve-aemv8a.acpi/uefi.asl | 21 ++
platforms/rtsm_ve-aemv8a.acpi/waet.asl | 22 ++
platforms/rtsm_ve-aemv8a.acpi/wdat.asl | 47 ++++
platforms/rtsm_ve-aemv8a.acpi/wddt.asl | 44 ++++
platforms/rtsm_ve-aemv8a.acpi/wdrt.asl | 42 +++
platforms/rtsm_ve-aemv8a.acpi/xsdt.asl | 39 +++
45 files changed, 2778 insertions(+)
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/.gitignore
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/apic.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/asf!.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/bert.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/bgrt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/boot.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/cpep.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/csrt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/dbgp.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/dmar.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/dsdt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/ecdt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/einj.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/erst.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/facp.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/facs.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/fpdt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/gtdt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/hest.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/hpet.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/ivrs.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/mcfg.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/mchi.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/mpst.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/msct.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/oem0.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/pmtt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/rsdp.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/s3pt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/sbst.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/slic.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/slit.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/spcr.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/spmi.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/srat.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/tcpa.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/tpm2.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/uefi.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/waet.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/wdat.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/wddt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/wdrt.asl
create mode 100644 platforms/rtsm_ve-aemv8a.acpi/xsdt.asl
diff --git a/platforms/rtsm_ve-aemv8a.acpi/.gitignore b/platforms/rtsm_ve-aemv8a.acpi/.gitignore
new file mode 100644
index 0000000..9585b50
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/.gitignore
@@ -0,0 +1,3 @@
+*.aml
+*.lst
+*.acpi
diff --git a/platforms/rtsm_ve-aemv8a.acpi/apic.asl b/platforms/rtsm_ve-aemv8a.acpi/apic.asl
new file mode 100644
index 0000000..0df308d
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/apic.asl
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [APIC] Multiple APIC Description Table (MADT)
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "APIC"
+[0004] Table Length : 000000F6
+[0001] Revision : 03
+[0001] Checksum : B0
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20110623
+
+[0004] Local Apic Address : 2C002000
+[0004] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 0
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 28
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000000 /* Should be equal to FDT provided or CPU hardware ID */
+[0004] Processor UID : 00000000
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C002000 /* this is the foundation model's GIC address */
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 28
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000001
+[0004] Processor UID : 00000001
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C002000
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 28
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000002
+[0004] Processor UID : 00000002
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C002000
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 28
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000003
+[0004] Processor UID : 00000003
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C002000
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 28
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000004
+[0004] Processor UID : 00000004
+[0004] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C002000
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 28
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000005
+[0004] Processor UID : 00000005
+[0004] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C002000
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 28
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000006
+[0004] Processor UID : 00000006
+[0004] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C002000
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 28
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000007
+[0004] Processor UID : 00000007
+[0004] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C002000
+
+[0001] Subtable Type : 0C [Generic Interrupt Distributor]
+[0001] Length : 18
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000000
+[0008] Base Address : 000000002C001000 /* armv8 foundation model's GIC distributor base addr */
+[0004] Interrupt Base : 00000000
+[0004] Reserved : 00000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/asf!.asl b/platforms/rtsm_ve-aemv8a.acpi/asf!.asl
new file mode 100644
index 0000000..a05f924
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/asf!.asl
@@ -0,0 +1,80 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [ASF!] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "ASF!" [Alert Standard Format table]
+[0004] Table Length : 00000072
+[0001] Revision : 10
+[0001] Checksum : 0B
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0001] Subtable Type : 00 [ASF Information]
+[0001] Reserved : 00
+[0002] Length : 0010
+[0001] Minimum Reset Value : 00
+[0001] Minimum Polling Interval : 00
+[0002] System ID : 0000
+[0004] Manufacturer ID : 00000000
+[0001] Flags : 00
+[0003] Reserved : 000000
+
+[0001] Subtable Type : 01 [ASF Alerts]
+[0001] Reserved : 00
+[0002] Length : 0014
+[0001] AssertMask : 00
+[0001] DeassertMask : 00
+[0001] Alert Count : 01
+[0001] Alert Data Length : 0C
+
+[0001] Address : 00
+[0001] Command : 00
+[0001] Mask : 00
+[0001] Value : 00
+[0001] SensorType : 00
+[0001] Type : 00
+[0001] Offset : 00
+[0001] SourceType : 00
+[0001] Severity : 00
+[0001] SensorNumber : 00
+[0001] Entity : 00
+[0001] Instance : 00
+
+[0001] Subtable Type : 02 [ASF Remote Control]
+[0001] Reserved : 00
+[0002] Length : 000C
+[0001] Control Count : 01
+[0001] Control Data Length : 04
+[0002] Reserved : 0000
+
+[0001] Function : 00
+[0001] Address : 00
+[0001] Command : 00
+[0001] Value : 00
+
+[0001] Subtable Type : 03 [ASF RMCP Boot Options]
+[0001] Reserved : 00
+[0002] Length : 0017
+[0007] Capabilities : 00 00 00 00 00 00 00
+[0001] Completion Code : 00
+[0004] Enterprise ID : 00000000
+[0001] Command : 00
+[0002] Parameter : 0000
+[0002] Boot Options : 0000
+[0002] Oem Parameters : 0000
+
+[0001] Subtable Type : 84 [ASF Address]
+[0001] Reserved : 00
+[0002] Length : 0007
+[0001] Eprom Address : 00
+[0001] Device Count : 01
+[0001] Addresses : 00
+
diff --git a/platforms/rtsm_ve-aemv8a.acpi/bert.asl b/platforms/rtsm_ve-aemv8a.acpi/bert.asl
new file mode 100644
index 0000000..6cb628c
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/bert.asl
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [BERT] Boot Error Record Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "BERT"
+[0004] Table Length : 00000030
+[0001] Revision : 01
+[0001] Checksum : 15
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Boot Error Region Length : 00000000
+[0008] Boot Error Region Address : 0000000000000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/bgrt.asl b/platforms/rtsm_ve-aemv8a.acpi/bgrt.asl
new file mode 100644
index 0000000..c8af10e
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/bgrt.asl
@@ -0,0 +1,25 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [BGRT] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "BGRT" [Boot Graphics Resource Table]
+[0004] Table Length : 00000038
+[0001] Revision : 01
+[0001] Checksum : 0D
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20110623
+
+[0002] Version : 0001
+[0001] Status : 00
+[0001] Image Type : 00
+[0008] Image Address : 0000000000000000
+[0004] Image OffsetX : 00000000
+[0004] Image OffsetY : 00000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/boot.asl b/platforms/rtsm_ve-aemv8a.acpi/boot.asl
new file mode 100644
index 0000000..5a567fb
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/boot.asl
@@ -0,0 +1,21 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [BOOT] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "BOOT" [Simple Boot Flag Table]
+[0004] Table Length : 00000028
+[0001] Revision : 01
+[0001] Checksum : 0D
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 06040000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0001] Boot Register Index : 00
+[0003] Reserved : 000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/cpep.asl b/platforms/rtsm_ve-aemv8a.acpi/cpep.asl
new file mode 100644
index 0000000..8f6b3b2
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/cpep.asl
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [CPEP] Corrected Platform Error Polling Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "CPEP"
+[0004] Table Length : 00000034
+[0001] Revision : 01
+[0001] Checksum : 0F
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0008] Reserved : 0000000000000000
+
+[0001] Subtable Type : 00
+[0001] Length : 08
+[0001] Processor ID : 00
+[0001] Processor EID : 00
+[0004] Polling Interval : 00000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/csrt.asl b/platforms/rtsm_ve-aemv8a.acpi/csrt.asl
new file mode 100644
index 0000000..ab43ea5
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/csrt.asl
@@ -0,0 +1,143 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [CSRT] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "CSRT" [Core System Resource Table]
+[0004] Table Length : 0000014C
+[0001] Revision : 01
+[0001] Checksum : 0D
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20121114
+
+
+[0004] Length : 00000088
+[0004] Vendor ID : 4C544E49
+[0004] Subvendor ID : 00000000
+[0002] Device ID : 9C60
+[0002] Subdevice ID : 0000
+[0002] Revision : 0002
+[0002] Reserved : 0000
+[0004] Shared Info Length : 0000001C
+
+[0002] Major Version : 0001
+[0002] Minor Version : 0000
+[0004] MMIO Base Address Low : B3A00000
+[0004] MMIO Base Address High : 00000000
+[0004] GSI Interrupt : 0000002A
+[0001] Interrupt Polarity : 02
+[0001] Interrupt Mode : 00
+[0001] Num Channels : 06
+[0001] DMA Address Width : 20
+[0002] Base Request Line : 0000
+[0002] Num Handshake Signals : 0010
+[0004] Max Block Size : 00000FFF
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0001
+[0004] UID : 20495053
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 30414843
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 31414843
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 32414843
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 33414843
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 34414843
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 35414843
+
+[0004] Length : 000000A0
+[0004] Vendor ID : 4C544E49
+[0004] Subvendor ID : 00000000
+[0002] Device ID : 9C60
+[0002] Subdevice ID : 0000
+[0002] Revision : 0003
+[0002] Reserved : 0000
+[0004] Shared Info Length : 0000001C
+
+[0002] Major Version : 0001
+[0002] Minor Version : 0000
+[0004] MMIO Base Address Low : 00000000
+[0004] MMIO Base Address High : 00000000
+[0004] GSI Interrupt : 0000002B
+[0001] Interrupt Polarity : 02
+[0001] Interrupt Mode : 00
+[0001] Num Channels : 08
+[0001] DMA Address Width : 20
+[0002] Base Request Line : 0010
+[0002] Num Handshake Signals : 0010
+[0004] Max Block Size : 00000FFF
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0001
+[0004] UID : 20433249
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 30414843
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 31414843
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 32414843
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 33414843
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 34414843
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 35414843
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 36414843
+
+[0004] Length : 0000000C
+[0002] Type : 0003
+[0002] Subtype : 0000
+[0004] UID : 37414843
diff --git a/platforms/rtsm_ve-aemv8a.acpi/dbgp.asl b/platforms/rtsm_ve-aemv8a.acpi/dbgp.asl
new file mode 100644
index 0000000..d1a826f
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/dbgp.asl
@@ -0,0 +1,29 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [DBGP] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "DBGP" [Debug Port table]
+[0004] Table Length : 00000034
+[0001] Revision : 01
+[0001] Checksum : 1A
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0001] Interface Type : 00
+[0003] Reserved : 000000
+
+[0012] Debug Port Register : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
diff --git a/platforms/rtsm_ve-aemv8a.acpi/dmar.asl b/platforms/rtsm_ve-aemv8a.acpi/dmar.asl
new file mode 100644
index 0000000..e10c8c3
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/dmar.asl
@@ -0,0 +1,68 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [DMAR] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "DMAR" [DMA Remapping table]
+[0004] Table Length : 0000008C
+[0001] Revision : 01
+[0001] Checksum : 15
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0001] Host Address Width : 2F
+[0001] Flags : 01
+
+[0002] Subtable Type : 0000 [Hardware Unit Definition]
+[0002] Length : 0018
+[0001] Flags : 01
+[0001] Reserved : 00
+[0002] PCI Segment Number : 0000
+[0008] Register Base Address : 00000000FD020000
+
+[0001] Device Scope Entry Type : 03
+[0001] Entry Length : 08
+[0002] Reserved : 0000
+[0001] Enumeration ID : 08
+[0001] PCI Bus Number : F0
+[0002] PCI Path : 1F,07
+
+[0002] Subtable Type : 0001 [Reserved Memory Region]
+[0002] Length : 0020
+[0002] Reserved : 0000
+[0002] PCI Segment Number : 0000
+[0008] Base Address : 0000000078C21000
+[0008] End Address (limit) : 0000000078C23FFF
+
+[0001] Device Scope Entry Type : 01
+[0001] Entry Length : 08
+[0002] Reserved : 0000
+[0001] Enumeration ID : 00
+[0001] PCI Bus Number : 00
+[0002] PCI Path : 1D,00
+
+[0002] Subtable Type : 0002 [Root Port ATS Capability]
+[0002] Length : 0010
+[0001] Flags : 00
+[0001] Reserved : 00
+[0002] PCI Segment Number : 0000
+
+[0001] Device Scope Entry Type : 02
+[0001] Entry Length : 08
+[0002] Reserved : 0000
+[0001] Enumeration ID : 00
+[0001] PCI Bus Number : 00
+[0002] PCI Path : 01,00
+
+[0002] Subtable Type : 0003 [Remapping Hardware Static Affinity]
+[0002] Length : 0014
+[0004] Reserved : 00000000
+[0008] Base Address : 00000000FD020000
+[0004] Proximity Domain : 00000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/dsdt.asl b/platforms/rtsm_ve-aemv8a.acpi/dsdt.asl
new file mode 100644
index 0000000..daefcd8
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/dsdt.asl
@@ -0,0 +1,234 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [DSDT] Description of the Arndale board (exynos5250)
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+DefinitionBlock (
+ "dsdt.aml", // output filename
+ "DSDT", // table signature
+ 1, // DSDT compliance revision
+ "LINARO", // OEM ID
+ "RTSMVEV8", // table ID
+ 0x00000002) // OEM revision
+{
+ Scope (\_SB)
+ {
+ Device (SCK0)
+ {
+ Name (_HID, "ACPI0004")
+ Name (_UID, 0x00)
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Device (PRC0)
+ {
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0x00)
+
+ /* CPU0 will be always present */
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Name (MAT0, Buffer (0x28)
+ {
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* type, len, reserved, gic_id */
+ /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, /* uid, flags */
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* parking_version, performance_interrupt */
+ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* parked_address */
+ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* base_address */
+ })
+
+ Name (MAT1, Buffer (0x28)
+ {
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+
+ Method (_MAT, 0, NotSerialized)
+ {
+ If (_STA())
+ {
+ Return (MAT0)
+ }
+ Else
+ {
+ Return (MAT1)
+ }
+ }
+ }
+
+ Device (PRC1)
+ {
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0x01)
+
+ Name (STA1, 0x0F)
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (STA1)
+ }
+
+ Method (_EJ0, 1, NotSerialized)
+ {
+ If (LEqual (STA1, 0x0F))
+ {
+ Store (0x00, STA1)
+ }
+ }
+
+ Name (MAT0, Buffer (0x28)
+ {
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+ /* 0008 */ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01,
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+
+ Name (MAT1, Buffer (0x28)
+ {
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+ /* 0008 */ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+
+ Method (_MAT, 0, NotSerialized)
+ {
+ If (_STA())
+ {
+ Return (MAT0)
+ }
+ Else
+ {
+ Return (MAT1)
+ }
+ }
+ }
+
+ Device (PRC2)
+ {
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0x02)
+
+ Name (STA2, 0x0F)
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (STA2)
+ }
+
+ Method (_EJ0, 1, NotSerialized)
+ {
+ If (LEqual (STA2, 0x0F))
+ {
+ Store (0x00, STA2)
+ }
+ }
+
+ Name (MAT0, Buffer (0x28)
+ {
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+ /* 0008 */ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+
+ Name (MAT1, Buffer (0x28)
+ {
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+ /* 0008 */ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+
+ Method (_MAT, 0, NotSerialized)
+ {
+ If (_STA())
+ {
+ Return (MAT0)
+ }
+ Else
+ {
+ Return (MAT1)
+ }
+ }
+ }
+
+ Device (PRC3)
+ {
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0x03)
+
+ Name (STA3, 0x0F)
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (STA3)
+ }
+
+ Method (_EJ0, 1, NotSerialized)
+ {
+ If (LEqual (STA3, 0x0F))
+ {
+ Store (0x00, STA3)
+ }
+ }
+
+ Name (MAT0, Buffer (0x28)
+ {
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+ /* 0008 */ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01,
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+
+ Name (MAT1, Buffer (0x28)
+ {
+ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+ /* 0008 */ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00,
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+
+ Method (_MAT, 0, NotSerialized)
+ {
+ If (_STA())
+ {
+ Return (MAT0)
+ }
+ Else
+ {
+ Return (MAT1)
+ }
+ }
+ }
+ }
+
+ Device (NET0) {
+ Name (_HID, "LINA0003")
+ Name (_UID, 0)
+
+ Method (_CRS, 0x0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0x1a000000, 0x00010000)
+ Interrupt (ResourceConsumer, Edge, ActiveBoth, Exclusive, , , ) {0x2F}
+ })
+ Return (RBUF)
+ }
+ }
+ }
+}
diff --git a/platforms/rtsm_ve-aemv8a.acpi/ecdt.asl b/platforms/rtsm_ve-aemv8a.acpi/ecdt.asl
new file mode 100644
index 0000000..75ffdc4
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/ecdt.asl
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [ECDT] Embedded Controller Boot Resources Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "ECDT"
+[0004] Table Length : 00000042
+[0001] Revision : 01
+[0001] Checksum : 2D
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+
+[0012] Command/Status Register : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000066
+
+[0012] Data Register : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000062
+
+[0004] UID : 00000000
+[0001] GPE Number : 09
+[0001] Namepath : ""
diff --git a/platforms/rtsm_ve-aemv8a.acpi/einj.asl b/platforms/rtsm_ve-aemv8a.acpi/einj.asl
new file mode 100644
index 0000000..e2d3f5e
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/einj.asl
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [EINJ] Error Injection Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "EINJ"
+[0004] Table Length : 00000130
+[0001] Revision : 01
+[0001] Checksum : 09
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Injection Header Length : 00000030
+[0001] Flags : 00
+[0003] Reserved : 000000
+[0004] Injection Entry Count : 0000000A
+
+[0001] Action : 00 [Begin Operation]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 01 [Get Trigger Table]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 02 [Set Error Type]
+[0001] Instruction : 02 [Write Register]
+[0001] Flags (decoded below) : 01
+ Preserve Register Bits : 1
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 03 [Get Error Type]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 04 [End Operation]
+[0001] Instruction : 03 [Write Register Value]
+[0001] Flags (decoded below) : 01
+ Preserve Register Bits : 1
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 05 [Execute Operation]
+[0001] Instruction : 03 [Write Register Value]
+[0001] Flags (decoded below) : 01
+ Preserve Register Bits : 1
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 10
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 02 [Word Access:16]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 06 [Check Busy Status]
+[0001] Instruction : 01 [Read Register Value]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 07 [Get Command Status]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 01
+ Preserve Register Bits : 1
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
diff --git a/platforms/rtsm_ve-aemv8a.acpi/erst.asl b/platforms/rtsm_ve-aemv8a.acpi/erst.asl
new file mode 100644
index 0000000..a453eab
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/erst.asl
@@ -0,0 +1,278 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [ERST] Error Record Serialization Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "ERST"
+[0004] Table Length : 00000230
+[0001] Revision : 01
+[0001] Checksum : AB
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Serialization Header Length : 00000030
+[0004] Reserved : 00000000
+[0004] Instruction Entry Count : 00000010
+
+[0001] Action : 00 [Begin Write Operation]
+[0001] Instruction : 03 [Write Register Value]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 01 [Begin Read Operation]
+[0001] Instruction : 03 [Write Register Value]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 02 [Begin Clear Operation]
+[0001] Instruction : 03 [Write Register Value]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 03 [End Operation]
+[0001] Instruction : 04 [Noop]
+[0001] Flags (decoded below) : 01
+ Preserve Register Bits : 1
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 04 [Set Record Offset]
+[0001] Instruction : 02 [Write Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 05 [Execute Operation]
+[0001] Instruction : 03 [Write Register Value]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 01 [Byte Access:8]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 06 [Check Busy Status]
+[0001] Instruction : 01 [Read Register Value]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 07 [Get Command Status]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 08 [Get Record Identifier]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 09 [Set Record Identifier]
+[0001] Instruction : 02 [Write Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 0A [Get Record Count]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 0B [Begin Dummy Write]
+[0001] Instruction : 03 [Write Register Value]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 0C [Unused/Unknown Action]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 0D [Get Error Address Range]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 0E [Get Error Address Length]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
+
+[0001] Action : 0F [Get Error Attributes]
+[0001] Instruction : 00 [Read Register]
+[0001] Flags (decoded below) : 00
+ Preserve Register Bits : 0
+[0001] Reserved : 00
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0008] Value : 0000000000000000
+[0008] Mask : FFFFFFFFFFFFFFFF
diff --git a/platforms/rtsm_ve-aemv8a.acpi/facp.asl b/platforms/rtsm_ve-aemv8a.acpi/facp.asl
new file mode 100644
index 0000000..c4713fe
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/facp.asl
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [FACP] ACPI Table
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "FACP"
+[0004] Table Length : 0000010C
+[0001] Revision : 05
+[0001] Checksum : 18
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20111123
+
+[0004] FACS Address : 00000000
+[0004] DSDT Address : 00000010
+[0001] Model : 00
+[0001] PM Profile : 04 /* Enterprise Server */
+[0002] SCI Interrupt : 0000
+[0004] SMI Command Port : 00000000
+[0001] ACPI Enable Value : 00
+[0001] ACPI Disable Value : 00
+[0001] S4BIOS Command : 00
+[0001] P-State Control : 00
+[0004] PM1A Event Block Address : 00000001
+[0004] PM1B Event Block Address : 00000000
+[0004] PM1A Control Block Address : 00000001
+[0004] PM1B Control Block Address : 00000000
+[0004] PM2 Control Block Address : 00000001
+[0004] PM Timer Block Address : 00000001
+[0004] GPE0 Block Address : 00000001
+[0004] GPE1 Block Address : 00000000
+[0001] PM1 Event Block Length : 04
+[0001] PM1 Control Block Length : 02
+[0001] PM2 Control Block Length : 01
+[0001] PM Timer Block Length : 04
+[0001] GPE0 Block Length : 08
+[0001] GPE1 Block Length : 00
+[0001] GPE1 Base Offset : 00
+[0001] _CST Support : 00
+[0002] C2 Latency : 0000
+[0002] C3 Latency : 0000
+[0002] CPU Cache Size : 0000
+[0002] Cache Flush Stride : 0000
+[0001] Duty Cycle Offset : 00
+[0001] Duty Cycle Width : 00
+[0001] RTC Day Alarm Index : 00
+[0001] RTC Month Alarm Index : 00
+[0001] RTC Century Index : 00
+[0002] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[0001] Reserved : 00
+[0004] Flags (decoded below) : 00000000
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 1
+ All CPUs support C1 (V1) : 0
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 1
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 0
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 0
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 1
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 0
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 1
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 1
+ Low Power S0 Idle (V5) : 1
+
+[0012] Reset Register : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 01 [Byte Access:8]
+[0008] Address : 0000000000000001
+
+[0001] Value to cause reset : 00
+[0003] Reserved : 000000
+[0008] FACS Address : 0000000000000000
+[0008] DSDT Address : 0000000000000010
+[0012] PM1A Event Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 20
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 02 [Word Access:16]
+[0008] Address : 0000000000000001
+
+[0012] PM1B Event Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 00
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+[0012] PM1A Control Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 10
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 02 [Word Access:16]
+[0008] Address : 0000000000000001
+
+[0012] PM1B Control Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 00
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+[0012] PM2 Control Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000001
+
+[0012] PM Timer Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 20
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 03 [DWord Access:32]
+[0008] Address : 0000000000000001
+
+[0012] GPE0 Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 80
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 01 [Byte Access:8]
+[0008] Address : 0000000000000001
+
+[0012] GPE1 Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 00
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+
+[0012] Sleep Control Register : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 01 [Byte Access:8]
+[0008] Address : 0000000000000000
+
+[0012] Sleep Status Register : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 01 [Byte Access:8]
+[0008] Address : 0000000000000000
+
diff --git a/platforms/rtsm_ve-aemv8a.acpi/facs.asl b/platforms/rtsm_ve-aemv8a.acpi/facs.asl
new file mode 100644
index 0000000..8d12b41
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/facs.asl
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [FACS] ACPI Table
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "FACS"
+[0004] Length : 00000040
+[0004] Hardware Signature : 00000000
+[0004] 32 Firmware Waking Vector : 00000000
+[0004] Global Lock : 00000000
+[0004] Flags (decoded below) : 00000000
+ S4BIOS Support Present : 0
+ 64-bit Wake Supported (V2) : 0
+[0008] 64 Firmware Waking Vector : 0000000000000000
+[0001] Version : 02
+[0003] Reserved : 000000
+[0004] OspmFlags (decoded below) : 00000000
+ 64-bit Wake Env Required (V2) : 0
diff --git a/platforms/rtsm_ve-aemv8a.acpi/fpdt.asl b/platforms/rtsm_ve-aemv8a.acpi/fpdt.asl
new file mode 100644
index 0000000..2b691b6
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/fpdt.asl
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [FPDT] Firmware Performance Data Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "FPDT"
+[0004] Table Length : 00000064
+[0001] Revision : 01
+[0001] Checksum : BD
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20110804
+
+
+[0002] Subtable Type : 0000
+[0001] Length : 30
+[0001] Revision : 01
+[0004] Reserved : 00000000
+[0008] Reset End : 0000000000000000
+[0008] Load Image Start : 0000000000000000
+[0008] Start Image Start : 0000000000000000
+[0008] Exit Services Entry : 0000000000000000
+[0008] Exit Services Exit : 0000000000000000
+
+[0002] Subtable Type : 0001
+[0001] Length : 10
+[0001] Revision : 01
+[0004] Reserved : 00000000
+[0008] S3PT Address : 0000000000000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl b/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl
new file mode 100644
index 0000000..ff2c08a
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/gtdt.asl
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [GTDT] Generic Timer Description Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "GTDT"
+[0004] Table Length : 00000050
+[0001] Revision : 01
+[0001] Checksum : F1
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20110623
+
+[0008] Timer Address : 0000000000000000
+[0004] Flags (decoded below) : 00000001
+ Memory Present : 1
+
+[0004] Secure PL1 Interrupt : 00000000
+[0004] SPL1 Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
+
+[0004] Non-Secure PL1 Interrupt : 00000000
+[0004] NSPL1 Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
+
+[0004] Virtual Timer Interrupt : 00000000
+[0004] VT Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
+
+[0004] Non-Secure PL2 Interrupt : 00000000
+[0004] NSPL2 Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
diff --git a/platforms/rtsm_ve-aemv8a.acpi/hest.asl b/platforms/rtsm_ve-aemv8a.acpi/hest.asl
new file mode 100644
index 0000000..05ddb24
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/hest.asl
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org
+ *
+ * [HEST] Hardware Error Source Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "HEST"
+[0004] Table Length : 000001D4
+[0001] Revision : 01
+[0001] Checksum : 20
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Error Source Count : 00000004
+
+[0002] Subtable Type : 0000 [IA-32 Machine Check Exception]
+[0002] Source Id : 0000
+[0002] Reserved1 : 0000
+[0001] Flags (decoded below) : 00
+ Firmware First : 0
+[0001] Enabled : 01
+[0004] Records To Preallocate : 00000001
+[0004] Max Sections Per Record : 00000001
+[0008] Global Capability Data : 0000000000000000
+[0008] Global Control Data : 0000000000000000
+[0001] Num Hardware Banks : 02
+[0007] Reserved2 : 00000000000000
+
+[0001] Bank Number : 00
+[0001] Clear Status On Init : 00
+[0001] Status Format : 00
+[0001] Reserved : 00
+[0004] Control Register : 00000000
+[0008] Control Data : 0000000000000000
+[0004] Status Register : 00000000
+[0004] Address Register : 00000000
+[0004] Misc Register : 00000000
+
+[0001] Bank Number : 01
+[0001] Clear Status On Init : 00
+[0001] Status Format : 00
+[0001] Reserved : 00
+[0004] Control Register : 00000000
+[0008] Control Data : 0000000000000000
+[0004] Status Register : 00000000
+[0004] Address Register : 00000000
+[0004] Misc Register : 00000000
+
+[0002] Subtable Type : 0001 [IA-32 Corrected Machine Check]
+[0002] Source Id : 0001
+[0002] Reserved1 : 0000
+[0001] Flags (decoded below) : 00
+ Firmware First : 0
+[0001] Enabled : 01
+[0004] Records To Preallocate : 00000001
+[0004] Max Sections Per Record : 00000001
+
+[0028] Notify : [Hardware Error Notification Structure]
+[0001] Notify Type : 00 [Polled]
+[0001] Notify Length : 00
+[0002] Configuration Write Enable : 0000
+[0004] PollInterval : 00000000
+[0004] Vector : 00000000
+[0004] Polling Threshold Value : 00000000
+[0004] Polling Threshold Window : 00000000
+[0004] Error Threshold Value : 00000000
+[0004] Error Threshold Window : 00000000
+
+[0001] Num Hardware Banks : 02
+[0003] Reserved2 : 000000
+
+[0001] Bank Number : 00
+[0001] Clear Status On Init : 00
+[0001] Status Format : 00
+[0001] Reserved : 00
+[0004] Control Register : 00000000
+[0008] Control Data : 0000000000000000
+[0004] Status Register : 00000000
+[0004] Address Register : 00000000
+[0004] Misc Register : 00000000
+
+[0001] Bank Number : 01
+[0001] Clear Status On Init : 00
+[0001] Status Format : 00
+[0001] Reserved : 00
+[0004] Control Register : 00000000
+[0008] Control Data : 0000000000000000
+[0004] Status Register : 00000000
+[0004] Address Register : 00000000
+[0004] Misc Register : 00000000
+
+[0002] Subtable Type : 0007 [PCI Express AER (AER Endpoint)]
+[0002] Source Id : 0000
+[0002] Reserved : 0000
+[0001] Flags (decoded below) : 00
+ Firmware First : 0
+[0001] Enabled : 01
+[0004] Records To Preallocate : 00000001
+[0004] Max Sections Per Record : 00000001
+[0004] Bus : 00000000
+[0002] Device : 0000
+[0002] Function : 0000
+[0002] DeviceControl : 0000
+[0002] Reserved : 0000
+[0004] Uncorrectable Mask : 00000000
+[0004] Uncorrectable Severity : 00000000
+[0004] Correctable Mask : 00000000
+[0004] Advanced Capabilities : 00000000
+
+[0002] Subtable Type : 0008 [PCI Express/PCI-X Bridge AER]
+[0002] Source Id : 0000
+[0002] Reserved : 0000
+[0001] Flags (decoded below) : 00
+ Firmware First : 0
+[0001] Enabled : 01
+[0004] Records To Preallocate : 00000001
+[0004] Max Sections Per Record : 00000001
+[0004] Bus : 00000000
+[0002] Device : 0000
+[0002] Function : 0000
+[0002] DeviceControl : 0000
+[0002] Reserved : 0000
+[0004] Uncorrectable Mask : 00000000
+[0004] Uncorrectable Severity : 00000000
+[0004] Correctable Mask : 00000000
+[0004] Advanced Capabilities : 00000000
+[0004] 2nd Uncorrectable Mask : 00000000
+[0004] 2nd Uncorrectable Severity : 00000000
+[0004] 2nd Advanced Capabilities : 00000000
+
+[0002] Subtable Type : 0009 [Generic Hardware Error Source]
+[0002] Source Id : 0002
+[0002] Related Source Id : FFFF
+[0001] Reserved : 00
+[0001] Enabled : 01
+[0004] Records To Preallocate : 00000001
+[0004] Max Sections Per Record : 00000001
+[0004] Max Raw Data Length : 00001000
+
+[0012] Error Status Address : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0028] Notify : [Hardware Error Notification Structure]
+[0001] Notify Type : 03 [SCI]
+[0001] Notify Length : 1C
+[0002] Configuration Write Enable : 0000
+[0004] PollInterval : 00000000
+[0004] Vector : 00000000
+[0004] Polling Threshold Value : 00000000
+[0004] Polling Threshold Window : 00000000
+[0004] Error Threshold Value : 00000000
+[0004] Error Threshold Window : 00000000
+
+[0004] Error Status Block Length : 00001000
+
+[0002] Subtable Type : 0009 [Generic Hardware Error Source]
+[0002] Source Id : 0003
+[0002] Related Source Id : 0000
+[0001] Reserved : 00
+[0001] Enabled : 01
+[0004] Records To Preallocate : 00000001
+[0004] Max Sections Per Record : 00000001
+[0004] Max Raw Data Length : 00001000
+
+[0012] Error Status Address : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 40
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [QWord Access:64]
+[0008] Address : 0000000000000000
+
+[0028] Notify : [Hardware Error Notification Structure]
+[0001] Notify Type : 04 [NMI]
+[0001] Notify Length : 1C
+[0002] Configuration Write Enable : 0000
+[0004] PollInterval : 00000000
+[0004] Vector : 00000000
+[0004] Polling Threshold Value : 00000000
+[0004] Polling Threshold Window : 00000000
+[0004] Error Threshold Value : 00000000
+[0004] Error Threshold Window : 00000000
+
+[0004] Error Status Block Length : 00001000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/hpet.asl b/platforms/rtsm_ve-aemv8a.acpi/hpet.asl
new file mode 100644
index 0000000..c150282
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/hpet.asl
@@ -0,0 +1,33 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [HPET] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "HPET" [High Precision Event Timer table]
+[0004] Table Length : 00000038
+[0001] Revision : 01
+[0001] Checksum : 09
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Hardware Block ID : 00000000
+
+[0012] Timer Block Register : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 00
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+[0001] Sequence Number : 00
+[0002] Minimum Clock Ticks : 0000
+[0001] Flags (decoded below) : 00
+ 4K Page Protect : 0
+ 64K Page Protect : 0
diff --git a/platforms/rtsm_ve-aemv8a.acpi/ivrs.asl b/platforms/rtsm_ve-aemv8a.acpi/ivrs.asl
new file mode 100644
index 0000000..9f64314
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/ivrs.asl
@@ -0,0 +1,86 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [IVRS] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "IVRS" [I/O Virtualization Reporting Structure]
+[0004] Table Length : 000000BC
+[0001] Revision : 01
+[0001] Checksum : 87
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Virtualization Info : 00000000
+[0008] Reserved : 0000000000000000
+
+[0001] Subtable Type : 10 [Hardware Definition Block]
+[0001] Flags : 14
+[0002] Length : 0034
+[0002] DeviceId : 0000
+
+[0002] Capability Offset : 0000
+[0008] Base Address : 0000000000000000
+[0002] PCI Segment Group : 0000
+[0002] Virtualization Info : 0000
+[0004] Reserved : 00000000
+
+[0001] Entry Type : 00
+[0002] Device ID : 0000
+[0001] Data Setting : 00
+
+[0001] Entry Type : 40
+[0002] Device ID : 0000
+[0001] Data Setting : 00
+[0004] Extended Data : 00000000
+
+[0001] Entry Type : 42
+[0002] Device ID : 0000
+[0001] Data Setting : 00
+[0001] Reserved : 00
+[0002] Source Used Device ID : 0000
+[0001] Reserved : 00
+
+[0001] Entry Type : 48
+[0002] Device ID : 0000
+[0001] Data Setting : 00
+[0001] Handle : 00
+[0002] Source Used Device ID : 0000
+[0001] Variety : 00
+
+[0001] Subtable Type : 20 [Memory Definition Block]
+[0001] Flags : 08
+[0002] Length : 0020
+[0002] DeviceId : 0000
+
+[0002] Auxiliary Data : 0000
+[0008] Reserved : 0000000000000000
+[0008] Start Address : 0000000000000000
+[0008] Memory Length : 0000000000000000
+
+[0001] Subtable Type : 21 [Memory Definition Block]
+[0001] Flags : 04
+[0002] Length : 0020
+[0002] DeviceId : 0000
+
+[0002] Auxiliary Data : 0000
+[0008] Reserved : 0000000000000000
+[0008] Start Address : 0000000000000000
+[0008] Memory Length : 0000000000000000
+
+[0001] Subtable Type : 10 [Hardware Definition Block]
+[0001] Flags : 14
+[0002] Length : 0018
+[0002] DeviceId : 0000
+
+[0002] Capability Offset : 0000
+[0008] Base Address : 0000000000000000
+[0002] PCI Segment Group : 0000
+[0002] Virtualization Info : 0000
+[0004] Reserved : 00000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/mcfg.asl b/platforms/rtsm_ve-aemv8a.acpi/mcfg.asl
new file mode 100644
index 0000000..cee9d6f
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/mcfg.asl
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [MCFG] PCIe Memory Mapped Configuration Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "MCFG"
+[0004] Table Length : 0000003C
+[0001] Revision : 01
+[0001] Checksum : 19
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0008] Reserved : 0000000000000000
+
+[0008] Base Address : 0000000000000000
+[0002] Segment Group Number : 0000
+[0001] Start Bus Number : 00
+[0001] End Bus Number : 00
+[0004] Reserved : 00000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/mchi.asl b/platforms/rtsm_ve-aemv8a.acpi/mchi.asl
new file mode 100644
index 0000000..2154c51
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/mchi.asl
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [MCHI] Management Controller Host Interface Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "MCHI"
+[0004] Table Length : 00000045
+[0001] Revision : 01
+[0001] Checksum : E4
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 02000715
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0001] Interface Type : 01
+[0001] Protocol : 00
+[0008] Protocol Data : 0000000000000000
+[0001] Interrupt Type : 00
+[0001] Gpe : 00
+[0001] Pci Device Flag : 00
+[0004] Global Interrupt : 00000000
+
+[0012] Control Register : [Generic Address Structure]
+[0001] Space ID : 02 [PCI_Config]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+[0001] Pci Segment : 00
+[0001] Pci Bus : 00
+[0001] Pci Device : 00
+[0001] Pci Function : 00
diff --git a/platforms/rtsm_ve-aemv8a.acpi/mpst.asl b/platforms/rtsm_ve-aemv8a.acpi/mpst.asl
new file mode 100644
index 0000000..1c6933b
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/mpst.asl
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [MPST] Memory Power State Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "MPST"
+[0004] Table Length : 000000B6
+[0001] Revision : 01
+[0001] Checksum : 77
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20120913
+
+[0001] Channel ID : 00
+[0003] Reserved : 000000
+[0002] Power Node Count : 0002
+[0002] Reserved : 0000
+
+[0001] Flags (decoded below) : 00
+ Node Enabled : 0
+ Power Managed : 0
+ Hot Plug Capable : 0
+[0001] Reserved : 00
+[0002] Node ID : 0000
+[0004] Length : 00000000
+[0008] Range Address : 0000000000000000
+[0008] Range Length : 0000000000000000
+[0004] Num Power States : 00000002
+[0004] Num Physical Components : 00000003
+
+[0001] Power State : 00
+[0001] InfoIndex : 00
+
+[0001] Power State : 00
+[0001] InfoIndex : 00
+
+[0002] Component Id : 0000
+[0002] Component Id : 0001
+[0002] Component Id : 0002
+
+[0001] Flags (decoded below) : 00
+ Node Enabled : 0
+ Power Managed : 0
+ Hot Plug Capable : 0
+[0001] Reserved : 00
+[0002] Node ID : 0000
+[0004] Length : 00000000
+[0008] Range Address : 0000000000000000
+[0008] Range Length : 0000000000000000
+[0004] Num Power States : 00000001
+[0004] Num Physical Components : 00000001
+
+[0001] Power State : 00
+[0001] InfoIndex : 00
+
+[0002] Component Id : 0000
+
+[0002] Characteristics Count : 0002
+[0002] Reserved : 0000
+
+[0001] Structure ID : 01
+[0001] Flags (decoded below) : 00
+ Memory Preserved : 0
+ Auto Entry : 0
+ Auto Exit : 0
+[0002] Reserved : 0000
+[0004] Average Power : 00000000
+[0004] Power Saving : 00000000
+[0008] Exit Latency : 0000000000000000
+[0008] Reserved : 0000000000000000
+
+[0001] Structure ID : 01
+[0001] Flags (decoded below) : 00
+ Memory Preserved : 0
+ Auto Entry : 0
+ Auto Exit : 0
+[0002] Reserved : 0000
+[0004] Average Power : 00000000
+[0004] Power Saving : 00000000
+[0008] Exit Latency : 0000000000000000
+[0008] Reserved : 0000000000000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/msct.asl b/platforms/rtsm_ve-aemv8a.acpi/msct.asl
new file mode 100644
index 0000000..dcaf33f
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/msct.asl
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [MSCT] Maximum System Characteristics Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "MSCT"
+[0004] Table Length : 00000090
+[0001] Revision : 01
+[0001] Checksum : B7
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Proximity Offset : 00000038
+[0004] Max Proximity Domains : 00000003
+[0004] Max Clock Domains : 00000000
+[0008] Max Physical Address : 00000FFFFFFFFFFF
+
+[0001] Revision : 01
+[0001] Length : 16
+[0004] Domain Range Start : 00000000
+[0004] Domain Range End : 00000003
+[0004] Processor Capacity : 00000010
+[0008] Memory Capacity : 0000004000000000
+
+[0001] Revision : 01
+[0001] Length : 16
+[0004] Domain Range Start : 00000000
+[0004] Domain Range End : 00000000
+[0004] Processor Capacity : 00000000
+[0008] Memory Capacity : 0000000000000000
+
+[0001] Revision : 01
+[0001] Length : 16
+[0004] Domain Range Start : 00000000
+[0004] Domain Range End : 00000000
+[0004] Processor Capacity : 00000000
+[0008] Memory Capacity : 0000000000000000
+
+[0001] Revision : 01
+[0001] Length : 16
+[0004] Domain Range Start : 00000000
+[0004] Domain Range End : 00000000
+[0004] Processor Capacity : 00000000
+[0008] Memory Capacity : 0000000000000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/oem0.asl b/platforms/rtsm_ve-aemv8a.acpi/oem0.asl
new file mode 100644
index 0000000..570ea27
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/oem0.asl
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [OEMx] OEM Specific Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "OEM0"
+[0004] Table Length : 00000024
+[0001] Revision : 01
+[0001] Checksum : 8B
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 0000000A
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
diff --git a/platforms/rtsm_ve-aemv8a.acpi/pmtt.asl b/platforms/rtsm_ve-aemv8a.acpi/pmtt.asl
new file mode 100644
index 0000000..a9c5c93
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/pmtt.asl
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [PMTT] Platform Memory Topology Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "PMTT"
+[0004] Table Length : 000000B4
+[0001] Revision : 01
+[0001] Checksum : 3A
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20110826
+
+[0004] Reserved : 00000000
+
+[0001] Subtable Type : 00 [Socket]
+[0001] Reserved : 00
+[0002] Length : 0080
+[0002] Flags (decoded below) : 0001
+ Top-level Device : 1
+ Physical Element : 0
+ Memory Type : 0
+[0002] Reserved : 0000
+[0002] Socket ID : 0000
+[0002] Reserved : 0000
+
+[0001] Subtable Type : 01 [Memory Controller]
+[0001] Reserved : 00
+[0002] Length : 0054
+[0002] Flags (decoded below) : 0005
+ Top-level Device : 1
+ Physical Element : 0
+ Memory Type : 1
+[0002] Reserved : 0000
+[0004] Read Latency : 00000000
+[0004] Write Latency : 00000000
+[0004] Read Bandwidth : 00000000
+[0004] Write Bandwidth : 00000000
+[0002] Access Width : 0000
+[0002] Alignment : 0000
+[0002] Reserved : 0000
+[0002] Domain Count : 0003
+[0004] Proximity Domain : 00000000
+[0004] Proximity Domain : 00000000
+[0004] Proximity Domain : 00000000
+
+[0001] Subtable Type : 02 [Physical Component (DIMM)]
+[0001] Reserved : 00
+[0002] Length : 0014
+[0002] Flags (decoded below) : 0002
+ Top-level Device : 0
+ Physical Element : 1
+ Memory Type : 0
+[0002] Reserved : 0000
+[0002] Component ID : 0000
+[0002] Reserved : 0000
+[0004] Memory Size : 00000000
+[0004] Bios Handle : 00000000
+
+[0001] Subtable Type : 02 [Physical Component (DIMM)]
+[0001] Reserved : 00
+[0002] Length : 0014
+[0002] Flags (decoded below) : 0002
+ Top-level Device : 0
+ Physical Element : 1
+ Memory Type : 0
+[0002] Reserved : 0000
+[0002] Component ID : 0000
+[0002] Reserved : 0000
+[0004] Memory Size : 00000000
+[0004] Bios Handle : 00000000
+
+[0001] Subtable Type : 01 [Memory Controller]
+[0001] Reserved : 00
+[0002] Length : 0020
+[0002] Flags (decoded below) : 0001
+ Top-level Device : 1
+ Physical Element : 0
+ Memory Type : 0
+[0002] Reserved : 0000
+[0004] Read Latency : 00000000
+[0004] Write Latency : 00000000
+[0004] Read Bandwidth : 00000000
+[0004] Write Bandwidth : 00000000
+[0002] Access Width : 0000
+[0002] Alignment : 0000
+[0002] Reserved : 0000
+[0002] Domain Count : 0000
+
+[0001] Subtable Type : 00 [Socket]
+[0001] Reserved : 00
+[0002] Length : 000C
+[0002] Flags (decoded below) : 0001
+ Top-level Device : 1
+ Physical Element : 0
+ Memory Type : 0
+[0002] Reserved : 0000
+[0002] Socket ID : 0000
+[0002] Reserved : 0000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/rsdp.asl b/platforms/rtsm_ve-aemv8a.acpi/rsdp.asl
new file mode 100644
index 0000000..3460a77
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/rsdp.asl
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [RSDP] ACPI Table
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0008] Signature : "RSD PTR "
+[0001] Checksum : 43
+[0006] Oem ID : "LINARO"
+[0001] Revision : 02
+[0004] RSDT Address : 00000000
+[0004] Length : 00000024
+[0008] XSDT Address : 0000000000000000
+[0001] Extended Checksum : DC
+[0003] Reserved : 000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest b/platforms/rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest
new file mode 100644
index 0000000..6b3a743
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/rtsm_ve-aemv8a.manifest
@@ -0,0 +1,34 @@
+#
+# Each line is either a comment, white space, or two fields:
+#
+# <signature> : <ASL file name>
+#
+# NB: for each file x.asl, an AML file called x.aml will be created
+#
+
+rsdp: rsdp.asl
+xsdt: xsdt.asl
+facp: facp.asl
+dsdt: dsdt.asl
+ssdt: ssdt0.asl
+bert: bert.asl
+ecdt: ecdt.asl
+facs: facs.asl
+gtdt: gtdt.asl
+hest: hest.asl
+apic: apic.asl
+mcfg: mcfg.asl
+mpst: mpst.asl
+oem: oem0.asl
+pmmt: pmmt.asl
+slit: slit.asl
+spmi: spmi.asl
+srat: srat.asl
+uefi: uefi.asl
+cpep: cpep.asl
+einj: einj.asl
+erst: erst.asl
+fpdt: fpdt.asl
+mchi: mchi.asl
+msct: msct.asl
+
diff --git a/platforms/rtsm_ve-aemv8a.acpi/s3pt.asl b/platforms/rtsm_ve-aemv8a.acpi/s3pt.asl
new file mode 100644
index 0000000..694caf7
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/s3pt.asl
@@ -0,0 +1,26 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [S3PT] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "S3PT" [S3 Performance Table]
+[0004] Length : 00000034
+
+[0002] Type : 0000
+[0001] Length : 18
+[0001] Revision : 01
+
+[0004] Resume Count : 00000000
+[0008] Full Resume : 0000000000000000
+[0008] Average Resume : 0000000000000000
+
+[0002] Type : 0001
+[0001] Length : 14
+[0001] Revision : 01
+
+[0008] Suspend Start : 0000000000000000
+[0008] Suspend End : 0000000000000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/sbst.asl b/platforms/rtsm_ve-aemv8a.acpi/sbst.asl
new file mode 100644
index 0000000..714b15f
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/sbst.asl
@@ -0,0 +1,22 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [SBST] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "SBST" [Smart Battery Specification Table]
+[0004] Table Length : 00000030
+[0001] Revision : 01
+[0001] Checksum : 06
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Warning Level : 00000000
+[0004] Low Level : 00000000
+[0004] Critical Level : 00000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/slic.asl b/platforms/rtsm_ve-aemv8a.acpi/slic.asl
new file mode 100644
index 0000000..df77bf2
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/slic.asl
@@ -0,0 +1,56 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [SLIC] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "SLIC" [Software Licensing Description Table]
+[0004] Table Length : 00000176
+[0001] Revision : 01
+[0001] Checksum : 07
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20110211
+
+
+[0004] Subtable Type : 00000000 [Public Key Structure]
+[0004] Length : 0000009C
+
+[0001] Key Type : 06
+[0001] Version : 02
+[0002] Reserved : 0000
+[0004] Algorithm : 00002400
+[0004] Magic : "RSA1"
+[0004] BitLength : 00000400
+[0004] Exponent : 00000000
+[0128] Modulus : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+[0004] Subtable Type : 00000001 [Windows Marker Structure]
+[0004] Length : 000000B6
+
+[0004] Version : 00020000
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0008] Windows Flag : "WINDOWS "
+[0004] SLIC Version : 00020001
+[0016] Reserved : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+[0128] Signature : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/platforms/rtsm_ve-aemv8a.acpi/slit.asl b/platforms/rtsm_ve-aemv8a.acpi/slit.asl
new file mode 100644
index 0000000..c34e4bb
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/slit.asl
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [SLIT] System Locality Information Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "SLIT"
+[0004] Table Length : 000001BC
+[0001] Revision : 01
+[0001] Checksum : 00
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20110316
+
+[0008] Localities : 0000000000000014
+[0020] Locality 0 : 0A 10 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 \
+ 24 25 26 27
+[0020] Locality 1 : 10 0A 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 \
+ 23 24 25 26
+[0020] Locality 2 : 16 15 0A 10 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 \
+ 22 23 24 25
+[0020] Locality 3 : 17 16 10 0A 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 \
+ 21 22 23 24
+[0020] Locality 4 : 18 17 16 15 0A 10 16 17 18 19 1A 1B 1C 1D 1E 1F \
+ 20 21 22 23
+[0020] Locality 5 : 19 18 17 16 10 0A 15 16 17 18 19 1A 1B 1C 1D 1E \
+ 1F 20 21 22
+[0020] Locality 6 : 1A 19 18 17 16 15 0A 10 16 17 18 19 1A 1B 1C 1D \
+ 1E 1F 20 21
+[0020] Locality 7 : 1B 1A 19 18 17 16 10 0A 15 16 17 18 19 1A 1B 1C \
+ 1D 1E 1F 20
+[0020] Locality 8 : 1C 1B 1A 19 18 17 16 15 0A 10 16 17 18 19 1A 1B \
+ 1C 1D 1E 1F
+[0020] Locality 9 : 1D 1C 1B 1A 19 18 17 16 10 0A 15 16 17 18 19 1A \
+ 1B 1C 1D 1E
+[0020] Locality 10 : 1E 1D 1C 1B 1A 19 18 17 16 15 0A 10 16 17 18 19 \
+ 1A 1B 1C 1D
+[0020] Locality 11 : 1F 1E 1D 1C 1B 1A 19 18 17 16 10 0A 15 16 17 18 \
+ 19 1A 1B 1C
+[0020] Locality 12 : 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 0A 10 16 17 \
+ 18 19 1A 1B
+[0020] Locality 13 : 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 10 0A 15 16 \
+ 17 18 19 1A
+[0020] Locality 14 : 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 0A 10 \
+ 16 17 18 19
+[0020] Locality 15 : 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 10 0A \
+ 15 16 17 18
+[0020] Locality 16 : 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 \
+ 0A 10 16 17
+[0020] Locality 17 : 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 \
+ 10 0A 15 16
+[0020] Locality 18 : 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 \
+ 16 15 0A 10
+[0020] Locality 19 : 27 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 \
+ 17 16 10 0A
diff --git a/platforms/rtsm_ve-aemv8a.acpi/spcr.asl b/platforms/rtsm_ve-aemv8a.acpi/spcr.asl
new file mode 100644
index 0000000..7998ba8
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/spcr.asl
@@ -0,0 +1,46 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [SPCR] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "SPCR" [Serial Port Console Redirection table]
+[0004] Table Length : 00000050
+[0001] Revision : 01
+[0001] Checksum : E3
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0001] Interface Type : 00
+[0003] Reserved : 000000
+
+[0012] Serial Port Register : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+[0001] Interrupt Type : 00
+[0001] PCAT-compatible IRQ : 00
+[0004] Interrupt : 00000000
+[0001] Baud Rate : 00
+[0001] Parity : 00
+[0001] Stop Bits : 00
+[0001] Flow Control : 00
+[0001] Terminal Type : 00
+[0001] Reserved : 00
+[0002] PCI Device ID : 0000
+[0002] PCI Vendor ID : 0000
+[0001] PCI Bus : 00
+[0001] PCI Device : 00
+[0001] PCI Function : 00
+[0004] PCI Flags : 00000000
+[0001] PCI Segment : 00
+[0004] Reserved : 00000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/spmi.asl b/platforms/rtsm_ve-aemv8a.acpi/spmi.asl
new file mode 100644
index 0000000..a9f244d
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/spmi.asl
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org
+ *
+ * [SPMI] Server Platform Management Interface Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "SPMI"
+[0004] Table Length : 00000041
+[0001] Revision : 04
+[0001] Checksum : ED
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0001] Interface Type : 00
+[0001] Reserved : 00
+[0002] IPMI Spec Version : 0000
+[0001] Interrupt Type : 00
+[0001] GPE Number : 00
+[0001] Reserved : 00
+[0001] PCI Device Flag : 00
+[0004] Interrupt : 00000000
+
+[0012] IPMI Register : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 01 [Byte Access:8]
+[0008] Address : 0000000000000000
+
+[0001] PCI Segment : 00
+[0001] PCI Bus : 00
+[0001] PCI Device : 00
+[0001] PCI Function : 00
+[0001] Reserved : 00
diff --git a/platforms/rtsm_ve-aemv8a.acpi/srat.asl b/platforms/rtsm_ve-aemv8a.acpi/srat.asl
new file mode 100644
index 0000000..6d549c3
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/srat.asl
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [SRAT] System Resource Affinity Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "SRAT"
+[0004] Table Length : 00000080
+[0001] Revision : 03
+[0001] Checksum : 5A
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Table Revision : 00000001
+[0008] Reserved : 0000000000000000
+
+[0001] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[0001] Length : 10
+
+[0001] Proximity Domain Low(8) : 00
+[0001] Apic ID : 00
+[0004] Flags (decoded below) : 00000001
+ Enabled : 1
+[0001] Local Sapic EID : 00
+[0003] Proximity Domain High(24) : 000000
+[0004] Reserved : 00000000
+
+[0001] Subtable Type : 01 [Memory Affinity]
+[0001] Length : 28
+
+[0004] Proximity Domain : 00000000
+[0002] Reserved1 : 0000
+[0008] Base Address : 0000000000000000
+[0008] Address Length : 000000000009FC00
+[0004] Reserved2 : 00000000
+[0004] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0008] Reserved3 : 0000000000000000
+
+[0001] Subtable Type : 02 [Processor Local x2APIC Affinity]
+[0001] Length : 18
+
+[0002] Reserved1 : 0000
+[0004] Proximity Domain : 00000000
+[0004] Apic ID : 00000000
+[0004] Flags (decoded below) : 00000001
+ Enabled : 1
+[0004] Clock Domain : 00000000
+[0004] Reserved2 : 00000000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl b/platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl
new file mode 100644
index 0000000..8975977
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/ssdt0.asl
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [SSDT] Description of the Arndale board (exynos5250) GPIO structure
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+DefinitionBlock (
+ "ssdt0.aml", // output filename
+ "SSDT", // table signature
+ 2, // SSDT compliance revision
+ "LINARO", // OEM ID
+ "RTSMVEV8", // table ID
+ 0x00000001) // OEM revision
+{
+}
diff --git a/platforms/rtsm_ve-aemv8a.acpi/tcpa.asl b/platforms/rtsm_ve-aemv8a.acpi/tcpa.asl
new file mode 100644
index 0000000..cfdfa39
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/tcpa.asl
@@ -0,0 +1,22 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [TCPA] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "TCPA" [Trusted Computing Platform Alliance table]
+[0004] Table Length : 00000032
+[0001] Revision : 01
+[0001] Checksum : 67
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00003180
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0002] Reserved : 0000
+[0004] Max Event Log Length : 00000000
+[0008] Event Log Address : 0000000000000001
diff --git a/platforms/rtsm_ve-aemv8a.acpi/tpm2.asl b/platforms/rtsm_ve-aemv8a.acpi/tpm2.asl
new file mode 100644
index 0000000..38cc502
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/tpm2.asl
@@ -0,0 +1,22 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [TPM2] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "TPM2" [Trusted Platform Module hardware interface table]
+[0004] Table Length : 00000034
+[0001] Revision : 03
+[0001] Checksum : 42
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20121114
+
+[0004] Flags : 00000000
+[0008] Control Address : 0011223344556677
+[0004] Start Method : 00000001
diff --git a/platforms/rtsm_ve-aemv8a.acpi/uefi.asl b/platforms/rtsm_ve-aemv8a.acpi/uefi.asl
new file mode 100644
index 0000000..855e330
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/uefi.asl
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [UEFI] UEFI Boot Optimization Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "UEFI"
+[0004] Table Length : 00000036
+[0001] Revision : 01
+[0001] Checksum : 9B
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0016] UUID Identifier : 03020100-0504-0706-0809-0A0B0C0D0E0F
+[0002] Data Offset : 0000
diff --git a/platforms/rtsm_ve-aemv8a.acpi/waet.asl b/platforms/rtsm_ve-aemv8a.acpi/waet.asl
new file mode 100644
index 0000000..b459110
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/waet.asl
@@ -0,0 +1,22 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [WAET] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "WAET" [Windows ACPI Emulated Devices Table]
+[0004] Table Length : 00000028
+[0001] Revision : 01
+[0001] Checksum : 19
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Flags (decoded below) : 00000000
+ RTC needs no INT ack : 0
+ PM timer, one read only : 0
diff --git a/platforms/rtsm_ve-aemv8a.acpi/wdat.asl b/platforms/rtsm_ve-aemv8a.acpi/wdat.asl
new file mode 100644
index 0000000..e49205a
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/wdat.asl
@@ -0,0 +1,47 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [WDAT] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "WDAT" [Watchdog Action Table]
+[0004] Table Length : 0000005C
+[0001] Revision : 01
+[0001] Checksum : E3
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0004] Header Length : 00000020
+[0002] PCI Segment : 00FF
+[0001] PCI Bus : FF
+[0001] PCI Device : FF
+[0001] PCI Function : FF
+[0003] Reserved : 000000
+[0004] Timer Period : 00000258
+[0004] Max Count : 000003FF
+[0004] Min Count : 00000002
+[0001] Flags (decoded below) : 00
+ Enabled : 0
+ Stopped When Asleep : 0
+[0003] Reserved : 000000
+[0004] Watchdog Entry Count : 0000000E
+
+[0001] Watchdog Action : 01
+[0001] Instruction : 02
+[0002] Reserved : 0000
+
+[0012] Register Region : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 10
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 02 [Word Access:16]
+[0008] Address : 0000000000000460
+
+[0004] Value : 00000001
+[0004] Register Mask : 00000001
diff --git a/platforms/rtsm_ve-aemv8a.acpi/wddt.asl b/platforms/rtsm_ve-aemv8a.acpi/wddt.asl
new file mode 100644
index 0000000..a0b039e
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/wddt.asl
@@ -0,0 +1,44 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [WDDT] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "WDDT" [Watchdog Description Table]
+[0004] Table Length : 00000040
+[0001] Revision : 01
+[0001] Checksum : 00
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0002] Specification Version : 0000
+[0002] Table Version : 0000
+[0002] PCI Vendor ID : 0000
+
+[0012] Timer Register : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : FF
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+[0002] Max Count : 0000
+[0002] Min Count : 0000
+[0002] Period : 0000
+[0002] Status (decoded below) : 0000
+ Available : 0
+ Active : 0
+ OS Owns : 0
+ User Reset : 0
+ Timeout Reset : 0
+ Power Fail Reset : 0
+ Unknown Reset : 0
+[0002] Capability (decoded below) : 0000
+ Auto Reset : 0
+ Timeout Alert : 0
diff --git a/platforms/rtsm_ve-aemv8a.acpi/wdrt.asl b/platforms/rtsm_ve-aemv8a.acpi/wdrt.asl
new file mode 100644
index 0000000..14453c7
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/wdrt.asl
@@ -0,0 +1,42 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [WDRT] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "WDRT" [Watchdog Resource Table]
+[0004] Table Length : 00000047
+[0001] Revision : 01
+[0001] Checksum : B0
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+
+[0012] Control Register : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 20
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+[0012] Count Register : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 20
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+[0002] PCI Device ID : FFFF
+[0002] PCI Vendor ID : FFFF
+[0001] PCI Bus : 00
+[0001] PCI Device : 00
+[0001] PCI Function : 00
+[0001] PCI Segment : 00
+[0002] Max Count : FFFF
+[0001] Counter Units : 00
diff --git a/platforms/rtsm_ve-aemv8a.acpi/xsdt.asl b/platforms/rtsm_ve-aemv8a.acpi/xsdt.asl
new file mode 100644
index 0000000..74f0c70
--- /dev/null
+++ b/platforms/rtsm_ve-aemv8a.acpi/xsdt.asl
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ *
+ * [XSDT] Extended System Description Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ * This source is released under the terms of the GPLv2.
+ */
+
+[0004] Signature : "XSDT"
+[0004] Table Length : 00000064
+[0001] Revision : 01
+[0001] Checksum : 8B
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000014
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0008] ACPI Table Address 0 : 0000000000000010
+[0008] ACPI Table Address 0 : 0000000000000020
+[0008] ACPI Table Address 0 : 0000000000000030
+[0008] ACPI Table Address 0 : 0000000000000040
+[0008] ACPI Table Address 0 : 0000000000000050
+[0008] ACPI Table Address 0 : 0000000000000060
+[0008] ACPI Table Address 0 : 0000000000000070
+[0008] ACPI Table Address 0 : 0000000000000080
+[0008] ACPI Table Address 0 : 0000000000000090
+[0008] ACPI Table Address 0 : 00000000000000A0
+[0008] ACPI Table Address 0 : 00000000000000B0
+[0008] ACPI Table Address 0 : 00000000000000C0
+[0008] ACPI Table Address 0 : 00000000000000D0
+[0008] ACPI Table Address 0 : 00000000000000E0
+[0008] ACPI Table Address 0 : 00000000000000F0
+[0008] ACPI Table Address 0 : 0000000000000100
+[0008] ACPI Table Address 0 : 0000000000000110
+[0008] ACPI Table Address 0 : 0000000000000120
+[0008] ACPI Table Address 0 : 0000000000000130
+[0008] ACPI Table Address 0 : 0000000000000140
--
1.7.10.4
11 years, 8 months
- 1
- 0
[PATCHv2] meta-linaro: acpica: fix style issues
by Graeme Gregory
Fix recipe to be OE compliant with spacing SRCREV and PV.
Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org>
---
meta-linaro/recipes-extra/acpica/acpica_20130626.bb | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/meta-linaro/recipes-extra/acpica/acpica_20130626.bb b/meta-linaro/recipes-extra/acpica/acpica_20130626.bb
index 58d7c4b..e4218fd 100644
--- a/meta-linaro/recipes-extra/acpica/acpica_20130626.bb
+++ b/meta-linaro/recipes-extra/acpica/acpica_20130626.bb
@@ -1,21 +1,20 @@
+SUMMARY = "ACPICA tools for the development and debug of ACPI tables"
DESCRIPTION = "The ACPI Component Architecture (ACPICA) project provides an \
OS-independent reference implementation of the Advanced Configuration and \
Power Interface Specification (ACPI). ACPICA code contains those portions of \
ACPI meant to be directly integrated into the host OS as a kernel-resident \
subsystem, and a small set of tools to assist in developing and debugging \
ACPI tables."
-SUMMARY = "ACPICA tools for the development and debug of ACPI tables"
HOMEPAGE = "http://www.acpica.org/"
SECTION = "console/tools"
LICENSE = "BSD | GPLv2"
LIC_FILES_CHKSUM = "file://generate/unix/readme.txt;md5=204407e197c1a01154a48f6c6280c3aa"
-DEPENDS="bison \
- flex"
-COMPATIBLE_HOST = "(i.86|x86_64|arm|aarch64).*-linux"
-
-PR="r2"
+DEPENDS = "bison flex"
+SRCREV = "780de9ee36e5a7b4acc29a2ccd43d6bdc5dd5219"
+PV = "20130626+git${SRCPV}"
+PR = "r3"
-SRC_URI="git://git.linaro.org/people/ahs3/acpica-tools.git \
+SRC_URI = "git://git.linaro.org/people/ahs3/acpica-tools.git \
file://fix_ftbfs_debian-kfreebsd.patch \
file://debian-big_endian.patch \
file://debian-unaligned.patch \
@@ -27,8 +26,6 @@ SRC_URI="git://git.linaro.org/people/ahs3/acpica-tools.git \
file://no-werror.patch \
file://fix-parallel-build.patch"
-SRCREV = "${AUTOREV}"
-
S = "${WORKDIR}/git"
EXTRA_OEMAKE = "'OPT_CFLAGS=-Wall'"
@@ -42,3 +39,6 @@ do_install() {
install -D -p -m0755 generate/unix/bin*/acpisrc ${D}${bindir}/acpisrc
install -D -p -m0755 generate/unix/bin*/acpixtract ${D}${bindir}/acpixtract
}
+
+COMPATIBLE_HOST = "(i.86|x86_64|arm|aarch64).*-linux"
+
--
1.7.10.4
11 years, 9 months
- 2
- 1
[RFC][PATCH 1/2] ARM64: add cpu topology definition
by Hanjun Guo
Power aware scheduling needs the cpu topology information to improve the
cpu scheduler decision making.
For ARM64, we can get the topology from the MPIDR register which defines the
the affinity of processors.
This patch is mainly based on arch/arm/kernel/topology.c written by
Vincent Guittot, and replaced the topology array with per cpu variable.
Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org>
---
arch/arm64/Kconfig | 9 +++
arch/arm64/include/asm/cputype.h | 11 ++++
arch/arm64/include/asm/topology.h | 41 ++++++++++++
arch/arm64/kernel/Makefile | 1 +
arch/arm64/kernel/smp.c | 6 ++
arch/arm64/kernel/topology.c | 128 +++++++++++++++++++++++++++++++++++++
6 files changed, 196 insertions(+)
create mode 100644 arch/arm64/include/asm/topology.h
create mode 100644 arch/arm64/kernel/topology.c
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 9737e97..f0ce91b 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -150,6 +150,15 @@ config SMP
If you don't know what to do here, say N.
+config ARM64_CPU_TOPOLOGY
+ bool "Support cpu topology definition"
+ depends on SMP && ARM64
+ default y
+ help
+ Support ARM64 cpu topology definition. The MPIDR register defines
+ affinity between processors which is then used to describe the cpu
+ topology of an ARM64 System.
+
config NR_CPUS
int "Maximum number of CPUs (2-32)"
range 2 32
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 5fe138e..68b55af 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -30,6 +30,17 @@
#define MPIDR_HWID_BITMASK 0xff00ffffff
+#define MPIDR_SMP_BITMASK (0x1 << 30)
+#define MPIDR_MT_BITMASK (0x1 << 24)
+
+#define MPIDR_LEVEL_BITS 8
+#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
+
+#define MPIDR_AFFINITY_LEVEL_0(mpidr) ((mpidr) & MPIDR_LEVEL_MASK)
+#define MPIDR_AFFINITY_LEVEL_1(mpidr) ((mpidr >> 8) & MPIDR_LEVEL_MASK)
+#define MPIDR_AFFINITY_LEVEL_2(mpidr) ((mpidr >> 16) & MPIDR_LEVEL_MASK)
+#define MPIDR_AFFINITY_LEVEL_3(mpidr) ((mpidr >> 32) & MPIDR_LEVEL_MASK)
+
#define read_cpuid(reg) ({ \
u64 __val; \
asm("mrs %0, " reg : "=r" (__val)); \
diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h
new file mode 100644
index 0000000..8631808
--- /dev/null
+++ b/arch/arm64/include/asm/topology.h
@@ -0,0 +1,41 @@
+#ifndef _ASM_ARM64_TOPOLOGY_H
+#define _ASM_ARM64_TOPOLOGY_H
+
+#ifdef CONFIG_ARM64_CPU_TOPOLOGY
+
+#include <linux/cpumask.h>
+
+struct cputopo_arm64 {
+ int thread_id;
+ int core_id;
+ int socket_id;
+ cpumask_t thread_sibling;
+ cpumask_t core_sibling;
+};
+
+DECLARE_PER_CPU(struct cputopo_arm64, cpu_topology);
+
+#define cpu_topo(cpu) per_cpu(cpu_topology, cpu)
+
+#define topology_physical_package_id(cpu) (cpu_topo(cpu).socket_id)
+#define topology_core_id(cpu) (cpu_topo(cpu).core_id)
+#define topology_core_cpumask(cpu) (&cpu_topo(cpu).core_sibling)
+#define topology_thread_cpumask(cpu) (&cpu_topo(cpu).thread_sibling)
+
+#define mc_capable() (cpu_topo(0).socket_id != -1)
+#define smt_capable() (cpu_topo(0).thread_id != -1)
+
+void init_cpu_topology(void);
+void store_cpu_topology(unsigned int cpuid);
+const struct cpumask *cpu_coregroup_mask(int cpu);
+
+#else
+
+static inline void init_cpu_topology(void) { }
+static inline void store_cpu_topology(unsigned int cpuid) { }
+
+#endif
+
+#include <asm-generic/topology.h>
+
+#endif /* _ASM_ARM64_TOPOLOGY_H */
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index 7b4b564..a47c359 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -18,6 +18,7 @@ arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o smp_psci.o
arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)+= hw_breakpoint.o
arm64-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+arm64-obj-$(CONFIG_ARM64_CPU_TOPOLOGY) += topology.o
obj-y += $(arm64-obj-y) vdso/
obj-m += $(arm64-obj-m)
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index fee5cce..197b1da 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -39,6 +39,7 @@
#include <asm/atomic.h>
#include <asm/cacheflush.h>
#include <asm/cputype.h>
+#include <asm/topology.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/pgalloc.h>
@@ -215,6 +216,8 @@ asmlinkage void secondary_start_kernel(void)
local_irq_enable();
local_fiq_enable();
+ store_cpu_topology(cpu);
+
/*
* OK, it's off to the idle thread for us
*/
@@ -387,6 +390,9 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
int cpu, err;
unsigned int ncores = num_possible_cpus();
+ init_cpu_topology();
+ store_cpu_topology(smp_processor_id());
+
/*
* are we trying to boot more cores than exist?
*/
diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c
new file mode 100644
index 0000000..1eb0435
--- /dev/null
+++ b/arch/arm64/kernel/topology.c
@@ -0,0 +1,128 @@
+/*
+ * arch/arm64/kernel/topology.c
+ *
+ * Copyright (C) 2013 Linaro Limited.
+ * Written by: Hanjun Guo
+ *
+ * based on arch/arm/kernel/topology.c
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/cpu.h>
+#include <linux/cpumask.h>
+#include <linux/init.h>
+#include <linux/percpu.h>
+#include <linux/sched.h>
+
+#include <asm/cputype.h>
+#include <asm/topology.h>
+
+DEFINE_PER_CPU(struct cputopo_arm64, cpu_topology);
+
+const struct cpumask *cpu_coregroup_mask(int cpu)
+{
+ return &cpu_topo(cpu).core_sibling;
+}
+
+void update_siblings_masks(unsigned int cpuid)
+{
+ struct cputopo_arm64 *topo, *cpuid_topo = &cpu_topo(cpuid);
+ int cpu;
+
+ /* update core and thread sibling masks */
+ for_each_possible_cpu(cpu) {
+ topo = &cpu_topo(cpu);
+
+ if (cpuid_topo->socket_id != topo->socket_id)
+ continue;
+
+ cpumask_set_cpu(cpuid, &topo->core_sibling);
+ if (cpu != cpuid)
+ cpumask_set_cpu(cpu, &cpuid_topo->core_sibling);
+
+ if (cpuid_topo->core_id != topo->core_id)
+ continue;
+
+ cpumask_set_cpu(cpuid, &topo->thread_sibling);
+ if (cpu != cpuid)
+ cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling);
+ }
+ smp_wmb();
+}
+
+/*
+ * store_cpu_topology is called at boot when only one cpu is running
+ * and with the mutex cpu_hotplug.lock locked, when several cpus have booted,
+ * which prevents simultaneous write access to cpu_topology array
+ */
+void store_cpu_topology(unsigned int cpuid)
+{
+ struct cputopo_arm64 *cpuid_topo = &cpu_topo(cpuid);
+ u64 mpidr;
+
+ /* If the cpu topology has been already set, just return */
+ if (cpuid_topo->core_id != -1)
+ return;
+
+ mpidr = read_cpuid_mpidr();
+
+ /* create cpu topology mapping */
+ if (!(mpidr & MPIDR_SMP_BITMASK)) {
+ /*
+ * This is a multiprocessor system
+ * multiprocessor format & multiprocessor mode field are set
+ */
+
+ if (mpidr & MPIDR_MT_BITMASK) {
+ /* core performance interdependency */
+ cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL_0(mpidr);
+ cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL_1(mpidr);
+ cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL_2(mpidr);
+ } else {
+ /* largely independent cores */
+ cpuid_topo->thread_id = -1;
+ cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL_0(mpidr);
+ cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL_1(mpidr);
+ }
+ } else {
+ /*
+ * This is an uniprocessor system
+ * we are in multiprocessor format but uniprocessor system
+ * or in the old uniprocessor format
+ */
+ cpuid_topo->thread_id = -1;
+ cpuid_topo->core_id = 0;
+ cpuid_topo->socket_id = -1;
+ }
+
+ update_siblings_masks(cpuid);
+
+ printk(KERN_INFO "CPU%u: thread %d, cpu %d, socket %d, mpidr 0x%llx\n",
+ cpuid, cpu_topo(cpuid).thread_id,
+ cpu_topo(cpuid).core_id,
+ cpu_topo(cpuid).socket_id, mpidr);
+}
+
+/*
+ * init_cpu_topology is called at boot when only one cpu is running
+ * which prevent simultaneous write access to cpu_topology array
+ */
+void __init init_cpu_topology(void)
+{
+ unsigned int cpu;
+
+ /* init core mask */
+ for_each_possible_cpu(cpu) {
+ struct cputopo_arm64 *topo = &cpu_topo(cpu);
+
+ topo->thread_id = -1;
+ topo->core_id = -1;
+ topo->socket_id = -1;
+ cpumask_clear(&topo->core_sibling);
+ cpumask_clear(&topo->thread_sibling);
+ }
+ smp_wmb();
+}
--
1.7.9.5
11 years, 9 months
- 9
- 20
[PATCH] ACPICA:enable 64bit build for aarch64 architecture
by naresh.bhat＠linaro.org
From: Naresh Bhat <naresh.bhat(a)linaro.org>
Signed-off-by: Naresh Bhat <naresh.bhat(a)linaro.org>
Enable 64 bit build for aarch64 architecture in ACPICA Linux
platform specific defines.
---
source/include/platform/aclinux.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/source/include/platform/aclinux.h b/source/include/platform/aclinux.h
index e561292..6b8b1ab 100644
--- a/source/include/platform/aclinux.h
+++ b/source/include/platform/aclinux.h
@@ -159,7 +159,7 @@
#define ACPI_FLUSH_CPU_CACHE()
#define ACPI_CAST_PTHREAD_T(pthread) ((ACPI_THREAD_ID) (pthread))
-#if defined(__ia64__) || defined(__x86_64__)
+#if defined(__ia64__) || defined(__x86_64__) || (__aarch64__)
#define ACPI_MACHINE_WIDTH 64
#define COMPILER_DEPENDENT_INT64 long
#define COMPILER_DEPENDENT_UINT64 unsigned long
--
1.7.9.5
11 years, 9 months
- 3
- 3
[PATCH] ACPICA:enable 64bit build for aarch64 architecture
by naresh.bhat＠linaro.org
From: Naresh Bhat <naresh.bhat(a)linaro.org>
Signed-off-by: Naresh Bhat <naresh.bhat(a)linaro.org>
Enable 64 bit build for aarch64 architecture in ACPICA Linux
platform specific defines.
---
src/acpica/source/include/platform/aclinux.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/acpica/source/include/platform/aclinux.h b/src/acpica/source/include/platform/aclinux.h
index e561292..6b8b1ab 100644
--- a/src/acpica/source/include/platform/aclinux.h
+++ b/src/acpica/source/include/platform/aclinux.h
@@ -159,7 +159,7 @@
#define ACPI_FLUSH_CPU_CACHE()
#define ACPI_CAST_PTHREAD_T(pthread) ((ACPI_THREAD_ID) (pthread))
-#if defined(__ia64__) || defined(__x86_64__)
+#if defined(__ia64__) || defined(__x86_64__) || (__aarch64__)
#define ACPI_MACHINE_WIDTH 64
#define COMPILER_DEPENDENT_INT64 long
#define COMPILER_DEPENDENT_UINT64 unsigned long
--
1.7.9.5
11 years, 9 months
- 2
- 1
[PATCH 0/3] acpi-asl.git: various mab bug repairs
by al.stone＠linaro.org
From: Al Stone <ahs3(a)redhat.com>
This is complete reorganization of what used to be "Various
fix-ups and additions to mab" patches 3 and 4 (5 has been
completely rethought as a seperate series to appear later).
What this patch does is add in a change log that should have been
there all along, and comment the versioning a little better. The
more substantial bug fix is that code that checked whether there
was enough room in the XSDT for all the tables being added would
only do so when verbose mode was being used. This error check now
occurs under all conditions as it should have.
Al Stone (3):
mab: add in a Changelog to improve documentation
mab: report an XSDT error regardless of whether we're verbose or not
mab: update version number (and comment it better)
tools/mab/Changelog | 9 +++++++++
tools/mab/mab.c | 19 +++++++++++--------
tools/mab/mab.h | 3 ++-
3 files changed, 22 insertions(+), 9 deletions(-)
create mode 100644 tools/mab/Changelog
--
1.8.3.1
11 years, 9 months
- 2
- 4
[PATCH 0/5] Various fix-ups and additions to mab
by al.stone＠linaro.org
From: Al Stone <ahs3(a)redhat.com>
These are mostly minor fixups to mab:
-- report usage properly
-- do not segfault if missing the -p <paddr> parameter
-- if the XSDT did not have enough room for tables, it would
not discover that or notify anyone unless it was being
verbose; now it will always report that error if found
-- and just because it wasn't verbose enough, add the final
relocated address of the table to the output
-- update the version number
Al Stone (5):
mab: minor cleanup of usage output
mab: if -p <paddr> is not given, we would segfault; die more
gracefully now
mab: update version number
mab: report an XSDT error regardless of whether we're verbose or not
mab: add final relocated address to verbose output
tools/mab/mab.c | 52 ++++++++++++++++++++++++++++++++++++----------------
tools/mab/mab.h | 4 +++-
2 files changed, 39 insertions(+), 17 deletions(-)
--
1.8.3.1
11 years, 9 months
- 3
- 14
[PATCH] meta-linaro: acpica: fix style issues
by Graeme Gregory
Fix recipe to be OE complient with spacing SRCREV and PV.
Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org>
---
meta-aarch64/conf/machine/genericarmv8.conf | 8 ++++----
meta-linaro/recipes-extra/acpica/acpica_20130626.bb | 18 +++++++++---------
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/meta-aarch64/conf/machine/genericarmv8.conf b/meta-aarch64/conf/machine/genericarmv8.conf
index 6d84e0d..ab8900e 100644
--- a/meta-aarch64/conf/machine/genericarmv8.conf
+++ b/meta-aarch64/conf/machine/genericarmv8.conf
@@ -23,15 +23,15 @@ PREFERRED_PROVIDER_virtual/kernel ?= "linux-linaro"
KERNEL_IMAGETYPE = "Image"
# We have to disable SERIAL_CONSOLE due to auto-serial-console
-#SERIAL_CONSOLE = "115200 ttyAMA0"
+SERIAL_CONSOLE = "115200 ttyAMA0"
# Force auto-serial-console to be used by all image types
# Ideally this would be part of core oe or as a bbclassappend,
# but as we don't have an easy way to append a class, defining
# it here
-EXTRA_IMAGE_FEATURES += "autoserial"
-PACKAGE_GROUP_autoserial = "auto-serial-console"
+#EXTRA_IMAGE_FEATURES += "autoserial"
+#PACKAGE_GROUP_autoserial = "auto-serial-console"
# we do not want to have getty running on tty1 as we run
# auto-serial-console there
-USE_VT = "0"
+#USE_VT = "0"
diff --git a/meta-linaro/recipes-extra/acpica/acpica_20130626.bb b/meta-linaro/recipes-extra/acpica/acpica_20130626.bb
index 58d7c4b..e4218fd 100644
--- a/meta-linaro/recipes-extra/acpica/acpica_20130626.bb
+++ b/meta-linaro/recipes-extra/acpica/acpica_20130626.bb
@@ -1,21 +1,20 @@
+SUMMARY = "ACPICA tools for the development and debug of ACPI tables"
DESCRIPTION = "The ACPI Component Architecture (ACPICA) project provides an \
OS-independent reference implementation of the Advanced Configuration and \
Power Interface Specification (ACPI). ACPICA code contains those portions of \
ACPI meant to be directly integrated into the host OS as a kernel-resident \
subsystem, and a small set of tools to assist in developing and debugging \
ACPI tables."
-SUMMARY = "ACPICA tools for the development and debug of ACPI tables"
HOMEPAGE = "http://www.acpica.org/"
SECTION = "console/tools"
LICENSE = "BSD | GPLv2"
LIC_FILES_CHKSUM = "file://generate/unix/readme.txt;md5=204407e197c1a01154a48f6c6280c3aa"
-DEPENDS="bison \
- flex"
-COMPATIBLE_HOST = "(i.86|x86_64|arm|aarch64).*-linux"
-
-PR="r2"
+DEPENDS = "bison flex"
+SRCREV = "780de9ee36e5a7b4acc29a2ccd43d6bdc5dd5219"
+PV = "20130626+git${SRCPV}"
+PR = "r3"
-SRC_URI="git://git.linaro.org/people/ahs3/acpica-tools.git \
+SRC_URI = "git://git.linaro.org/people/ahs3/acpica-tools.git \
file://fix_ftbfs_debian-kfreebsd.patch \
file://debian-big_endian.patch \
file://debian-unaligned.patch \
@@ -27,8 +26,6 @@ SRC_URI="git://git.linaro.org/people/ahs3/acpica-tools.git \
file://no-werror.patch \
file://fix-parallel-build.patch"
-SRCREV = "${AUTOREV}"
-
S = "${WORKDIR}/git"
EXTRA_OEMAKE = "'OPT_CFLAGS=-Wall'"
@@ -42,3 +39,6 @@ do_install() {
install -D -p -m0755 generate/unix/bin*/acpisrc ${D}${bindir}/acpisrc
install -D -p -m0755 generate/unix/bin*/acpixtract ${D}${bindir}/acpixtract
}
+
+COMPATIBLE_HOST = "(i.86|x86_64|arm|aarch64).*-linux"
+
--
1.7.10.4
11 years, 9 months
- 1
- 1
[PATCH v2] exynos5250-arndale: DSDT requires _CRS to be serialized
by al.stone＠linaro.org
From: Al Stone <ahs3(a)redhat.com>
This patch applies to the acpi-asl.git tree.
This corrects a minor error reported by iasl
when compiling the DSDT for Arndale. The error
is minor enough that iasl still produces a
table but it could potentially affect operation.
Changes for v2:
-- added some sort of explanation for the patch
Signed-off-by: Al Stone <al.stone(a)linaro.org>
---
platforms/exynos5250-arndale.acpi/dsdt.asl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/platforms/exynos5250-arndale.acpi/dsdt.asl b/platforms/exynos5250-arndale.acpi/dsdt.asl
index 2cca765..7f05c6b 100644
--- a/platforms/exynos5250-arndale.acpi/dsdt.asl
+++ b/platforms/exynos5250-arndale.acpi/dsdt.asl
@@ -23,7 +23,7 @@ DefinitionBlock (
Name (_HID, "LINA0001")
Name (_UID, 0)
- Method (_CRS, 0x0, NotSerialized) {
+ Method (_CRS, 0x0, Serialized) {
Name (RBUF, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0x12C60000, 0x00000100)
--
1.8.3.1
11 years, 9 months
- 2
- 1
[PATCH] ARM: EXYNOS: Set 64-bit DMA mask for EXYNOS5250
by al.stone＠linaro.org
From: Al Stone <ahs3(a)redhat.com>
This patch is a re-submittal of a previous patch from the
Samsung LT, specifically 5bf534ab87a62e717771d5548b66296ca8e9fbe5.
It has been redone to fit the acpi-ltfixes branch of acpi.git,
and is needed to prevent DMA errors from occurring.
This is required when LPAE is enabled.
Signed-off-by: Tushar Behera <tushar.behera(a)linaro.org>
Signed-off-by: Al Stone <al.stone(a)linaro.org>
---
arch/arm/mach-exynos/mach-exynos5-dt.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index f874b77..863042d 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -14,6 +14,7 @@
#include <linux/memblock.h>
#include <linux/io.h>
#include <linux/clocksource.h>
+#include <linux/dma-mapping.h>
#include <asm/mach/arch.h>
#include <mach/regs-pmu.h>
@@ -23,6 +24,26 @@
#include "common.h"
+static u64 dma_mask64 = DMA_BIT_MASK(64);
+
+static int exynos5250_platform_notifier(struct notifier_block *nb,
+ unsigned long event, void *__dev)
+{
+ struct device *dev = __dev;
+
+ if (event != BUS_NOTIFY_ADD_DEVICE)
+ return NOTIFY_DONE;
+
+ dev->dma_mask = &dma_mask64;
+ dev->coherent_dma_mask = DMA_BIT_MASK(64);
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block exynos5250_platform_nb = {
+ .notifier_call = exynos5250_platform_notifier,
+};
+
static void __init exynos5_dt_machine_init(void)
{
struct device_node *i2c_np;
@@ -47,6 +68,9 @@ static void __init exynos5_dt_machine_init(void)
}
}
+ if (of_machine_is_compatible("samsung,exynos5250"))
+ bus_register_notifier(&platform_bus_type, &exynos5250_platform_nb);
+
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
--
1.8.3.1
11 years, 9 months
- 3
- 2
[PATCH 1/3] cpufreq / gx: Fix __init attribute locations
by Hanjun Guo
__init belongs after the return type on functions, not before it.
Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org>
---
drivers/cpufreq/gx-suspmod.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cpufreq/gx-suspmod.c b/drivers/cpufreq/gx-suspmod.c
index 3dfc99b..e30fd16 100644
--- a/drivers/cpufreq/gx-suspmod.c
+++ b/drivers/cpufreq/gx-suspmod.c
@@ -183,7 +183,7 @@ static void gx_write_byte(int reg, int value)
* gx_detect_chipset:
*
**/
-static __init struct pci_dev *gx_detect_chipset(void)
+static struct pci_dev * __init gx_detect_chipset(void)
{
struct pci_dev *gx_pci = NULL;
--
1.7.9.5
11 years, 9 months
- 2
- 3
[PATCH 1/3] ACPI / dock: Fix __init attribute locations
by Hanjun Guo
__init belongs after the return type on functions, not before it.
Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org>
---
drivers/acpi/dock.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/acpi/dock.c b/drivers/acpi/dock.c
index 8265607..c90112c 100644
--- a/drivers/acpi/dock.c
+++ b/drivers/acpi/dock.c
@@ -1055,7 +1055,7 @@ err_unregister:
*
* This is called by acpi_walk_namespace to look for dock stations and bays.
*/
-static __init acpi_status
+static acpi_status __init
find_dock_and_bay(acpi_handle handle, u32 lvl, void *context, void **rv)
{
if (is_dock(handle) || is_ejectable_bay(handle))
--
1.7.9.5
11 years, 9 months
- 2
- 3
[PATCH] Fix typecast warning on aarch64
by naresh.bhat＠linaro.org
From: Naresh Bhat <naresh.bhat(a)linaro.org>
Signed-off-by: Naresh Bhat<naresh.bhat(a)linaro.org>
This patch fix all typecast warnings being treated as errors
occured while compiling on ARMv8 aarch64 architecture.
---
src/acpi/method/method.c | 92 +++++++++++++++++++++++-----------------------
1 file changed, 46 insertions(+), 46 deletions(-)
diff --git a/src/acpi/method/method.c b/src/acpi/method/method.c
index f46fdff..327a887 100644
--- a/src/acpi/method/method.c
+++ b/src/acpi/method/method.c
@@ -976,14 +976,14 @@ static void method_test_HID_return(
tmp, sizeof(tmp)))
fwts_passed(fw, "%s returned an integer "
"0x%8.8" PRIx64 " (EISA ID %s).",
- name, obj->Integer.Value, tmp);
+ name, (long unsigned int)obj->Integer.Value, tmp);
else
fwts_failed(fw, LOG_LEVEL_MEDIUM,
"MethodHIDInvalidInteger",
"%s returned a integer 0x%8.8" PRIx64 " "
"(EISA ID %s) but the this is not a valid "
"EISA ID encoded PNP ID.",
- name, obj->Integer.Value, tmp);
+ name, (long unsigned int)obj->Integer.Value, tmp);
break;
default:
fwts_failed(fw, LOG_LEVEL_MEDIUM, "Method_HIDBadReturnType",
@@ -1865,7 +1865,7 @@ static void method_test_FIX_return(
"%s returned an integer "
"0x%8.8" PRIx64 " in package element "
"%" PRIu32 " that is not a valid "
- "EISA ID.", name, obj->Integer.Value, i);
+ "EISA ID.", name, (long unsigned int)obj->Integer.Value, i);
failed = true;
}
}
@@ -2092,7 +2092,7 @@ static void method_test_SEG_return(
"%s returned value 0x%8.8" PRIx64 " and some of the "
"upper 16 reserved bits are set when they "
"should in fact be zero.",
- name, obj->Integer.Value);
+ name, (long unsigned int)obj->Integer.Value);
fwts_tag_failed(fw, FWTS_TAG_ACPI_METHOD_RETURN);
} else
method_passed_sane_uint64(fw, name, obj->Integer.Value);
@@ -2333,9 +2333,9 @@ static void method_test_Sx__return(
}
fwts_log_info(fw, "%s PM1a_CNT.SLP_TYP value: 0x%8.8" PRIx64, name,
- obj->Package.Elements[0].Integer.Value);
+ (long unsigned int)obj->Package.Elements[0].Integer.Value);
fwts_log_info(fw, "%s PM1b_CNT.SLP_TYP value: 0x%8.8" PRIx64, name,
- obj->Package.Elements[1].Integer.Value);
+ (long unsigned int)obj->Package.Elements[1].Integer.Value);
if (!failed)
method_passed_sane(fw, name, "package");
@@ -2484,7 +2484,7 @@ static void method_test_CSD_return(
"%s sub-package %d element 0 (NumEntries) "
"was expected to have value 0x%" PRIx64 ".",
name, i,
- pkg->Package.Elements[0].Integer.Value);
+ (long unsigned int)pkg->Package.Elements[0].Integer.Value);
fwts_tag_failed(fw, FWTS_TAG_ACPI_METHOD_RETURN);
failed = true;
}
@@ -2496,7 +2496,7 @@ static void method_test_CSD_return(
"was expected to have value 1, instead it "
"was 0x%" PRIx64 ".",
name, i,
- pkg->Package.Elements[1].Integer.Value);
+ (long unsigned int)pkg->Package.Elements[1].Integer.Value);
fwts_tag_failed(fw, FWTS_TAG_ACPI_METHOD_RETURN);
failed = true;
}
@@ -2511,7 +2511,7 @@ static void method_test_CSD_return(
"0xfd (SW_ANY) or 0xfe (HW_ALL), instead it "
"was 0x%" PRIx64 ".",
name, i,
- pkg->Package.Elements[3].Integer.Value);
+ (long unsigned int)pkg->Package.Elements[3].Integer.Value);
fwts_tag_failed(fw, FWTS_TAG_ACPI_METHOD_RETURN);
failed = true;
}
@@ -2581,7 +2581,7 @@ static void method_test_CST_return(
"%" PRIu32 " returned C state sub-elements yet _CST "
"reports it has %" PRIu64 " C states.",
name, obj->Package.Count - 1,
- obj->Package.Elements[0].Integer.Value);
+ (long unsigned int)obj->Package.Elements[0].Integer.Value);
fwts_tag_failed(fw, FWTS_TAG_ACPI_METHOD_RETURN);
return;
}
@@ -2677,9 +2677,9 @@ static void method_test_CST_return(
fwts_log_info_verbatum(fw,
"%2" PRIu32 " C%" PRIu64 " %6" PRIu64 " %6" PRIu64,
i,
- pkg->Package.Elements[1].Integer.Value,
- pkg->Package.Elements[2].Integer.Value,
- pkg->Package.Elements[3].Integer.Value);
+ (long unsigned int)pkg->Package.Elements[1].Integer.Value,
+ (long unsigned int)pkg->Package.Elements[2].Integer.Value,
+ (long unsigned int)pkg->Package.Elements[3].Integer.Value);
} else {
fwts_log_info_verbatum(fw,
"%2" PRIu32 " -- ----- -----", i);
@@ -2850,10 +2850,10 @@ static void method_test_PSS_return(
fwts_log_info_verbatum(fw, " %3d %7" PRIu64 " %8" PRIu64
" %5" PRIu64 " %5" PRIu64,
i,
- pstate->Package.Elements[0].Integer.Value,
- pstate->Package.Elements[1].Integer.Value,
- pstate->Package.Elements[2].Integer.Value,
- pstate->Package.Elements[3].Integer.Value);
+ (long unsigned int)pstate->Package.Elements[0].Integer.Value,
+ (long unsigned int)pstate->Package.Elements[1].Integer.Value,
+ (long unsigned int)pstate->Package.Elements[2].Integer.Value,
+ (long unsigned int)pstate->Package.Elements[3].Integer.Value);
} else {
fwts_log_info_verbatum(fw,
" %3d ---- ----- -- -- (invalid)", i);
@@ -3004,7 +3004,7 @@ static void method_test_TSD_return(
" element 0 (NumEntries) "
"was expected to have value 0x%" PRIx64 ".",
name, i,
- pkg->Package.Elements[0].Integer.Value);
+ (long unsigned int)pkg->Package.Elements[0].Integer.Value);
fwts_tag_failed(fw, FWTS_TAG_ACPI_METHOD_RETURN);
failed = true;
}
@@ -3017,7 +3017,7 @@ static void method_test_TSD_return(
"was expected to have value 1, instead it "
"was 0x%" PRIx64 ".",
name, i,
- pkg->Package.Elements[1].Integer.Value);
+ (long unsigned int)pkg->Package.Elements[1].Integer.Value);
fwts_tag_failed(fw, FWTS_TAG_ACPI_METHOD_RETURN);
failed = true;
}
@@ -3033,7 +3033,7 @@ static void method_test_TSD_return(
"0xfd (SW_ANY) or 0xfe (HW_ALL), instead it "
"was 0x%" PRIx64 ".",
name, i,
- pkg->Package.Elements[3].Integer.Value);
+ (long unsigned int)pkg->Package.Elements[3].Integer.Value);
fwts_tag_failed(fw, FWTS_TAG_ACPI_METHOD_RETURN);
failed = true;
}
@@ -3140,7 +3140,7 @@ static void method_test_TSS_return(
"was expected to have value 1..100, instead "
"was %" PRIu64 ".",
name, i,
- pkg->Package.Elements[0].Integer.Value);
+ (long unsigned int)pkg->Package.Elements[0].Integer.Value);
fwts_tag_failed(fw, FWTS_TAG_ACPI_METHOD_RETURN);
failed = true;
}
@@ -3159,11 +3159,11 @@ static void method_test_TSS_return(
fwts_log_info_verbatum(fw,
" %3d %3" PRIu64 "%% %7" PRIu64 " %7" PRIu64
" %2.2" PRIx64 " %2.2" PRIx64, i,
- pkg->Package.Elements[0].Integer.Value,
- pkg->Package.Elements[1].Integer.Value,
- pkg->Package.Elements[2].Integer.Value,
- pkg->Package.Elements[3].Integer.Value,
- pkg->Package.Elements[4].Integer.Value);
+ (long unsigned int)pkg->Package.Elements[0].Integer.Value,
+ (long unsigned int)pkg->Package.Elements[1].Integer.Value,
+ (long unsigned int)pkg->Package.Elements[2].Integer.Value,
+ (long unsigned int)pkg->Package.Elements[3].Integer.Value,
+ (long unsigned int)pkg->Package.Elements[4].Integer.Value);
} else {
fwts_log_info_verbatum(fw,
" %3d ---- ----- ----- -- -- (invalid)", i);
@@ -3243,7 +3243,7 @@ static void method_test_GCP_return(
"%s returned %" PRId64 ", should be between 0 and 15, "
"one or more of the reserved bits 4..31 seem "
"to be set.",
- name, obj->Integer.Value);
+ name, (long unsigned int)obj->Integer.Value);
fwts_tag_failed(fw, FWTS_TAG_ACPI_METHOD_RETURN);
} else
method_passed_sane_uint64(fw, name, obj->Integer.Value);
@@ -3308,7 +3308,7 @@ static void method_test_GWS_return(
"%s returned %" PRIu64 ", should be between 0 and 3, "
"one or more of the reserved bits 2..31 seem "
"to be set.",
- name, obj->Integer.Value);
+ name, (long unsigned int)obj->Integer.Value);
fwts_tag_failed(fw, FWTS_TAG_ACPI_METHOD_RETURN);
} else
method_passed_sane_uint64(fw, name, obj->Integer.Value);
@@ -3400,13 +3400,13 @@ static void method_test_SBS_return(
switch (obj->Integer.Value) {
case 0 ... 4:
fwts_passed(fw, "%s correctly returned value %" PRIu64 " %s",
- name, obj->Integer.Value,
+ name, (long unsigned int)obj->Integer.Value,
sbs_info[obj->Integer.Value]);
break;
default:
fwts_failed(fw, LOG_LEVEL_MEDIUM, "Method_SBSReturn",
"%s returned %" PRIu64 ", should be between 0 and 4.",
- name, obj->Integer.Value);
+ name, (long unsigned int)obj->Integer.Value);
fwts_tag_failed(fw, FWTS_TAG_ACPI_METHOD_RETURN);
fwts_advice(fw,
"Smart Battery %s is incorrectly informing "
@@ -3485,7 +3485,7 @@ static void method_test_BIF_return(
"Method_BIFBadUnits",
"%s: Expected Power Unit (Element 0) to be "
"0 (mWh) or 1 (mAh), got 0x%8.8" PRIx64 ".",
- name, obj->Package.Elements[0].Integer.Value);
+ name, (long unsigned int)obj->Package.Elements[0].Integer.Value);
fwts_tag_failed(fw, FWTS_TAG_ACPI_METHOD_RETURN);
failed = true;
}
@@ -3522,7 +3522,7 @@ static void method_test_BIF_return(
"%s: Expected Battery Technology Unit "
"(Element 3) to be 0 (Primary) or 1 "
"(Secondary), got 0x%8.8" PRIx64 ".",
- name, obj->Package.Elements[3].Integer.Value);
+ name, (long unsigned int)obj->Package.Elements[3].Integer.Value);
fwts_tag_failed(fw, FWTS_TAG_ACPI_METHOD_RETURN);
failed = true;
}
@@ -3630,7 +3630,7 @@ static void method_test_BIX_return(
"%s: Expected %s (Element 1) to be "
"0 (mWh) or 1 (mAh), got 0x%8.8" PRIx64 ".",
name, elements[1].name,
- obj->Package.Elements[1].Integer.Value);
+ (long unsigned int)obj->Package.Elements[1].Integer.Value);
fwts_tag_failed(fw, FWTS_TAG_ACPI_METHOD_RETURN);
failed = true;
}
@@ -3670,7 +3670,7 @@ static void method_test_BIX_return(
"(Element 4) to be 0 (Primary) or 1 "
"(Secondary), got 0x%8.8" PRIx64 ".",
name, elements[4].name,
- obj->Package.Elements[4].Integer.Value);
+ (long unsigned int)obj->Package.Elements[4].Integer.Value);
fwts_tag_failed(fw, FWTS_TAG_ACPI_METHOD_RETURN);
failed = true;
}
@@ -3786,7 +3786,7 @@ static void method_test_BST_return(
"Method_BSTBadState",
"%s: Expected Battery State (Element 0) to "
"be 0..7, got 0x%8.8" PRIx64 ".",
- name, obj->Package.Elements[0].Integer.Value);
+ name, (long unsigned int)obj->Package.Elements[0].Integer.Value);
fwts_tag_failed(fw, FWTS_TAG_ACPI_METHOD_RETURN);
failed = true;
}
@@ -3797,7 +3797,7 @@ static void method_test_BST_return(
"%s: Battery State (Element 0) is "
"indicating both charging and discharginng "
"which is not allowed. Got value 0x%8.8" PRIx64 ".",
- name, obj->Package.Elements[0].Integer.Value);
+ name, (long unsigned int)obj->Package.Elements[0].Integer.Value);
fwts_tag_failed(fw, FWTS_TAG_ACPI_METHOD_RETURN);
failed = true;
}
@@ -3943,7 +3943,7 @@ static void method_test_PSR_return(
"Method_PSRZeroOrOne",
"%s returned 0x%8.8" PRIx64 ", expected 0 "
"(offline) or 1 (online)",
- name, obj->Integer.Value);
+ name, (long unsigned int)obj->Integer.Value);
fwts_tag_failed(fw, FWTS_TAG_ACPI_METHOD_RETURN);
} else
method_passed_sane_uint64(fw, name, obj->Integer.Value);
@@ -4117,7 +4117,7 @@ static void method_test_THERM_return(
"%s correctly returned sane looking "
"value 0x%8.8" PRIx64 " (%5.1f degrees K)",
method,
- obj->Integer.Value,
+ (long unsigned int)obj->Integer.Value,
(float)((uint64_t)obj->Integer.Value) / 10.0);
} else {
fwts_failed(fw, LOG_LEVEL_MEDIUM,
@@ -4126,7 +4126,7 @@ static void method_test_THERM_return(
"0 degrees C: 0x%8.8" PRIx64 " (%5.1f "
"degrees K)",
method,
- obj->Integer.Value,
+ (long unsigned int)obj->Integer.Value,
(float)((uint64_t)obj->Integer.Value) / 10.0);
fwts_tag_failed(fw, FWTS_TAG_ACPI_METHOD_RETURN);
fwts_advice(fw,
@@ -4596,8 +4596,8 @@ static void method_test_BCL_return(
" power (%" PRIu64 ") is less than "
"brightness level when on "
"battery power (%" PRIu64 ").",
- obj->Package.Elements[0].Integer.Value,
- obj->Package.Elements[1].Integer.Value);
+ (long unsigned int)obj->Package.Elements[0].Integer.Value,
+ (long unsigned int)obj->Package.Elements[1].Integer.Value);
fwts_tag_failed(fw, FWTS_TAG_ACPI_METHOD_RETURN);
failed = true;
}
@@ -4611,8 +4611,8 @@ static void method_test_BCL_return(
"than brightness level %" PRIu64
" (index %d" PRIu32 "), should "
"be in ascending order.",
- obj->Package.Elements[i].Integer.Value, i,
- obj->Package.Elements[i+1].Integer.Value, i+1);
+ (long unsigned int)obj->Package.Elements[i].Integer.Value, i,
+ (long unsigned int)obj->Package.Elements[i+1].Integer.Value, i+1);
ascending_levels = true;
failed = true;
}
@@ -4629,14 +4629,14 @@ static void method_test_BCL_return(
}
fwts_log_info(fw, "Brightness levels for %s:" ,name);
- fwts_log_info_verbatum(fw, " Level on full power : %" PRIu64, obj->Package.Elements[0].Integer.Value);
- fwts_log_info_verbatum(fw, " Level on battery power: %" PRIu64, obj->Package.Elements[1].Integer.Value);
+ fwts_log_info_verbatum(fw, " Level on full power : %" PRIu64, (long unsigned int)obj->Package.Elements[0].Integer.Value);
+ fwts_log_info_verbatum(fw, " Level on battery power: %" PRIu64, (long unsigned int)obj->Package.Elements[1].Integer.Value);
for (i = 2; i < obj->Package.Count; i++) {
char tmp[12];
snprintf(tmp, sizeof(tmp), "%s%" PRIu64,
i == 2 ? "" : ", ",
- obj->Package.Elements[i].Integer.Value);
+ (long unsigned int)obj->Package.Elements[i].Integer.Value);
str = fwts_realloc_strcat(str, tmp);
if (!str)
break;
--
1.7.9.5
11 years, 9 months
- 3
- 2
[PATCHv2 0/2] make mab not cross 4k boundaries
by Graeme Gregory
This will eventually need to be fixed in kernel but for now to allow work to
progress alter mab so it will not attempt to place a table across a page
boundary.
If people could give this patch some proper testing it would be good as there
may be some corner cases I missed constructing this. I have boot tested the
result on Arndale.
While working on this I discovered that write_table was allocating buffers
which were never used and never had free() called on them.
Thanks
Graeme
11 years, 9 months
- 2
- 3
[PATCHv2] ACPI: ARM: remove relocate code
by Graeme Gregory
Relocate code is no longer needed as mab can generate physcially
relocated blobs for us.
Relocate code was also causing problems when tables are passed in from
UEFI bootloader as they were already located in memory and adding an
aditional offset breaks this.
Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org>
---
drivers/acpi/plat/arm/boot.c | 83 ------------------------------------------
1 file changed, 83 deletions(-)
diff --git a/drivers/acpi/plat/arm/boot.c b/drivers/acpi/plat/arm/boot.c
index 82b7bd6..8600cd0 100644
--- a/drivers/acpi/plat/arm/boot.c
+++ b/drivers/acpi/plat/arm/boot.c
@@ -713,82 +713,6 @@ static void __init acpi_process_madt(void)
return;
}
-void set_checksum(u8 *start, int len, u8 *cksum)
-{
- u8 newsum, oldsum;
- u8 *p;
-
- newsum = 0;
- for (p = (u8 *)start; p < (u8 *)(start + len); p++)
- newsum += *p;
-
- oldsum = *cksum;
- newsum = (u8)(newsum - oldsum);
-
- *cksum = (u8)(0 - newsum);
-}
-
-void __init acpi_arm_blob_relocate(void)
-{
- /*
- * Fortunately, there are only a few tables that need to
- * have their offsets converted to actual addresses.
- *
- * NB: all values in the blob are little-endian.
- */
-
- struct acpi_table_rsdp *rp;
- struct acpi_table_xsdt *xp;
- struct acpi_table_fadt *fp;
- phys_addr_t paddress;
- void *vaddress;
- u32 entries;
- u32 ii;
- u64 *tmp;
-
- if (!acpi_arm_rsdp_info.phys_address && !acpi_arm_rsdp_info.size) {
- printk(KERN_ERR "(E) ACPI: failed to find rsdp info\n");
- return;
- }
-
- paddress = acpi_arm_rsdp_info.phys_address;
- paddress += ACPI_BLOB_HEADER_SIZE;
- vaddress = phys_to_virt(paddress);
-
- /* fixups for the rsdp */
- rp = (struct acpi_table_rsdp *)vaddress;
- if (rp->rsdt_physical_address)
- rp->rsdt_physical_address += paddress;
- if (rp->xsdt_physical_address)
- rp->xsdt_physical_address += paddress;
- set_checksum((u8 *)rp, rp->length, &(rp->checksum));
-
- /* fixups for the xsdt */
- vaddress = phys_to_virt(rp->xsdt_physical_address);
- xp = (struct acpi_table_xsdt *)vaddress;
- entries = xp->header.length - sizeof (struct acpi_table_header);
- entries /= 8; /* length is in bytes */
- tmp = (u64 *)(&(xp->table_offset_entry[0]));
- for (ii = 0; ii < entries; ii++)
- *tmp++ += paddress;
- set_checksum((u8 *)xp, xp->header.length, &(xp->header.checksum));
-
- /* fixups for the fadt */
- vaddress = phys_to_virt(xp->table_offset_entry[0]);
- fp = (struct acpi_table_fadt *)vaddress;
- if (fp->facs)
- fp->facs += paddress;
- if (fp->dsdt)
- fp->dsdt += paddress;
- if (fp->Xfacs)
- fp->Xfacs += paddress;
- if (fp->Xdsdt)
- fp->Xdsdt += paddress;
-
- /* Always fix up the checksums since we've changed bits. */
- set_checksum((u8 *)fp, fp->header.length, &(fp->header.checksum));
-}
-
/*
* ========== OLD COMMENTS FROM x86 =================================
* acpi_boot_table_init() and acpi_boot_init()
@@ -828,13 +752,6 @@ void __init acpi_boot_table_init(void)
return;
/*
- * Fix up the addresses in the ACPI we've loaded
- * in. The blob has them as offsets and we need
- * actual addresses.
- */
- acpi_arm_blob_relocate();
-
- /*
* Initialize the ACPI boot-time table parser.
*/
if (acpi_table_init()) {
--
1.7.10.4
11 years, 9 months
- 2
- 2
[PATCH -v3] ARM64: Add cpu topology definition
by Hanjun Guo
Power aware scheduling needs the cpu topology information to improve the
cpu scheduler decision making. sched_mc and sched_smt will use the topology
information.
For ARM64, we can get the topology from the MPIDR register which defines the
the affinity of processors.
This patch is mainly based on arch/arm/kernel/topology.c written by
Vincent Guittot, and replaced the topology array with per cpu variable.
v2:
Make the changelog easier to understand.
Use 'u64' for MPIDR value on arm64.
Some typo fix.
v3:
Rebased the patch on the latest linaro acpi git tree.
Put store_cpu_topology(cpu) before set_cpu_online(cpu, true) to make
the system boot without problem.
Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org>
---
arch/arm64/Kconfig | 25 ++++++++
arch/arm64/include/asm/cputype.h | 11 ++++
arch/arm64/include/asm/topology.h | 35 +++++++++++
arch/arm64/kernel/Makefile | 5 +-
arch/arm64/kernel/smp.c | 6 ++
arch/arm64/kernel/topology.c | 120 +++++++++++++++++++++++++++++++++++++
6 files changed, 198 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index ae80184..b0fd1aa 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -150,6 +150,31 @@ config SMP
If you don't know what to do here, say N.
+config ARM64_CPU_TOPOLOGY
+ bool "Support cpu topology definition"
+ depends on SMP && ARM64
+ default y
+ help
+ Support ARM64 cpu topology definition. The MPIDR register defines
+ affinity between processors which is then used to describe the cpu
+ topology of an ARM64 System.
+
+config SCHED_MC
+ bool "Multi-core scheduler support"
+ depends on ARM64_CPU_TOPOLOGY
+ help
+ Multi-core scheduler support improves the CPU scheduler's decision
+ making when dealing with multi-core CPU chips at a cost of slightly
+ increased overhead in some places. If unsure say N here.
+
+config SCHED_SMT
+ bool "SMT scheduler support"
+ depends on ARM64_CPU_TOPOLOGY
+ help
+ Improves the CPU scheduler's decision making when dealing with
+ MultiThreading at a cost of slightly increased overhead in some
+ places. If unsure say N here.
+
config NR_CPUS
int "Maximum number of CPUs (2-32)"
range 2 32
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 5fe138e..58a595f 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -30,6 +30,17 @@
#define MPIDR_HWID_BITMASK 0xff00ffffff
+#define MPIDR_SMP_BITMASK (0x1 << 30)
+#define MPIDR_MT_BITMASK (0x1 << 24)
+
+#define MPIDR_LEVEL_BITS 8
+#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
+
+#define MPIDR_AFFINITY_LEVEL_0(mpidr) ((mpidr) & MPIDR_LEVEL_MASK)
+#define MPIDR_AFFINITY_LEVEL_1(mpidr) ((mpidr >> 8) & MPIDR_LEVEL_MASK)
+#define MPIDR_AFFINITY_LEVEL_2(mpidr) ((mpidr >> 16) & MPIDR_LEVEL_MASK)
+#define MPIDR_AFFINITY_LEVEL_3(mpidr) ((mpidr >> 32) & MPIDR_LEVEL_MASK)
+
#define read_cpuid(reg) ({ \
u64 __val; \
asm("mrs %0, " reg : "=r" (__val)); \
diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h
index 22c9421..06440d4 100644
--- a/arch/arm64/include/asm/topology.h
+++ b/arch/arm64/include/asm/topology.h
@@ -1,8 +1,43 @@
#ifndef _ASM_ARM64_TOPOLOGY_H
#define _ASM_ARM64_TOPOLOGY_H
+#ifdef CONFIG_ARM64_CPU_TOPOLOGY
+
+#include <linux/cpumask.h>
+
+struct cputopo_arm64 {
+ int thread_id;
+ int core_id;
+ int socket_id;
+ cpumask_t thread_sibling;
+ cpumask_t core_sibling;
+};
+
+DECLARE_PER_CPU(struct cputopo_arm64, cpu_topology);
+
+#define cpu_topo(cpu) per_cpu(cpu_topology, cpu)
+
+#define topology_physical_package_id(cpu) (cpu_topo(cpu).socket_id)
+#define topology_core_id(cpu) (cpu_topo(cpu).core_id)
+#define topology_core_cpumask(cpu) (&cpu_topo(cpu).core_sibling)
+#define topology_thread_cpumask(cpu) (&cpu_topo(cpu).thread_sibling)
+
+#define mc_capable() (cpu_topo(0).socket_id != -1)
+#define smt_capable() (cpu_topo(0).thread_id != -1)
+
+void init_cpu_topology(void);
+void store_cpu_topology(unsigned int cpuid);
+const struct cpumask *cpu_coregroup_mask(int cpu);
void arch_fix_phys_package_id(int num, u32 slot);
+#else
+
+static inline void arch_fix_phys_package_id(int num, u32 slot) {}
+static inline void init_cpu_topology(void) { }
+static inline void store_cpu_topology(unsigned int cpuid) { }
+
+#endif
+
#include <asm-generic/topology.h>
#endif /* _ASM_ARM64_TOPOLOGY_H */
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index c5e29d5..a47c359 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -18,6 +18,7 @@ arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o smp_psci.o
arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)+= hw_breakpoint.o
arm64-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+arm64-obj-$(CONFIG_ARM64_CPU_TOPOLOGY) += topology.o
obj-y += $(arm64-obj-y) vdso/
obj-m += $(arm64-obj-m)
@@ -27,7 +28,3 @@ extra-y := $(head-y) vmlinux.lds
# vDSO - this must be built first to generate the symbol offsets
$(call objectify,$(arm64-obj-y)): $(obj)/vdso/vdso-offsets.h
$(obj)/vdso/vdso-offsets.h: $(obj)/vdso
-
-# Hack for now
-obj-y += topology.o
-
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index 1049238..b923cfc 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -39,6 +39,7 @@
#include <asm/atomic.h>
#include <asm/cacheflush.h>
#include <asm/cputype.h>
+#include <asm/topology.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/pgalloc.h>
@@ -199,6 +200,8 @@ asmlinkage void secondary_start_kernel(void)
raw_spin_lock(&boot_lock);
raw_spin_unlock(&boot_lock);
+ store_cpu_topology(cpu);
+
/*
* OK, now it's safe to let the boot CPU continue. Wait for
* the CPU migration code to notice that the CPU is online
@@ -408,6 +411,9 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
int cpu, err;
unsigned int ncores = num_possible_cpus();
+ init_cpu_topology();
+ store_cpu_topology(smp_processor_id());
+
/*
* are we trying to boot more cores than exist?
*/
diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c
index 5c8e69c..947fcc2 100644
--- a/arch/arm64/kernel/topology.c
+++ b/arch/arm64/kernel/topology.c
@@ -1,3 +1,16 @@
+/*
+ * arch/arm64/kernel/topology.c
+ *
+ * Copyright (C) 2013 Linaro Limited.
+ * Written by: Hanjun Guo
+ *
+ * based on arch/arm/kernel/topology.c
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
#include <linux/cpu.h>
#include <linux/cpumask.h>
#include <linux/export.h>
@@ -13,6 +26,113 @@
#include <asm/topology.h>
#include <asm/cpu.h>
+DEFINE_PER_CPU(struct cputopo_arm64, cpu_topology);
+
+const struct cpumask *cpu_coregroup_mask(int cpu)
+{
+ return &cpu_topo(cpu).core_sibling;
+}
+
+void update_siblings_masks(unsigned int cpuid)
+{
+ struct cputopo_arm64 *topo, *cpuid_topo = &cpu_topo(cpuid);
+ int cpu;
+
+ /* update core and thread sibling masks */
+ for_each_possible_cpu(cpu) {
+ topo = &cpu_topo(cpu);
+
+ if (cpuid_topo->socket_id != topo->socket_id)
+ continue;
+
+ cpumask_set_cpu(cpuid, &topo->core_sibling);
+ if (cpu != cpuid)
+ cpumask_set_cpu(cpu, &cpuid_topo->core_sibling);
+
+ if (cpuid_topo->core_id != topo->core_id)
+ continue;
+
+ cpumask_set_cpu(cpuid, &topo->thread_sibling);
+ if (cpu != cpuid)
+ cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling);
+ }
+ smp_wmb();
+}
+
+/*
+ * store_cpu_topology is called at boot when only one cpu is running
+ * and with the mutex cpu_hotplug.lock locked, when several cpus have booted,
+ * which prevents simultaneous write access to cpu_topology array
+ */
+void store_cpu_topology(unsigned int cpuid)
+{
+ struct cputopo_arm64 *cpuid_topo = &cpu_topo(cpuid);
+ u64 mpidr;
+
+ /* If the cpu topology has been already set, just return */
+ if (cpuid_topo->core_id != -1)
+ return;
+
+ mpidr = read_cpuid_mpidr();
+
+ /* create cpu topology mapping */
+ if (!(mpidr & MPIDR_SMP_BITMASK)) {
+ /*
+ * This is a multiprocessor system
+ * multiprocessor format & multiprocessor mode field are set
+ */
+
+ if (mpidr & MPIDR_MT_BITMASK) {
+ /* core performance interdependency */
+ cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL_0(mpidr);
+ cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL_1(mpidr);
+ cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL_2(mpidr);
+ } else {
+ /* largely independent cores */
+ cpuid_topo->thread_id = -1;
+ cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL_0(mpidr);
+ cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL_1(mpidr);
+ }
+ } else {
+ /*
+ * This is an uniprocessor system
+ * we are in multiprocessor format but uniprocessor system
+ * or in the old uniprocessor format
+ */
+ cpuid_topo->thread_id = -1;
+ cpuid_topo->core_id = 0;
+ cpuid_topo->socket_id = -1;
+ }
+
+ update_siblings_masks(cpuid);
+
+ pr_info("CPU%u: thread %d, cpu %d, socket %d, mpidr 0x%llx\n",
+ cpuid, cpu_topo(cpuid).thread_id,
+ cpu_topo(cpuid).core_id,
+ cpu_topo(cpuid).socket_id, mpidr);
+}
+
+/*
+ * init_cpu_topology is called at boot when only one cpu is running
+ * which prevent simultaneous write access to cpu_topology array
+ */
+void __init init_cpu_topology(void)
+{
+ unsigned int cpu;
+
+ /* init core mask */
+ for_each_possible_cpu(cpu) {
+ struct cputopo_arm64 *topo = &cpu_topo(cpu);
+
+ topo->thread_id = -1;
+ topo->core_id = -1;
+ topo->socket_id = -1;
+ cpumask_clear(&topo->core_sibling);
+ cpumask_clear(&topo->thread_sibling);
+ }
+ smp_wmb();
+}
+
void arch_fix_phys_package_id(int num, u32 slot)
{
}
--
1.7.9.5
11 years, 9 months
- 2
- 1
[PATCH -v2] ARM64: Add cpu topology definition
by Hanjun Guo
Power aware scheduling needs the cpu topology information to improve the
cpu scheduler decision making. sched_mc and sched_smt will use the topology
information.
For ARM64, we can get the topology from the MPIDR register which defines the
the affinity of processors.
This patch is mainly based on arch/arm/kernel/topology.c written by
Vincent Guittot, and replaced the topology array with per cpu variable.
v2:
Make the changelog easier to understand.
Use 'u64' for MPIDR value on arm64.
Some typo fix.
Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org>
---
arch/arm64/Kconfig | 25 ++++++++
arch/arm64/include/asm/cputype.h | 11 ++++
arch/arm64/include/asm/topology.h | 35 +++++++++++
arch/arm64/kernel/Makefile | 5 +-
arch/arm64/kernel/smp.c | 6 ++
arch/arm64/kernel/topology.c | 120 +++++++++++++++++++++++++++++++++++++
6 files changed, 198 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index c967b11..67c1c53 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -144,6 +144,31 @@ config SMP
If you don't know what to do here, say N.
+config ARM64_CPU_TOPOLOGY
+ bool "Support cpu topology definition"
+ depends on SMP && ARM64
+ default y
+ help
+ Support ARM64 cpu topology definition. The MPIDR register defines
+ affinity between processors which is then used to describe the cpu
+ topology of an ARM64 System.
+
+config SCHED_MC
+ bool "Multi-core scheduler support"
+ depends on ARM64_CPU_TOPOLOGY
+ help
+ Multi-core scheduler support improves the CPU scheduler's decision
+ making when dealing with multi-core CPU chips at a cost of slightly
+ increased overhead in some places. If unsure say N here.
+
+config SCHED_SMT
+ bool "SMT scheduler support"
+ depends on ARM64_CPU_TOPOLOGY
+ help
+ Improves the CPU scheduler's decision making when dealing with
+ MultiThreading at a cost of slightly increased overhead in some
+ places. If unsure say N here.
+
config NR_CPUS
int "Maximum number of CPUs (2-32)"
range 2 32
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index cf27494..ef7e682 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -30,6 +30,17 @@
#define MPIDR_HWID_BITMASK 0xff00ffffff
+#define MPIDR_SMP_BITMASK (0x1 << 30)
+#define MPIDR_MT_BITMASK (0x1 << 24)
+
+#define MPIDR_LEVEL_BITS 8
+#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
+
+#define MPIDR_AFFINITY_LEVEL_0(mpidr) ((mpidr) & MPIDR_LEVEL_MASK)
+#define MPIDR_AFFINITY_LEVEL_1(mpidr) ((mpidr >> 8) & MPIDR_LEVEL_MASK)
+#define MPIDR_AFFINITY_LEVEL_2(mpidr) ((mpidr >> 16) & MPIDR_LEVEL_MASK)
+#define MPIDR_AFFINITY_LEVEL_3(mpidr) ((mpidr >> 32) & MPIDR_LEVEL_MASK)
+
#define read_cpuid(reg) ({ \
u64 __val; \
asm("mrs %0, " reg : "=r" (__val)); \
diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h
index 22c9421..06440d4 100644
--- a/arch/arm64/include/asm/topology.h
+++ b/arch/arm64/include/asm/topology.h
@@ -1,8 +1,43 @@
#ifndef _ASM_ARM64_TOPOLOGY_H
#define _ASM_ARM64_TOPOLOGY_H
+#ifdef CONFIG_ARM64_CPU_TOPOLOGY
+
+#include <linux/cpumask.h>
+
+struct cputopo_arm64 {
+ int thread_id;
+ int core_id;
+ int socket_id;
+ cpumask_t thread_sibling;
+ cpumask_t core_sibling;
+};
+
+DECLARE_PER_CPU(struct cputopo_arm64, cpu_topology);
+
+#define cpu_topo(cpu) per_cpu(cpu_topology, cpu)
+
+#define topology_physical_package_id(cpu) (cpu_topo(cpu).socket_id)
+#define topology_core_id(cpu) (cpu_topo(cpu).core_id)
+#define topology_core_cpumask(cpu) (&cpu_topo(cpu).core_sibling)
+#define topology_thread_cpumask(cpu) (&cpu_topo(cpu).thread_sibling)
+
+#define mc_capable() (cpu_topo(0).socket_id != -1)
+#define smt_capable() (cpu_topo(0).thread_id != -1)
+
+void init_cpu_topology(void);
+void store_cpu_topology(unsigned int cpuid);
+const struct cpumask *cpu_coregroup_mask(int cpu);
void arch_fix_phys_package_id(int num, u32 slot);
+#else
+
+static inline void arch_fix_phys_package_id(int num, u32 slot) {}
+static inline void init_cpu_topology(void) { }
+static inline void store_cpu_topology(unsigned int cpuid) { }
+
+#endif
+
#include <asm-generic/topology.h>
#endif /* _ASM_ARM64_TOPOLOGY_H */
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index c5e29d5..a47c359 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -18,6 +18,7 @@ arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o smp_psci.o
arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)+= hw_breakpoint.o
arm64-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+arm64-obj-$(CONFIG_ARM64_CPU_TOPOLOGY) += topology.o
obj-y += $(arm64-obj-y) vdso/
obj-m += $(arm64-obj-m)
@@ -27,7 +28,3 @@ extra-y := $(head-y) vmlinux.lds
# vDSO - this must be built first to generate the symbol offsets
$(call objectify,$(arm64-obj-y)): $(obj)/vdso/vdso-offsets.h
$(obj)/vdso/vdso-offsets.h: $(obj)/vdso
-
-# Hack for now
-obj-y += topology.o
-
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index 5ec1723..36d09fe 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -39,6 +39,7 @@
#include <asm/atomic.h>
#include <asm/cacheflush.h>
#include <asm/cputype.h>
+#include <asm/topology.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/pgalloc.h>
@@ -206,6 +207,8 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
local_irq_enable();
local_fiq_enable();
+ store_cpu_topology(cpu);
+
/*
* OK, now it's safe to let the boot CPU continue. Wait for
* the CPU migration code to notice that the CPU is online
@@ -407,6 +410,9 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
int cpu, err;
unsigned int ncores = num_possible_cpus();
+ init_cpu_topology();
+ store_cpu_topology(smp_processor_id());
+
/*
* are we trying to boot more cores than exist?
*/
diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c
index 5c8e69c..947fcc2 100644
--- a/arch/arm64/kernel/topology.c
+++ b/arch/arm64/kernel/topology.c
@@ -1,3 +1,16 @@
+/*
+ * arch/arm64/kernel/topology.c
+ *
+ * Copyright (C) 2013 Linaro Limited.
+ * Written by: Hanjun Guo
+ *
+ * based on arch/arm/kernel/topology.c
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
#include <linux/cpu.h>
#include <linux/cpumask.h>
#include <linux/export.h>
@@ -13,6 +26,113 @@
#include <asm/topology.h>
#include <asm/cpu.h>
+DEFINE_PER_CPU(struct cputopo_arm64, cpu_topology);
+
+const struct cpumask *cpu_coregroup_mask(int cpu)
+{
+ return &cpu_topo(cpu).core_sibling;
+}
+
+void update_siblings_masks(unsigned int cpuid)
+{
+ struct cputopo_arm64 *topo, *cpuid_topo = &cpu_topo(cpuid);
+ int cpu;
+
+ /* update core and thread sibling masks */
+ for_each_possible_cpu(cpu) {
+ topo = &cpu_topo(cpu);
+
+ if (cpuid_topo->socket_id != topo->socket_id)
+ continue;
+
+ cpumask_set_cpu(cpuid, &topo->core_sibling);
+ if (cpu != cpuid)
+ cpumask_set_cpu(cpu, &cpuid_topo->core_sibling);
+
+ if (cpuid_topo->core_id != topo->core_id)
+ continue;
+
+ cpumask_set_cpu(cpuid, &topo->thread_sibling);
+ if (cpu != cpuid)
+ cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling);
+ }
+ smp_wmb();
+}
+
+/*
+ * store_cpu_topology is called at boot when only one cpu is running
+ * and with the mutex cpu_hotplug.lock locked, when several cpus have booted,
+ * which prevents simultaneous write access to cpu_topology array
+ */
+void store_cpu_topology(unsigned int cpuid)
+{
+ struct cputopo_arm64 *cpuid_topo = &cpu_topo(cpuid);
+ u64 mpidr;
+
+ /* If the cpu topology has been already set, just return */
+ if (cpuid_topo->core_id != -1)
+ return;
+
+ mpidr = read_cpuid_mpidr();
+
+ /* create cpu topology mapping */
+ if (!(mpidr & MPIDR_SMP_BITMASK)) {
+ /*
+ * This is a multiprocessor system
+ * multiprocessor format & multiprocessor mode field are set
+ */
+
+ if (mpidr & MPIDR_MT_BITMASK) {
+ /* core performance interdependency */
+ cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL_0(mpidr);
+ cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL_1(mpidr);
+ cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL_2(mpidr);
+ } else {
+ /* largely independent cores */
+ cpuid_topo->thread_id = -1;
+ cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL_0(mpidr);
+ cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL_1(mpidr);
+ }
+ } else {
+ /*
+ * This is an uniprocessor system
+ * we are in multiprocessor format but uniprocessor system
+ * or in the old uniprocessor format
+ */
+ cpuid_topo->thread_id = -1;
+ cpuid_topo->core_id = 0;
+ cpuid_topo->socket_id = -1;
+ }
+
+ update_siblings_masks(cpuid);
+
+ pr_info("CPU%u: thread %d, cpu %d, socket %d, mpidr 0x%llx\n",
+ cpuid, cpu_topo(cpuid).thread_id,
+ cpu_topo(cpuid).core_id,
+ cpu_topo(cpuid).socket_id, mpidr);
+}
+
+/*
+ * init_cpu_topology is called at boot when only one cpu is running
+ * which prevent simultaneous write access to cpu_topology array
+ */
+void __init init_cpu_topology(void)
+{
+ unsigned int cpu;
+
+ /* init core mask */
+ for_each_possible_cpu(cpu) {
+ struct cputopo_arm64 *topo = &cpu_topo(cpu);
+
+ topo->thread_id = -1;
+ topo->core_id = -1;
+ topo->socket_id = -1;
+ cpumask_clear(&topo->core_sibling);
+ cpumask_clear(&topo->thread_sibling);
+ }
+ smp_wmb();
+}
+
void arch_fix_phys_package_id(int num, u32 slot)
{
}
--
1.7.9.5
11 years, 9 months
- 2
- 8
[PATCH 0/2] Remove Deprecated RSDT
by al.stone＠linaro.org
From: Al Stone <ahs3(a)redhat.com>
No one should be using an RSDT any longer; they are
essentially deprecated and no longer useful. This
patch simply removes the table definitions from the
currently defined platforms.
Al Stone (2):
ASL: exynos5250-arndale.acpi: Remove deprecated RSDT table
ASL: foundation-v8.acpi: Remove deprecated RSDT files
platforms/exynos5250-arndale.acpi/rsdt.asl | 20 --------------------
platforms/foundation-v8.acpi/rsdt.asl | 20 --------------------
2 files changed, 40 deletions(-)
delete mode 100644 platforms/exynos5250-arndale.acpi/rsdt.asl
delete mode 100644 platforms/foundation-v8.acpi/rsdt.asl
--
1.8.1.4
11 years, 9 months
- 2
- 3
[PATCH v2] Create a minimal set of tables for load testing
by al.stone＠linaro.org
From: Al Stone <ahs3(a)redhat.com>
The prior version of this created a "dummy" platform; I did not
think that specific enough so the platform is now called "loadtest".
What this patch to acpi-asl does is define only the ACPI tables that
are absolutely required to determine if ACPI will initialize properly
during kernel boot. These tables contain essentially *no* configuration
information and should not.
Changes for v2:
-- rename "dummy" to "loadtest"
-- reduce tables to bare minimum (including removing the RSDT
which has been deprecated)
Al Stone (1):
ASL : loadtest.acpi : add in a minimal table set that can be used
for testing of core ACPI table loading
platforms/loadtest.acpi/.gitignore | 3 +
platforms/loadtest.acpi/dsdt.asl | 17 +++
platforms/loadtest.acpi/facp.asl | 167 ++++++++++++++++++++++++++++++
platforms/loadtest.acpi/facs.asl | 21 ++++
platforms/loadtest.acpi/loadtest.manifest | 13 +++
platforms/loadtest.acpi/rsdp.asl | 17 +++
platforms/loadtest.acpi/xsdt.asl | 23 ++++
7 files changed, 261 insertions(+)
create mode 100644 platforms/loadtest.acpi/.gitignore
create mode 100644 platforms/loadtest.acpi/dsdt.asl
create mode 100644 platforms/loadtest.acpi/facp.asl
create mode 100644 platforms/loadtest.acpi/facs.asl
create mode 100644 platforms/loadtest.acpi/loadtest.manifest
create mode 100644 platforms/loadtest.acpi/rsdp.asl
create mode 100644 platforms/loadtest.acpi/xsdt.asl
--
1.8.1.4
11 years, 9 months
- 2
- 2