linaro-kernel May 2012

linaro-kernel@lists.linaro.org

47 participants
48 discussions

[PATCH v2 0/6] Merge ram_console into pstore

by Anton Vorontsov

Hi all, In v2: - Updated documentation per Colin Cross' comments; - Corrected return value in ramoops_pstore_write() (noticed by Kees Cook); - Fixed large writes handling in pstore_console_write(), i.e. when log_buf write is larger than pstore bufsize. Also Noticed by Kees Cook. These patches depend on the the following series: http://thread.gmane.org/gmane.linux.kernel/1298642 "[PATCH v3 0/3] Merge ramoops and persistent_ram, generic pstore RAM backend" And a rationale for the series: Currently pstore doesn't support logging kernel messages in run-time, it only dumps dmesg when kernel oopses/panics. This makes pstore useless for debugging hangs caused by HW issues or improper use of HW (e.g. weird device inserted -> driver tried to write reserved bits -> SoC hanged. In that case we don't get any messages in the pstore. This series add a new message type for pstore, i.e. PSTORE_TYPE_CONSOLE, plus make pstore/ram.c handle the new messages. The old ram_console driver is removed. This might probably cause some pain for out-of-tree code, as it would need to be adjusted... but "no pain, no gain"? :-) Though, if there's some serious resistance, we can probably postpone the last two patches. Thanks! -- Anton Vorontsov Email: cbouatmailru(a)gmail.com

12 years, 1 month

[PATCH v3 0/3] Merge ramoops and persistent_ram, generic pstore RAM backend

by Anton Vorontsov

Hi all, Here comes v3: - Rebased on current staging-next tree, so only 3 patches left; - Fixed ram_console dependency in Kconfig (issue noticed by Greg KH). And the boilerplate, background for the series: There are currently two competing debug facilities to store kernel messages in a persistent storage: a generic pstore and Google's persistent_ram. Not so long ago (https://lkml.org/lkml/2012/3/8/252), it was decided that we should fix this situation. Recently ramoops has switched to pstore, which basically means that it became a RAM backend for the pstore framework. persistent_ram+ram_console and ramoops+pstore have almost the same features, except: 1. Ramoops doesn't support ECC. Having ECC is useful when a hardware reset was used to bring the machine back to life (i.e. a watchdog triggered). In such cases, RAM may be somewhat corrupt, but usually it is restorable. 2. Pstore doesn't support logging kernel messages in run-time, it only dumps dmesg when kernel oopses/panics. This makes pstore useless for debugging hangs caused by HW issues or improper use of HW (e.g. weird device inserted -> driver tried to write a reserved bits -> SoC hanged. In that case we don't get any messages in the pstore. These patches solve the first issue, plus move things to their proper places. --- Documentation/ramoops.txt | 6 + drivers/staging/android/Kconfig | 10 +- drivers/staging/android/Makefile | 1 - drivers/staging/android/persistent_ram.c | 532 ------------------------------ drivers/staging/android/persistent_ram.h | 82 ----- drivers/staging/android/ram_console.c | 2 +- fs/pstore/Kconfig | 7 +- fs/pstore/Makefile | 2 +- fs/pstore/ram.c | 119 ++++--- fs/pstore/ram_core.c | 532 ++++++++++++++++++++++++++++++ include/linux/pstore_ram.h | 81 +++++ 11 files changed, 697 insertions(+), 677 deletions(-) -- Anton Vorontsov Email: cbouatmailru(a)gmail.com

12 years, 1 month

[ACTIVITY] (Saugata Das) May 14th - May 18th

by Saugata Das

== Saugata Das sdas == === Activity Summary === * Pushed 4KB native sector patch in mmc-next (https://blueprints.launchpad.net/linux-linaro/+spec/emmc4.5-native-sector) * Resubmitted "req meta" patch in ext4 and fsdevel mailing list (https://blueprints.launchpad.net/linux-linaro/+spec/emmc4.5-data-tag) * Submitted RFC patch on context ID in ext4, fsdevel, mmc mailing list (https://blueprints.launchpad.net/linux-linaro/+spec/emmc4.5-context-id) * Resubmitted power OFF notify patch in mmc mailing list * Work ongoing on studying Tixy's traces * Work ongoing on ext4 mkfs study https://blueprints.launchpad.net/linux-linaro/+spec/journal-enhanced-emmc) === Plans === * Continue working on Tixy's traces and mkfs === Issues === * None

12 years, 1 month

[PATCH v2 0/6] Merge ramoops and persistent_ram, generic pstore RAM backend

by Anton Vorontsov

Hi all, Here is v2 of the previous patch set. The series do not include patches that were already merged. I believe I addressed all the previous comments, plus now the series include another small cleanup patch. Here's some background for the series: There are currently two competing debug facilities to store kernel messages in a persistent storage: a generic pstore and Google's persistent_ram. Not so long ago (https://lkml.org/lkml/2012/3/8/252), it was decided that we should fix this situation. Recently ramoops has switched to pstore, which basically means that it became a RAM backend for the pstore framework. persistent_ram+ram_console and ramoops+pstore have almost the same features, except: 1. Ramoops doesn't support ECC. Having ECC is useful when a hardware reset was used to bring the machine back to life (i.e. a watchdog triggered). In such cases, RAM may be somewhat corrupt, but usually it is restorable. 2. Pstore doesn't support logging kernel messages in run-time, it only dumps dmesg when kernel oopses/panics. This makes pstore useless for debugging hangs caused by HW issues or improper use of HW (e.g. weird device inserted -> driver tried to write a reserved bits -> SoC hanged. In that case we don't get any messages in the pstore. These patches solve the first issue, plus move things to their proper places. Patches that will fix the second issue will be sent shortly. --- Documentation/ramoops.txt | 8 +- drivers/char/Kconfig | 9 - drivers/char/Makefile | 1 - drivers/char/ramoops.c | 362 -------------------- drivers/staging/android/Kconfig | 10 +- drivers/staging/android/Makefile | 1 - drivers/staging/android/persistent_ram.c | 530 ----------------------------- drivers/staging/android/persistent_ram.h | 84 ----- drivers/staging/android/ram_console.c | 2 +- fs/pstore/Kconfig | 17 + fs/pstore/Makefile | 3 + fs/pstore/ram.c | 383 +++++++++++++++++++++ fs/pstore/ram_core.c | 532 ++++++++++++++++++++++++++++++ include/linux/pstore_ram.h | 98 ++++++ include/linux/ramoops.h | 17 - 15 files changed, 1042 insertions(+), 1015 deletions(-) -- Anton Vorontsov Email: cbouatmailru(a)gmail.com

12 years, 1 month

[PATCH 0/6] Merge ram_console into pstore

by Anton Vorontsov

Hi all, Currently pstore doesn't support logging kernel messages in run-time, it only dumps dmesg when kernel oopses/panics. This makes pstore useless for debugging hangs caused by HW issues or improper use of HW (e.g. weird device inserted -> driver tried to write reserved bits -> SoC hanged. In that case we don't get any messages in the pstore. This series add a new message type for pstore, i.e. PSTORE_TYPE_CONSOLE, plus make pstore/ram.c handle the new messages. The old ram_console driver is removed. This might probably cause some pain for out-of-tree code, as it would need to be adjusted... but "no pain, no gain"? :-) Though, if there's some serious resistance, we can probably postpone the last two patches. These patches depend on the following series: http://thread.gmane.org/gmane.linux.kernel/1298179 "[PATCH v2 0/6] Merge ramoops and persistent_ram, generic pstore RAM backend" Thanks! --- Documentation/ramoops.txt | 15 +++ drivers/staging/android/Kconfig | 5 - drivers/staging/android/Makefile | 1 - drivers/staging/android/ram_console.c | 179 --------------------------------- fs/pstore/Kconfig | 7 ++ fs/pstore/inode.c | 3 + fs/pstore/platform.c | 25 +++++ fs/pstore/ram.c | 39 +++++-- fs/pstore/ram_core.c | 81 +-------------- include/linux/pstore.h | 1 + include/linux/pstore_ram.h | 19 ---- 11 files changed, 83 insertions(+), 292 deletions(-) -- Anton Vorontsov Email: cbouatmailru(a)gmail.com

12 years, 1 month

Common struct clk for Versatile Express

by Jon Medhurst (Tixy)

Hi All Does anyone know of any efforts or plans to port Versatile Express to the common struct clk? -- Tixy

12 years, 1 month

[RESEND PATCH 1/2] ARM: OMAP2+: nand: Make board_onenand_init() visible to board code

by Javier Martinez Canillas

board_onenand_init() and board_nand_init() initialization functions are used to initialize OneNAND and NAND memories respectively. But only board_nand_init() was visible to be used from board code. This patch makes possible to initialize a OneNAND flash memory within platform code. Signed-off-by: Javier Martinez Canillas <javier(a)dowhile0.org> --- arch/arm/mach-omap2/board-flash.c | 4 ++-- arch/arm/mach-omap2/board-flash.h | 11 +++++++++++ 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index 0349fd2..70a81f9 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -87,7 +87,7 @@ static struct omap_onenand_platform_data board_onenand_data = { .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */ }; -static void +void __init board_onenand_init(struct mtd_partition *onenand_parts, u8 nr_parts, u8 cs) { @@ -98,7 +98,7 @@ __init board_onenand_init(struct mtd_partition *onenand_parts, gpmc_onenand_init(&board_onenand_data); } #else -static void +void __init board_onenand_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs) { } diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h index d25503a..c44b70d 100644 --- a/arch/arm/mach-omap2/board-flash.h +++ b/arch/arm/mach-omap2/board-flash.h @@ -47,3 +47,14 @@ static inline void board_nand_init(struct mtd_partition *nand_parts, { } #endif + +#if defined(CONFIG_MTD_ONENAND_OMAP2) || \ + defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) +extern void board_onenand_init(struct mtd_partition *nand_parts, + u8 nr_parts, u8 cs); +#else +static inline void board_onenand_init(struct mtd_partition *nand_parts, + u8 nr_parts, u8 cs) +{ +} +#endif -- 1.7.7.6

12 years, 1 month

PATCH: add small infrastructure and definitions to export debugfs files for OMAP powerdomain attributes

by eric van tassell

- These changes make OMAP power state register fields available as attributes per field in debugfs decoded as text with the hex value - pwrdm_read_reg_field() might replace a lot of the explicit functions for reading register fields and clean up the existing OMAP code a bit. - the changes are usable via debugfs standalone or with the patch coming for powerdebug - I've only implemented the support for the MPU PD - to support additional the other powerdomains all that's needed is to add the register_def_t's and field_def_t's here's a screenshot: ./powerdebug -P -d failed to initialize sensors Power Domain Information: ******************* mpu_pwrdm context lostcontext_dff 0:false lostmem_l1 0:false lostmem_l2 0:false lostmem_ram 0:false rstst emulation_rst 0:false pwrstctl powerstate 3:on-active logicretstate 1:whole lowpowerstatechange 0:false l1_retstate 1:retention l2_retstate 1:retention ram_retstate 1:retention l1_onstate 3:on-active l2_onstate 3:on-active ram_onstate 3:on-active pwrst powerstatest 3:on-active logicstatest 1:on l1_statest 3:on-active l2_statest 3:on-active ram_statest 3:on-active intransition 0:false lastpowerstateentered 3:on-active and the patch against Linaro 12.04 kernel is: >From 4b762379805848eebd3454d6bb344a50012069d4 Mon Sep 17 00:00:00 2001 From: Eric van Tassell <evt(a)evtM17x.(none)> Date: Sat, 5 May 2012 15:05:48 -0500 Subject: [PATCH] + basic infrastructure for creating powerdomain attribute files in debugfs + definitions to create the attributes for mpu power domain --- arch/arm/mach-omap2/pm-debug.c | 4 ++ arch/arm/mach-omap2/pm44xx.c | 3 +- arch/arm/mach-omap2/powerdomain.c | 89 +++++++++++++++++++++++++++ arch/arm/mach-omap2/powerdomain.h | 46 +++++++++++++- arch/arm/mach-omap2/powerdomain44xx.c | 23 +++++++ arch/arm/mach-omap2/powerdomains44xx_data.c | 85 +++++++++++++++++++++++++ arch/arm/mach-omap2/prm44xx.h | 1 + 8 files changed, 254 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 4411163..2e365e3 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -224,6 +224,10 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir) (void) debugfs_create_file("suspend", S_IRUGO|S_IWUSR, d, (void *)pwrdm, &pwrdm_suspend_fops); +#ifdef CONFIG_PM_DEBUG + if (d) + pwrdm_create_register_dirs(pwrdm, d); +#endif // CONFIG_PM_DEBUG return 0; } diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c index 4ab9b9d..f5c189e 100644 --- a/arch/arm/mach-omap2/pm44xx.c +++ b/arch/arm/mach-omap2/pm44xx.c @@ -155,7 +155,7 @@ static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) } -static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) +static int __init pwrdms_setup(struct powerdomain *pwrdm, void *arg) { struct power_state *pwrst; @@ -365,6 +365,7 @@ static int __init omap4_pm_init(void) OMAP44XX_IRQ_PRCM); goto err2; } + ret = pwrdm_for_each(pwrdms_setup, NULL); if (ret) { pr_err("Failed to setup powerdomains\n"); diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 8a18d1b..b392760 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -37,6 +37,11 @@ #define PWRDM_TRACE_STATES_FLAG (1<<31) +#ifdef CONFIG_PM_DEBUG +#include "prm-regbits-44xx.h" +#include <linux/debugfs.h> +#endif // CONFIG_PM_DEBUG + enum { PWRDM_STATE_NOW = 0, PWRDM_STATE_PREV, @@ -201,6 +206,90 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused) /* Public functions */ +#ifdef CONFIG_PM_DEBUG +///////////////////////////////////////////////////////////////////////////// +int pwrdm_read_reg_field(field_def_t *f) +{ + int ret = -EINVAL; + + + if (!f ) + return -EINVAL; + + if (!(f->reg)) + return -EINVAL; + + if (!f->reg->pwrdm) + return -EINVAL; + + if (arch_pwrdm && arch_pwrdm->pwrdm_read_reg_field) + ret = arch_pwrdm->pwrdm_read_reg_field(f); + return ret; +} + +#define BUFMAX 4096 +static char scratch[BUFMAX]; + + +static ssize_t pwrdm_dbg_read(struct file *file, char __user *buf, + size_t count, loff_t *ppos) +{ + field_def_t *f = (field_def_t *)file->private_data; + int n; + int val; + + val = pwrdm_read_reg_field(f); + memset(scratch, 0, BUFMAX); + n = sprintf(scratch, "%d:%s", val, f->decoder(val)); + return simple_read_from_buffer(buf, count, ppos, scratch, n + 1); +} + +static int pwrdm_dbg_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + return 0; +} + +static const struct file_operations pwrdm_dbg_ops = { + .read = pwrdm_dbg_read, + .open = pwrdm_dbg_open, +}; +/////////////////////////////////////////////////////////////////////////////debug + +static void pwrdm_create_1register_dir(register_def_t *r, struct dentry *pd_dentry) +{ + struct dentry *reg_dentry; + int i; + + reg_dentry = debugfs_create_dir(r->name, pd_dentry); + for (i = 0; i < r->num_fields; i++) { + field_def_t *f = &(r->fields[i]); + + f->reg = r; // link field to register + + debugfs_create_file(f->name, + S_IRUGO, + reg_dentry, + (void *)&(r->fields[i]), + &pwrdm_dbg_ops); + } +} + +void pwrdm_create_register_dirs(struct powerdomain *p, struct dentry *pd_dentry) +{ + int i; + + if ((p == (struct powerdomain *)NULL) || (pd_dentry == (struct dentry *)NULL)) + return; + + for (i = 0; i < p->num_reg_defs; i++) { + p->register_defs[i]->pwrdm = p; + pwrdm_create_1register_dir(p->register_defs[i], pd_dentry); + } +} + +#endif // CONFIG_PM_DEBUG + /** * pwrdm_register_platform_funcs - register powerdomain implementation fns * @po: func pointers for arch specific implementations diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h index 0d72a8a..5eaf08c 100644 --- a/arch/arm/mach-omap2/powerdomain.h +++ b/arch/arm/mach-omap2/powerdomain.h @@ -76,6 +76,47 @@ struct clockdomain; struct powerdomain; +#ifdef CONFIG_PM_DEBUG +/* general PD decoder definitions */ + +/* field definitions for PD_MPU */ + +typedef struct { + char *name; + u32 shift; + u32 mask; + char * (*decoder)(u8); // note: decoder may be NULL + struct _register_def_t_ *reg; +} field_def_t; + +typedef struct _register_def_t_ { + u32 ix; + char *name; + field_def_t *fields; + u8 num_fields; + struct powerdomain *pwrdm; +} register_def_t; + +#define NUM_ELTS(whole, part) (sizeof(whole)/sizeof(part)) +#define NUM_FIELDS(whole) (sizeof(whole)/sizeof(field_def_t)) + +#define DECODER(name) \ + char *decode_##name(u8 ix) { \ + if (ix > sizeof(name)/sizeof(char *)) \ + return "*invalid*"; \ + else \ + return name[ix]; \ +} + +#define FIELD_ATTR(name_str, base_name, funcp) \ + { \ + .name = name_str, \ + .shift = base_name ## _SHIFT , \ + .mask = base_name ## _MASK , \ + .decoder = funcp \ + } + +#endif //CONFIG_PM_DEBUG /** * struct powerdomain - OMAP powerdomain @@ -124,6 +165,8 @@ struct powerdomain { #ifdef CONFIG_PM_DEBUG s64 timer; s64 state_timer[PWRDM_MAX_PWRSTS]; + register_def_t **register_defs; + int num_reg_defs; #endif }; @@ -149,6 +192,7 @@ struct powerdomain { * @pwrdm_wait_transition: Wait for a pd state transition to complete */ struct pwrdm_ops { + int (*pwrdm_read_reg_field)(field_def_t *f); int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst); int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm); int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm); @@ -173,6 +217,7 @@ int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs); int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list); int pwrdm_complete_init(void); +void pwrdm_create_register_dirs(struct powerdomain *p, struct dentry *pd_dentry); struct powerdomain *pwrdm_lookup(const char *name); int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), @@ -237,5 +282,4 @@ extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank); extern struct powerdomain wkup_omap2_pwrdm; extern struct powerdomain gfx_omap2_pwrdm; - #endif diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c index a7880af..3d6d026 100644 --- a/arch/arm/mach-omap2/powerdomain44xx.c +++ b/arch/arm/mach-omap2/powerdomain44xx.c @@ -44,6 +44,28 @@ static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) return v; } +static int omap4_pwrdm_read_reg_field(field_def_t *f) +{ + u32 v; + struct powerdomain *pwrdm; + register_def_t *reg; + + if ((reg = f->reg) == (register_def_t *)NULL) + return(0xdeadbeee); + + if ((pwrdm = reg->pwrdm) == (struct powerdomain *)NULL) + return(0xdeadbeef); + + v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, + pwrdm->prcm_offs, + reg->ix); + v &= f->mask; + v >>= f->shift; + return v; + + +} + static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm) { u32 v; @@ -210,6 +232,7 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm) struct pwrdm_ops omap4_pwrdm_operations = { .pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst, .pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst, + .pwrdm_read_reg_field = omap4_pwrdm_read_reg_field, .pwrdm_read_pwrst = omap4_pwrdm_read_pwrst, .pwrdm_read_prev_pwrst = omap4_pwrdm_read_prev_pwrst, .pwrdm_set_lowpwrstchange = omap4_pwrdm_set_lowpwrstchange, diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c index fbd4c5f..45d4a03 100644 --- a/arch/arm/mach-omap2/powerdomains44xx_data.c +++ b/arch/arm/mach-omap2/powerdomains44xx_data.c @@ -30,6 +30,83 @@ #include "prm44xx.h" #include "prcm_mpu44xx.h" +#if CONFIG_PM_DEBUG + +char *pwrst_vals[] = {"off", "retention", "on-inactive", "on-active"}; +char *boolean_vals[] = {"false", "true"}; +char *statest_vals[] = {"off", "retention", "on-inactive", "on-active"}; +char *logicst_vals[] = {"off", "on"}; +char *logic_retst_vals[] = {"retention regigsters", "whole logic"}; + +DECODER(pwrst_vals); +DECODER(boolean_vals); +DECODER(statest_vals); +DECODER(logicst_vals); +DECODER(logic_retst_vals); + +field_def_t pwrst_fields[] = { + FIELD_ATTR("lastpowerstateentered", OMAP4430_LASTPOWERSTATEENTERED, decode_pwrst_vals), + FIELD_ATTR("intransition", OMAP4430_INTRANSITION, decode_boolean_vals), + FIELD_ATTR("ram_statest", OMAP4430_MPU_RAM_STATEST, decode_statest_vals), + FIELD_ATTR("l2_statest", OMAP4430_MPU_L2_STATEST, decode_statest_vals), + FIELD_ATTR("l1_statest", OMAP4430_MPU_L1_STATEST, decode_statest_vals), + FIELD_ATTR("logicstatest", OMAP4430_LOGICSTATEST, decode_logicst_vals), + FIELD_ATTR("powerstatest", OMAP_POWERSTATEST, decode_pwrst_vals), +}; + +field_def_t pwrstctl_fields[] = { + FIELD_ATTR("ram_onstate", OMAP4430_MPU_RAM_ONSTATE, decode_statest_vals), + FIELD_ATTR("l2_onstate", OMAP4430_MPU_L2_ONSTATE, decode_statest_vals), + FIELD_ATTR("l1_onstate", OMAP4430_MPU_L1_ONSTATE, decode_statest_vals), + FIELD_ATTR("ram_retstate", OMAP4430_MPU_RAM_RETSTATE, decode_statest_vals), + FIELD_ATTR("l2_retstate", OMAP4430_MPU_L2_RETSTATE, decode_statest_vals), + FIELD_ATTR("l1_retstate", OMAP4430_MPU_L1_RETSTATE, decode_statest_vals), + FIELD_ATTR("lowpowerstatechange", OMAP4430_LOWPOWERSTATECHANGE, decode_boolean_vals), + FIELD_ATTR("logicretstate", OMAP4430_LOGICRETSTATE, decode_logic_retst_vals), + FIELD_ATTR("powerstate", OMAP_POWERSTATE, decode_pwrst_vals), +}; + +field_def_t rstst_fields[] = { + + FIELD_ATTR("emulation_rst", OMAP4430_EMULATION_RST, decode_boolean_vals), +}; + +field_def_t ctx_fields[] = { + FIELD_ATTR("lostmem_ram", OMAP4430_LOSTMEM_MPU_RAM, decode_boolean_vals), + FIELD_ATTR("lostmem_l2", OMAP4430_LOSTMEM_MPU_L2, decode_boolean_vals), + FIELD_ATTR("lostmem_l1", OMAP4430_LOSTMEM_MPU_L1, decode_boolean_vals), + FIELD_ATTR("lostcontext_dff", OMAP4430_LOSTCONTEXT_DFF, decode_boolean_vals), +}; + + +register_def_t omap4_mpu_pwrst = {OMAP4_PM_PWSTST, + "pwrst", + pwrst_fields, + NUM_FIELDS(pwrst_fields)}; +register_def_t omap4_mpu_pwrstctl = {OMAP4_PM_PWSTCTRL, + "pwrstctl", + pwrstctl_fields, + NUM_FIELDS(pwrstctl_fields)}; +register_def_t omap4_mpu_rstst = {OMAP4_RM_RSTST, + "rstst", + rstst_fields, + NUM_FIELDS(rstst_fields)}; +register_def_t omap4_mpu_ctx = {OMAP4_RM_MPU_CONTEXT, + "context", + ctx_fields, + NUM_FIELDS(ctx_fields)}; + +register_def_t *omap4_mpu_regs[] = { + &omap4_mpu_pwrst, + &omap4_mpu_pwrstctl, + &omap4_mpu_rstst, + &omap4_mpu_ctx +}; + + +#endif // CONFIG_PM_DEBUG + + /* core_44xx_pwrdm: CORE power domain */ static struct powerdomain core_44xx_pwrdm = { .name = "core_pwrdm", @@ -218,6 +295,10 @@ static struct powerdomain mpu_443x_pwrdm = { [1] = PWRSTS_ON, /* mpu_l2 */ [2] = PWRSTS_ON, /* mpu_ram */ }, +#ifdef CONFIG_PM_DEBUG + .register_defs = omap4_mpu_regs, + .num_reg_defs = NUM_ELTS(omap4_mpu_regs,register_def_t *), +#endif }; static struct powerdomain mpu_446x_pwrdm = { @@ -236,6 +317,10 @@ static struct powerdomain mpu_446x_pwrdm = { [0] = PWRSTS_ON, /* mpu_l2 */ [1] = PWRSTS_ON, /* mpu_ram */ }, +#ifdef CONFIG_PM_DEBUG + .register_defs = omap4_mpu_regs, + .num_reg_defs = NUM_ELTS(omap4_mpu_regs,register_def_t *), +#endif }; /* ivahd_44xx_pwrdm: IVA-HD power domain */ diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h index 3d66ccd..926257f 100644 --- a/arch/arm/mach-omap2/prm44xx.h +++ b/arch/arm/mach-omap2/prm44xx.h @@ -66,6 +66,7 @@ #define OMAP4_RM_RSTST 0x0008 #define OMAP4_PM_PWSTCTRL 0x0000 #define OMAP4_PM_PWSTST 0x0004 +#define OMAP4_RM_MPU_CONTEXT 0x0024 /* PRM */ -- 1.7.9.5 -- - evt (Eric van Tassell) twitter: evt_texelsoft linked-in: linkedin.com/in/evttxl

12 years, 1 month

[ACTIVITY] (Deepak Saxena) May 6 - 12

by Deepak Saxena

=== Highlights === * Synced up with interested parties David R. and Jon M. on Enterprise kernel sessions * Synced up with Grant on DT status and session at connect * Synced up with Michael Hope on STM * Connect session planning === Plans === * Google Hangout on Air interview for marketing/outreach of Connect training sessions. * Continue Connect session planning: creating detailed outlines, coordinating facilitators, slides, etc... * Usual 1:1's and meetings * Work on slides for Upstreaming 101 and Linux Con JP Single zImage presentation. * Work on some wiki page updates === Issues === * Lots to do before leaving, might use all of Portland's coffee supply. === Travel/Time Off === * May 22nd - June 12th: Austin to sync up with Mounir, Rob Herring, Doug Deao Linaro Connect Few days of vacation in Beijing Linux Con Japan A few days of vacation in Tokyo Back Home! * Travel to visit family 7/27 - 8/1. Will be working from CST time zone instead of PST. * Tentatively out August 22nd- Sept 5th. Will be in the middle of nowhere and have no connectivity.

12 years, 1 month

[ACTIVITY] (Dong Aisheng) May-7-May-11

by Dong Aisheng

=== Highlights === === Pinctrl === * reviewed some converting imx driver to use pinctrl patches * sent out a few pinctrl core fix and clean up patches * added pinctrl mx5(mx51/mx53) support * wrote a draft patch to implement per bin based config in a group, but it seemed not good engouht and found that current pinctrl config implementation is not suitable for extend this feature due to different SoC's characteristic and requirements, may think more on it and open the issue for discussion with some other people involved. * pinctrl gpio support, did not spend too much time on it this week. Due to the gpio base of dt is dynamically allocated which is not suitable for current design, still not found good idea to address this issue. For IMX, we decided to config gpio in dts file as other pins temporarily. Will keep tracking on it. === mxs dt === * reviewd some mxs dt converting patches === Plan === * pinctrl per bin based config in the same group * pinctrl gpio dt support improvement. * convert remain imx drivers to use pinctrl * convert mxs driver to support dt

12 years, 1 month

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linaro-kernel May 2012