From: Mark Brown <broonie(a)linaro.org>
The current si476x I/O implementation wraps the regmap for the core with
functions that make the register map cache only when the device is powered
down. This implementation appears to be incomplete since there is no code
to synchronise the cache so writes done while the core is powered down
will be ignored, the device will only be configured if it is powered.
A better and more idiomatic approach would be to have the MFD manage the
cache, making the device cache only when it powers things down. This also
allows ASoC to use the standard regmap helpers for the device which helps
remove the ASoC custom ones so do convert to do that.
Signed-off-by: Mark Brown <broonie(a)linaro.org>
---
sound/soc/codecs/si476x.c | 46 +---------------------------------------------
1 file changed, 1 insertion(+), 45 deletions(-)
diff --git a/sound/soc/codecs/si476x.c b/sound/soc/codecs/si476x.c
index 38f3b10..ec29d26 100644
--- a/sound/soc/codecs/si476x.c
+++ b/sound/soc/codecs/si476x.c
@@ -60,48 +60,6 @@ enum si476x_pcm_format {
SI476X_PCM_FORMAT_S24_LE = 6,
};
-static unsigned int si476x_codec_read(struct snd_soc_codec *codec,
- unsigned int reg)
-{
- int err;
- unsigned int val;
- struct si476x_core *core = codec->control_data;
-
- si476x_core_lock(core);
- if (!si476x_core_is_powered_up(core))
- regcache_cache_only(core->regmap, true);
-
- err = regmap_read(core->regmap, reg, &val);
-
- if (!si476x_core_is_powered_up(core))
- regcache_cache_only(core->regmap, false);
- si476x_core_unlock(core);
-
- if (err < 0)
- return err;
-
- return val;
-}
-
-static int si476x_codec_write(struct snd_soc_codec *codec,
- unsigned int reg, unsigned int val)
-{
- int err;
- struct si476x_core *core = codec->control_data;
-
- si476x_core_lock(core);
- if (!si476x_core_is_powered_up(core))
- regcache_cache_only(core->regmap, true);
-
- err = regmap_write(core->regmap, reg, val);
-
- if (!si476x_core_is_powered_up(core))
- regcache_cache_only(core->regmap, false);
- si476x_core_unlock(core);
-
- return err;
-}
-
static const struct snd_soc_dapm_widget si476x_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("LOUT"),
SND_SOC_DAPM_OUTPUT("ROUT"),
@@ -239,7 +197,7 @@ static int si476x_codec_hw_params(struct snd_pcm_substream *substream,
static int si476x_codec_probe(struct snd_soc_codec *codec)
{
- codec->control_data = i2c_mfd_cell_to_core(codec->dev);
+ codec->control_data = dev_get_regmap(codec->dev.parent);
return 0;
}
@@ -268,8 +226,6 @@ static struct snd_soc_dai_driver si476x_dai = {
static struct snd_soc_codec_driver soc_codec_dev_si476x = {
.probe = si476x_codec_probe,
- .read = si476x_codec_read,
- .write = si476x_codec_write,
.dapm_widgets = si476x_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(si476x_dapm_widgets),
.dapm_routes = si476x_dapm_routes,
--
1.8.4.rc3
It is quite subtle why we mask the timer on behalf of the guest when
then guest has programmed the timer and it fires and is handled on the
host.
Add a comment to that effect.
Signed-off-by: Christoffer Dall <christoffer.dall(a)linaro.org>
---
virt/kvm/arm/arch_timer.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
index c2e1ef4..8168437 100644
--- a/virt/kvm/arm/arch_timer.c
+++ b/virt/kvm/arm/arch_timer.c
@@ -63,6 +63,12 @@ static void kvm_timer_inject_irq(struct kvm_vcpu *vcpu)
{
struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
+ /*
+ * Mask the virtual timer, because otherwise, the guest would never
+ * execute its interrupt handler because the virtual timer interrupt
+ * would continously preempt guest execution as the hardware interrupt
+ * traps to Hyp mode.
+ */
timer->cntv_ctl |= ARCH_TIMER_CTRL_IT_MASK;
kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id,
timer->irq->irq,
--
1.7.10.4
From: Mark Brown <broonie(a)linaro.org>
Ensure that the FIFOs are fully drained before we deassert /CS or do any
delays that have been requested in order to ensure that the behaviour
visible on the bus matches that which was requested by the caller.
Signed-off-by: Mark Brown <broonie(a)linaro.org>
---
drivers/spi/spi-s3c64xx.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 229c6b9..2e267ce 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -960,6 +960,8 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
goto out;
}
+ flush_fifo(sdd);
+
if (xfer->delay_usecs)
udelay(xfer->delay_usecs);
@@ -972,8 +974,6 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
}
msg->actual_length += xfer->len;
-
- flush_fifo(sdd);
}
out:
--
1.8.4.rc3
Hi all,
This series patches base on Tom's "Initial drm/kms driver for pl111"[1]
with linaro release 13.07 and migrate the CDFv3 for evaluation.
please notes that I set VGA as default output and tested on RTSM only.
[1] http://lwn.net/Articles/561344/
Cheers,
Show Liu
Show Liu (3):
Add display entities and pipe link for pl111
Add display entity and set VGA output(site MB) as default
add pipe link for display entity
arch/arm/boot/dts/rtsm_ve-motherboard.dtsi | 46 +++
arch/arm/boot/dts/rtsm_ve-v2p-ca15x1-ca7x1.dts | 4 +
drivers/gpu/drm/pl111/pl111_drm.h | 23 +-
drivers/gpu/drm/pl111/pl111_drm_device.c | 374 ++++++++++++++++++++++--
drivers/video/vexpress-dvi.c | 94 +++++-
5 files changed, 503 insertions(+), 38 deletions(-)
--
1.7.9.5
These patches are for separating the SOC On-Chip ohci host controller
from ohci-hcd host code and making per SOC driver module similar to EHCI
module available in the kernel. This work is part of enabling multi-platform
kernel on ARM.
Before I was sending three different ohci patch set as below.
1. Six series patch set is having exynos, omap, omap3, spear, at91 and s3c2410.
2. ohci-nxp a separate driver patch.
3. Two series patch set is having ep93xx and pxa27x.
In this patch set all three previous ohci series have been combined into single
series as all these patches are related to OHCI.
This patch series is rebased on greghk/usb-next 3.12 rc1.
Manjunath Goudar (9):
USB: OHCI: make ohci-exynos a separate driver
USB: OHCI: make ohci-omap a separate driver
USB: OHCI: make ohci-omap3 a separate driver
USB: OHCI: make ohci-spear a separate driver
USB: OHCI: make ohci-at91 a separate driver
USB: OHCI: make ohci-s3c2410 a separate driver
USB: OHCI: make ohci-nxp a separate driver
USB: OHCI: make ohci-ep93xx a separate driver
USB: OHCI: make ohci-pxa27x a separate driver
drivers/usb/host/Kconfig | 56 ++++++++-
drivers/usb/host/Makefile | 9 ++
drivers/usb/host/ohci-at91.c | 156 ++++++++++++-------------
drivers/usb/host/ohci-ep93xx.c | 72 +++++-------
drivers/usb/host/ohci-exynos.c | 167 +++++++++++----------------
drivers/usb/host/ohci-hcd.c | 149 ------------------------
drivers/usb/host/ohci-nxp.c | 123 ++++++++------------
drivers/usb/host/ohci-omap.c | 156 +++++++++----------------
drivers/usb/host/ohci-omap3.c | 118 +++++++------------
drivers/usb/host/ohci-pxa27x.c | 240 +++++++++++++++++----------------------
drivers/usb/host/ohci-s3c2410.c | 128 ++++++++++-----------
drivers/usb/host/ohci-spear.c | 140 +++++++++--------------
12 files changed, 587 insertions(+), 927 deletions(-)
--
1.7.9.5
On 27/09/13 12:53, Mark Brown wrote:
> From: Mark Brown <broonie(a)linaro.org>
>
> Otherwise we may try to start transfers immediately and then fail to
> runtime resume the device causing us not to have clocks enabled.
>
> Signed-off-by: Mark Brown <broonie(a)linaro.org>
Reviewed-by: Sylwester Nawrocki <s.nawrocki(a)samsung.com>
There is only a small typo in the subject line, thanks.
Implement save/restore of the VGIC state using the newer KVM Device
Control API. This requries some number of changes to existing code in
addition to actually supporting save/restore of the necessary state.
The first patches (01-03) support creating the VGIC using the Device
Control API. This change is necessary because there are no other
suitable KVM APIs that we can leverage to access the VGIC state from
user space and the device control API was crafted exactly for this
purpose.
Subsequent patches add the missing infrastructure and user space API
pieces necessary to actually save and restore the VGIC state. The GIC
v2.0 architecture specification already specifies registers that can be
used to save and restore the complete VGIC state for suspend/resume
purposes on real hardware, and we can resuse this interface for the
VGIC. The API is therefore based on the memory-mapped register accesses
defined in the specs. See the individual patches for details.
The patches are based on kvm-arm-next:
git://git.linaro.org/people/cdall/linux-kvm-arm.git kvm-arm-next
This patch series based on the above can be cloned from:
git://git.linaro.org/people/cdall/linux-kvm-arm.git vgic-migrate-v2
User space patches for QEMU also posted on the list. Tested on Versatile
Express TC2.
Changelogs in the individual patches.
Christoffer Dall (8):
ARM: KVM: Allow creating the VGIC after VCPUs
KVM: arm-vgic: Support KVM_CREATE_DEVICE for VGIC
KVM: arm-vgic: Set base addr through device API
irqchip: arm-gic: Define additional MMIO offsets and masks
KVM: arm-vgic: Make vgic mmio functions more generic
KVM: arm-vgic: Add vgic reg access from dev attr
KVM: arm-vgic: Add GICD_SPENDSGIR and GICD_CPENDSGIR handlers
KVM: arm-vgic: Support CPU interface reg access
Documentation/virtual/kvm/api.txt | 6 +-
Documentation/virtual/kvm/devices/arm-vgic.txt | 71 ++++
arch/arm/include/uapi/asm/kvm.h | 8 +
arch/arm/kvm/arm.c | 10 +-
include/kvm/arm_vgic.h | 2 +-
include/linux/irqchip/arm-gic.h | 14 +
include/linux/kvm_host.h | 1 +
include/uapi/linux/kvm.h | 1 +
virt/kvm/arm/vgic.c | 494 ++++++++++++++++++++++--
virt/kvm/kvm_main.c | 5 +
10 files changed, 580 insertions(+), 32 deletions(-)
create mode 100644 Documentation/virtual/kvm/devices/arm-vgic.txt
--
1.7.10.4