linaro-kernel July 2014

linaro-kernel@lists.linaro.org

85 participants
233 discussions

[PATCH] irqchip: gic-v3: Only define gic_peek_irq() when building SMP

by Mark Brown

From: Mark Brown <broonie(a)linaro.org> If building with CONFIG_SMP disbled (for example, with allnoconfig) then GCC complains that the static function gic_peek_irq() is defined but not used since the only reference is in the SMP initialisation code. Fix this by moving the function definition inside the ifdef. Signed-off-by: Mark Brown <broonie(a)linaro.org> --- drivers/irqchip/irq-gic-v3.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 81519bae0453..30130f955151 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -200,19 +200,6 @@ static void gic_poke_irq(struct irq_data *d, u32 offset) rwp_wait(); } -static int gic_peek_irq(struct irq_data *d, u32 offset) -{ - u32 mask = 1 << (gic_irq(d) % 32); - void __iomem *base; - - if (gic_irq_in_rdist(d)) - base = gic_data_rdist_sgi_base(); - else - base = gic_data.dist_base; - - return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); -} - static void gic_mask_irq(struct irq_data *d) { gic_poke_irq(d, GICD_ICENABLER); @@ -401,6 +388,19 @@ static void gic_cpu_init(void) } #ifdef CONFIG_SMP +static int gic_peek_irq(struct irq_data *d, u32 offset) +{ + u32 mask = 1 << (gic_irq(d) % 32); + void __iomem *base; + + if (gic_irq_in_rdist(d)) + base = gic_data_rdist_sgi_base(); + else + base = gic_data.dist_base; + + return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); +} + static int gic_secondary_init(struct notifier_block *nfb, unsigned long action, void *hcpu) { -- 2.0.1

9 years, 8 months

[PATCH] arm64: topology: add MPIDR-based detection

by Mark Brown

From: Zi Shen Lim <zlim(a)broadcom.com> Create cpu topology based on MPIDR. When hardware sets MPIDR to sane values, this method will always work. Therefore it should also work well as the fallback method. [1] When we have multiple processing elements in the system, we create the cpu topology by mapping each affinity level (from lowest to highest) to threads (if they exist), cores, and clusters. We combine data from all higher affinity levels into cluster_id so we don't lose any information from MPIDR. [2] [1] http://www.spinics.net/lists/arm-kernel/msg317445.html [2] https://lkml.org/lkml/2014/4/23/703 Signed-off-by: Zi Shen Lim <zlim(a)broadcom.com> Signed-off-by: Mark Brown <broonie(a)linaro.org> --- arch/arm64/include/asm/cputype.h | 2 ++ arch/arm64/kernel/topology.c | 51 +++++++++++++++++++++++++++++----------- 2 files changed, 39 insertions(+), 14 deletions(-) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 27f54a7cc81b..ed48a3a7836a 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -18,6 +18,8 @@ #define INVALID_HWID ULONG_MAX +#define MPIDR_UP_BITMASK (0x1 << 30) +#define MPIDR_MT_BITMASK (0x1 << 24) #define MPIDR_HWID_BITMASK 0xff00ffffff #define MPIDR_LEVEL_BITS_SHIFT 3 diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 43514f905916..9a0160068503 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -20,6 +20,7 @@ #include <linux/of.h> #include <linux/sched.h> +#include <asm/cputype.h> #include <asm/topology.h> static int __init get_cpu_for_node(struct device_node *node) @@ -188,13 +189,9 @@ static int __init parse_dt_topology(void) * Check that all cores are in the topology; the SMP code will * only mark cores described in the DT as possible. */ - for_each_possible_cpu(cpu) { - if (cpu_topology[cpu].cluster_id == -1) { - pr_err("CPU%d: No topology information specified\n", - cpu); + for_each_possible_cpu(cpu) + if (cpu_topology[cpu].cluster_id == -1) ret = -EINVAL; - } - } out_map: of_node_put(map); @@ -219,14 +216,6 @@ static void update_siblings_masks(unsigned int cpuid) struct cpu_topology *cpu_topo, *cpuid_topo = &cpu_topology[cpuid]; int cpu; - if (cpuid_topo->cluster_id == -1) { - /* - * DT does not contain topology information for this cpu. - */ - pr_debug("CPU%u: No topology information configured\n", cpuid); - return; - } - /* update core and thread sibling masks */ for_each_possible_cpu(cpu) { cpu_topo = &cpu_topology[cpu]; @@ -249,6 +238,40 @@ static void update_siblings_masks(unsigned int cpuid) void store_cpu_topology(unsigned int cpuid) { + struct cpu_topology *cpuid_topo = &cpu_topology[cpuid]; + u64 mpidr; + + if (cpuid_topo->cluster_id != -1) + goto topology_populated; + + mpidr = read_cpuid_mpidr(); + + /* Create cpu topology mapping based on MPIDR. */ + if (mpidr & MPIDR_UP_BITMASK) { + /* Uniprocessor system */ + cpuid_topo->thread_id = -1; + cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cpuid_topo->cluster_id = 0; + } else if (mpidr & MPIDR_MT_BITMASK) { + /* Multiprocessor system : Multi-threads per core */ + cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 1); + cpuid_topo->cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 2) | + MPIDR_AFFINITY_LEVEL(mpidr, 3) << 8; + } else { + /* Multiprocessor system : Single-thread per core */ + cpuid_topo->thread_id = -1; + cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cpuid_topo->cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 1) | + MPIDR_AFFINITY_LEVEL(mpidr, 2) << 8 | + MPIDR_AFFINITY_LEVEL(mpidr, 3) << 16; + } + + pr_debug("CPU%u: cluster %d core %d thread %d mpidr %llx\n", + cpuid, cpuid_topo->cluster_id, cpuid_topo->core_id, + cpuid_topo->thread_id, mpidr); + +topology_populated: update_siblings_masks(cpuid); } -- 2.0.0.rc4

9 years, 8 months

[RFC] cpufreq: Add bindings for CPU clock sharing topology

by Viresh Kumar

Clock lines may or may not be shared among different CPUs on a platform. When clock lines are shared between CPUs, they change DVFS state together. Possible configurations: 1.) All CPUs share a single clock line. 2.) All CPUs have independent clock lines. 3.) CPUs within a group/cluster share clock line but each group/cluster have a separate line for itself. There is no generic way available today to detect which CPUs share clock lines and so this is an attempt towards that. Much of the information is present in the commit and so no point duplicating it here. These are obviously not finalized yet and this is an attempt to initiate a discussion around this. Please share your valuable feedback. Signed-off-by: Viresh Kumar <viresh.kumar(a)linaro.org> --- I wasn't sure about the path/name of this file, so please don't blast me on that :) .../devicetree/bindings/cpufreq/cpu_clocks.txt | 159 +++++++++++++++++++++ 1 file changed, 159 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/cpu_clocks.txt diff --git a/Documentation/devicetree/bindings/cpufreq/cpu_clocks.txt b/Documentation/devicetree/bindings/cpufreq/cpu_clocks.txt new file mode 100644 index 0000000..30ce9ad --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpu_clocks.txt @@ -0,0 +1,159 @@ +* Generic CPUFreq clock bindings + +Clock lines may or may not be shared among different CPUs on a platform. + +Possible configurations: +1.) All CPUs share a single clock line +2.) All CPUs have independent clock lines +3.) CPUs within a group/cluster share clock line but each group/cluster have a + separate line for itself + +Optional Properties: +- clock-master: This declares cpu as clock master. Other CPUs can either define + "clock-ganged" or "clock-master" property, but shouldn't be missing both. + +- clock-ganged: Should have phandle of a cpu declared as "clock-master". + +If any cpu node, doesn't have both "clock-master" and "clock-ganged" properties +defined, it would be assumed that all CPUs on that platform share a single clock +line. This will help supporting already upstreamed platforms. + + +Examples: +1.) All CPUs share a single clock line + +cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a15"; + reg = <0>; + next-level-cache = <&L2>; + clock-master; + operating-points = < + /* kHz uV */ + 792000 1100000 + 396000 950000 + 198000 850000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a15"; + reg = <1>; + next-level-cache = <&L2>; + clock-ganged = <&cpu0>; + }; +}; + +OR (clock-master/ganged aren't defined) + +cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a15"; + reg = <0>; + next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 792000 1100000 + 396000 950000 + 198000 850000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a15"; + reg = <1>; + next-level-cache = <&L2>; + }; +}; + +2.) All CPUs have independent clock lines +cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a15"; + reg = <0>; + next-level-cache = <&L2>; + clock-master; + operating-points = < + /* kHz uV */ + 792000 1100000 + 396000 950000 + 198000 850000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a15"; + reg = <1>; + next-level-cache = <&L2>; + clock-master; + operating-points = < + /* kHz uV */ + 792000 1100000 + 396000 950000 + 198000 850000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + }; +}; + +3.) CPUs within a group/cluster share single clock line but each group/cluster +have a separate line for itself + +cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a15"; + reg = <0>; + next-level-cache = <&L2>; + clock-master; + operating-points = < + /* kHz uV */ + 792000 1100000 + 396000 950000 + 198000 850000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a15"; + reg = <1>; + next-level-cache = <&L2>; + clock-ganged = <&cpu0>; + }; + + cpu2: cpu@100 { + compatible = "arm,cortex-a7"; + reg = <100>; + next-level-cache = <&L2>; + clock-master; + operating-points = < + /* kHz uV */ + 792000 950000 + 396000 750000 + 198000 450000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + }; + + cpu3: cpu@101 { + compatible = "arm,cortex-a7"; + reg = <101>; + next-level-cache = <&L2>; + clock-ganged = <&cpu2>; + }; +}; -- 2.0.0.rc2

9 years, 8 months

[PATCH] mfd: wm8994: Allow modular build

by Mark Brown

From: Mark Brown <broonie(a)linaro.org> The interfaces that used to be built in only (interrupts IIRC) no longer are so allow the driver to be built as a module fixing arm64 allmodconfig builds. Signed-off-by: Mark Brown <broonie(a)linaro.org> Acked-by: Charles Keepax <ckeepax(a)opensource.wolfsonmicro.com> --- drivers/mfd/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index de5abf244746..8d5fad23a4b7 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1228,11 +1228,11 @@ config MFD_WM8350_I2C selected to enable support for the functionality of the chip. config MFD_WM8994 - bool "Wolfson Microelectronics WM8994" + tristate "Wolfson Microelectronics WM8994" select MFD_CORE select REGMAP_I2C select REGMAP_IRQ - depends on I2C=y + depends on I2C help The WM8994 is a highly integrated hi-fi CODEC designed for smartphone applicatiosn. As well as audio functionality it -- 2.0.1

9 years, 8 months

[PATCH v3] ARM: add get_user() support for 8 byte types

by Daniel Thompson

A new atomic modeset/pageflip ioctl being developed in DRM requires get_user() to work for 64bit types (in addition to just put_user()). v1: original v2: pass correct size to check_uaccess, and better handling of narrowing double word read with __get_user_xb() (Russell King's suggestion) v3: fix a couple of checkpatch issues Signed-off-by: Rob Clark <robdclark(a)gmail.com> Signed-off-by: Daniel Thompson <daniel.thompson(a)linaro.org> Cc: Russell King - ARM Linux <linux(a)arm.linux.org.uk> --- Notes: I'd like to wake this patch up again. It was rejected back in 2012 on the grounds that other architectures (notably x86-32) didn't implement this so adding for ARM risked portability problems in drivers. However shortly after the discussion (in fact I believe that as a *result* of that discussion) support for 64-bit get_user() was added for x86-32. A quick review of different architectures uaccess.h shows that ARM is in the minority (even after excluding 64-bit architectures) in not implementing this feature. The reasons to wake it up are the same as before. Recent contributions, including to DRM[1] and binder[2] would prefer to use the 64-bit values in their interfaces without gotchas like having to use copy_from_user(). [1] http://thread.gmane.org/gmane.comp.video.dri.devel/102135/focus=102149 [2] http://thread.gmane.org/gmane.linux.kernel/1653448/focus=1653449 arch/arm/include/asm/uaccess.h | 18 +++++++++++++++++- arch/arm/lib/getuser.S | 17 ++++++++++++++++- 2 files changed, 33 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h index 75d9579..5f7db3fb 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h @@ -107,6 +107,7 @@ static inline void set_fs(mm_segment_t fs) extern int __get_user_1(void *); extern int __get_user_2(void *); extern int __get_user_4(void *); +extern int __get_user_8(void *); #define __GUP_CLOBBER_1 "lr", "cc" #ifdef CONFIG_CPU_USE_DOMAINS @@ -115,6 +116,7 @@ extern int __get_user_4(void *); #define __GUP_CLOBBER_2 "lr", "cc" #endif #define __GUP_CLOBBER_4 "lr", "cc" +#define __GUP_CLOBBER_8 "lr", "cc" #define __get_user_x(__r2,__p,__e,__l,__s) \ __asm__ __volatile__ ( \ @@ -125,11 +127,19 @@ extern int __get_user_4(void *); : "0" (__p), "r" (__l) \ : __GUP_CLOBBER_##__s) +/* narrowing a double-word get into a single 32bit word register: */ +#ifdef BIG_ENDIAN +#define __get_user_xb(__r2, __p, __e, __l, __s) \ + __get_user_x(__r2, (uintptr_t)__p + 4, __e, __l, __s) +#else +#define __get_user_xb __get_user_x +#endif + #define __get_user_check(x,p) \ ({ \ unsigned long __limit = current_thread_info()->addr_limit - 1; \ register const typeof(*(p)) __user *__p asm("r0") = (p);\ - register unsigned long __r2 asm("r2"); \ + register typeof(x) __r2 asm("r2"); \ register unsigned long __l asm("r1") = __limit; \ register int __e asm("r0"); \ switch (sizeof(*(__p))) { \ @@ -142,6 +152,12 @@ extern int __get_user_4(void *); case 4: \ __get_user_x(__r2, __p, __e, __l, 4); \ break; \ + case 8: \ + if (sizeof((x)) < 8) \ + __get_user_xb(__r2, __p, __e, __l, 4); \ + else \ + __get_user_x(__r2, __p, __e, __l, 8); \ + break; \ default: __e = __get_user_bad(); break; \ } \ x = (typeof(*(p))) __r2; \ diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S index 9b06bb4..ed98707 100644 --- a/arch/arm/lib/getuser.S +++ b/arch/arm/lib/getuser.S @@ -18,7 +18,7 @@ * Inputs: r0 contains the address * r1 contains the address limit, which must be preserved * Outputs: r0 is the error code - * r2 contains the zero-extended value + * r2, r3 contains the zero-extended value * lr corrupted * * No other registers must be altered. (see <asm/uaccess.h> @@ -66,6 +66,19 @@ ENTRY(__get_user_4) mov pc, lr ENDPROC(__get_user_4) +ENTRY(__get_user_8) + check_uaccess r0, 8, r1, r2, __get_user_bad +#ifdef CONFIG_THUMB2_KERNEL +5: TUSER(ldr) r2, [r0] +6: TUSER(ldr) r3, [r0, #4] +#else +5: TUSER(ldr) r2, [r0], #4 +6: TUSER(ldr) r3, [r0] +#endif + mov r0, #0 + mov pc, lr +ENDPROC(__get_user_8) + __get_user_bad: mov r2, #0 mov r0, #-EFAULT @@ -77,4 +90,6 @@ ENDPROC(__get_user_bad) .long 2b, __get_user_bad .long 3b, __get_user_bad .long 4b, __get_user_bad + .long 5b, __get_user_bad + .long 6b, __get_user_bad .popsection -- 1.9.3

9 years, 8 months

[PATCH 0/3] kdb: Infrastructure to display sequence files

by Daniel Thompson

This patchset started out as a simple patch to introduce the irqs command from Android's FIQ debugger to kdb. However it has since grown more powerful because allowing kdb to reuse existing kernel infrastructure gives us extra opportunities. Based on the comments at the top of irqdesc.h (plotting to take the irq_desc structure private to kernel/irq) and the relative similarity between FIQ debugger's irqs command and the contents /proc/interrupts we start by adding a kdb feature to print seq_files. This forms the foundation for a new command, interrupts. I have also been able to implement a much more generic command, seq_file, that can display a good number of files from pseudo filesystems. This command is very powerful although that power does mean care must be taken to deploy it safely. It is deliberately and by default aimed at your foot! Note that the risk associated with the seq_file command is why I implemented the interrupts command in C (in principle it could have been a kdb macro). Doing it in C codifies the need for show_interrupts() to continue using spin locks as its locking strategy. To give an idea of what can be done with this command. The following seq_operations structures worked correctly and report no errors: cpuinfo_op extfrag_op fragmentation_op gpiolib_seq_ops int_seq_ops (a.k.a. /proc/interrupts) pagetypeinfo_op unusable_op vmalloc_op zoneinfo_op The following display the information correctly but triggered errors (sleeping function called from invalid context) with lock debugging enabled: consoles_op crypto_seq_ops diskstats_op partitions_op slabinfo_op vmstat_op All tests are run on an ARM multi_v7_defconfig kernel (plus lots of debug features) and halted using magic SysRq so that kdb has interrupt context. Note also that some of the seq_operations structures hook into driver supplied code that will only be called if that driver is enabled so the test above are useful but cannot be exhaustive. Daniel Thompson (3): kdb: Add framework to display sequence files proc: Provide access to /proc/interrupts from kdb kdb: Implement seq_file command fs/proc/interrupts.c | 10 +++++++++ include/linux/kdb.h | 3 +++ kernel/debug/kdb/kdb_io.c | 51 +++++++++++++++++++++++++++++++++++++++++++++ kernel/debug/kdb/kdb_main.c | 28 +++++++++++++++++++++++++ 4 files changed, 92 insertions(+) -- 1.9.0

9 years, 8 months

[PATCH v5 0/3] arm64: Add seccomp support

by AKASHI Takahiro

(Please apply this patch after my audit patch in order to avoid some conflict on arm64/Kconfig.) This patch enables secure computing (system call filtering) on arm64. System calls can be allowed or denied by loaded bpf-style rules. Architecture specific part is to run secure_computing() on syscall entry and check the result. See [3/3] Prerequisites are: * "arm64: Add audit support" patch This code is tested on ARMv8 fast model using * libseccomp v2.1.1 with modifications for arm64 and verified by its "live" tests, 20, 21 and 24. * modified version of Kees' seccomp test for 'changing/skipping a syscall' behavior Changes v4 -> v5: * rebased to v3.16-rc * add patch [1/3] to allow ptrace to change a system call (please note that this patch should be applied even without seccomp.) Changes v3 -> v4: * removed the following patch and moved it to "arm64: prerequisites for audit and ftrace" patchset since it is required for audit and ftrace in case of !COMPAT, too. "arm64: is_compat_task is defined both in asm/compat.h and linux/compat.h" Changes v2 -> v3: * removed unnecessary 'type cast' operations [2/3] * check for a return value (-1) of secure_computing() explicitly [2/3] * aligned with the patch, "arm64: split syscall_trace() into separate functions for enter/exit" [2/3] * changed default of CONFIG_SECCOMP to n [2/3] Changes v1 -> v2: * added generic seccomp.h for arm64 to utilize it [1,2/3] * changed syscall_trace() to return more meaningful value (-EPERM) on seccomp failure case [2/3] * aligned with the change in "arm64: make a single hook to syscall_trace() for all syscall features" v2 [2/3] * removed is_compat_task() definition from compat.h [3/3] AKASHI Takahiro (3): arm64: ptrace: reload a syscall number after ptrace operations asm-generic: Add generic seccomp.h for secure computing mode 1 arm64: Add seccomp support arch/arm64/Kconfig | 14 ++++++++++++++ arch/arm64/include/asm/seccomp.h | 25 +++++++++++++++++++++++++ arch/arm64/include/asm/unistd.h | 3 +++ arch/arm64/kernel/entry.S | 2 ++ arch/arm64/kernel/ptrace.c | 18 ++++++++++++++++++ include/asm-generic/seccomp.h | 28 ++++++++++++++++++++++++++++ 6 files changed, 90 insertions(+) create mode 100644 arch/arm64/include/asm/seccomp.h create mode 100644 include/asm-generic/seccomp.h -- 1.7.9.5

9 years, 8 months

[PATCH] Exynos4: cpuidle: support dual CPUs with AFTR state

by Daniel Lezcano

The following driver is for exynos4210. I did not yet finished the other boards, so I created a specific driver for 4210 which could be merged later. The driver is based on Colin Cross's driver found at: https://android.googlesource.com/kernel/exynos/+/e686b1ec67423c40b4fdf811f9… This one was based on a 3.4 kernel and an old API. It has been refreshed, simplified and based on the recent code cleanup I sent today. The AFTR could be entered when all the cpus (except cpu0) are down. In order to reach this situation, the couple idle states are used. There is a sync barrier at the entry and the exit of the low power function. So all cpus will enter and exit the function at the same time. At this point, CPU0 knows the other cpu will power down itself. CPU0 waits for the CPU1 to be powered down and then initiate the AFTR power down sequence. No interrupts are handled by CPU1, this is why we switch to the timer broadcast even if the local timer is not impacted by the idle state. When CPU0 wakes up, it powers up CPU1 and waits for it to boot. Then they both exit the idle function. This driver allows the exynos4210 to have the same power consumption at idle time than the one when we have to unplug CPU1 in order to let CPU0 to reach the AFTR state. This patch is a RFC because, we have to find a way to remove the macros definitions and cpu powerdown function without pulling the arch dependent headers. Signed-off-by: Daniel Lezcano <daniel.lezcano(a)linaro.org> --- arch/arm/mach-exynos/common.c | 11 +- drivers/cpuidle/Kconfig.arm | 8 ++ drivers/cpuidle/Makefile | 1 + drivers/cpuidle/cpuidle-exynos4210.c | 226 ++++++++++++++++++++++++++++++++++ 4 files changed, 245 insertions(+), 1 deletion(-) create mode 100644 drivers/cpuidle/cpuidle-exynos4210.c diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index d5fa21e..1765a98 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -299,9 +299,18 @@ static struct platform_device exynos_cpuidle = { .id = -1, }; +static struct platform_device exynos4210_cpuidle = { + .name = "exynos4210-cpuidle", + .dev.platform_data = exynos_sys_powerdown_aftr, + .id = -1, +}; + void __init exynos_cpuidle_init(void) { - platform_device_register(&exynos_cpuidle); + if (soc_is_exynos4210()) + platform_device_register(&exynos4210_cpuidle); + else + platform_device_register(&exynos_cpuidle); } void __init exynos_cpufreq_init(void) diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm index 92f0c12..2772130 100644 --- a/drivers/cpuidle/Kconfig.arm +++ b/drivers/cpuidle/Kconfig.arm @@ -51,3 +51,11 @@ config ARM_EXYNOS_CPUIDLE depends on ARCH_EXYNOS help Select this to enable cpuidle for Exynos processors + +config ARM_EXYNOS4210_CPUIDLE + bool "Cpu Idle Driver for the Exynos 4210 processor" + default y + depends on ARCH_EXYNOS + select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP + help + Select this to enable cpuidle for the Exynos 4210 processors diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile index 0d1540a..e0ec9bc 100644 --- a/drivers/cpuidle/Makefile +++ b/drivers/cpuidle/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_ARM_ZYNQ_CPUIDLE) += cpuidle-zynq.o obj-$(CONFIG_ARM_U8500_CPUIDLE) += cpuidle-ux500.o obj-$(CONFIG_ARM_AT91_CPUIDLE) += cpuidle-at91.o obj-$(CONFIG_ARM_EXYNOS_CPUIDLE) += cpuidle-exynos.o +obj-$(CONFIG_ARM_EXYNOS4210_CPUIDLE) += cpuidle-exynos4210.o ############################################################################### # POWERPC drivers diff --git a/drivers/cpuidle/cpuidle-exynos4210.c b/drivers/cpuidle/cpuidle-exynos4210.c new file mode 100644 index 0000000..56f6d51 --- /dev/null +++ b/drivers/cpuidle/cpuidle-exynos4210.c @@ -0,0 +1,226 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Copyright (c) 2014 Linaro : Daniel Lezcano <daniel.lezcano(a)linaro.org> + * http://www.linaro.org + * + * Based on the work of Colin Cross <ccross(a)android.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/cpuidle.h> +#include <linux/cpu_pm.h> +#include <linux/io.h> +#include <linux/platform_device.h> + +#include <asm/proc-fns.h> +#include <asm/suspend.h> +#include <asm/cpuidle.h> + +#include <plat/pm.h> +#include <plat/cpu.h> +#include <plat/map-base.h> +#include <plat/map-s5p.h> + +static atomic_t exynos_idle_barrier; +static atomic_t cpu1_wakeup = ATOMIC_INIT(0); + +#define BOOT_VECTOR S5P_VA_SYSRAM +#define S5P_VA_PMU S3C_ADDR(0x02180000) +#define S5P_PMUREG(x) (S5P_VA_PMU + (x)) +#define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080) +#define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084) + +static void (*exynos_aftr)(void); + +static int cpu_suspend_finish(unsigned long flags) +{ + if (flags) + exynos_aftr(); + + cpu_do_idle(); + + return -1; +} + +static int exynos_cpu0_enter_aftr(void) +{ + int ret = -1; + + /* + * If the other cpu is powered on, we have to power it off, because + * the AFTR state won't work otherwise + */ + if (cpu_online(1)) { + + /* + * We reach a sync point with the coupled idle state, we know + * the other cpu will power down itself or will abort the + * sequence, let's wait for one of these to happen + */ + while (__raw_readl(S5P_ARM_CORE1_STATUS) & 3) { + + /* + * The other cpu may skip idle and boot back + * up again + */ + if (atomic_read(&cpu1_wakeup)) + goto abort; + + /* + * The other cpu may bounce through idle and + * boot back up again, getting stuck in the + * boot rom code + */ + if (__raw_readl(BOOT_VECTOR) == 0) + goto abort; + + cpu_relax(); + } + } + + cpu_pm_enter(); + + ret = cpu_suspend(1, cpu_suspend_finish); + + cpu_pm_exit(); + +abort: + if (cpu_online(1)) { + /* + * Set the boot vector to something non-zero + */ + __raw_writel(virt_to_phys(s3c_cpu_resume), + BOOT_VECTOR); + dsb(); + + /* + * Turn on cpu1 and wait for it to be on + */ + __raw_writel(0x3, S5P_ARM_CORE1_CONFIGURATION); + while ((__raw_readl(S5P_ARM_CORE1_STATUS) & 3) != 3) + cpu_relax(); + + /* + * Wait for cpu1 to get stuck in the boot rom + */ + while ((__raw_readl(BOOT_VECTOR) != 0) && + !atomic_read(&cpu1_wakeup)) + cpu_relax(); + + if (!atomic_read(&cpu1_wakeup)) { + /* + * Poke cpu1 out of the boot rom + */ + __raw_writel(virt_to_phys(s3c_cpu_resume), + BOOT_VECTOR); + dsb_sev(); + } + + /* + * Wait for cpu1 to finish booting + */ + while (!atomic_read(&cpu1_wakeup)) + cpu_relax(); + } + + return ret; +} + +static int exynos_powerdown_cpu1(void) +{ + int ret = -1; + + /* + * Idle sequence for cpu1 + */ + if (cpu_pm_enter()) + goto cpu1_aborted; + + /* + * Turn off cpu 1 + */ + __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION); + + ret = cpu_suspend(0, cpu_suspend_finish); + + cpu_pm_exit(); + +cpu1_aborted: + dsb(); + /* + * Notify cpu 0 that cpu 1 is awake + */ + atomic_set(&cpu1_wakeup, 1); + + return ret; +} + +static int exynos_enter_aftr(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) +{ + int ret; + + __raw_writel(virt_to_phys(s3c_cpu_resume), BOOT_VECTOR); + + /* + * Waiting all cpus to reach this point at the same moment + */ + cpuidle_coupled_parallel_barrier(dev, &exynos_idle_barrier); + + /* + * Both cpus will reach this point at the same time + */ + ret = dev->cpu ? exynos_powerdown_cpu1() : exynos_cpu0_enter_aftr(); + if (ret) + index = ret; + + /* + * Waiting all cpus to finish the power sequence before going further + */ + cpuidle_coupled_parallel_barrier(dev, &exynos_idle_barrier); + + atomic_set(&cpu1_wakeup, 0); + + return index; +} + +static struct cpuidle_driver exynos_idle_driver = { + .name = "exynos4210_idle", + .owner = THIS_MODULE, + .states = { + ARM_CPUIDLE_WFI_STATE, + [1] = { + .enter = exynos_enter_aftr, + .exit_latency = 5000, + .target_residency = 10000, + .flags = CPUIDLE_FLAG_TIME_VALID | + CPUIDLE_FLAG_COUPLED | CPUIDLE_FLAG_TIMER_STOP, + .name = "C1", + .desc = "ARM power down", + }, + }, + .state_count = 2, + .safe_state_index = 0, +}; + +static int exynos_cpuidle_probe(struct platform_device *pdev) +{ + exynos_aftr = (void *)(pdev->dev.platform_data); + + return cpuidle_register(&exynos_idle_driver, cpu_possible_mask); +} + +static struct platform_driver exynos_cpuidle_driver = { + .driver = { + .name = "exynos4210-cpuidle", + .owner = THIS_MODULE, + }, + .probe = exynos_cpuidle_probe, +}; + +module_platform_driver(exynos_cpuidle_driver); -- 1.7.9.5

9 years, 8 months

[PATCH] arm64: audit: Fix build for audit changes

by Mark Brown

From: Mark Brown <broonie(a)linaro.org> Commit 3efe33f5d2 (audit: x86: drop arch from __audit_syscall_entry() interface) removed the arch parameter from __audit_syscall_entry() and updated the only current user in mainline but this breaks the ARMv8 audit code that has been added in -next. Fix this by making the equivalent update to ARMv8. Signed-off-by: Mark Brown <broonie(a)linaro.org> --- arch/arm64/kernel/ptrace.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c index 70526cfda056..310842e3d477 100644 --- a/arch/arm64/kernel/ptrace.c +++ b/arch/arm64/kernel/ptrace.c @@ -1115,8 +1115,8 @@ asmlinkage int syscall_trace_enter(struct pt_regs *regs) if (test_thread_flag(TIF_SYSCALL_TRACEPOINT)) trace_sys_enter(regs, regs->syscallno); - audit_syscall_entry(syscall_get_arch(), regs->syscallno, - regs->orig_x0, regs->regs[1], regs->regs[2], regs->regs[3]); + audit_syscall_entry(regs->syscallno, regs->orig_x0, regs->regs[1], + regs->regs[2], regs->regs[3]); return regs->syscallno; } -- 2.0.1

9 years, 8 months

[PATCH] gpiolib: Don't allow drivers to specify a base with DT

by Mark Brown

From: Mark Brown <broonie(a)linaro.org> DT based systems should have no reason to use fixed GPIO numbers but some drivers that work on both DT and non-DT platforms specify them anyway. In order to improve robustness in cases where drivers use gpio_is_valid() to check for a valid GPIO on data initialized to zero as a default and avoid bugs due to assuptions about fixed numbers creeping in ignore any specified base when DT is in use. Signed-off-by: Mark Brown <broonie(a)linaro.org> --- drivers/gpio/gpiolib.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 768f0831db18..11d3cf1cbca7 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -234,7 +234,7 @@ int gpiochip_add(struct gpio_chip *chip) spin_lock_irqsave(&gpio_lock, flags); - if (base < 0) { + if (base < 0 || of_have_populated_dt()) { base = gpiochip_find_base(chip->ngpio); if (base < 0) { status = base; -- 2.0.1

9 years, 8 months

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linaro-kernel July 2014