linaro-kernel December 2016

linaro-kernel@lists.linaro.org

35 participants
119 discussions

[PATCH V3 00/16] PM / OPP: Introduce APIs to transition OPPs

by Viresh Kumar

Hi Guys, This patchset add APIs in OPP layer to allow OPPs transitioning from within OPP layer. Currently all OPP users need to replicate the same code to switch between OPPs. While the same can be handled easily by OPP-core. The first 7 patches update the OPP core to introduce the new APIs and the next Nine patches update cpufreq-dt for the same. 11 out of 17 are already Reviewed by Stephen, only few are left :) I hope this is the last version of the series :) Testing: - Tested on exynos 5250-arndale (dual-cortex-A15) - Tested for both Old-V1 bindings and New V2 bindings - Tested with regulator names as: 'cpu-supply' and 'cpu0-supply' - Tested with Unsupported supply ranges as well, to check the opp-disable logic V2->V3: - Very minor updates. - find_supply_name() doesn't return an error value now, and so its callers don't check for it. - And so we don't need to initialize name to NULL Viresh Kumar (16): PM / OPP: get/put regulators from OPP core PM / OPP: Disable OPPs that aren't supported by the regulator PM / OPP: Introduce dev_pm_opp_get_max_volt_latency() PM / OPP: Introduce dev_pm_opp_get_max_transition_latency() PM / OPP: Parse clock-latency and voltage-tolerance for v1 bindings PM / OPP: Manage device clk PM / OPP: Add dev_pm_opp_set_rate() cpufreq: dt: Convert few pr_debug/err() calls to dev_dbg/err() cpufreq: dt: Rename 'need_update' to 'opp_v1' cpufreq: dt: OPP layers handles clock-latency for V1 bindings as well cpufreq: dt: Pass regulator name to the OPP core cpufreq: dt: Unsupported OPPs are already disabled cpufreq: dt: Reuse dev_pm_opp_get_max_transition_latency() cpufreq: dt: Use dev_pm_opp_set_rate() to switch frequency cpufreq: dt: No need to fetch voltage-tolerance cpufreq: dt: No need to allocate resources anymore drivers/base/power/opp/core.c | 420 ++++++++++++++++++++++++++++++++++++++++++ drivers/base/power/opp/opp.h | 13 ++ drivers/cpufreq/cpufreq-dt.c | 300 +++++++++++------------------- include/linux/pm_opp.h | 27 +++ 4 files changed, 565 insertions(+), 195 deletions(-) -- 2.7.1.370.gb2aa7f8

6 years, 7 months

[PATCH 00/34] CPUFreq: Move freq change notifications out of drivers

by Viresh Kumar

Another 452 lines gone :) Total stats upto now for all the 5 patchsets: Viresh Kumar (186): ... 69 files changed, 700 insertions(+), 2451 deletions(-) Net: 1751 lines gone.. -----x-------------x---------------- Most of the drivers do following in their ->target_index() routines: struct cpufreq_freqs freqs; freqs.old = old freq... freqs.new = new freq... cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE); /* Change rate here */ cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE); This is replicated over all cpufreq drivers today and there doesn't exists a good enough reason why this shouldn't be moved to cpufreq core instead. There are few special cases though, like exynos5440, which doesn't do everything on the call to ->target_index() routine and call some kind of bottom halves for doing this work, work/tasklet/etc.. They may continue doing notification from their own code and so this patch introduces another flag: CPUFREQ_NO_NOTIFICATION, which will be set by such drivers. This is Fifth part of my cleanup work for CPUFreq, first three are (And obviously its rebased over them): 1: cpufreq: Introduce cpufreq_table_validate_and_show() https://lkml.org/lkml/2013/8/8/263 2: cpufreq: define generic routines for cpufreq drivers https://lkml.org/lkml/2013/8/10/48 3. CPUFreq: Implement light weight ->target(): for 3.13 https://lkml.org/lkml/2013/8/13/349 4. CPUFreq: set policy->cur in cpufreq core instead of drivers https://lkml.org/lkml/2013/8/14/288 All these are pushed here: https://git.linaro.org/gitweb?p=people/vireshk/linux.git;a=shortlog;h=refs/… -- viresh Cc: Andrew Lunn <andrew(a)lunn.ch> Cc: David S. Miller <davem(a)davemloft.net> Cc: Dmitry Eremin-Solenikov <dbaryshkov(a)gmail.com> Cc: Eric Miao <eric.y.miao(a)gmail.com> Cc: Hans-Christian Egtvedt <egtvedt(a)samfundet.no> Cc: Jesper Nilsson <jesper.nilsson(a)axis.com> Cc: John Crispin <blogic(a)openwrt.org> Cc: Kukjin Kim <kgene.kim(a)samsung.com> Cc: Linus Walleij <linus.walleij(a)linaro.org> Cc: linux-cris-kernel(a)axis.com Cc: Mikael Starvik <starvik(a)axis.com> Cc: Russell King <linux(a)arm.linux.org.uk> Cc: Santosh Shilimkar <santosh.shilimkar(a)ti.com> Cc: Sekhar Nori <nsekhar(a)ti.com> Cc: Shawn Guo <shawn.guo(a)linaro.org> Cc: sparclinux(a)vger.kernel.org Cc: spear-devel(a)list.st.com Cc: Stephen Warren <swarren(a)nvidia.com> Cc: Steven Miao <realmz6(a)gmail.com> Cc: Tony Luck <tony.luck(a)intel.com> Viresh Kumar (34): cpufreq: move freq change notifications to cpufreq core cpufreq: acpi: remove calls to cpufreq_notify_transition() cpufreq: arm_big_little: remove calls to cpufreq_notify_transition() cpufreq: at32ap: remove calls to cpufreq_notify_transition() cpufreq: blackfin: remove calls to cpufreq_notify_transition() cpufreq: cpu0: remove calls to cpufreq_notify_transition() cpufreq: cris: remove calls to cpufreq_notify_transition() cpufreq: davinci: remove calls to cpufreq_notify_transition() cpufreq: dbx500: remove calls to cpufreq_notify_transition() cpufreq: e_powersaver: remove calls to cpufreq_notify_transition() cpufreq: elanfreq: remove calls to cpufreq_notify_transition() cpufreq: exynos: remove calls to cpufreq_notify_transition() cpufreq: exynos5440: set CPUFREQ_NO_NOTIFICATION flag cpufreq: ia64-acpi: remove calls to cpufreq_notify_transition() cpufreq: imx6q: remove calls to cpufreq_notify_transition() cpufreq: kirkwood: remove calls to cpufreq_notify_transition() cpufreq: longhaul: set CPUFREQ_NO_NOTIFICATION flag cpufreq: loongson2: remove calls to cpufreq_notify_transition() cpufreq: maple: remove calls to cpufreq_notify_transition() cpufreq: omap: remove calls to cpufreq_notify_transition() cpufreq: p4-clockmod: remove calls to cpufreq_notify_transition() cpufreq: pasemi: remove calls to cpufreq_notify_transition() cpufreq: pmac: remove calls to cpufreq_notify_transition() cpufreq: powernow: remove calls to cpufreq_notify_transition() cpufreq: ppc: remove calls to cpufreq_notify_transition() cpufreq: pxa: remove calls to cpufreq_notify_transition() cpufreq: s3c: remove calls to cpufreq_notify_transition() cpufreq: s5pv210: remove calls to cpufreq_notify_transition() cpufreq: sa11x0: remove calls to cpufreq_notify_transition() cpufreq: sc520: remove calls to cpufreq_notify_transition() cpufreq: sparc: remove calls to cpufreq_notify_transition() cpufreq: SPEAr: remove calls to cpufreq_notify_transition() cpufreq: speedstep: remove calls to cpufreq_notify_transition() cpufreq: tegra: remove calls to cpufreq_notify_transition() drivers/cpufreq/acpi-cpufreq.c | 14 ++------- drivers/cpufreq/arm_big_little.c | 25 ++-------------- drivers/cpufreq/at32ap-cpufreq.c | 22 ++++++-------- drivers/cpufreq/blackfin-cpufreq.c | 22 +++++--------- drivers/cpufreq/cpufreq-cpu0.c | 33 ++++++++------------- drivers/cpufreq/cpufreq.c | 34 +++++++++++++++++++++ drivers/cpufreq/cris-artpec3-cpufreq.c | 8 ----- drivers/cpufreq/cris-etraxfs-cpufreq.c | 8 ----- drivers/cpufreq/davinci-cpufreq.c | 30 +++++++------------ drivers/cpufreq/dbx500-cpufreq.c | 22 +------------- drivers/cpufreq/e_powersaver.c | 23 ++------------- drivers/cpufreq/elanfreq.c | 13 -------- drivers/cpufreq/exynos-cpufreq.c | 28 +++++------------- drivers/cpufreq/exynos5440-cpufreq.c | 2 +- drivers/cpufreq/ia64-acpi-cpufreq.c | 19 ------------ drivers/cpufreq/imx6q-cpufreq.c | 39 ++++++++++-------------- drivers/cpufreq/kirkwood-cpufreq.c | 54 +++++++++++++--------------------- drivers/cpufreq/longhaul.c | 1 + drivers/cpufreq/loongson2_cpufreq.c | 16 ---------- drivers/cpufreq/maple-cpufreq.c | 18 +----------- drivers/cpufreq/omap-cpufreq.c | 39 +++++++++--------------- drivers/cpufreq/p4-clockmod.c | 10 ------- drivers/cpufreq/pasemi-cpufreq.c | 14 +-------- drivers/cpufreq/pmac32-cpufreq.c | 20 +++---------- drivers/cpufreq/pmac64-cpufreq.c | 18 +----------- drivers/cpufreq/powernow-k6.c | 8 ----- drivers/cpufreq/powernow-k7.c | 11 +------ drivers/cpufreq/powernow-k8.c | 15 +--------- drivers/cpufreq/ppc-corenet-cpufreq.c | 19 +----------- drivers/cpufreq/ppc_cbe_cpufreq.c | 19 +----------- drivers/cpufreq/pxa2xx-cpufreq.c | 27 ++++------------- drivers/cpufreq/pxa3xx-cpufreq.c | 12 -------- drivers/cpufreq/s3c2416-cpufreq.c | 21 +++---------- drivers/cpufreq/s3c64xx-cpufreq.c | 48 ++++++++++-------------------- drivers/cpufreq/s5pv210-cpufreq.c | 16 ++++------ drivers/cpufreq/sa1100-cpufreq.c | 17 ++++------- drivers/cpufreq/sa1110-cpufreq.c | 12 ++------ drivers/cpufreq/sc520_freq.c | 11 ------- drivers/cpufreq/sparc-us2e-cpufreq.c | 7 ----- drivers/cpufreq/sparc-us3-cpufreq.c | 7 ----- drivers/cpufreq/spear-cpufreq.c | 13 +------- drivers/cpufreq/speedstep-centrino.c | 20 +------------ drivers/cpufreq/speedstep-ich.c | 9 ------ drivers/cpufreq/speedstep-smi.c | 7 ----- drivers/cpufreq/tegra-cpufreq.c | 25 ++++------------ include/linux/cpufreq.h | 6 ++++ 46 files changed, 205 insertions(+), 657 deletions(-) -- 1.7.12.rc2.18.g61b472e

7 years, 4 months

[PATCH v6] clk: mediatek: Export CPU mux clocks for CPU frequency control

by Pi-Cheng Chen

From: "pi-cheng.chen" <pi-cheng.chen(a)linaro.org> This patch adds CPU mux clocks which are used by Mediatek cpufreq driver for intermediate clock source switching. Signed-off-by: Pi-Cheng Chen <pi-cheng.chen(a)linaro.org> --- Changes in v6: - Relace __clk_get_num_parents with clk_hw_get_num_parents to reflect API change Changes in v5: - Replace __initdata with __initconst to fix compiling error Changes in v4: - Fix some minor issues for v3 - Rebase to the patch that adds 13mhz clock for MT8173[1] Changes in v3: - Rebase to 4.2-rc1 - Fix some issues of v2 Changes in v2: - Remove use of .determine_rate callback --- drivers/clk/mediatek/Makefile | 2 +- drivers/clk/mediatek/clk-cpumux.c | 127 +++++++++++++++++++++++++++++++++ drivers/clk/mediatek/clk-cpumux.h | 22 ++++++ drivers/clk/mediatek/clk-mt8173.c | 23 ++++++ include/dt-bindings/clock/mt8173-clk.h | 4 +- 5 files changed, 176 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/mediatek/clk-cpumux.c create mode 100644 drivers/clk/mediatek/clk-cpumux.h diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 8e4b2a4..299917a 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -1,4 +1,4 @@ -obj-y += clk-mtk.o clk-pll.o clk-gate.o +obj-y += clk-mtk.o clk-pll.o clk-gate.o clk-cpumux.o obj-$(CONFIG_RESET_CONTROLLER) += reset.o obj-y += clk-mt8135.o obj-y += clk-mt8173.o diff --git a/drivers/clk/mediatek/clk-cpumux.c b/drivers/clk/mediatek/clk-cpumux.c new file mode 100644 index 0000000..91b5238 --- /dev/null +++ b/drivers/clk/mediatek/clk-cpumux.c @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2015 Linaro Ltd. + * Author: Pi-Cheng Chen <pi-cheng.chen(a)linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/mfd/syscon.h> +#include <linux/slab.h> + +#include "clk-mtk.h" +#include "clk-cpumux.h" + +struct mtk_clk_cpumux { + struct clk_hw hw; + struct regmap *regmap; + u32 reg; + u32 mask; + u8 shift; +}; + +static inline struct mtk_clk_cpumux *to_clk_mux(struct clk_hw *_hw) +{ + return container_of(_hw, struct mtk_clk_cpumux, hw); +} + +static u8 clk_cpumux_get_parent(struct clk_hw *hw) +{ + struct mtk_clk_cpumux *mux = to_clk_mux(hw); + int num_parents = clk_hw_get_num_parents(hw); + unsigned int val; + + regmap_read(mux->regmap, mux->reg, &val); + + val >>= mux->shift; + val &= mux->mask; + + if (val >= num_parents) + return -EINVAL; + + return val; +} + +static int clk_cpumux_set_parent(struct clk_hw *hw, u8 index) +{ + struct mtk_clk_cpumux *mux = to_clk_mux(hw); + u32 mask, val; + + val = index << mux->shift; + mask = mux->mask << mux->shift; + + return regmap_update_bits(mux->regmap, mux->reg, mask, val); +} + +static const struct clk_ops clk_cpumux_ops = { + .get_parent = clk_cpumux_get_parent, + .set_parent = clk_cpumux_set_parent, +}; + +static struct clk __init *mtk_clk_register_cpumux(const struct mtk_composite *mux, + struct regmap *regmap) +{ + struct mtk_clk_cpumux *cpumux; + struct clk *clk; + struct clk_init_data init; + + cpumux = kzalloc(sizeof(*cpumux), GFP_KERNEL); + if (!cpumux) + return ERR_PTR(-ENOMEM); + + init.name = mux->name; + init.ops = &clk_cpumux_ops; + init.parent_names = mux->parent_names; + init.num_parents = mux->num_parents; + init.flags = mux->flags; + + cpumux->reg = mux->mux_reg; + cpumux->shift = mux->mux_shift; + cpumux->mask = BIT(mux->mux_width) - 1; + cpumux->regmap = regmap; + cpumux->hw.init = &init; + + clk = clk_register(NULL, &cpumux->hw); + if (IS_ERR(clk)) + kfree(cpumux); + + return clk; +} + +int __init mtk_clk_register_cpumuxes(struct device_node *node, + const struct mtk_composite *clks, int num, + struct clk_onecell_data *clk_data) +{ + int i; + struct clk *clk; + struct regmap *regmap; + + regmap = syscon_node_to_regmap(node); + if (IS_ERR(regmap)) { + pr_err("Cannot find regmap for %s: %ld\n", node->full_name, + PTR_ERR(regmap)); + return PTR_ERR(regmap); + } + + for (i = 0; i < num; i++) { + const struct mtk_composite *mux = &clks[i]; + + clk = mtk_clk_register_cpumux(mux, regmap); + if (IS_ERR(clk)) { + pr_err("Failed to register clk %s: %ld\n", + mux->name, PTR_ERR(clk)); + continue; + } + + clk_data->clks[mux->id] = clk; + } + + return 0; +} diff --git a/drivers/clk/mediatek/clk-cpumux.h b/drivers/clk/mediatek/clk-cpumux.h new file mode 100644 index 0000000..52c769f --- /dev/null +++ b/drivers/clk/mediatek/clk-cpumux.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2015 Linaro Ltd. + * Author: Pi-Cheng Chen <pi-cheng.chen(a)linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DRV_CLK_CPUMUX_H +#define __DRV_CLK_CPUMUX_H + +int mtk_clk_register_cpumuxes(struct device_node *node, + const struct mtk_composite *clks, int num, + struct clk_onecell_data *clk_data); + +#endif /* __DRV_CLK_CPUMUX_H */ diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index 9ea6aa1..b02d310 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -20,6 +20,7 @@ #include "clk-mtk.h" #include "clk-gate.h" +#include "clk-cpumux.h" #include <dt-bindings/clock/mt8173-clk.h> @@ -518,6 +519,25 @@ static const char * const i2s3_b_ck_parents[] __initconst = { "apll2_div5" }; +static const char * const ca53_parents[] __initconst = { + "clk26m", + "armca7pll", + "mainpll", + "univpll" +}; + +static const char * const ca57_parents[] __initconst = { + "clk26m", + "armca15pll", + "mainpll", + "univpll" +}; + +static const struct mtk_composite cpu_muxes[] __initconst = { + MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2), + MUX(CLK_INFRA_CA57SEL, "infra_ca57_sel", ca57_parents, 0x0000, 2, 2), +}; + static const struct mtk_composite top_muxes[] __initconst = { /* CLK_CFG_0 */ MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3), @@ -760,6 +780,9 @@ static void __init mtk_infrasys_init(struct device_node *node) clk_data); mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); + mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), + clk_data); + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) pr_err("%s(): could not register clock provider: %d\n", diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h index fa2a2bb..a17cbaa 100644 --- a/include/dt-bindings/clock/mt8173-clk.h +++ b/include/dt-bindings/clock/mt8173-clk.h @@ -188,7 +188,9 @@ #define CLK_INFRA_PMICSPI 10 #define CLK_INFRA_PMICWRAP 11 #define CLK_INFRA_CLK_13M 12 -#define CLK_INFRA_NR_CLK 13 +#define CLK_INFRA_CA53SEL 13 +#define CLK_INFRA_CA57SEL 14 +#define CLK_INFRA_NR_CLK 15 /* PERI_SYS */ -- 1.9.1

8 years

[PATCH 00/12] PM / OPP: Use kref and move away from RCU locking

by Viresh Kumar

Hi Rafael, You can pretty much ignore this series until all other OPP cleanup/fixes get merged. I am posting these to get early reviews from Stephen as these patches have been lying with me for almost a week now. And I am also _not_ pushing these for 4.10-rc1. It all depends on how the reviews go. The RCU locking isn't well suited for the OPP core. The RCU locking fits better for reader heavy stuff, while the OPP core have at max one or two readers only at a time. Over that, it was getting very confusing the way RCU locking was used within the OPP core. The individual OPPs are mostly well handled, i.e. for an update a new structure was created and then that replaced the older one. But the OPP tables were updated directly all the time from various parts of the core. Though they were mostly used from within RCU locked region, they didn't had much to do with RCU and were governed by the mutex instead. And that mixed with the 'opp_table_lock' has made the core even more confusing. Similar concerns were shared by Stephen Boyd earlier [1]. This patchset simplifies the locking in OPP core to great extent using Kernel reference counting mechanism along with per OPP table mutex. And finally it gets rid of RCU locking as well. Each and every patch of this series is individually: - build tested - boot tested with cpufreq-dt.ko module. Insmod and rmmod to make sure the OPPs and the OPP tables are getting freed. More testing is also done by various build and boot bots for last few days. And they reported lots of issues (both build and boot time) that helped making this series more robust: - Kernel CI (Linaro) - Fengguang Wu's bot (Intel) This series has few dependencies though. It is rebased over: pm/bleeding-edge + OPP cleanup series [2] + few devfreq fixes [3], [4], and [5]. + A recent revert [6] Though all of those shall get merged before we end up reviewing this series. -- viresh [1] https://marc.info/?l=linux-kernel&m=147742717527548&w=2 [2] https://marc.info/?l=linux-pm&m=148108573618896&w=2 [3] https://patchwork.kernel.org/patch/9455789/ [4] https://patchwork.kernel.org/patch/9455757/ [5] https://marc.info/?l=linux-pm&m=148090824301852&w=2 [6] https://marc.info/?l=linux-kernel&m=148110674223377&w=2 Viresh Kumar (12): PM / OPP: Add per OPP table mutex PM / OPP: Add 'struct kref' to OPP table PM / OPP: Return opp_table from dev_pm_opp_set_*() routines PM / OPP: Take reference of the OPP table while adding/removing OPPs PM / OPP: Use dev_pm_opp_get_opp_table() instead of _add_opp_table() PM / OPP: Add 'struct kref' to struct dev_pm_opp PM / OPP: Update OPP users to put reference PM / OPP: Take kref from _find_opp_table() PM / OPP: Move away from RCU locking PM / OPP: Simplify _opp_set_availability() PM / OPP: Simplify dev_pm_opp_get_max_volt_latency() PM / OPP: Update Documentation to remove RCU specific bits Documentation/power/opp.txt | 47 +- arch/arm/mach-omap2/pm.c | 5 +- drivers/base/power/opp/core.c | 888 +++++++++++------------------------ drivers/base/power/opp/cpu.c | 66 +-- drivers/base/power/opp/of.c | 94 +--- drivers/base/power/opp/opp.h | 31 +- drivers/clk/tegra/clk-dfll.c | 17 +- drivers/cpufreq/exynos5440-cpufreq.c | 5 +- drivers/cpufreq/imx6q-cpufreq.c | 10 +- drivers/cpufreq/mt8173-cpufreq.c | 8 +- drivers/cpufreq/omap-cpufreq.c | 4 +- drivers/cpufreq/sti-cpufreq.c | 13 +- drivers/devfreq/devfreq.c | 14 +- drivers/devfreq/exynos-bus.c | 14 +- drivers/devfreq/governor_passive.c | 4 +- drivers/devfreq/rk3399_dmc.c | 16 +- drivers/devfreq/tegra-devfreq.c | 4 +- drivers/thermal/cpu_cooling.c | 11 +- drivers/thermal/devfreq_cooling.c | 14 +- include/linux/pm_opp.h | 48 +- 20 files changed, 429 insertions(+), 884 deletions(-) -- 2.7.1.410.g6faf27b

8 years, 1 month

[PATCH v2 3/3] phy: rockchip-inno-usb2: Set EXTCON_USB when EXTCON_CHG_USB_SDP was set

by Baolin Wang

According to the documentation, we should set the EXTCON_USB when one SDP charger connector was reported. Signed-off-by: Baolin Wang <baolin.wang(a)linaro.org> Reviewed-by: Chanwoo Choi <cw00.choi(a)samsung.com> --- Changes since v1: - Change extcon_set_cable_state_() to extcon_set_state_sync(). - Add reviewed tag by Chanwoo Choi. --- drivers/phy/phy-rockchip-inno-usb2.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c index 2f99ec9..4ea95c2 100644 --- a/drivers/phy/phy-rockchip-inno-usb2.c +++ b/drivers/phy/phy-rockchip-inno-usb2.c @@ -595,9 +595,14 @@ static void rockchip_usb2phy_otg_sm_work(struct work_struct *work) if (rport->vbus_attached != vbus_attach) { rport->vbus_attached = vbus_attach; - if (notify_charger && rphy->edev) + if (notify_charger && rphy->edev) { extcon_set_cable_state_(rphy->edev, cable, vbus_attach); + if (cable == EXTCON_CHG_USB_SDP) + extcon_set_state_sync(rphy->edev, + EXTCON_USB, + vbus_attach); + } } break; case OTG_STATE_B_PERIPHERAL: -- 1.7.9.5

8 years, 1 month

[PATCH V2 0/2] PM / Domains / OPP: Introduce domain-performance-state binding

by Viresh Kumar

Hello, Some platforms have the capability to configure the performance state of their Power Domains. The performance levels are represented by positive integer values, a lower value represents lower performance state. We had some discussions about it in the past on the PM list [1], which is followed by discussions during the LPC. The outcome of all that was that we should extend Power Domain framework to support active state power management as well. The power-domains until now were only concentrating on the idle state management of the device and this needs to change in order to reuse the infrastructure of power domains for active state management. To get a complete picture of the proposed plan, following is what we need to do: - Create DT bindings to get domain performance state information for the platforms. - Enhance OPP framework to parse these and call into the PM Qos framework with a performance state request. - Enhance PM Qos framework to provide the API to be used by consumers (or OPP framework) and pass it on to the (Generic) Power Domain framework. - Enhance Generic Power Domain framework to accept such requests, accumulate all belonging to a single power domain and call domain driver specific callback with the performance state we want for the domain. - The domain driver shall then, in a platform specific way, set the requested performance level. - Note that these features are applicable to the CPU, GPU and other IIO or non-IIO devices. - There can be cases where a device can choose between multiple power domains based on what performance level we want for the device. In such cases, we should represent the multiplexer with a separate power domain. In effect, the device (or OPP table) will correspond to a single power domain, but the backend driver of that domain shall implement the multiplexing functionality. This patchset implements the very first part of this chain and introduces a new optional property for the consumers of the power-domains: domain-performance-state. This property can be used directly by the consumer or its OPP table. V1->V2: - The performance states get their own nodes as they can have multiple values. - Allow optional property domain-microvolt for the performance states -- viresh [1] https://marc.info/?l=linux-pm&m=147747923708075&w=2 Viresh Kumar (2): PM / Domains: Introduce domain-performance-states binding PM / OPP: Introduce domain-performance-state binding to OPP nodes Documentation/devicetree/bindings/opp/opp.txt | 59 ++++++++++++++++++ .../devicetree/bindings/power/power_domain.txt | 69 ++++++++++++++++++++++ 2 files changed, 128 insertions(+) -- 2.7.1.410.g6faf27b

8 years, 1 month

[PATCH] usb: dwc3: gadget: Avoid race between dwc3 interrupt handler and irq thread handler

by Baolin Wang

On some platfroms(like x86 platform), when one core is running the USB gadget irq thread handler by dwc3_thread_interrupt(), meanwhile another core also can respond other interrupts from dwc3 controller and modify the event buffer by dwc3_interrupt() function, that will cause getting the wrong event count in irq thread handler to make the USB function abnormal. We should add spin_lock/unlock() in dwc3_check_event_buf() to avoid this race. Signed-off-by: Baolin Wang <baolin.wang(a)linaro.org> --- drivers/usb/dwc3/gadget.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 6785595..1a1e1f4 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -2894,10 +2894,13 @@ static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt) return IRQ_HANDLED; } + spin_lock(&dwc->lock); count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); count &= DWC3_GEVNTCOUNT_MASK; - if (!count) + if (!count) { + spin_unlock(&dwc->lock); return IRQ_NONE; + } evt->count = count; evt->flags |= DWC3_EVENT_PENDING; @@ -2914,6 +2917,7 @@ static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt) memcpy(evt->cache, evt->buf, count - amount); dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count); + spin_unlock(&dwc->lock); return IRQ_WAKE_THREAD; } -- 1.7.9.5

8 years, 1 month

[PATCH v6 0/8] Add PWM and IIO timer drivers for STM32

by Benjamin Gaignard

version 6: - rename stm32-gptimer in stm32-timers. - change "st,stm32-gptimer" compatible to "st,stm32-timers". - modify "st,breakinput" parameter in pwm part. - split DT patch in 2 version 5: - fix comments done on version 4 - rebased on kernel 4.9-rc8 - change nodes names and re-order then by addresses version 4: - fix comments done on version 3 - don't use interrupts anymore in IIO timer - detect hardware capabilities at probe time to simplify binding version 3: - no change on mfd and pwm divers patches - add cross reference between bindings - change compatible to "st,stm32-timer-trigger" - fix attributes access rights - use string instead of int for master_mode and slave_mode - document device attributes in sysfs-bus-iio-timer-stm32 - update DT with the new compatible version 2: - keep only one compatible per driver - use DT parameters to describe hardware block configuration: - pwm channels, complementary output, counter size, break input - triggers accepted and create by IIO timers - change DT to limite use of reference to the node - interrupt is now in IIO timer driver - rename stm32-mfd-timer to stm32-timers (for general purpose timer) The following patches enable PWM and IIO Timer features for STM32 platforms. Those two features are mixed into the registers of the same hardware block (named general purpose timer) which lead to introduce a multifunctions driver on the top of them to be able to share the registers. In STM32f4 14 instances of timer hardware block exist, even if they all have the same register mapping they could have a different number of pwm channels and/or different triggers capabilities. We use various parameters in DT to describe the differences between hardware blocks The MFD (stm32-timers.c) takes care of clock and register mapping by using regmap. stm32_timers structure is provided to its sub-node to share those information. PWM driver is implemented into pwm-stm32.c. Depending of the instance we may have up to 4 channels, sometime with complementary outputs or 32 bits counter instead of 16 bits. Some hardware blocks may also have a break input function which allows to stop pwm depending of a level, defined in devicetree, on an external pin. IIO timer driver (stm32-timer-trigger.c and stm32-timer-trigger.h) define a list of hardware triggers usable by hardware blocks like ADC, DAC or other timers. The matrix of possible connections between blocks is quite complex so we use trigger names and is_stm32_iio_timer_trigger() function to be sure that triggers are valid and configure the IPs. At run time IIO timer hardware blocks can configure (through "master_mode" IIO device attribute) which internal signal (counter enable, reset, comparison block, etc...) is used to generate the trigger. By using "slave_mode" IIO device attribute timer can also configure on which event (level, rising edge) of the block is enabled. Since we can use trigger from one hardware to control an other block, we can use a pwm to control an other one. The following example shows how to configure pwm1 and pwm3 to make pwm3 generate pulse only when pwm1 pulse level is high. /sys/bus/iio/devices # ls iio:device0 iio:device1 trigger0 trigger1 configure timer1 to use pwm1 channel 0 as output trigger /sys/bus/iio/devices # echo 'OC1REF' > iio\:device0/master_mode configure timer3 to enable only when input is high /sys/bus/iio/devices # echo 'gated' > iio\:device1/slave_mode /sys/bus/iio/devices # cat trigger0/name tim1_trgo configure timer2 to use timer1 trigger is input /sys/bus/iio/devices # echo "tim1_trgo" > iio\:device1/trigger/current_trigger configure pwm3 channel 0 to generate a signal with a period of 100ms and a duty cycle of 50% /sys/devices/platform/soc/40000400.timers/40000400.timers:pwm/pwm/pwmchip4 # echo 0 > export /sys/devices/platform/soc/40000400.timers/40000400.timers:pwm/pwm/pwmchip4 # echo 100000000 > pwm0/period /sys/devices/platform/soc/40000400.timers/40000400.timers:pwm/pwm/pwmchip4 # echo 50000000 > pwm0/duty_cycle /sys/devices/platform/soc/40000400.timers/40000400.timers:pwm/pwm/pwmchip4 # echo 1 > pwm0/enable here pwm3 channel 0, as expected, doesn't start because has to be triggered by pwm1 channel 0 configure pwm1 channel 0 to generate a signal with a period of 1s and a duty cycle of 50% /sys/devices/platform/soc/40010000.timers/40010000.timers:pwm/pwm/pwmchip0 # echo 0 > export /sys/devices/platform/soc/40010000.timers/40010000.timers:pwm/pwm/pwmchip0 # echo 1000000000 > pwm0/period /sys/devices/platform/soc/40010000.timers/40010000.timers:pwm/pwm/pwmchip0 # echo 500000000 > pwm0/duty_cycle /sys/devices/platform/soc/40010000.timers/40010000.timers:pwm/pwm/pwmchip0 # echo 1 > pwm0/enable finally pwm1 starts and pwm3 only generates pulse when pwm1 signal is high An other example to use a timer as source of clock for another device. Here timer1 is used a source clock for pwm3: /sys/bus/iio/devices # echo 100000 > trigger0/sampling_frequency /sys/bus/iio/devices # echo "tim1_trgo" > iio\:device1/trigger/current_trigger /sys/bus/iio/devices # echo 'external_clock' > iio\:device1/slave_mode /sys/devices/platform/soc/40000400.timers/40000400.timers:pwm/pwm/pwmchip4 # echo 0 > export /sys/devices/platform/soc/40000400.timers/40000400.timers:pwm/pwm/pwmchip4 # echo 1000000 > pwm0/period /sys/devices/platform/soc/40000400.timers/40000400.timers:pwm/pwm/pwmchip4 # echo 500000 > pwm0/duty_cycle /sys/devices/platform/soc/40000400.timers/40000400.timers:pwm/pwm/pwmchip4 # echo 1 > pwm0/enable Benjamin Gaignard (8): MFD: add bindings for STM32 Timers driver MFD: add STM32 Timers driver PWM: add pwm-stm32 DT bindings PWM: add PWM driver for STM32 plaftorm IIO: add bindings for STM32 timer trigger driver IIO: add STM32 timer trigger driver ARM: dts: stm32: add Timers driver for stm32f429 MCU ARM: dts: stm32: Enable pw1 and pwm3 for stm32f469-disco .../ABI/testing/sysfs-bus-iio-timer-stm32 | 55 +++ .../bindings/iio/timer/stm32-timer-trigger.txt | 23 + .../devicetree/bindings/mfd/stm32-timers.txt | 46 ++ .../devicetree/bindings/pwm/pwm-stm32.txt | 33 ++ arch/arm/boot/dts/stm32f429.dtsi | 275 ++++++++++++ arch/arm/boot/dts/stm32f469-disco.dts | 28 ++ drivers/iio/Kconfig | 2 +- drivers/iio/Makefile | 1 + drivers/iio/timer/Kconfig | 13 + drivers/iio/timer/Makefile | 1 + drivers/iio/timer/stm32-timer-trigger.c | 466 +++++++++++++++++++++ drivers/iio/trigger/Kconfig | 1 - drivers/mfd/Kconfig | 11 + drivers/mfd/Makefile | 2 + drivers/mfd/stm32-timers.c | 80 ++++ drivers/pwm/Kconfig | 9 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-stm32.c | 434 +++++++++++++++++++ include/linux/iio/timer/stm32-timer-trigger.h | 62 +++ include/linux/mfd/stm32-timers.h | 71 ++++ 20 files changed, 1612 insertions(+), 2 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timers.txt create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt create mode 100644 drivers/iio/timer/Kconfig create mode 100644 drivers/iio/timer/Makefile create mode 100644 drivers/iio/timer/stm32-timer-trigger.c create mode 100644 drivers/mfd/stm32-timers.c create mode 100644 drivers/pwm/pwm-stm32.c create mode 100644 include/linux/iio/timer/stm32-timer-trigger.h create mode 100644 include/linux/mfd/stm32-timers.h -- 1.9.1

8 years, 1 month

master build: 0 failures 0 warnings (v4.10-rc1-25-g238d1d0)

by Build bot for Mark Brown

Tree/Branch: master Git describe: v4.10-rc1-25-g238d1d0 Commit: 238d1d0f79 Merge tag 'docs-4.10-rc1-fix' of git://git.lwn.net/linux Build Time: 103 min 22 sec Passed: 10 / 10 (100.00 %) Failed: 0 / 10 ( 0.00 %) Errors: 0 Warnings: 0 Section Mismatches: 0 ------------------------------------------------------------------------------- defconfigs with issues (other than build errors): ------------------------------------------------------------------------------- =============================================================================== Detailed per-defconfig build reports below: ------------------------------------------------------------------------------- Passed with no errors, warnings or mismatches: arm64-allnoconfig arm64-allmodconfig arm-multi_v5_defconfig arm-multi_v7_defconfig x86_64-defconfig arm-allmodconfig arm-allnoconfig x86_64-allnoconfig arm-multi_v4t_defconfig arm64-defconfig close failed in file object destructor: sys.excepthook is missing lost sys.stderr

8 years, 1 month

master build: 0 failures 0 warnings (v4.10-rc1-19-g98473f9)

by Build bot for Mark Brown

Tree/Branch: master Git describe: v4.10-rc1-19-g98473f9 Commit: 98473f9f3f mm/filemap: fix parameters to test_bit() Build Time: 98 min 54 sec Passed: 10 / 10 (100.00 %) Failed: 0 / 10 ( 0.00 %) Errors: 0 Warnings: 0 Section Mismatches: 0 ------------------------------------------------------------------------------- defconfigs with issues (other than build errors): ------------------------------------------------------------------------------- =============================================================================== Detailed per-defconfig build reports below: ------------------------------------------------------------------------------- Passed with no errors, warnings or mismatches: arm64-allnoconfig arm64-allmodconfig arm-multi_v5_defconfig arm-multi_v7_defconfig x86_64-defconfig arm-allmodconfig arm-allnoconfig x86_64-allnoconfig arm-multi_v4t_defconfig arm64-defconfig close failed in file object destructor: sys.excepthook is missing lost sys.stderr

8 years, 1 month

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linaro-kernel December 2016