On 12/03/2012 08:06 PM, Leo Yan wrote:
On 12/03/2012 10:06 AM, Leo Yan wrote:
hi,
i saw Nico's git for the developing the big.LITTLE's cluster power control for MP. In the kernel code. the cluster's first man need enable the CCI's port and snooping for the cluster in non-secure world; In CCI-400's spec, it says need to set the Secure Access Register (0x90008) bit 0 so that we can enable non-secure access to CCI-400 registers.
On fast model, i added the code in boot-wrapper to set bit_0 for CCI's Secure Access Register; but after set this bit, the boot-wrapper code cannot change to hypervisor mode successfully.
On fast model, can we use CCI's secure access register? Current i use the fast model version is: FE000-KT-00002-r7p1-80rel0.tgz, so if it's related with the fast model's version?
Also, could u kindly point out there have boot-swapper's git for reference?
i found the key point is to add "dsb" to insure the register has been modified completely.
Below is the patch for the repo http://git.linaro.org/git-ro/people/pundiramit/boot-wrapper.git:
From: Leo Yan leoy@marvell.com Date: Mon, 3 Dec 2012 19:57:55 +0800 Subject: [PATCH] bootwrapper: enable CCI-400's non-secure access
Signed-off-by: Leo Yan leoy@marvell.com
boot.S | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/boot.S b/boot.S index 60b59a6..eec50d9 100644 --- a/boot.S +++ b/boot.S @@ -80,6 +80,10 @@ start: tst r3, #1 bne 0b
mov r3, #1 @ enable CCI-400'ssecure access
str r3, [r4, #0x8]dsb@ Set up hvbar so hvc comes back here. ldr r0, =vectors mov r7, #0xfffffff0
Here i also have some questions for big.LITTLE's coherency. so far, my working are mainly based on the fast model; but i found on fast model the coherency behavior is very sensitive.
Let's see my experiment on fast model: I used Nico's DCSCB patch for the core run into LPM; sometimes during A15 core want to run into reset state, it need flush its L1 cache to inner sharable PoU, then it's very easily to let A7 get in-consistent data and introduce the kernel panic. But after i commented out A15's flush operations and just let A15 core run into infinite loop, then the system is stable, and the kernel panic issue will dismiss. So i believe A7 core has not get the coherence cache data so that it will introduce the kernel panic.
i know now in this mail list, there have many guys are working for big.LITTLE's mp and IKS and work with fast model; so below are some questions: 1. On Fast model, its cache's coherency and consistent have the same behavior with the real TC2 chip? 2. On Fast model, after the core has set the SMP bit in ACTRL register, then we can say the core's cache for secure and non-secure both will be automatically synced with other core's and cluster, right? 3. On Fast model, if we use the DCSCB, there have extra operations for the cache/TLB maintenance?
Very appreciate your help.
Thx, Leo Yan