On 7 February 2018 at 15:21, Alex Shi alex.shi@linaro.org wrote:
Hi All,
This patchset was asked a bit urgent, since no testing show issue till now, I just pushed the branch to https://git.linaro.org/kernel/speculation-fixes-staging.git
Please go ahead for reviewing. I will rebase the branch if sth need change.
Thanks Alex
$ git shortlog v4.9.79.. AKASHI Takahiro (1): module: extend 'rodata=off' boot cmdline parameter to module mappings
Ard Biesheuvel (1): arm64: alternatives: apply boot time fixups via the linear mapping
Jayachandran C (1): arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs
Laura Abbott (1): mm: Introduce lm_alias
Marc Zyngier (11): arm64: Allow checking of a CPU-local erratum arm64: Move post_ttbr_update_workaround to C code arm64: KVM: Make PSCI_VERSION a fast path arm64: cpu_errata: Allow an erratum to be match for all revisions of a core arm64: KVM: Use per-CPU vector when BP hardening is enabled arm: Add BTB invalidation on switch_mm for Cortex-A9, A12 and A17 arm: KVM: Invalidate BTB on guest exit arm: Add icache invalidation on switch_mm for Cortex-A15 arm: KVM: Invalidate icache on guest exit for Cortex-A15 arm: Invalidate BTB on prefetch abort outside of user mapping on Cortex A8, A9, A12 and A17 arm: Invalidate icache on prefetch abort outside of user mapping on Cortex-A15
Mark Rutland (1): arm64: factor out entry stack manipulation
Suzuki K Poulose (1): arm64: capabilities: Handle duplicate entries for a capability
Will Deacon (21): arm64: mm: Use non-global mappings for kernel space arm64: mm: Move ASID from TTBR0 to TTBR1 arm64: mm: Allocate ASIDs in pairs arm64: mm: Add arm64_kernel_unmapped_at_el0 helper arm64: mm: Invalidate both kernel and user ASIDs when performing TLBI arm64: entry: Add exception trampoline page for exceptions from EL0 arm64: mm: Map entry trampoline into trampoline and kernel page tables arm64: entry: Explicitly pass exception level to kernel_ventry macro arm64: entry: Hook up entry trampoline to exception vectors arm64: tls: Avoid unconditional zeroing of tpidrro_el0 for native tasks arm64: entry: Add fake CPU feature for unmapping the kernel at EL0 arm64: Kconfig: Add CONFIG_UNMAP_KERNEL_AT_EL0 arm64: kaslr: Put kernel vectors address in separate data page arm64: cpufeature: Pass capability structure to ->enable callback arm64: use RET instruction for exiting the trampoline arm64: Kconfig: Reword UNMAP_KERNEL_AT_EL0 kconfig entry arm64: Take into account ID_AA64PFR0_EL1.CSV3 drivers/firmware: Expose psci_get_version through psci_ops structure arm64: cputype: Add missing MIDR values for Cortex-A72 and Cortex-A75 arm64: Add skeleton to harden the branch predictor against aliasing attacks arm64: Implement branch predictor hardening for affected Cortex-A CPUs
Xie XiuQi (1): arm64: entry.S: move SError handling into a C function for future expansion
On 02/07/2018 06:45 AM, Alex Shi wrote:
Hi All,
I found out the previous booting issue which caused by 5ea5306c3235a1 arm64: alternatives: apply boot time fixups via the linear mapping
After picked up this commit both hikey and qemu booted well, w and w/o kvm mode. but kernelci.org didn't give me result yet from yesterday. Anyway it should be fine to send out fore review.
The draft version backport is git://git.linaro.org/kernel/linux-linaro-stable.git lts-v4.9-kpti
The backport based on arm tree: https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git/log/?h=kpti
The following commit aren't included for couple reasons: a, bpf patch included in LTS; b falkor isn't supported in LTS c, PAN isn't supported on LTS;
bpf: prevent out-of-bounds speculation arm64: Implement branch predictor hardening for Falkor arm64: kpti: Fix the interaction between ASID switching and software PAN arm64: mm: Introduce TTBR_ASID_MASK for getting at the ASID in the TTBR perf: arm_spe: Fail device probe when arm64_kernel_unmapped_at_el0() arm64: erratum: Work around Falkor erratum #E1003 in trampoline code arm64: mm: Fix and re-enable ARM64_SW_TTBR0_PAN arm64: mm: Rename post_ttbr0_update_workaround arm64: mm: Remove pre_ttbr0_update_workaround for Falkor erratum #E1003 arm64: mm: Temporarily disable ARM64_SW_TTBR0_PAN
Any comments are appreciated!
I see some issues with the v4.9 based backport.
First of all, S/W PAN is enabled on LSK but not on LTS, and the way it interoperates with KPTI is rather intricate. So perhaps it makes sense to only do the backport for LSK directly, rather than backport it to LTS and merge it in.
Then, there is the handling of to contiguous bit in the page tables. These patches that you backported into the kpti-v4.9-temp branch
arm64: mm: set the contiguous bit for kernel mappings where appropriate arm64: mm: replace 'block_mappings_allowed' with 'page_mappings_only' arm64: mm: BUG on unsupported manipulations of live kernel mappings
(which I wrote myself btw) have been reverted and replaced upstream, and adding those to a stable kernel is likely to cause breakage (i.e, TLB conflict aborts)
So first of all, we need to decide on the scope for this backport (LTS or LSK). Also, whether we want Meltdown mitigations (which are essential for Cortex-A75 but only a nice to have for other cores iff KASLR is enabled).
Mark, do you have any insight into what the members are requesting exactly for v4.9?
Thanks, Ard.