On 12/11/2012 07:10 PM, Leo Yan wrote:
On 12/11/2012 08:47 AM, Leo Yan wrote:
On 12/11/2012 12:45 AM, Nicolas Pitre wrote:
On Mon, 10 Dec 2012, Leo Yan wrote:
Here i also have some questions for big.LITTLE's coherency. so far, my working are mainly based on the fast model; but i found on fast model the coherency behavior is very sensitive.
Let's see my experiment on fast model: I used Nico's DCSCB patch for the core run into LPM;
Which one? If you are using the bL_cluster_pm branch, please note that it is lagging behind current development and probably has some bugs. I'd suggest you look at the tc2_pm_api branch which has support for both TC2 and RTSM.
Nico, thx for response.
Yes, i have used tc2_pm_api's patches. But here may have one difference is i have not directly used your branch, instead i migrate your patches into my own kernel.
Here have some things want to confirm:
- now i use the boot-wrapper is:
http://git.linaro.org/git-ro/arm/models/boot-wrapper.git; because in bootwrapper there have some stuffs related with trustzone related registers, so the boot-wapper's setting is enough for non-secure world, right?
- When we use the DCSCB to release the core, do we need to invalidate
I$/D$/TLB or not? For CA9, we need do that, but for CA7/CA15, we can skip all these operations, right?
- When we launch the fast model, do we need enable the cluster's
configuration for l1_dcache-state_modelled/l1_icache-state_modelled/l2_cache-state_modelled,
because i saw the spec in Cortex_A15_A7_RTSM_UG.pdf, these configurations are related with memory attribute with TLB, but i have not enabled them yet.
- I saw the code in dcscb.c, before the core run into "wfi", it will
flush the l1 cache twice, the code likes below: flush_cache_louis(); -> cpu_proc_fin(); -> flush_cache_louis(); -> clear SMP bit; -> wfi(); so there have some special reason need flush the cache twice? it's caused by fast model?
hi Nico,
Today i also get one VE TC2 board to try your kernel image. With your kernel image, it can only boot up one core (the first CA15 core); i reviewed the code, tc2_pm_api branch have changed to use SPC's bxadd register.
so i just wander i need update the boot monitor; could u kindly tell me there have some modification for the boot sequence? Can i get the code for the updated sequence (such as the boot monitor)?
hi Nico,
I used the modeldebugger to dig into the code for the core's power off, and found some issues in the code.
In the ARM spec, it recommend the flow for core's suspend should look like below: 1. clear SCTLR.C bit; 2. flush l1 cache; 3. clear ACTLR.SMP bit; 4. dsb; 5. wfi;
But in dcscb.c or tc2_pm.c files, when the core what to run into LPM, we use the function *flush_cache_louis()* to flush L1 cache. But in this function it will NOT only flush l1 cache by set/way, but also it will invalidate I cache with below command: mcr p15, 0, r0, c7, c1, 0; From my experiment result, i believe this sentence will introduce unexpected behavior so that later instructions cannot execute properly. so i manually re-write the flush l1 cache flow for core's power off (almostly same with *flush_cache_louis()*, except remove invalidate I cache instruction), then i saw it's much more stable.
i also believe this is a common issue for both fast model and TC2. how about u think for this?
Thx, Leo Yan