Hi Yadwinder,
On Thursday 30 of May 2013 12:25:40 Yadwinder Singh Brar wrote:
Hi Doug,
On Thu, May 30, 2013 at 5:14 AM, Doug Anderson dianders@chromium.org
wrote:
Vikas / Yadwinder,
On Wed, May 29, 2013 at 6:37 AM, Vikas Sajjan vikas.sajjan@linaro.org
wrote:
From: Yadwinder Singh Brar yadi.brar@samsung.com
This patch defines a common rate_table which will contain recommended p, m, s, k values for supported rates that needs to be changed for changing corresponding PLL's rate.
Signed-off-by: Yadwinder Singh Brar yadi.brar@samsung.com
drivers/clk/samsung/clk-exynos4.c | 8 ++++---- drivers/clk/samsung/clk-exynos5250.c | 14 +++++++------- drivers/clk/samsung/clk-pll.c | 14 ++++++++++++-- drivers/clk/samsung/clk-pll.h | 33 +++++++++++++++++++++++++++++++-- 4 files changed, 54 insertions(+), 15 deletions(-)
I also reviewed this in our gerrit https://gerrit.chromium.org/gerrit/#/c/56742/, but I'll summarize here for the list...
struct clk * __init samsung_clk_register_pll35xx(const char *name,
const char *pname, const void __iomem *base)
const char *pname, const void __iomem *base,const struct samsung_pll_rate_table *rate_table,const unsigned int rate_count)Feels like you should document here that rate_table needs to be sorted and the sort order.
sure, we will add comment to sort the table in descending order.
+struct samsung_pll_rate_table {
unsigned int rate;nit: extra space before "int" should be removed.
ok
Also: you can include rate here if you need a convenient place to store it (which sadly means that this structure can't be const). ...but I do like Tomasz's idea of actually calculating it. You can't know it at compile time since the parent rate comes from the device tree.
compatible = "samsung,clock-xxti"; clock-frequency = <24000000>;
Actually this table should contain the recommended values and if we see the user manual, the input(parent) rate is also a part of recommended table of different output rate for a particular PLL for that SoC.
From what I understood in the documentation is that there is a set of
recommended P, M, S (, K) tuples for each PLL and they are not dependent on input frequency - f_in and f_out are provided in the table just for reference to see the relation between output frequency and input frequency.
I think we should ask some H/W engineer about that to make sure and choose the proper implementation, which will work properly for future cases, instead of ending with something that works just with current cases.
Best regards,