Hi all :

the arm bug is described in the previous mail ,please refer to the below mail.

Arm's recommendation is to use "dc civac" instead of "dc cvau" and "dc cvac" instructions, but we can see from current version, in arch/arm64/mm/cache.s, there is a "dc cvau" instruction as below code. So do you plan to patch the bug in LSK later release? thanks

ENTRY(__flush_cache_user_range) dcache_line_size x2, x3 sub x3, x2, #1 bic x4, x0, x3 1: USER(9f, dc cvau, x4 ) // clean D line to PoU add x4, x4, x2 cmp x4, x1 b.lo 1b dsb sy icache_line_size x2, x3 sub x3, x2, #1 bic x4, x0, x3 1: USER(9f, ic ivau, x4 ) // invalidate I line PoU add x4, x4, x2 cmp x4, x1 b.lo 1b 9: // ignore any faulting cache operation dsb sy isb ret ENDPROC(flush_icache_range) ENDPROC(__flush_cache_user_range)

________________________________ 发件人: Panshilin (Peter) 发送时间: 2014年4月25日 14:53 收件人: alex.shi@linaro.org; linaro-kernel@lists.linaro.org 主题: Urgency,thanks: Arm declared the current A53 bugs:one's recommended soution is given below. using DCCIMVAC instead ,don't use DCCMVAC or DCCMVAU

________________________________ 发件人: Panshilin (Peter) 发送时间: 2014年4月25日 13:52 收件人: linaro-kernel@lists.linaro.org 主题: Arm declared the current A53 bugs:one's recommended soution is given below. using DCCIMVAC instead ,don't use DCCMVAC or DCCMVAU

Hi all:

Arm has declared the current A53 bugs:one's recommended soution is given below. has linaro kernel team known and is there patches in current LSK for aarch64?

824069: Cache line might not be marked as clean after a CleanShared snoop Status Affects: Cortex-A53 MPCore Fault Type: Programmer Category B Fault Status: Present in: r0p0, r0p1, r0p2 Open. Description If a Cortex-A53 processor is executing a store or PLDW instruction at the same time as a processor in another cluster is executing a cache maintenance operation to the same address, then this erratum might cause a clean cache line to be incorrectly marked as dirty.

Configurations affected This erratum affects all configurations of the Cortex-A53 processor when it is connected to a coherent interconnect.

Workaround Date of Issue: 11-Mar-2014 ARM Product Errata Notice Document Revision 9.0 ARM-EPM-048405 v9.0 Confidential. Page 24 of 40 © Copyright ARM 2014. All rights reserved. The majority of systems will not need a workaround for this erratum. For any systems that do need a workaround, any software that uses DCCMVAC or DCCMVAU instructions can replace them with DCCIMVAC instructions, or their AArch64 equivalents. Note that this workaround must be applied to all the masters in the system that might generate a snoop into the Cortex-A53 cluster. For example, on a big.LITTLE configuration with one Cortex-A53 processor and one Cortex-A57 processor, the workaround needs to be applied to all software running on the Cortex-A57 processor. On a Cortex-A57 processor it is possible to set bit 44 in the CPUACTLR_EL1 register to automatically convert all DCCMVAC and DCCMVAU instructions into DCCIMVAC instructions.