This patchset implements a clock driver for STM32F42xxx and STM32F43xxx series devices.
There are a few small caveats at the present:
1. Relies on "Add support to STMicroeletronics STM32 family", v8 by Maxime Coquelin: http://thread.gmane.org/gmane.linux.kernel.cross-arch/27569
2. Allocating ~80 clock components appears to fragment memory enough to prevent busybox (.text is ~300K, non-XIP) from running getty. I have to use "init=/bin/sh" to avoid OOM problems.
3. Support for I2S and SAI is not included in this patchset.
Daniel Thompson (3): dt-bindings: Document the STM32F4 clock bindings clk: stm32: Add clock driver for STM32F4[23]xxx devices ARM: dts: stm32f429: Adopt STM32F4 clock driver
.../devicetree/bindings/clock/st,stm32-rcc.txt | 65 ++++ arch/arm/boot/dts/stm32f429.dtsi | 83 ++--- drivers/clk/Makefile | 1 + drivers/clk/clk-stm32f4.c | 365 +++++++++++++++++++++ 4 files changed, 457 insertions(+), 57 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/st,stm32-rcc.txt create mode 100644 drivers/clk/clk-stm32f4.c
-- 2.1.0
This adds documentation of device tree bindings for the clock related portions of the STM32 RCC block.
Signed-off-by: Daniel Thompson daniel.thompson@linaro.org --- .../devicetree/bindings/clock/st,stm32-rcc.txt | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt new file mode 100644 index 0000000..9715d09 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt @@ -0,0 +1,65 @@ +STMicroelectronics STM32 Reset and Clock Controller +=================================================== + +The RCC IP is both a reset and a clock controller. This documentation only +describes the clock part. + +Please also refer to clock-bindings.txt in this directory for common clock +controller binding usage. + +Required properties: +- compatible: Should be "st,stm32f42xx-rcc" +- reg: should be register base and length as documented in the + datasheet +- #clock-cells: 2, device nodes should specify the clock in their "clocks" + property, containing a phandle to the clock device node, an index selecting + between gated clocks and other clocks and an index specifying the clock to + use. + +Example: + + rcc: rcc@40023800 { + #clock-cells = <2> + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; + reg = <0x40023800 0x400>; + }; + +Specifying gated clocks +======================= + +The primary index must be set to 0. + +The secondary index is the bit number within the RCC register bank, starting +from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30). + +It is calculated as: index = register_offset / 4 * 32 + bit_offset. +Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31). + +Example: + + /* Gated clock, AHB1 bit 0 (GPIOA) */ + ... { + clocks = <&rcc 0 0> + }; + + /* Gated clock, AHB2 bit 4 (GPIOA) */ + ... { + clocks = <&rcc 0 36> + }; + +Specifying other clocks +======================= + +The primary index must be set to 1. + +The secondary index is bound with the following magic numbers: + + 0 SYSTICK + 1 FCLK + +Example: + + /* Misc clock, FCLK */ + ... { + clocks = <&rcc 1 1> + };
The driver supports decoding and statically modelling PLL state (i.e. we inherit state from bootloader) and provides support for all peripherals that support simple one-bit gated clocks. The covers all peripherals whose clocks come from the AHB, APB1 or APB2 buses.
It has been tested (for non-regression only) on an STM32F429I-Discovery boards. The clock counts for TIM2, USART1 and SYSTICK are all set correctly and time and the wall clock looks OK when checked with a stopwatch.
Signed-off-by: Daniel Thompson daniel.thompson@linaro.org --- drivers/clk/Makefile | 1 + drivers/clk/clk-stm32f4.c | 365 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 366 insertions(+) create mode 100644 drivers/clk/clk-stm32f4.c
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 3d00c25..2c5433b 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o +obj-$(CONFIG_ARCH_STM32) += clk-stm32f4.o obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o obj-$(CONFIG_ARCH_U300) += clk-u300.o obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c new file mode 100644 index 0000000..e494ccb --- /dev/null +++ b/drivers/clk/clk-stm32f4.c @@ -0,0 +1,365 @@ +/* + * Author: Daniel Thompson daniel.thompson@linaro.org + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see http://www.gnu.org/licenses/. + */ + +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/clk-provider.h> +#include <linux/spinlock.h> +#include <linux/of.h> +#include <linux/of_address.h> + +#include <linux/debugfs.h> + +#define STM32F4_RCC_PLLCFGR 0x04 +#define STM32F4_RCC_CFGR 0x08 +#define STM32F4_RCC_AHB1ENR 0x30 +#define STM32F4_RCC_AHB2ENR 0x34 +#define STM32F4_RCC_AHB3ENR 0x38 +#define STM32F4_RCC_APB1ENR 0x40 +#define STM32F4_RCC_APB2ENR 0x44 + +struct stm32f4_gate_data { + u8 offset; + u8 bit_idx; + const char *name; + const char *parent_name; + unsigned long flags; +}; + +static const struct stm32f4_gate_data stm32f4_gates[] __initconst = { + { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 20, "ccmdatam", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" }, + + { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" }, + { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" }, + { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" }, + { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" }, + { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" }, + + { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div", + CLK_IGNORE_UNUSED }, + + { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 17, "uart2", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 18, "uart3", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 19, "uart4", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 20, "uart5", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 21, "i2c1", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 22, "i2c2", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 23, "i2c3", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 30, "uart7", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 31, "uart8", "apb1_div" }, + + { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" }, + { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" }, + { STM32F4_RCC_APB2ENR, 4, "usart1", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 5, "usart6", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 11, "sdio", "pll48" }, + { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" }, + { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" }, + { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" }, + { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" }, +}; + +/* + * MAX_CLKS is the maximum value in the enumeration below plus the combined + * hweight of stm32f42xx_gate_map (plus one). + */ +#define MAX_CLKS 74 + +enum { SYSTICK, FCLK }; + +/* + * This bitmask tells us which bit offsets (0..192) on STM32F4[23]xxx + * have gate bits associated with them. Its combined hweight is 71. + */ +static const u64 stm32f42xx_gate_map[] = { 0x000000f17ef417ff, + 0x0000000000000001, + 0x04777f33f6fec9ff }; + +static struct clk *clks[MAX_CLKS]; +static DEFINE_SPINLOCK(stm32f4_clk_lock); +static void __iomem *base; + +/* + * "Multiplier" device for APBx clocks. + * + * The APBx dividers are power-of-two dividers and, if *not* running in 1:1 + * mode, they also tap out the one of the low order state bits to run the + * timers. ST datasheets represent this feature as a (conditional) clock + * multiplier. + */ +struct clk_apb_mul { + struct clk_hw hw; + u8 bit_idx; +}; + +#define to_clk_apb_mul(_hw) container_of(_hw, struct clk_apb_mul, hw) + +static unsigned long clk_apb_mul_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_apb_mul *am = to_clk_apb_mul(hw); + + if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) + return parent_rate * 2; + + return parent_rate; +} + +static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_apb_mul *am = to_clk_apb_mul(hw); + unsigned long mult = 1; + + if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) + mult *= 2; + + if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) { + unsigned long best_parent = rate / mult; + + *prate = + __clk_round_rate(__clk_get_parent(hw->clk), best_parent); + } + + return *prate * mult; +} + +static int clk_apb_mul_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + return 0; +} + +static struct clk_ops clk_apb_mul_factor_ops = { + .round_rate = clk_apb_mul_round_rate, + .set_rate = clk_apb_mul_set_rate, + .recalc_rate = clk_apb_mul_recalc_rate, +}; + +struct clk *clk_register_apb_mul(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + u8 bit_idx) +{ + struct clk_apb_mul *am; + struct clk_init_data init; + struct clk *clk; + + am = kzalloc(sizeof(*am), GFP_KERNEL); + if (!am) + return ERR_PTR(-ENOMEM); + + am->bit_idx = bit_idx; + am->hw.init = &init; + + init.name = name; + init.ops = &clk_apb_mul_factor_ops; + init.flags = flags | CLK_IS_BASIC; + init.parent_names = &parent_name; + init.num_parents = 1; + + clk = clk_register(dev, &am->hw); + + if (IS_ERR(clk)) + kfree(am); + + return clk; +} + +/* + * Decode current PLL state and (statically) model the state we inherit from + * the bootloader. + */ +static void stm32f4_rcc_register_pll(const char *hse_clk, const char *hsi_clk) +{ + unsigned long pllcfgr = readl(base + STM32F4_RCC_PLLCFGR); + + unsigned long pllm = pllcfgr & 0x3f; + unsigned long plln = (pllcfgr >> 6) & 0x1ff; + unsigned long pllp = BIT(((pllcfgr >> 16) & 3) + 1); + const char *pllsrc = pllcfgr & BIT(22) ? hse_clk : hsi_clk; + unsigned long pllq = (pllcfgr >> 24) & 0xf; + + clk_register_fixed_factor(NULL, "vco", pllsrc, 0, plln, pllm); + clk_register_fixed_factor(NULL, "pll", "vco", 0, 1, pllp); + clk_register_fixed_factor(NULL, "pll48", "vco", 0, 1, pllq); +} + +/* + * Converts the primary and secondary indices (as they appear in DT) to an + * offset into our struct clock array. + */ +static unsigned int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary) +{ + u64 table[ARRAY_SIZE(stm32f42xx_gate_map)]; + + if (primary == 1) { + BUG_ON(secondary > FCLK); + return secondary; + } + + memcpy(table, stm32f42xx_gate_map, sizeof(table)); + + /* only bits set in table can be used as indices */ + BUG_ON(secondary > 8 * sizeof(table) || + 0 == (table[BIT_ULL_WORD(secondary)] & BIT_ULL_MASK(secondary))); + + /* mask out bits above our current index */ + table[BIT_ULL_WORD(secondary)] &= + GENMASK_ULL(secondary % BITS_PER_LONG_LONG, 0); + + return FCLK + hweight64(table[0]) + + (BIT_ULL_WORD(secondary) >= 1 ? hweight64(table[1]) : 0) + + (BIT_ULL_WORD(secondary) >= 2 ? hweight64(table[2]) : 0); +} + +struct clk *stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data) +{ + return clks[stm32f4_rcc_lookup_clk_idx(clkspec->args[0], + clkspec->args[1])]; +} + +static const char __initdata *sys_parents[] = { "hsi", NULL, "pll" }; + +static struct clk_div_table ahb_div_table[] = { + { 0x0, 1 }, { 0x1, 1 }, { 0x2, 1 }, { 0x3, 1 }, + { 0x4, 1 }, { 0x5, 1 }, { 0x6, 1 }, { 0x7, 1 }, + { 0x8, 2 }, { 0x9, 4 }, { 0xa, 8 }, { 0xb, 16 }, + { 0xc, 64 }, { 0xd, 128 }, { 0xe, 256 }, { 0xf, 512 }, + { 0 }, +}; + +static struct clk_div_table apb_div_table[] = { + { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, + { 4, 2 }, { 5, 4 }, { 6, 8 }, { 7, 16 }, + { 0 }, +}; + +static void __init stm32f4_rcc_init(struct device_node *np) +{ + struct clk *clk; + const char *hse_clk; + int n; + + base = of_iomap(np, 0); + if (!base) { + pr_err("%s: unable to map resource", np->name); + return; + } + + hse_clk = of_clk_get_parent_name(np, 0); + + clk_register_fixed_rate_with_accuracy(NULL, "hsi", NULL, 0, + 16000000, 160000); + stm32f4_rcc_register_pll(hse_clk, "hsi"); + + sys_parents[1] = hse_clk; + clk_register_mux_table( + NULL, "sys", sys_parents, ARRAY_SIZE(sys_parents), 0, + base + STM32F4_RCC_CFGR, 0, 3, 0, NULL, &stm32f4_clk_lock); + + clk_register_divider_table(NULL, "ahb_div", "sys", + CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR, + 4, 4, 0, ahb_div_table, &stm32f4_clk_lock); + + clk_register_divider_table(NULL, "apb1_div", "ahb_div", + CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR, + 10, 3, 0, apb_div_table, &stm32f4_clk_lock); + clk_register_apb_mul(NULL, "apb1_mul", "apb1_div", + CLK_SET_RATE_PARENT, 12); + + clk_register_divider_table(NULL, "apb2_div", "ahb_div", + CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR, + 13, 3, 0, apb_div_table, &stm32f4_clk_lock); + clk_register_apb_mul(NULL, "apb2_mul", "apb2_div", + CLK_SET_RATE_PARENT, 15); + + clks[SYSTICK] = clk_register_fixed_factor(NULL, "systick", "ahb_div", + 0, 1, 8); + clks[FCLK] = clk_register_fixed_factor(NULL, "fclk", "ahb_div", + 0, 1, 1); + + for (n = 0; n < ARRAY_SIZE(stm32f4_gates); n++) { + const struct stm32f4_gate_data *gd = &stm32f4_gates[n]; + unsigned int secondary = + 8 * (gd->offset - STM32F4_RCC_AHB1ENR) + gd->bit_idx; + unsigned int idx = stm32f4_rcc_lookup_clk_idx(0, secondary); + + clks[idx] = clk_register_gate( + NULL, gd->name, gd->parent_name, gd->flags, + base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock); + + if (IS_ERR(clks[n])) { + pr_err("%s: Unable to register leaf clock %s\n", + np->full_name, gd->name); + goto fail; + } + } + + of_clk_add_provider(np, stm32f4_rcc_lookup_clk, NULL); + return; +fail: + iounmap(base); +} +CLK_OF_DECLARE(stm32f4_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
On 05/22, Daniel Thompson wrote:
+#include <linux/clk.h>
Are you using this include?
+#include <linux/clkdev.h>
Are you using this include?
+#include <linux/err.h> +#include <linux/io.h> +#include <linux/clk-provider.h> +#include <linux/spinlock.h> +#include <linux/of.h> +#include <linux/of_address.h>
+#include <linux/debugfs.h>
Are you using this include?
+static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)+{
- struct clk_apb_mul *am = to_clk_apb_mul(hw);
- unsigned long mult = 1;
- if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
mult *= 2;
Isn't this the same as mult = 2? I guess we could rely on the compiler to figure out this one.
- if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
unsigned long best_parent = rate / mult;*prate =__clk_round_rate(__clk_get_parent(hw->clk), best_parent);- }
- return *prate * mult;
+}
+static int clk_apb_mul_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)+{
Why don't we need to do anything here?
- return 0;
+}
+static struct clk_ops clk_apb_mul_factor_ops = {
const?
- .round_rate = clk_apb_mul_round_rate,
- .set_rate = clk_apb_mul_set_rate,
- .recalc_rate = clk_apb_mul_recalc_rate,
+};
+struct clk *clk_register_apb_mul(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,u8 bit_idx)+{
- struct clk_apb_mul *am;
- struct clk_init_data init;
- struct clk *clk;
- am = kzalloc(sizeof(*am), GFP_KERNEL);
- if (!am)
return ERR_PTR(-ENOMEM);- am->bit_idx = bit_idx;
- am->hw.init = &init;
- init.name = name;
- init.ops = &clk_apb_mul_factor_ops;
- init.flags = flags | CLK_IS_BASIC;
Is it basic?
- init.parent_names = &parent_name;
- init.num_parents = 1;
- clk = clk_register(dev, &am->hw);
- if (IS_ERR(clk))
kfree(am);- return clk;
+}
+static const char __initdata *sys_parents[] = { "hsi", NULL, "pll" };
__initdata goes after the []
On 04/06/15 23:07, Stephen Boyd wrote:
On 05/22, Daniel Thompson wrote:
+#include <linux/clk.h>
Are you using this include?
+#include <linux/clkdev.h>
Are you using this include?
Not very much?
Turns out I was relying on these to get kzalloc() defined but there are better headers for me to use for that!
+#include <linux/err.h> +#include <linux/io.h> +#include <linux/clk-provider.h> +#include <linux/spinlock.h> +#include <linux/of.h> +#include <linux/of_address.h>
+#include <linux/debugfs.h>
Are you using this include?
No (this is already gone in v2).
+static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)+{
- struct clk_apb_mul *am = to_clk_apb_mul(hw);
- unsigned long mult = 1;
- if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
mult *= 2;Isn't this the same as mult = 2? I guess we could rely on the compiler to figure out this one.
I'll fix this.
- if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
unsigned long best_parent = rate / mult;*prate =__clk_round_rate(__clk_get_parent(hw->clk), best_parent);- }
- return *prate * mult;
+}
+static int clk_apb_mul_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)+{
Why don't we need to do anything here?
This clock cannot change its own rate. It is very nearly a fixed factor clock but with the additional quirk that the "fixed" factor changes depending upon the rate of the parent clock.
This is the same implementation as clk-fixed-factor. I concluded that it returns success because round rate should always result in the set rate for this clock being a nop.
- return 0;
+}
+static struct clk_ops clk_apb_mul_factor_ops = {
const?
Makes sense...
You want a patch for clk-fixed-factor too?
+struct clk *clk_register_apb_mul(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,u8 bit_idx)+{
- struct clk_apb_mul *am;
- struct clk_init_data init;
- struct clk *clk;
- am = kzalloc(sizeof(*am), GFP_KERNEL);
- if (!am)
return ERR_PTR(-ENOMEM);- am->bit_idx = bit_idx;
- am->hw.init = &init;
- init.name = name;
- init.ops = &clk_apb_mul_factor_ops;
- init.flags = flags | CLK_IS_BASIC;
Is it basic?
Tough question.
The absence of this flag appears grants arch code permission to use secret backdoors to do "weird stuff" but making special assumptions about the type of the clock. This clock keeps its implementation private so noone outside the compilation unit can usefully cast it.
However, it also looks like only omap2 is the only platform that makes these special assumptions so when this code is run on STM32 there is nothing to actually consume the CLK_IS_BASIC flag at runtime.
In other words the flag is useless but, I think, also correctly applied.
I'd be happy to remove it if anyone disagrees with the guesswork above.
Alternatively, I could write a patch to *invert* CLK_IS_BASIC and rename it CLK_CASTABLE on the grounds that only the people doing "weird stuff" should have to care about this flag at all. Any interest in that?
- init.parent_names = &parent_name;
- init.num_parents = 1;
- clk = clk_register(dev, &am->hw);
- if (IS_ERR(clk))
kfree(am);- return clk;
+}
+static const char __initdata *sys_parents[] = { "hsi", NULL, "pll" };
__initdata goes after the []
Thanks. I'll fix this.
On 06/05, Daniel Thompson wrote:
On 04/06/15 23:07, Stephen Boyd wrote:
On 05/22, Daniel Thompson wrote:
+#include <linux/clkdev.h>
Are you using this include?
Not very much?
Turns out I was relying on these to get kzalloc() defined but there are better headers for me to use for that!
Hah ok. We should delete some of those arch specific clkdev.h files...
+#include <linux/err.h> +#include <linux/io.h> +#include <linux/clk-provider.h> +#include <linux/spinlock.h> +#include <linux/of.h> +#include <linux/of_address.h>
+#include <linux/debugfs.h>
Are you using this include?
No (this is already gone in v2).
Oh hrm.. I must have missed v2.
- if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
unsigned long best_parent = rate / mult;*prate =__clk_round_rate(__clk_get_parent(hw->clk), best_parent);- }
- return *prate * mult;
+}
+static int clk_apb_mul_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)+{
Why don't we need to do anything here?
This clock cannot change its own rate. It is very nearly a fixed factor clock but with the additional quirk that the "fixed" factor changes depending upon the rate of the parent clock.
This is the same implementation as clk-fixed-factor. I concluded that it returns success because round rate should always result in the set rate for this clock being a nop.
Ok. A comment here would be helpful in the future. We probably ought to have a comment in clk-fixed-factor as well.
- return 0;
+}
+static struct clk_ops clk_apb_mul_factor_ops = {
const?
Makes sense...
You want a patch for clk-fixed-factor too?
Sure.
+struct clk *clk_register_apb_mul(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,u8 bit_idx)+{
- struct clk_apb_mul *am;
- struct clk_init_data init;
- struct clk *clk;
- am = kzalloc(sizeof(*am), GFP_KERNEL);
- if (!am)
return ERR_PTR(-ENOMEM);- am->bit_idx = bit_idx;
- am->hw.init = &init;
- init.name = name;
- init.ops = &clk_apb_mul_factor_ops;
- init.flags = flags | CLK_IS_BASIC;
Is it basic?
Tough question.
The absence of this flag appears grants arch code permission to use secret backdoors to do "weird stuff" but making special assumptions about the type of the clock. This clock keeps its implementation private so noone outside the compilation unit can usefully cast it.
However, it also looks like only omap2 is the only platform that makes these special assumptions so when this code is run on STM32 there is nothing to actually consume the CLK_IS_BASIC flag at runtime.
In other words the flag is useless but, I think, also correctly applied.
I'd be happy to remove it if anyone disagrees with the guesswork above.
Alternatively, I could write a patch to *invert* CLK_IS_BASIC and rename it CLK_CASTABLE on the grounds that only the people doing "weird stuff" should have to care about this flag at all. Any interest in that?
No I think we should delete CLK_IS_BASIC. So please remove it unless you actually need it.
New bindings and driver have been created for STM32F42xxx series parts. This patch integrates these changes.
Note: Earlier device tree blobs (those without st,stm32f42xxx compatibles for the rcc) could still be used to boot basic systems. Such systems rely on the bootloader to configure the clocks for vital periperhals.
Signed-off-by: Daniel Thompson daniel.thompson@linaro.org --- arch/arm/boot/dts/stm32f429.dtsi | 83 +++++++++++++--------------------------- 1 file changed, 26 insertions(+), 57 deletions(-)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index aa3b3e3..6da8d7f 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -50,48 +50,10 @@
/ { clocks { - clk_sysclk: clk-sysclk { + clk_hse: clk-hse { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <168000000>; - }; - - clk_hclk: clk-hclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <168000000>; - }; - - clk_pclk1: clk-pclk1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <42000000>; - }; - - clk_pclk2: clk-pclk2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <84000000>; - }; - - clk_pmtr1: clk-pmtr1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <84000000>; - }; - - clk_pmtr2: clk-pmtr2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <168000000>; - }; - - clk_systick: clk-systick { - compatible = "fixed-factor-clock"; - clocks = <&clk_hclk>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; + clock-frequency = <8000000>; }; };
@@ -101,7 +63,7 @@ reg = <0x40000000 0x400>; interrupts = <28>; resets = <&rcc STM32F4_APB1_RESET(TIM2)>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 128>; status = "disabled"; };
@@ -110,7 +72,7 @@ reg = <0x40000400 0x400>; interrupts = <29>; resets = <&rcc STM32F4_APB1_RESET(TIM3)>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 129>; status = "disabled"; };
@@ -119,7 +81,7 @@ reg = <0x40000800 0x400>; interrupts = <30>; resets = <&rcc STM32F4_APB1_RESET(TIM4)>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 130>; status = "disabled"; };
@@ -128,7 +90,7 @@ reg = <0x40000c00 0x400>; interrupts = <50>; resets = <&rcc STM32F4_APB1_RESET(TIM5)>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 131>; status = "disabled"; };
@@ -137,7 +99,7 @@ reg = <0x40001000 0x400>; interrupts = <54>; resets = <&rcc STM32F4_APB1_RESET(TIM6)>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 132>; status = "disabled"; };
@@ -146,7 +108,7 @@ reg = <0x40001400 0x400>; interrupts = <55>; resets = <&rcc STM32F4_APB1_RESET(TIM7)>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 133>; status = "disabled"; };
@@ -154,7 +116,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; interrupts = <38>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 145>; status = "disabled"; };
@@ -162,7 +124,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; interrupts = <39>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 146>; status = "disabled"; };
@@ -170,7 +132,7 @@ compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; interrupts = <52>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 147>; status = "disabled"; };
@@ -178,7 +140,7 @@ compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; interrupts = <53>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 148>; status = "disabled"; };
@@ -186,7 +148,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40007800 0x400>; interrupts = <82>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 158>; status = "disabled"; };
@@ -194,7 +156,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40007c00 0x400>; interrupts = <83>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 159>; status = "disabled"; };
@@ -202,7 +164,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011000 0x400>; interrupts = <37>; - clocks = <&clk_pclk2>; + clocks = <&rcc 0 164>; status = "disabled"; };
@@ -210,19 +172,26 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011400 0x400>; interrupts = <71>; - clocks = <&clk_pclk2>; + clocks = <&rcc 0 165>; status = "disabled"; };
rcc: rcc@40023810 { #reset-cells = <1>; - compatible = "st,stm32-rcc"; + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; reg = <0x40023800 0x400>; - }; + clocks = <&clk_hse>; + #clock-cells = <2>; + }; +#if 0 + of_property_read_string_index(dev, "reg-names", "gates"); + index = of_property_read_string_index(dev, "reg-names", "gates"); + of_iomap(np, index); +#endif }; };
&systick { - clocks = <&clk_systick>; + clocks = <&rcc 1 0>; status = "okay"; };
Hi Daniel,
2015-05-22 22:41 GMT+02:00 Daniel Thompson daniel.thompson@linaro.org:
- Allocating ~80 clock components appears to fragment memory enough to prevent busybox (.text is ~300K, non-XIP) from running getty. I have to use "init=/bin/sh" to avoid OOM problems.
Yes, I reproduced the same issue while testing your work.
Could you try with: CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
It solves (hides) the problem on my side. You can eventually setting it once booted to 1 via procfs.
Kind regards, Maxime
On 26/05/15 17:41, Maxime Coquelin wrote:
- Allocating ~80 clock components appears to fragment memory enough to prevent busybox (.text is ~300K, non-XIP) from running getty. I have to use "init=/bin/sh" to avoid OOM problems.
Yes, I reproduced the same issue while testing your work.
Could you try with: CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
It solves (hides) the problem on my side. You can eventually setting it once booted to 1 via procfs.
That works for me too. Thanks.
Incidentally switching to SLOB also reduced the problem for me. It was OK whilst I had ~20 clocks (and debugfs) but not enough for me to run with all the clocks registered.
Daniel.
This patchset implements a clock driver for STM32F42xxx and STM32F43xxx series devices. It supports decoding the state configured by the bootloader (PLL, clock select, bus dividers) and all the gates clocks. It does not currently support the I2S and SAI PLLs.
Relies on "Add support to STMicroeletronics STM32 family" v9 by Maxime Coquelin: http://thread.gmane.org/gmane.linux.kernel/1961049 .
For completeness I've also included a small config patch I needed to get my board to boot once I had rebased. I suspect Maxime may have the same patch tucked away somewhere :-).
v2: * Move the HSE crystal frequency to stm32f429-disco.dts (was prevsiously in stm32f429.dtsi) * Fixed compiler warning that I overlooked the first time round. * Removed dead code in the .dtsi file. * Rebased on linux-next+v9 from Maxime.
Daniel Thompson (4): ARM: stm32: Enable clock source dt-bindings: Document the STM32F4 clock bindings clk: stm32: Add clock driver for STM32F4[23]xxx devices ARM: dts: stm32f429: Adopt STM32F4 clock driver
.../devicetree/bindings/clock/st,stm32-rcc.txt | 65 ++++ arch/arm/Kconfig | 1 + arch/arm/boot/dts/stm32f429-disco.dts | 4 + arch/arm/boot/dts/stm32f429.dtsi | 79 ++--- drivers/clk/Makefile | 1 + drivers/clk/clk-stm32f4.c | 364 +++++++++++++++++++++ 6 files changed, 459 insertions(+), 55 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/st,stm32-rcc.txt create mode 100644 drivers/clk/clk-stm32f4.c
-- 2.1.0
Currently STM32F4 systems do not complete the boot process. This is trivially fixed by enabling a suitable clock source when ARCH_STM32 is set.
Signed-off-by: Daniel Thompson daniel.thompson@linaro.org --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e717642..462c1ee 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -978,6 +978,7 @@ config ARCH_STM32 depends on ARM_SINGLE_ARMV7M select ARCH_HAS_RESET_CONTROLLER select ARMV7M_SYSTICK + select CLKSRC_STM32 select RESET_CONTROLLER help Support for STMicroelectronics STM32 processors.
This adds documentation of device tree bindings for the clock related portions of the STM32 RCC block.
Signed-off-by: Daniel Thompson daniel.thompson@linaro.org --- .../devicetree/bindings/clock/st,stm32-rcc.txt | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt new file mode 100644 index 0000000..9715d09 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt @@ -0,0 +1,65 @@ +STMicroelectronics STM32 Reset and Clock Controller +=================================================== + +The RCC IP is both a reset and a clock controller. This documentation only +describes the clock part. + +Please also refer to clock-bindings.txt in this directory for common clock +controller binding usage. + +Required properties: +- compatible: Should be "st,stm32f42xx-rcc" +- reg: should be register base and length as documented in the + datasheet +- #clock-cells: 2, device nodes should specify the clock in their "clocks" + property, containing a phandle to the clock device node, an index selecting + between gated clocks and other clocks and an index specifying the clock to + use. + +Example: + + rcc: rcc@40023800 { + #clock-cells = <2> + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; + reg = <0x40023800 0x400>; + }; + +Specifying gated clocks +======================= + +The primary index must be set to 0. + +The secondary index is the bit number within the RCC register bank, starting +from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30). + +It is calculated as: index = register_offset / 4 * 32 + bit_offset. +Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31). + +Example: + + /* Gated clock, AHB1 bit 0 (GPIOA) */ + ... { + clocks = <&rcc 0 0> + }; + + /* Gated clock, AHB2 bit 4 (GPIOA) */ + ... { + clocks = <&rcc 0 36> + }; + +Specifying other clocks +======================= + +The primary index must be set to 1. + +The secondary index is bound with the following magic numbers: + + 0 SYSTICK + 1 FCLK + +Example: + + /* Misc clock, FCLK */ + ... { + clocks = <&rcc 1 1> + };
HI Daniel,
On 05/30/2015 09:54 AM, Daniel Thompson wrote:
This adds documentation of device tree bindings for the clock related portions of the STM32 RCC block.
Signed-off-by: Daniel Thompson daniel.thompson@linaro.org
.../devicetree/bindings/clock/st,stm32-rcc.txt | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt new file mode 100644 index 0000000..9715d09 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt @@ -0,0 +1,65 @@ +STMicroelectronics STM32 Reset and Clock Controller +===================================================
+The RCC IP is both a reset and a clock controller. This documentation only +describes the clock part.
+Please also refer to clock-bindings.txt in this directory for common clock +controller binding usage.
+Required properties: +- compatible: Should be "st,stm32f42xx-rcc" +- reg: should be register base and length as documented in the
- datasheet
+- #clock-cells: 2, device nodes should specify the clock in their "clocks"
- property, containing a phandle to the clock device node, an index selecting
- between gated clocks and other clocks and an index specifying the clock to
- use.
+Example:
- rcc: rcc@40023800 {
#clock-cells = <2>compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";reg = <0x40023800 0x400>;- };
+Specifying gated clocks +=======================
+The primary index must be set to 0.
+The secondary index is the bit number within the RCC register bank, starting +from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
+It is calculated as: index = register_offset / 4 * 32 + bit_offset. +Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).
+Example:
- /* Gated clock, AHB1 bit 0 (GPIOA) */
- ... {
clocks = <&rcc 0 0>- };
- /* Gated clock, AHB2 bit 4 (GPIOA) */
s/GPIOA/CRYP/
- ... {
clocks = <&rcc 0 36>- };
+Specifying other clocks +=======================
+The primary index must be set to 1.
+The secondary index is bound with the following magic numbers:
- 0 SYSTICK
- 1 FCLK
How do you plan to handle the SAI & I2S clocks? By adding index 3?
On 30/05/15 10:21, Maxime Coquelin wrote:
HI Daniel,
On 05/30/2015 09:54 AM, Daniel Thompson wrote:
This adds documentation of device tree bindings for the clock related portions of the STM32 RCC block.
Signed-off-by: Daniel Thompson daniel.thompson@linaro.org
.../devicetree/bindings/clock/st,stm32-rcc.txt | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+)
<snip> +Example: + + /* Gated clock, AHB1 bit 0 (GPIOA) */ + ... { + clocks = <&rcc 0 0> + }; + + /* Gated clock, AHB2 bit 4 (GPIOA) */
s/GPIOA/CRYP/
Oops! Will fix.
- ... {
clocks = <&rcc 0 36>- };
+Specifying other clocks +=======================
+The primary index must be set to 1.
+The secondary index is bound with the following magic numbers:
- 0 SYSTICK
- 1 FCLK
How do you plan to handle the SAI & I2S clocks? By adding index 3?
Pretty much. Tentatively I'm thinking of:
2 I2S clocks 3 SAI1_A clock 4 SAI1_B clock 5 LCD-TFT clock
Note: Sort order is based on the vertical ordering in the clock tree diagram in the data sheet.
Only reason not to include these in the bindings immediately is that I wanted to check how/if these clocks are gated. The clock tree diagram shows them having individual clock gates so before proposing them using magic numbers I wanted to double check if these values can be identified at gates clocks.
Daniel.
The driver supports decoding and statically modelling PLL state (i.e. we inherit state from bootloader) and provides support for all peripherals that support simple one-bit gated clocks. The covers all peripherals whose clocks come from the AHB, APB1 or APB2 buses.
It has been tested (for non-regression only) on an STM32F429I-Discovery boards. The clock counts for TIM2, USART1 and SYSTICK are all set correctly and time and the wall clock looks OK when checked with a stopwatch.
Signed-off-by: Daniel Thompson daniel.thompson@linaro.org --- drivers/clk/Makefile | 1 + drivers/clk/clk-stm32f4.c | 364 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 365 insertions(+) create mode 100644 drivers/clk/clk-stm32f4.c
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index d2d5e6c..79cd0d4 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o +obj-$(CONFIG_ARCH_STM32) += clk-stm32f4.o obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o obj-$(CONFIG_ARCH_U300) += clk-u300.o obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c new file mode 100644 index 0000000..68f9962 --- /dev/null +++ b/drivers/clk/clk-stm32f4.c @@ -0,0 +1,364 @@ +/* + * Author: Daniel Thompson daniel.thompson@linaro.org + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see http://www.gnu.org/licenses/. + */ + +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/clk-provider.h> +#include <linux/spinlock.h> +#include <linux/of.h> +#include <linux/of_address.h> + +#include <linux/debugfs.h> + +#define STM32F4_RCC_PLLCFGR 0x04 +#define STM32F4_RCC_CFGR 0x08 +#define STM32F4_RCC_AHB1ENR 0x30 +#define STM32F4_RCC_AHB2ENR 0x34 +#define STM32F4_RCC_AHB3ENR 0x38 +#define STM32F4_RCC_APB1ENR 0x40 +#define STM32F4_RCC_APB2ENR 0x44 + +struct stm32f4_gate_data { + u8 offset; + u8 bit_idx; + const char *name; + const char *parent_name; + unsigned long flags; +}; + +static const struct stm32f4_gate_data stm32f4_gates[] __initconst = { + { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 20, "ccmdatam", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" }, + + { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" }, + { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" }, + { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" }, + { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" }, + { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" }, + + { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div", + CLK_IGNORE_UNUSED }, + + { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 17, "uart2", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 18, "uart3", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 19, "uart4", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 20, "uart5", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 21, "i2c1", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 22, "i2c2", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 23, "i2c3", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 30, "uart7", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 31, "uart8", "apb1_div" }, + + { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" }, + { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" }, + { STM32F4_RCC_APB2ENR, 4, "usart1", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 5, "usart6", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 11, "sdio", "pll48" }, + { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" }, + { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" }, + { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" }, + { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" }, +}; + +/* + * MAX_CLKS is the maximum value in the enumeration below plus the combined + * hweight of stm32f42xx_gate_map (plus one). + */ +#define MAX_CLKS 74 + +enum { SYSTICK, FCLK }; + +/* + * This bitmask tells us which bit offsets (0..192) on STM32F4[23]xxx + * have gate bits associated with them. Its combined hweight is 71. + */ +static const u64 stm32f42xx_gate_map[] = { 0x000000f17ef417ff, + 0x0000000000000001, + 0x04777f33f6fec9ff }; + +static struct clk *clks[MAX_CLKS]; +static DEFINE_SPINLOCK(stm32f4_clk_lock); +static void __iomem *base; + +/* + * "Multiplier" device for APBx clocks. + * + * The APBx dividers are power-of-two dividers and, if *not* running in 1:1 + * mode, they also tap out the one of the low order state bits to run the + * timers. ST datasheets represent this feature as a (conditional) clock + * multiplier. + */ +struct clk_apb_mul { + struct clk_hw hw; + u8 bit_idx; +}; + +#define to_clk_apb_mul(_hw) container_of(_hw, struct clk_apb_mul, hw) + +static unsigned long clk_apb_mul_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_apb_mul *am = to_clk_apb_mul(hw); + + if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) + return parent_rate * 2; + + return parent_rate; +} + +static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_apb_mul *am = to_clk_apb_mul(hw); + unsigned long mult = 1; + + if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) + mult *= 2; + + if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) { + unsigned long best_parent = rate / mult; + + *prate = + __clk_round_rate(__clk_get_parent(hw->clk), best_parent); + } + + return *prate * mult; +} + +static int clk_apb_mul_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + return 0; +} + +static struct clk_ops clk_apb_mul_factor_ops = { + .round_rate = clk_apb_mul_round_rate, + .set_rate = clk_apb_mul_set_rate, + .recalc_rate = clk_apb_mul_recalc_rate, +}; + +struct clk *clk_register_apb_mul(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + u8 bit_idx) +{ + struct clk_apb_mul *am; + struct clk_init_data init; + struct clk *clk; + + am = kzalloc(sizeof(*am), GFP_KERNEL); + if (!am) + return ERR_PTR(-ENOMEM); + + am->bit_idx = bit_idx; + am->hw.init = &init; + + init.name = name; + init.ops = &clk_apb_mul_factor_ops; + init.flags = flags | CLK_IS_BASIC; + init.parent_names = &parent_name; + init.num_parents = 1; + + clk = clk_register(dev, &am->hw); + + if (IS_ERR(clk)) + kfree(am); + + return clk; +} + +/* + * Decode current PLL state and (statically) model the state we inherit from + * the bootloader. + */ +static void stm32f4_rcc_register_pll(const char *hse_clk, const char *hsi_clk) +{ + unsigned long pllcfgr = readl(base + STM32F4_RCC_PLLCFGR); + + unsigned long pllm = pllcfgr & 0x3f; + unsigned long plln = (pllcfgr >> 6) & 0x1ff; + unsigned long pllp = BIT(((pllcfgr >> 16) & 3) + 1); + const char *pllsrc = pllcfgr & BIT(22) ? hse_clk : hsi_clk; + unsigned long pllq = (pllcfgr >> 24) & 0xf; + + clk_register_fixed_factor(NULL, "vco", pllsrc, 0, plln, pllm); + clk_register_fixed_factor(NULL, "pll", "vco", 0, 1, pllp); + clk_register_fixed_factor(NULL, "pll48", "vco", 0, 1, pllq); +} + +/* + * Converts the primary and secondary indices (as they appear in DT) to an + * offset into our struct clock array. + */ +static unsigned int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary) +{ + u64 table[ARRAY_SIZE(stm32f42xx_gate_map)]; + + if (primary == 1) { + BUG_ON(secondary > FCLK); + return secondary; + } + + memcpy(table, stm32f42xx_gate_map, sizeof(table)); + + /* only bits set in table can be used as indices */ + BUG_ON(secondary > 8 * sizeof(table) || + 0 == (table[BIT_ULL_WORD(secondary)] & BIT_ULL_MASK(secondary))); + + /* mask out bits above our current index */ + table[BIT_ULL_WORD(secondary)] &= + GENMASK_ULL(secondary % BITS_PER_LONG_LONG, 0); + + return FCLK + hweight64(table[0]) + + (BIT_ULL_WORD(secondary) >= 1 ? hweight64(table[1]) : 0) + + (BIT_ULL_WORD(secondary) >= 2 ? hweight64(table[2]) : 0); +} + +struct clk *stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data) +{ + return clks[stm32f4_rcc_lookup_clk_idx(clkspec->args[0], + clkspec->args[1])]; +} + +static const char __initdata *sys_parents[] = { "hsi", NULL, "pll" }; + +static struct clk_div_table ahb_div_table[] = { + { 0x0, 1 }, { 0x1, 1 }, { 0x2, 1 }, { 0x3, 1 }, + { 0x4, 1 }, { 0x5, 1 }, { 0x6, 1 }, { 0x7, 1 }, + { 0x8, 2 }, { 0x9, 4 }, { 0xa, 8 }, { 0xb, 16 }, + { 0xc, 64 }, { 0xd, 128 }, { 0xe, 256 }, { 0xf, 512 }, + { 0 }, +}; + +static struct clk_div_table apb_div_table[] = { + { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, + { 4, 2 }, { 5, 4 }, { 6, 8 }, { 7, 16 }, + { 0 }, +}; + +static void __init stm32f4_rcc_init(struct device_node *np) +{ + const char *hse_clk; + int n; + + base = of_iomap(np, 0); + if (!base) { + pr_err("%s: unable to map resource", np->name); + return; + } + + hse_clk = of_clk_get_parent_name(np, 0); + + clk_register_fixed_rate_with_accuracy(NULL, "hsi", NULL, 0, + 16000000, 160000); + stm32f4_rcc_register_pll(hse_clk, "hsi"); + + sys_parents[1] = hse_clk; + clk_register_mux_table( + NULL, "sys", sys_parents, ARRAY_SIZE(sys_parents), 0, + base + STM32F4_RCC_CFGR, 0, 3, 0, NULL, &stm32f4_clk_lock); + + clk_register_divider_table(NULL, "ahb_div", "sys", + CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR, + 4, 4, 0, ahb_div_table, &stm32f4_clk_lock); + + clk_register_divider_table(NULL, "apb1_div", "ahb_div", + CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR, + 10, 3, 0, apb_div_table, &stm32f4_clk_lock); + clk_register_apb_mul(NULL, "apb1_mul", "apb1_div", + CLK_SET_RATE_PARENT, 12); + + clk_register_divider_table(NULL, "apb2_div", "ahb_div", + CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR, + 13, 3, 0, apb_div_table, &stm32f4_clk_lock); + clk_register_apb_mul(NULL, "apb2_mul", "apb2_div", + CLK_SET_RATE_PARENT, 15); + + clks[SYSTICK] = clk_register_fixed_factor(NULL, "systick", "ahb_div", + 0, 1, 8); + clks[FCLK] = clk_register_fixed_factor(NULL, "fclk", "ahb_div", + 0, 1, 1); + + for (n = 0; n < ARRAY_SIZE(stm32f4_gates); n++) { + const struct stm32f4_gate_data *gd = &stm32f4_gates[n]; + unsigned int secondary = + 8 * (gd->offset - STM32F4_RCC_AHB1ENR) + gd->bit_idx; + unsigned int idx = stm32f4_rcc_lookup_clk_idx(0, secondary); + + clks[idx] = clk_register_gate( + NULL, gd->name, gd->parent_name, gd->flags, + base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock); + + if (IS_ERR(clks[n])) { + pr_err("%s: Unable to register leaf clock %s\n", + np->full_name, gd->name); + goto fail; + } + } + + of_clk_add_provider(np, stm32f4_rcc_lookup_clk, NULL); + return; +fail: + iounmap(base); +} +CLK_OF_DECLARE(stm32f4_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
Hi Daniel,
Nice driver, please find my comments below.
Once fixed, you can add: Reviewed-by: Maxime Coquelin mcoquelin.stm32@gmail.com
On 05/30/2015 09:54 AM, Daniel Thompson wrote:
The driver supports decoding and statically modelling PLL state (i.e. we inherit state from bootloader) and provides support for all peripherals that support simple one-bit gated clocks. The covers all peripherals whose clocks come from the AHB, APB1 or APB2 buses.
It has been tested (for non-regression only) on an STM32F429I-Discovery boards. The clock counts for TIM2, USART1 and SYSTICK are all set correctly and time and the wall clock looks OK when checked with a stopwatch.
Signed-off-by: Daniel Thompson daniel.thompson@linaro.org
drivers/clk/Makefile | 1 + drivers/clk/clk-stm32f4.c | 364 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 365 insertions(+) create mode 100644 drivers/clk/clk-stm32f4.c
...
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c new file mode 100644 index 0000000..68f9962 --- /dev/null +++ b/drivers/clk/clk-stm32f4.c @@ -0,0 +1,364 @@
...
+/*
- Converts the primary and secondary indices (as they appear in DT) to an
- offset into our struct clock array.
- */
+static unsigned int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary) +{
- u64 table[ARRAY_SIZE(stm32f42xx_gate_map)];
- if (primary == 1) {
BUG_ON(secondary > FCLK);
Maybe the function could return a signed int, an propagate errors instead of using BUG_ON?
return secondary;- }
- memcpy(table, stm32f42xx_gate_map, sizeof(table));
- /* only bits set in table can be used as indices */
- BUG_ON(secondary > 8 * sizeof(table) ||
0 == (table[BIT_ULL_WORD(secondary)] & BIT_ULL_MASK(secondary)));
Ditto.
- /* mask out bits above our current index */
- table[BIT_ULL_WORD(secondary)] &=
GENMASK_ULL(secondary % BITS_PER_LONG_LONG, 0);- return FCLK + hweight64(table[0]) +
(BIT_ULL_WORD(secondary) >= 1 ? hweight64(table[1]) : 0) +(BIT_ULL_WORD(secondary) >= 2 ? hweight64(table[2]) : 0);+}
+struct clk *stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data) +{
- return clks[stm32f4_rcc_lookup_clk_idx(clkspec->args[0],
clkspec->args[1])];
If stm32f4_rcc_lookup_clk_idx() returns an error, you could propagate it using ERR_PTR().
+}
+static const char __initdata *sys_parents[] = { "hsi", NULL, "pll" };
+static struct clk_div_table ahb_div_table[] = {
Should be const.
- { 0x0, 1 }, { 0x1, 1 }, { 0x2, 1 }, { 0x3, 1 },
- { 0x4, 1 }, { 0x5, 1 }, { 0x6, 1 }, { 0x7, 1 },
- { 0x8, 2 }, { 0x9, 4 }, { 0xa, 8 }, { 0xb, 16 },
- { 0xc, 64 }, { 0xd, 128 }, { 0xe, 256 }, { 0xf, 512 },
- { 0 },
+};
+static struct clk_div_table apb_div_table[] = {
Ditto.
- { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
- { 4, 2 }, { 5, 4 }, { 6, 8 }, { 7, 16 },
- { 0 },
+};
Thanks! Maxime
On 30/05/15 10:15, Maxime Coquelin wrote:
Hi Daniel,
Nice driver, please find my comments below. Once fixed, you can add:Reviewed-by: Maxime Coquelin mcoquelin.stm32@gmail.com
Thanks for the review.
No concerns at my end. I'll act on all of the issues you raised.
Daniel.
New bindings and driver have been created for STM32F42xxx series parts. This patch integrates these changes.
Note: Earlier device tree blobs (those without st,stm32f42xxx compatibles for the rcc) could still be used to boot basic systems. Such systems rely on the bootloader to configure the clock gates for vital periperhals.
Signed-off-by: Daniel Thompson daniel.thompson@linaro.org --- arch/arm/boot/dts/stm32f429-disco.dts | 4 ++ arch/arm/boot/dts/stm32f429.dtsi | 79 +++++++++++------------------------ 2 files changed, 28 insertions(+), 55 deletions(-)
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index 17cbb83..97028da 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -66,6 +66,10 @@ }; };
+&clk_hse { + clock-frequency = <8000000>; +}; + &usart1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index ef6d382..748b886 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -49,48 +49,10 @@
/ { clocks { - clk_sysclk: clk-sysclk { + clk_hse: clk-hse { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <168000000>; - }; - - clk_hclk: clk-hclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <168000000>; - }; - - clk_pclk1: clk-pclk1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <42000000>; - }; - - clk_pclk2: clk-pclk2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <84000000>; - }; - - clk_pmtr1: clk-pmtr1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <84000000>; - }; - - clk_pmtr2: clk-pmtr2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <168000000>; - }; - - clk_systick: clk-systick { - compatible = "fixed-factor-clock"; - clocks = <&clk_hclk>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; + clock-frequency = <0>; }; };
@@ -99,7 +61,7 @@ compatible = "st,stm32-timer"; reg = <0x40000000 0x400>; interrupts = <28>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 128>; status = "disabled"; };
@@ -107,7 +69,7 @@ compatible = "st,stm32-timer"; reg = <0x40000400 0x400>; interrupts = <29>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 129>; status = "disabled"; };
@@ -115,7 +77,7 @@ compatible = "st,stm32-timer"; reg = <0x40000800 0x400>; interrupts = <30>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 130>; status = "disabled"; };
@@ -123,7 +85,7 @@ compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; interrupts = <50>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 131>; status = "disabled"; };
@@ -131,7 +93,7 @@ compatible = "st,stm32-timer"; reg = <0x40001000 0x400>; interrupts = <54>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 132>; status = "disabled"; };
@@ -139,7 +101,7 @@ compatible = "st,stm32-timer"; reg = <0x40001400 0x400>; interrupts = <55>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 133>; status = "disabled"; };
@@ -147,7 +109,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; interrupts = <38>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 145>; status = "disabled"; };
@@ -155,7 +117,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; interrupts = <39>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 146>; status = "disabled"; };
@@ -163,7 +125,7 @@ compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; interrupts = <52>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 147>; status = "disabled"; };
@@ -171,7 +133,7 @@ compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; interrupts = <53>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 148>; status = "disabled"; };
@@ -179,7 +141,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40007800 0x400>; interrupts = <82>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 158>; status = "disabled"; };
@@ -187,7 +149,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40007c00 0x400>; interrupts = <83>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 159>; status = "disabled"; };
@@ -195,7 +157,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011000 0x400>; interrupts = <37>; - clocks = <&clk_pclk2>; + clocks = <&rcc 0 164>; status = "disabled"; };
@@ -203,13 +165,20 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011400 0x400>; interrupts = <71>; - clocks = <&clk_pclk2>; + clocks = <&rcc 0 165>; status = "disabled"; }; + + rcc: rcc@40023810 { + #clock-cells = <2>; + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; + reg = <0x40023800 0x400>; + clocks = <&clk_hse>; + }; }; };
&systick { - clocks = <&clk_systick>; + clocks = <&rcc 1 0>; status = "okay"; };
On 05/30/2015 09:54 AM, Daniel Thompson wrote:
New bindings and driver have been created for STM32F42xxx series parts. This patch integrates these changes.
Note: Earlier device tree blobs (those without st,stm32f42xxx compatibles for the rcc) could still be used to boot basic systems. Such systems rely on the bootloader to configure the clock gates for vital periperhals.
Signed-off-by: Daniel Thompson daniel.thompson@linaro.org
arch/arm/boot/dts/stm32f429-disco.dts | 4 ++ arch/arm/boot/dts/stm32f429.dtsi | 79 +++++++++++------------------------ 2 files changed, 28 insertions(+), 55 deletions(-)
Reviewed-by: Maxime Coquelin mcoquelin.stm32@gmail.com
Thanks! Maxime
On 05/30/2015 09:54 AM, Daniel Thompson wrote:
For completeness I've also included a small config patch I needed to get my board to boot once I had rebased. I suspect Maxime may have the same patch tucked away somewhere:-).
You are right, I already sent the same patch to Arnd. But it looks it is not applied to arm-soc tree yet.
Regards, Maxime
This patchset implements a clock driver for STM32F42xxx and STM32F43xxx series devices. It supports decoding the state configured by the bootloader (PLL, clock select, bus dividers) and all the gates clocks. It does not currently support the I2S and SAI PLLs.
Relies on "Add support to STMicroeletronics STM32 family" v9 by Maxime Coquelin: http://thread.gmane.org/gmane.linux.kernel/1961049 .
v3: * Fix propagation of errors from clock idx lookup function (Maxime Coquelin). * Added const to a couple of static lookup tables (Maxime Coquelin). * Fixed typo in the binding docs (Maxime Coquelin). * Removed unnecessary header files and other small code simplifications (Stephen Boyd). * Remove CLK_IS_BASIC from the APB clock "multipliers" and improved commenting for the implementation (Stephen Boyd) * Fixed missing const and misplaced __initdata (Stephen Boyd) * Apply relavent review comments to existing code (Stephen Boyd)
v2: * Move the HSE crystal frequency to stm32f429-disco.dts (was prevsiously in stm32f429.dtsi) * Fixed compiler warning that I overlooked the first time round. * Removed dead code in the .dtsi file. * Rebased on linux-next+v9 from Maxime.
Daniel Thompson (3): dt-bindings: Document the STM32F4 clock bindings clk: stm32: Add clock driver for STM32F4[23]xxx devices ARM: dts: stm32f429: Adopt STM32F4 clock driver
.../devicetree/bindings/clock/st,stm32-rcc.txt | 65 ++++ arch/arm/boot/dts/stm32f429-disco.dts | 4 + arch/arm/boot/dts/stm32f429.dtsi | 79 ++--- drivers/clk/Makefile | 1 + drivers/clk/clk-stm32f4.c | 379 +++++++++++++++++++++ 5 files changed, 473 insertions(+), 55 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/st,stm32-rcc.txt create mode 100644 drivers/clk/clk-stm32f4.c
-- 2.4.2
This adds documentation of device tree bindings for the clock related portions of the STM32 RCC block.
Signed-off-by: Daniel Thompson daniel.thompson@linaro.org --- .../devicetree/bindings/clock/st,stm32-rcc.txt | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt new file mode 100644 index 0000000..fee3205 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt @@ -0,0 +1,65 @@ +STMicroelectronics STM32 Reset and Clock Controller +=================================================== + +The RCC IP is both a reset and a clock controller. This documentation only +describes the clock part. + +Please also refer to clock-bindings.txt in this directory for common clock +controller binding usage. + +Required properties: +- compatible: Should be "st,stm32f42xx-rcc" +- reg: should be register base and length as documented in the + datasheet +- #clock-cells: 2, device nodes should specify the clock in their "clocks" + property, containing a phandle to the clock device node, an index selecting + between gated clocks and other clocks and an index specifying the clock to + use. + +Example: + + rcc: rcc@40023800 { + #clock-cells = <2> + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; + reg = <0x40023800 0x400>; + }; + +Specifying gated clocks +======================= + +The primary index must be set to 0. + +The secondary index is the bit number within the RCC register bank, starting +from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30). + +It is calculated as: index = register_offset / 4 * 32 + bit_offset. +Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31). + +Example: + + /* Gated clock, AHB1 bit 0 (GPIOA) */ + ... { + clocks = <&rcc 0 0> + }; + + /* Gated clock, AHB2 bit 4 (CRYP) */ + ... { + clocks = <&rcc 0 36> + }; + +Specifying other clocks +======================= + +The primary index must be set to 1. + +The secondary index is bound with the following magic numbers: + + 0 SYSTICK + 1 FCLK + +Example: + + /* Misc clock, FCLK */ + ... { + clocks = <&rcc 1 1> + };
Hi Daniel,
2015-06-10 22:09 GMT+02:00 Daniel Thompson daniel.thompson@linaro.org:
This adds documentation of device tree bindings for the clock related portions of the STM32 RCC block.
Signed-off-by: Daniel Thompson daniel.thompson@linaro.org
.../devicetree/bindings/clock/st,stm32-rcc.txt | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
You can add: Acked-by: Maxime Coquelin maxime.coquelin@st.com
Thanks! Maxime
On 06/10, Daniel Thompson wrote:
This adds documentation of device tree bindings for the clock related portions of the STM32 RCC block.
Signed-off-by: Daniel Thompson daniel.thompson@linaro.org
Applied to clk-next
The driver supports decoding and statically modelling PLL state (i.e. we inherit state from bootloader) and provides support for all peripherals that support simple one-bit gated clocks. The covers all peripherals whose clocks come from the AHB, APB1 or APB2 buses.
It has been tested on an STM32F429I-Discovery board. The clock counts for TIM2, USART1 and SYSTICK are all set correctly and the wall clock looks OK when checked with a stopwatch. I have also tested a prototype driver for the RNG hardware. The RNG clock is correctly enabled by the framework (also did inverse test and proved that by changing DT to configure the wrong clock bit then we observe the RNG driver to fail).
Signed-off-by: Daniel Thompson daniel.thompson@linaro.org Reviewed-by: Maxime Coquelin mcoquelin.stm32@gmail.com --- drivers/clk/Makefile | 1 + drivers/clk/clk-stm32f4.c | 379 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 380 insertions(+) create mode 100644 drivers/clk/clk-stm32f4.c
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 02f17e3..a75a238 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o +obj-$(CONFIG_ARCH_STM32) += clk-stm32f4.o obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o obj-$(CONFIG_ARCH_U300) += clk-u300.o obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c new file mode 100644 index 0000000..c825bbd --- /dev/null +++ b/drivers/clk/clk-stm32f4.c @@ -0,0 +1,379 @@ +/* + * Author: Daniel Thompson daniel.thompson@linaro.org + * + * Inspired by clk-asm9260.c . + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see http://www.gnu.org/licenses/. + */ + +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/spinlock.h> +#include <linux/of.h> +#include <linux/of_address.h> + +#define STM32F4_RCC_PLLCFGR 0x04 +#define STM32F4_RCC_CFGR 0x08 +#define STM32F4_RCC_AHB1ENR 0x30 +#define STM32F4_RCC_AHB2ENR 0x34 +#define STM32F4_RCC_AHB3ENR 0x38 +#define STM32F4_RCC_APB1ENR 0x40 +#define STM32F4_RCC_APB2ENR 0x44 + +struct stm32f4_gate_data { + u8 offset; + u8 bit_idx; + const char *name; + const char *parent_name; + unsigned long flags; +}; + +static const struct stm32f4_gate_data stm32f4_gates[] __initconst = { + { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 20, "ccmdatam", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" }, + { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" }, + + { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" }, + { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" }, + { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" }, + { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" }, + { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" }, + + { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div", + CLK_IGNORE_UNUSED }, + + { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" }, + { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 17, "uart2", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 18, "uart3", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 19, "uart4", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 20, "uart5", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 21, "i2c1", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 22, "i2c2", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 23, "i2c3", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 30, "uart7", "apb1_div" }, + { STM32F4_RCC_APB1ENR, 31, "uart8", "apb1_div" }, + + { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" }, + { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" }, + { STM32F4_RCC_APB2ENR, 4, "usart1", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 5, "usart6", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 11, "sdio", "pll48" }, + { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" }, + { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" }, + { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" }, + { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" }, + { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" }, +}; + +/* + * MAX_CLKS is the maximum value in the enumeration below plus the combined + * hweight of stm32f42xx_gate_map (plus one). + */ +#define MAX_CLKS 74 + +enum { SYSTICK, FCLK }; + +/* + * This bitmask tells us which bit offsets (0..192) on STM32F4[23]xxx + * have gate bits associated with them. Its combined hweight is 71. + */ +static const u64 stm32f42xx_gate_map[] = { 0x000000f17ef417ff, + 0x0000000000000001, + 0x04777f33f6fec9ff }; + +static struct clk *clks[MAX_CLKS]; +static DEFINE_SPINLOCK(stm32f4_clk_lock); +static void __iomem *base; + +/* + * "Multiplier" device for APBx clocks. + * + * The APBx dividers are power-of-two dividers and, if *not* running in 1:1 + * mode, they also tap out the one of the low order state bits to run the + * timers. ST datasheets represent this feature as a (conditional) clock + * multiplier. + */ +struct clk_apb_mul { + struct clk_hw hw; + u8 bit_idx; +}; + +#define to_clk_apb_mul(_hw) container_of(_hw, struct clk_apb_mul, hw) + +static unsigned long clk_apb_mul_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_apb_mul *am = to_clk_apb_mul(hw); + + if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) + return parent_rate * 2; + + return parent_rate; +} + +static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_apb_mul *am = to_clk_apb_mul(hw); + unsigned long mult = 1; + + if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) + mult = 2; + + if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) { + unsigned long best_parent = rate / mult; + + *prate = + __clk_round_rate(__clk_get_parent(hw->clk), best_parent); + } + + return *prate * mult; +} + +static int clk_apb_mul_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + /* + * We must report success but we can do so unconditionally because + * clk_apb_mul_round_rate returns values that ensure this call is a + * nop. + */ + + return 0; +} + +static const struct clk_ops clk_apb_mul_factor_ops = { + .round_rate = clk_apb_mul_round_rate, + .set_rate = clk_apb_mul_set_rate, + .recalc_rate = clk_apb_mul_recalc_rate, +}; + +struct clk *clk_register_apb_mul(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + u8 bit_idx) +{ + struct clk_apb_mul *am; + struct clk_init_data init; + struct clk *clk; + + am = kzalloc(sizeof(*am), GFP_KERNEL); + if (!am) + return ERR_PTR(-ENOMEM); + + am->bit_idx = bit_idx; + am->hw.init = &init; + + init.name = name; + init.ops = &clk_apb_mul_factor_ops; + init.flags = flags; + init.parent_names = &parent_name; + init.num_parents = 1; + + clk = clk_register(dev, &am->hw); + + if (IS_ERR(clk)) + kfree(am); + + return clk; +} + +/* + * Decode current PLL state and (statically) model the state we inherit from + * the bootloader. + */ +static void stm32f4_rcc_register_pll(const char *hse_clk, const char *hsi_clk) +{ + unsigned long pllcfgr = readl(base + STM32F4_RCC_PLLCFGR); + + unsigned long pllm = pllcfgr & 0x3f; + unsigned long plln = (pllcfgr >> 6) & 0x1ff; + unsigned long pllp = BIT(((pllcfgr >> 16) & 3) + 1); + const char *pllsrc = pllcfgr & BIT(22) ? hse_clk : hsi_clk; + unsigned long pllq = (pllcfgr >> 24) & 0xf; + + clk_register_fixed_factor(NULL, "vco", pllsrc, 0, plln, pllm); + clk_register_fixed_factor(NULL, "pll", "vco", 0, 1, pllp); + clk_register_fixed_factor(NULL, "pll48", "vco", 0, 1, pllq); +} + +/* + * Converts the primary and secondary indices (as they appear in DT) to an + * offset into our struct clock array. + */ +static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary) +{ + u64 table[ARRAY_SIZE(stm32f42xx_gate_map)]; + + if (primary == 1) { + if (WARN_ON(secondary > FCLK)) + return -EINVAL; + return secondary; + } + + memcpy(table, stm32f42xx_gate_map, sizeof(table)); + + /* only bits set in table can be used as indices */ + if (WARN_ON(secondary > 8 * sizeof(table) || + 0 == (table[BIT_ULL_WORD(secondary)] & + BIT_ULL_MASK(secondary)))) + return -EINVAL; + + /* mask out bits above our current index */ + table[BIT_ULL_WORD(secondary)] &= + GENMASK_ULL(secondary % BITS_PER_LONG_LONG, 0); + + return FCLK + hweight64(table[0]) + + (BIT_ULL_WORD(secondary) >= 1 ? hweight64(table[1]) : 0) + + (BIT_ULL_WORD(secondary) >= 2 ? hweight64(table[2]) : 0); +} + +struct clk *stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data) +{ + int i = stm32f4_rcc_lookup_clk_idx(clkspec->args[0], clkspec->args[1]); + + if (i < 0) + return ERR_PTR(-EINVAL); + + return clks[i]; +} + +static const char *sys_parents[] __initdata = { "hsi", NULL, "pll" }; + +static const struct clk_div_table ahb_div_table[] = { + { 0x0, 1 }, { 0x1, 1 }, { 0x2, 1 }, { 0x3, 1 }, + { 0x4, 1 }, { 0x5, 1 }, { 0x6, 1 }, { 0x7, 1 }, + { 0x8, 2 }, { 0x9, 4 }, { 0xa, 8 }, { 0xb, 16 }, + { 0xc, 64 }, { 0xd, 128 }, { 0xe, 256 }, { 0xf, 512 }, + { 0 }, +}; + +static const struct clk_div_table apb_div_table[] = { + { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, + { 4, 2 }, { 5, 4 }, { 6, 8 }, { 7, 16 }, + { 0 }, +}; + +static void __init stm32f4_rcc_init(struct device_node *np) +{ + const char *hse_clk; + int n; + + base = of_iomap(np, 0); + if (!base) { + pr_err("%s: unable to map resource", np->name); + return; + } + + hse_clk = of_clk_get_parent_name(np, 0); + + clk_register_fixed_rate_with_accuracy(NULL, "hsi", NULL, 0, + 16000000, 160000); + stm32f4_rcc_register_pll(hse_clk, "hsi"); + + sys_parents[1] = hse_clk; + clk_register_mux_table( + NULL, "sys", sys_parents, ARRAY_SIZE(sys_parents), 0, + base + STM32F4_RCC_CFGR, 0, 3, 0, NULL, &stm32f4_clk_lock); + + clk_register_divider_table(NULL, "ahb_div", "sys", + CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR, + 4, 4, 0, ahb_div_table, &stm32f4_clk_lock); + + clk_register_divider_table(NULL, "apb1_div", "ahb_div", + CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR, + 10, 3, 0, apb_div_table, &stm32f4_clk_lock); + clk_register_apb_mul(NULL, "apb1_mul", "apb1_div", + CLK_SET_RATE_PARENT, 12); + + clk_register_divider_table(NULL, "apb2_div", "ahb_div", + CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR, + 13, 3, 0, apb_div_table, &stm32f4_clk_lock); + clk_register_apb_mul(NULL, "apb2_mul", "apb2_div", + CLK_SET_RATE_PARENT, 15); + + clks[SYSTICK] = clk_register_fixed_factor(NULL, "systick", "ahb_div", + 0, 1, 8); + clks[FCLK] = clk_register_fixed_factor(NULL, "fclk", "ahb_div", + 0, 1, 1); + + for (n = 0; n < ARRAY_SIZE(stm32f4_gates); n++) { + const struct stm32f4_gate_data *gd = &stm32f4_gates[n]; + unsigned int secondary = + 8 * (gd->offset - STM32F4_RCC_AHB1ENR) + gd->bit_idx; + int idx = stm32f4_rcc_lookup_clk_idx(0, secondary); + + if (idx < 0) + goto fail; + + clks[idx] = clk_register_gate( + NULL, gd->name, gd->parent_name, gd->flags, + base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock); + + if (IS_ERR(clks[n])) { + pr_err("%s: Unable to register leaf clock %s\n", + np->full_name, gd->name); + goto fail; + } + } + + of_clk_add_provider(np, stm32f4_rcc_lookup_clk, NULL); + return; +fail: + iounmap(base); +} +CLK_OF_DECLARE(stm32f4_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
On 06/10, Daniel Thompson wrote:
The driver supports decoding and statically modelling PLL state (i.e. we inherit state from bootloader) and provides support for all peripherals that support simple one-bit gated clocks. The covers all peripherals whose clocks come from the AHB, APB1 or APB2 buses.
It has been tested on an STM32F429I-Discovery board. The clock counts for TIM2, USART1 and SYSTICK are all set correctly and the wall clock looks OK when checked with a stopwatch. I have also tested a prototype driver for the RNG hardware. The RNG clock is correctly enabled by the framework (also did inverse test and proved that by changing DT to configure the wrong clock bit then we observe the RNG driver to fail).
Signed-off-by: Daniel Thompson daniel.thompson@linaro.org Reviewed-by: Maxime Coquelin mcoquelin.stm32@gmail.com
Applied to clk-next
On 06/10, Daniel Thompson wrote:
The driver supports decoding and statically modelling PLL state (i.e. we inherit state from bootloader) and provides support for all peripherals that support simple one-bit gated clocks. The covers all peripherals whose clocks come from the AHB, APB1 or APB2 buses.
It has been tested on an STM32F429I-Discovery board. The clock counts for TIM2, USART1 and SYSTICK are all set correctly and the wall clock looks OK when checked with a stopwatch. I have also tested a prototype driver for the RNG hardware. The RNG clock is correctly enabled by the framework (also did inverse test and proved that by changing DT to configure the wrong clock bit then we observe the RNG driver to fail).
Signed-off-by: Daniel Thompson daniel.thompson@linaro.org Reviewed-by: Maxime Coquelin mcoquelin.stm32@gmail.com
I also squashed in some sparse fixes. Please check.
drivers/clk/clk-stm32f4.c:135:44: warning: constant 0x000000f17ef417ff is so big it is long drivers/clk/clk-stm32f4.c:137:44: warning: constant 0x04777f33f6fec9ff is so big it is long drivers/clk/clk-stm32f4.c:206:12: warning: symbol 'clk_register_apb_mul' was not declared. Should it be static? drivers/clk/clk-stm32f4.c:285:12: warning: symbol 'stm32f4_rcc_lookup_clk' was not declared. Should it be static?
---8<---- diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index c825bbd4335f..b9b12a742970 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -132,9 +132,9 @@ enum { SYSTICK, FCLK }; * This bitmask tells us which bit offsets (0..192) on STM32F4[23]xxx * have gate bits associated with them. Its combined hweight is 71. */ -static const u64 stm32f42xx_gate_map[] = { 0x000000f17ef417ff, - 0x0000000000000001, - 0x04777f33f6fec9ff }; +static const u64 stm32f42xx_gate_map[] = { 0x000000f17ef417ffull, + 0x0000000000000001ull, + 0x04777f33f6fec9ffull };
static struct clk *clks[MAX_CLKS]; static DEFINE_SPINLOCK(stm32f4_clk_lock); @@ -186,7 +186,7 @@ static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate, }
static int clk_apb_mul_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) + unsigned long parent_rate) { /* * We must report success but we can do so unconditionally because @@ -203,9 +203,9 @@ static const struct clk_ops clk_apb_mul_factor_ops = { .recalc_rate = clk_apb_mul_recalc_rate, };
-struct clk *clk_register_apb_mul(struct device *dev, const char *name, - const char *parent_name, unsigned long flags, - u8 bit_idx) +static struct clk *clk_register_apb_mul(struct device *dev, const char *name, + const char *parent_name, + unsigned long flags, u8 bit_idx) { struct clk_apb_mul *am; struct clk_init_data init; @@ -282,7 +282,8 @@ static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary) (BIT_ULL_WORD(secondary) >= 2 ? hweight64(table[2]) : 0); }
-struct clk *stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data) +static struct clk * +stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data) { int i = stm32f4_rcc_lookup_clk_idx(clkspec->args[0], clkspec->args[1]);
On 23/06/15 00:21, Stephen Boyd wrote:
On 06/10, Daniel Thompson wrote:
The driver supports decoding and statically modelling PLL state (i.e. we inherit state from bootloader) and provides support for all peripherals that support simple one-bit gated clocks. The covers all peripherals whose clocks come from the AHB, APB1 or APB2 buses.
It has been tested on an STM32F429I-Discovery board. The clock counts for TIM2, USART1 and SYSTICK are all set correctly and the wall clock looks OK when checked with a stopwatch. I have also tested a prototype driver for the RNG hardware. The RNG clock is correctly enabled by the framework (also did inverse test and proved that by changing DT to configure the wrong clock bit then we observe the RNG driver to fail).
Signed-off-by: Daniel Thompson daniel.thompson@linaro.org Reviewed-by: Maxime Coquelin mcoquelin.stm32@gmail.com
I also squashed in some sparse fixes. Please check.
That was extremely generous! Thanks.
The changes all eyeball OK but I'll double check things tonight just in case.
Daniel.
New bindings and driver have been created for STM32F42xxx series parts. This patch integrates these changes.
Note: Earlier device tree blobs (those without st,stm32f42xxx compatibles for the rcc) could still be used to boot basic systems. Such systems rely on the bootloader to configure the clock gates for vital periperhals.
Signed-off-by: Daniel Thompson daniel.thompson@linaro.org Reviewed-by: Maxime Coquelin mcoquelin.stm32@gmail.com --- arch/arm/boot/dts/stm32f429-disco.dts | 4 ++ arch/arm/boot/dts/stm32f429.dtsi | 79 +++++++++++------------------------ 2 files changed, 28 insertions(+), 55 deletions(-)
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index 17cbb83..97028da 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -66,6 +66,10 @@ }; };
+&clk_hse { + clock-frequency = <8000000>; +}; + &usart1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index ef6d382..748b886 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -49,48 +49,10 @@
/ { clocks { - clk_sysclk: clk-sysclk { + clk_hse: clk-hse { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <168000000>; - }; - - clk_hclk: clk-hclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <168000000>; - }; - - clk_pclk1: clk-pclk1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <42000000>; - }; - - clk_pclk2: clk-pclk2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <84000000>; - }; - - clk_pmtr1: clk-pmtr1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <84000000>; - }; - - clk_pmtr2: clk-pmtr2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <168000000>; - }; - - clk_systick: clk-systick { - compatible = "fixed-factor-clock"; - clocks = <&clk_hclk>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; + clock-frequency = <0>; }; };
@@ -99,7 +61,7 @@ compatible = "st,stm32-timer"; reg = <0x40000000 0x400>; interrupts = <28>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 128>; status = "disabled"; };
@@ -107,7 +69,7 @@ compatible = "st,stm32-timer"; reg = <0x40000400 0x400>; interrupts = <29>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 129>; status = "disabled"; };
@@ -115,7 +77,7 @@ compatible = "st,stm32-timer"; reg = <0x40000800 0x400>; interrupts = <30>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 130>; status = "disabled"; };
@@ -123,7 +85,7 @@ compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; interrupts = <50>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 131>; status = "disabled"; };
@@ -131,7 +93,7 @@ compatible = "st,stm32-timer"; reg = <0x40001000 0x400>; interrupts = <54>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 132>; status = "disabled"; };
@@ -139,7 +101,7 @@ compatible = "st,stm32-timer"; reg = <0x40001400 0x400>; interrupts = <55>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 133>; status = "disabled"; };
@@ -147,7 +109,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; interrupts = <38>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 145>; status = "disabled"; };
@@ -155,7 +117,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; interrupts = <39>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 146>; status = "disabled"; };
@@ -163,7 +125,7 @@ compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; interrupts = <52>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 147>; status = "disabled"; };
@@ -171,7 +133,7 @@ compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; interrupts = <53>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 148>; status = "disabled"; };
@@ -179,7 +141,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40007800 0x400>; interrupts = <82>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 158>; status = "disabled"; };
@@ -187,7 +149,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40007c00 0x400>; interrupts = <83>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 159>; status = "disabled"; };
@@ -195,7 +157,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011000 0x400>; interrupts = <37>; - clocks = <&clk_pclk2>; + clocks = <&rcc 0 164>; status = "disabled"; };
@@ -203,13 +165,20 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011400 0x400>; interrupts = <71>; - clocks = <&clk_pclk2>; + clocks = <&rcc 0 165>; status = "disabled"; }; + + rcc: rcc@40023810 { + #clock-cells = <2>; + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; + reg = <0x40023800 0x400>; + clocks = <&clk_hse>; + }; }; };
&systick { - clocks = <&clk_systick>; + clocks = <&rcc 1 0>; status = "okay"; };
Hi Daniel,
2015-06-10 22:09 GMT+02:00 Daniel Thompson daniel.thompson@linaro.org:
New bindings and driver have been created for STM32F42xxx series parts. This patch integrates these changes.
Note: Earlier device tree blobs (those without st,stm32f42xxx compatibles for the rcc) could still be used to boot basic systems. Such systems rely on the bootloader to configure the clock gates for vital periperhals.
Signed-off-by: Daniel Thompson daniel.thompson@linaro.org Reviewed-by: Maxime Coquelin mcoquelin.stm32@gmail.com
arch/arm/boot/dts/stm32f429-disco.dts | 4 ++ arch/arm/boot/dts/stm32f429.dtsi | 79 +++++++++++------------------------ 2 files changed, 28 insertions(+), 55 deletions(-)
Patch applied to next/dt-for-v4.3 of stm32 tree.
Thanks! Maxime
On 06/10, Daniel Thompson wrote:
This patchset implements a clock driver for STM32F42xxx and STM32F43xxx series devices. It supports decoding the state configured by the bootloader (PLL, clock select, bus dividers) and all the gates clocks. It does not currently support the I2S and SAI PLLs.
Relies on "Add support to STMicroeletronics STM32 family" v9 by Maxime Coquelin: http://thread.gmane.org/gmane.linux.kernel/1961049 .
I applied 1 and 2. Looks like #3 should go through arm-soc at some later time?
On 22/06/15 23:48, Stephen Boyd wrote:
On 06/10, Daniel Thompson wrote:
This patchset implements a clock driver for STM32F42xxx and STM32F43xxx series devices. It supports decoding the state configured by the bootloader (PLL, clock select, bus dividers) and all the gates clocks. It does not currently support the I2S and SAI PLLs.
Relies on "Add support to STMicroeletronics STM32 family" v9 by Maxime Coquelin: http://thread.gmane.org/gmane.linux.kernel/1961049 .
I applied 1 and 2. Looks like #3 should go through arm-soc at some later time?
Agreed (that is also the patch that must be correctly ordered w.r.t. Maxime's patches).
Thanks.
Daniel.
2015-06-23 10:22 GMT+02:00 Daniel Thompson daniel.thompson@linaro.org:
On 22/06/15 23:48, Stephen Boyd wrote:
On 06/10, Daniel Thompson wrote:
This patchset implements a clock driver for STM32F42xxx and STM32F43xxx series devices. It supports decoding the state configured by the bootloader (PLL, clock select, bus dividers) and all the gates clocks. It does not currently support the I2S and SAI PLLs.
Relies on "Add support to STMicroeletronics STM32 family" v9 by Maxime Coquelin: http://thread.gmane.org/gmane.linux.kernel/1961049 .
I applied 1 and 2. Looks like #3 should go through arm-soc at some later time?
Agreed (that is also the patch that must be correctly ordered w.r.t. Maxime's patches).
Indeed, I will take care of patch 3.
Thanks, Maxime
linaro-kernel@lists.linaro.org
-
Daniel Thompson -
Maxime Coquelin -
Stephen Boyd