[PATCH v2 0/2] Add GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250
Adds GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250.
changes since v1: - addressed comments from Tomasz Figa tomasz.figa@gmail.com
is rebased on Mike's https://git.linaro.org/gitweb?p=people/mturquette/linux.git%3Ba=shortlog%3Bh... and on top of Tomasz Figa's clk clean-up patch series http://www.spinics.net/lists/arm-kernel/msg269848.html
Vikas Sajjan (2): clk: samsung: Add GPLL freq table for exynos5250 SoC clk: samsung: Add APLL, KPLL, EPLL and VPLL freq table for exynos5420 SoC
drivers/clk/samsung/clk-exynos5250.c | 19 ++++++++- drivers/clk/samsung/clk-exynos5420.c | 78 ++++++++++++++++++++++++++++++++++ 2 files changed, 96 insertions(+), 1 deletion(-)
Adds GPLL freq table for exynos5250 SoC.
Signed-off-by: Vikas Sajjan vikas.sajjan@linaro.org --- drivers/clk/samsung/clk-exynos5250.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 00a80e4..6b7ad2a 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -494,6 +494,21 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0), };
+static struct samsung_pll_rate_table gpll_24mhz_tbl[] __initdata = { + /* sorted in descending order */ + /* PLL_35XX_RATE(rate, m, p, s) */ + PLL_35XX_RATE(1400000000, 175, 3, 0), /* for 466MHz */ + PLL_35XX_RATE(800000000, 100, 3, 0), /* for 400MHz, 200MHz */ + PLL_35XX_RATE(666857142, 389, 7, 1), /* for 333MHz, 222MHz, 166MHz */ + PLL_35XX_RATE(600000000, 200, 4, 1), /* for 300MHz, 200MHz, 150MHz */ + PLL_35XX_RATE(533000000, 533, 12, 1), /* for 533MHz, 266MHz, 133MHz */ + PLL_35XX_RATE(450000000, 450, 12, 1), /* for 450Hz */ + PLL_35XX_RATE(400000000, 100, 3, 1), + PLL_35XX_RATE(333000000, 222, 4, 2), + PLL_35XX_RATE(200000000, 100, 3, 2), + { }, +}; + static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { /* sorted in descending order */ /* PLL_36XX_RATE(rate, m, p, s, k) */ @@ -561,8 +576,10 @@ static void __init exynos5250_clk_init(struct device_node *np) samsung_clk_register_mux(exynos5250_pll_pmux_clks, ARRAY_SIZE(exynos5250_pll_pmux_clks));
- if (_get_rate("fin_pll") == 24 * MHZ) + if (_get_rate("fin_pll") == 24 * MHZ) { exynos5250_plls[epll].rate_table = epll_24mhz_tbl; + exynos5250_plls[gpll].rate_table = gpll_24mhz_tbl; + }
if (_get_rate("mout_vpllsrc") == 24 * MHZ) exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl;
Adds APLL, KPLL, EPLL and VPLL freq table for exynos5420 SoC.
Signed-off-by: Vikas Sajjan vikas.sajjan@linaro.org --- drivers/clk/samsung/clk-exynos5420.c | 78 ++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index e035fd0..5cbe313 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -757,6 +757,76 @@ static struct of_device_id ext_clk_match[] __initdata = { { }, };
+static struct samsung_pll_rate_table apll_24mhz_tbl[] __initdata = { + /* sorted in descending order */ + /* PLL_35XX_RATE(rate, m, p, s) */ + PLL_35XX_RATE(2000000000, 250, 3, 0), + PLL_35XX_RATE(1900000000, 475, 6, 0), + PLL_35XX_RATE(1800000000, 225, 3, 0), + PLL_35XX_RATE(1700000000, 425, 6, 0), + PLL_35XX_RATE(1600000000, 200, 3, 0), + PLL_35XX_RATE(1500000000, 250, 4, 0), + PLL_35XX_RATE(1400000000, 175, 3, 0), + PLL_35XX_RATE(1300000000, 325, 6, 0), + PLL_35XX_RATE(1200000000, 200, 2, 1), + PLL_35XX_RATE(1100000000, 275, 3, 1), + PLL_35XX_RATE(1000000000, 250, 3, 1), + PLL_35XX_RATE(900000000, 150, 2, 1), + PLL_35XX_RATE(800000000, 200, 3, 1), + PLL_35XX_RATE(700000000, 175, 3, 1), + PLL_35XX_RATE(600000000, 200, 2, 2), + PLL_35XX_RATE(500000000, 250, 3, 2), + PLL_35XX_RATE(400000000, 200, 3, 2), + PLL_35XX_RATE(300000000, 400, 4, 3), + PLL_35XX_RATE(200000000, 200, 3, 3), + { }, +}; + +static struct samsung_pll_rate_table kpll_24mhz_tbl[] __initdata = { + /* sorted in descending order */ + /* PLL_35XX_RATE(rate, m, p, s) */ + PLL_35XX_RATE(1300000000, 325, 6, 0), + PLL_35XX_RATE(1200000000, 200, 2, 1), + PLL_35XX_RATE(1100000000, 275, 3, 1), + PLL_35XX_RATE(1000000000, 250, 3, 1), + PLL_35XX_RATE(900000000, 150, 2, 1), + PLL_35XX_RATE(800000000, 200, 3, 1), + PLL_35XX_RATE(700000000, 175, 3, 1), + PLL_35XX_RATE(600000000, 200, 2, 2), + PLL_35XX_RATE(500000000, 250, 3, 2), + PLL_35XX_RATE(400000000, 200, 3, 2), + PLL_35XX_RATE(300000000, 400, 4, 3), + PLL_35XX_RATE(200000000, 200, 3, 3), + { }, +}; + +static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = { + /* sorted in descending order */ + /* PLL_36XX_RATE(rate, m, p, s, k) */ + PLL_36XX_RATE(192000000, 64, 2, 2, 0), + PLL_36XX_RATE(180633605, 45, 3, 1, 10381), + PLL_36XX_RATE(180000000, 45, 3, 1, 0), + PLL_36XX_RATE(73728000, 98, 2, 4, 19923), + PLL_36XX_RATE(67737602, 90, 2, 4, 20762), + PLL_36XX_RATE(49152000, 98, 3, 4, 19923), + PLL_36XX_RATE(45158401, 90, 3, 4, 20762), + PLL_36XX_RATE(32768001, 131, 3, 5, 4719), + { }, +}; + +static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { + /* sorted in descending order */ + /* PLL_35XX_RATE(rate, m, p, s) */ + PLL_35XX_RATE(533000000, 533, 6, 2), + PLL_35XX_RATE(480000000, 160, 2, 2), + PLL_35XX_RATE(420000000, 140, 2, 2), + PLL_35XX_RATE(350000000, 175, 3, 2), + PLL_35XX_RATE(266000000, 266, 3, 3), + PLL_35XX_RATE(177000000, 118, 2, 3), + PLL_35XX_RATE(100000000, 200, 3, 4), + { }, +}; + /* register exynos5420 clocks */ static void __init exynos5420_clk_init(struct device_node *np) { @@ -776,6 +846,14 @@ static void __init exynos5420_clk_init(struct device_node *np) samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks, ARRAY_SIZE(exynos5420_fixed_rate_ext_clks), ext_clk_match); + + if (_get_rate("fin_pll") == 24 * MHZ) { + exynos5420_plls[apll].rate_table = apll_24mhz_tbl; + exynos5420_plls[kpll].rate_table = kpll_24mhz_tbl; + exynos5420_plls[epll].rate_table = epll_24mhz_tbl; + exynos5420_plls[vpll].rate_table = vpll_24mhz_tbl; + } + samsung_clk_register_pll(exynos5420_plls, ARRAY_SIZE(exynos5420_plls), reg_base); samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks,
On Wednesday 28 of August 2013 19:09:56 Vikas Sajjan wrote:
Adds GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250.
changes since v1:
- addressed comments from Tomasz Figa tomasz.figa@gmail.com
is rebased on Mike's https://git.linaro.org/gitweb?p=people/mturquette/linux.git%3Ba=shortlog%3Bh... refs/heads/clk-next and on top of Tomasz Figa's clk clean-up patch series http://www.spinics.net/lists/arm-kernel/msg269848.html
Vikas Sajjan (2): clk: samsung: Add GPLL freq table for exynos5250 SoC clk: samsung: Add APLL, KPLL, EPLL and VPLL freq table for exynos5420 SoC
drivers/clk/samsung/clk-exynos5250.c | 19 ++++++++- drivers/clk/samsung/clk-exynos5420.c | 78 ++++++++++++++++++++++++++++++++++ 2 files changed, 96 insertions(+), 1 deletion(-)
For the whole series:
Reviewed-by: Tomasz Figa t.figa@samsung.com
Best regards, Tomasz
Quoting Vikas Sajjan (2013-08-28 06:39:56)
Adds GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250.
changes since v1: - addressed comments from Tomasz Figa tomasz.figa@gmail.com
is rebased on Mike's https://git.linaro.org/gitweb?p=people/mturquette/linux.git%3Ba=shortlog%3Bh... and on top of Tomasz Figa's clk clean-up patch series http://www.spinics.net/lists/arm-kernel/msg269848.html
Looks good to me but it will have to wait until Tomasz's cleanup series is merged. I'm waiting on that get to get reviewed-by's and then I'll take them both in.
Regards, Mike
Vikas Sajjan (2): clk: samsung: Add GPLL freq table for exynos5250 SoC clk: samsung: Add APLL, KPLL, EPLL and VPLL freq table for exynos5420 SoC
drivers/clk/samsung/clk-exynos5250.c | 19 ++++++++- drivers/clk/samsung/clk-exynos5420.c | 78 ++++++++++++++++++++++++++++++++++ 2 files changed, 96 insertions(+), 1 deletion(-)
-- 1.7.9.5
Sure, Mike.
On 29 August 2013 08:12, Mike Turquette mturquette@linaro.org wrote:
Quoting Vikas Sajjan (2013-08-28 06:39:56)
Adds GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250.
changes since v1: - addressed comments from Tomasz Figa tomasz.figa@gmail.com
is rebased on Mike's https://git.linaro.org/gitweb?p=people/mturquette/linux.git%3Ba=shortlog%3Bh... and on top of Tomasz Figa's clk clean-up patch series http://www.spinics.net/lists/arm-kernel/msg269848.html
Looks good to me but it will have to wait until Tomasz's cleanup series is merged. I'm waiting on that get to get reviewed-by's and then I'll take them both in.
Regards, Mike
Vikas Sajjan (2): clk: samsung: Add GPLL freq table for exynos5250 SoC clk: samsung: Add APLL, KPLL, EPLL and VPLL freq table for exynos5420 SoC
drivers/clk/samsung/clk-exynos5250.c | 19 ++++++++- drivers/clk/samsung/clk-exynos5420.c | 78 ++++++++++++++++++++++++++++++++++ 2 files changed, 96 insertions(+), 1 deletion(-)
-- 1.7.9.5
On Thu, Aug 29, 2013 at 8:12 AM, Mike Turquette mturquette@linaro.org wrote:
Quoting Vikas Sajjan (2013-08-28 06:39:56)
Adds GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250.
changes since v1: - addressed comments from Tomasz Figa tomasz.figa@gmail.com
is rebased on Mike's https://git.linaro.org/gitweb?p=people/mturquette/linux.git%3Ba=shortlog%3Bh... and on top of Tomasz Figa's clk clean-up patch series http://www.spinics.net/lists/arm-kernel/msg269848.html
Looks good to me but it will have to wait until Tomasz's cleanup series is merged. I'm waiting on that get to get reviewed-by's and then I'll take them both in.
Can you take these patchset.
Regards, Mike
Vikas Sajjan (2): clk: samsung: Add GPLL freq table for exynos5250 SoC clk: samsung: Add APLL, KPLL, EPLL and VPLL freq table for exynos5420 SoC
drivers/clk/samsung/clk-exynos5250.c | 19 ++++++++- drivers/clk/samsung/clk-exynos5420.c | 78 ++++++++++++++++++++++++++++++++++ 2 files changed, 96 insertions(+), 1 deletion(-)
-- 1.7.9.5
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Hi Mike,
On Thu, Aug 29, 2013 at 8:12 AM, Mike Turquette mturquette@linaro.org wrote:
Quoting Vikas Sajjan (2013-08-28 06:39:56)
Adds GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250.
changes since v1: - addressed comments from Tomasz Figa tomasz.figa@gmail.com
is rebased on Mike's https://git.linaro.org/gitweb?p=people/mturquette/linux.git%3Ba=shortlog%3Bh... and on top of Tomasz Figa's clk clean-up patch series http://www.spinics.net/lists/arm-kernel/msg269848.html
Looks good to me but it will have to wait until Tomasz's cleanup series is merged. I'm waiting on that get to get reviewed-by's and then I'll take them both in.
Can you apply these patches.
Regards, Mike
Vikas Sajjan (2): clk: samsung: Add GPLL freq table for exynos5250 SoC clk: samsung: Add APLL, KPLL, EPLL and VPLL freq table for exynos5420 SoC
drivers/clk/samsung/clk-exynos5250.c | 19 ++++++++- drivers/clk/samsung/clk-exynos5420.c | 78 ++++++++++++++++++++++++++++++++++ 2 files changed, 96 insertions(+), 1 deletion(-)
-- 1.7.9.5
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