version 9: - fix pwm commit message header - re-oerder nodes in DT file
version 8: - rebase on v4.10-rc4 - fix comments done by Thierry on PWM - reword "reg" parameter description - change kernel kernel in IIO ABI documentation
version 7: - rebase on v4.10-rc2 - remove iio_device code from driver and keep only the trigger part
version 6: - rename stm32-gptimer in stm32-timers. - change "st,stm32-gptimer" compatible to "st,stm32-timers". - modify "st,breakinput" parameter in pwm part. - split DT patch in 2
version 5: - fix comments done on version 4 - rebased on kernel 4.9-rc8 - change nodes names and re-order then by addresses
version 4: - fix comments done on version 3 - don't use interrupts anymore in IIO timer - detect hardware capabilities at probe time to simplify binding
version 3: - no change on mfd and pwm divers patches - add cross reference between bindings - change compatible to "st,stm32-timer-trigger" - fix attributes access rights - use string instead of int for master_mode and slave_mode - document device attributes in sysfs-bus-iio-timer-stm32 - update DT with the new compatible
version 2: - keep only one compatible per driver - use DT parameters to describe hardware block configuration: - pwm channels, complementary output, counter size, break input - triggers accepted and create by IIO timers - change DT to limite use of reference to the node - interrupt is now in IIO timer driver - rename stm32-mfd-timer to stm32-timers (for general purpose timer)
The following patches enable PWM and IIO Timer features for STM32 platforms.
Those two features are mixed into the registers of the same hardware block (named general purpose timer) which lead to introduce a multifunctions driver on the top of them to be able to share the registers.
In STM32f4 14 instances of timer hardware block exist, even if they all have the same register mapping they could have a different number of pwm channels and/or different triggers capabilities. We use various parameters in DT to describe the differences between hardware blocks
The MFD (stm32-timers.c) takes care of clock and register mapping by using regmap. stm32_timers structure is provided to its sub-node to share those information.
PWM driver is implemented into pwm-stm32.c. Depending of the instance we may have up to 4 channels, sometime with complementary outputs or 32 bits counter instead of 16 bits. Some hardware blocks may also have a break input function which allows to stop pwm depending of a level, defined in devicetree, on an external pin.
IIO timer driver (stm32-timer-trigger.c and stm32-timer-trigger.h) define a list of hardware triggers usable by hardware blocks like ADC, DAC or other timers.
The matrix of possible connections between blocks is quite complex so we use trigger names and is_stm32_iio_timer_trigger() function to be sure that triggers are valid and configure the IPs.
At run time IIO timer hardware blocks can configure (through "master_mode" IIO device attribute) which internal signal (counter enable, reset, comparison block, etc...) is used to generate the trigger.
Benjamin Gaignard (8): MFD: add bindings for STM32 Timers driver MFD: add STM32 Timers driver dt-bindings: pwm: Add STM32 bindings pwm: add driver for STM32 plaftorm IIO: add bindings for STM32 timer trigger driver IIO: add STM32 timer trigger driver ARM: dts: stm32: add Timers driver for stm32f429 MCU ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco
.../ABI/testing/sysfs-bus-iio-timer-stm32 | 29 ++ .../bindings/iio/timer/stm32-timer-trigger.txt | 23 ++ .../devicetree/bindings/mfd/stm32-timers.txt | 46 +++ .../devicetree/bindings/pwm/pwm-stm32.txt | 35 ++ arch/arm/boot/dts/stm32f429.dtsi | 275 ++++++++++++++ arch/arm/boot/dts/stm32f469-disco.dts | 28 ++ drivers/iio/trigger/Kconfig | 9 + drivers/iio/trigger/Makefile | 1 + drivers/iio/trigger/stm32-timer-trigger.c | 342 ++++++++++++++++++ drivers/mfd/Kconfig | 11 + drivers/mfd/Makefile | 2 + drivers/mfd/stm32-timers.c | 80 +++++ drivers/pwm/Kconfig | 9 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-stm32.c | 398 +++++++++++++++++++++ include/linux/iio/timer/stm32-timer-trigger.h | 62 ++++ include/linux/mfd/stm32-timers.h | 71 ++++ 17 files changed, 1422 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timers.txt create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt create mode 100644 drivers/iio/trigger/stm32-timer-trigger.c create mode 100644 drivers/mfd/stm32-timers.c create mode 100644 drivers/pwm/pwm-stm32.c create mode 100644 include/linux/iio/timer/stm32-timer-trigger.h create mode 100644 include/linux/mfd/stm32-timers.h
Add bindings information for STM32 Timers
version 6: - rename stm32-gtimer to stm32-timers - change compatible - add description about the IPs
version 2: - rename stm32-mfd-timer to stm32-gptimer - only keep one compatible string
Signed-off-by: Benjamin Gaignard benjamin.gaignard@st.com Acked-by: Lee Jones lee.jones@linaro.org Acked-by: Rob Herring robh@kernel.org --- .../devicetree/bindings/mfd/stm32-timers.txt | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timers.txt
diff --git a/Documentation/devicetree/bindings/mfd/stm32-timers.txt b/Documentation/devicetree/bindings/mfd/stm32-timers.txt new file mode 100644 index 0000000..bbd083f --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/stm32-timers.txt @@ -0,0 +1,46 @@ +STM32 Timers driver bindings + +This IP provides 3 types of timer along with PWM functionality: +- advanced-control timers consist of a 16-bit auto-reload counter driven by a programmable + prescaler, break input feature, PWM outputs and complementary PWM ouputs channels. +- general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a + programmable prescaler and PWM outputs. +- basic timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. + +Required parameters: +- compatible: must be "st,stm32-timers" + +- reg: Physical base address and length of the controller's + registers. +- clock-names: Set to "int". +- clocks: Phandle to the clock used by the timer module. + For Clk properties, please refer to ../clock/clock-bindings.txt + +Optional parameters: +- resets: Phandle to the parent reset controller. + See ../reset/st,stm32-rcc.txt + +Optional subnodes: +- pwm: See ../pwm/pwm-stm32.txt +- timer: See ../iio/timer/stm32-timer-trigger.txt + +Example: + timers@40010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40010000 0x400>; + clocks = <&rcc 0 160>; + clock-names = "clk_int"; + + pwm { + compatible = "st,stm32-pwm"; + pinctrl-0 = <&pwm1_pins>; + pinctrl-names = "default"; + }; + + timer@0 { + compatible = "st,stm32-timer-trigger"; + reg = <0>; + }; + };
This hardware block could at used at same time for PWM generation and IIO timers. PWM and IIO timer configuration are mixed in the same registers so we need a multi fonction driver to be able to share those registers.
version 7: - rebase on v4.10-rc2
version 6: - rename files to stm32-timers - rename functions to stm32_timers_xxx
version 5: - fix Lee comments about detect function - add missing dependency on REGMAP_MMIO
version 4: - add a function to detect Auto Reload Register (ARR) size - rename the structure shared with other drivers
version 2: - rename driver "stm32-gptimer" to be align with SoC documentation - only keep one compatible - use of_platform_populate() instead of devm_mfd_add_devices()
Signed-off-by: Benjamin Gaignard benjamin.gaignard@st.com Acked-by: Lee Jones lee.jones@linaro.org Acked-by: Rob Herring robh@kernel.org --- drivers/mfd/Kconfig | 11 ++++++ drivers/mfd/Makefile | 2 + drivers/mfd/stm32-timers.c | 80 ++++++++++++++++++++++++++++++++++++++++ include/linux/mfd/stm32-timers.h | 71 +++++++++++++++++++++++++++++++++++ 4 files changed, 164 insertions(+) create mode 100644 drivers/mfd/stm32-timers.c create mode 100644 include/linux/mfd/stm32-timers.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 4ce3b6f..d0c14b8 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1621,6 +1621,17 @@ config MFD_STW481X in various ST Microelectronics and ST-Ericsson embedded Nomadik series.
+config MFD_STM32_TIMERS + tristate "Support for STM32 Timers" + depends on (ARCH_STM32 && OF) || COMPILE_TEST + select MFD_CORE + select REGMAP + select REGMAP_MMIO + help + Select this option to enable STM32 timers driver used + for PWM and IIO Timer. This driver allow to share the + registers between the others drivers. + menu "Multimedia Capabilities Port drivers" depends on ARCH_SA1100
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index dda4d4f..876ca86 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -212,3 +212,5 @@ obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o obj-$(CONFIG_MFD_SUN4I_GPADC) += sun4i-gpadc.o + +obj-$(CONFIG_MFD_STM32_TIMERS) += stm32-timers.o diff --git a/drivers/mfd/stm32-timers.c b/drivers/mfd/stm32-timers.c new file mode 100644 index 0000000..41bd901 --- /dev/null +++ b/drivers/mfd/stm32-timers.c @@ -0,0 +1,80 @@ +/* + * Copyright (C) STMicroelectronics 2016 + * + * Author: Benjamin Gaignard benjamin.gaignard@st.com + * + * License terms: GNU General Public License (GPL), version 2 + */ + +#include <linux/mfd/stm32-timers.h> +#include <linux/module.h> +#include <linux/of_platform.h> +#include <linux/reset.h> + +static const struct regmap_config stm32_timers_regmap_cfg = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = sizeof(u32), + .max_register = 0x400, +}; + +static void stm32_timers_get_arr_size(struct stm32_timers *ddata) +{ + /* + * Only the available bits will be written so when readback + * we get the maximum value of auto reload register + */ + regmap_write(ddata->regmap, TIM_ARR, ~0L); + regmap_read(ddata->regmap, TIM_ARR, &ddata->max_arr); + regmap_write(ddata->regmap, TIM_ARR, 0x0); +} + +static int stm32_timers_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct stm32_timers *ddata; + struct resource *res; + void __iomem *mmio; + + ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); + if (!ddata) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mmio = devm_ioremap_resource(dev, res); + if (IS_ERR(mmio)) + return PTR_ERR(mmio); + + ddata->regmap = devm_regmap_init_mmio_clk(dev, "int", mmio, + &stm32_timers_regmap_cfg); + if (IS_ERR(ddata->regmap)) + return PTR_ERR(ddata->regmap); + + ddata->clk = devm_clk_get(dev, NULL); + if (IS_ERR(ddata->clk)) + return PTR_ERR(ddata->clk); + + stm32_timers_get_arr_size(ddata); + + platform_set_drvdata(pdev, ddata); + + return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); +} + +static const struct of_device_id stm32_timers_of_match[] = { + { .compatible = "st,stm32-timers", }, + { /* end node */ }, +}; +MODULE_DEVICE_TABLE(of, stm32_timers_of_match); + +static struct platform_driver stm32_timers_driver = { + .probe = stm32_timers_probe, + .driver = { + .name = "stm32-timers", + .of_match_table = stm32_timers_of_match, + }, +}; +module_platform_driver(stm32_timers_driver); + +MODULE_DESCRIPTION("STMicroelectronics STM32 Timers"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/mfd/stm32-timers.h b/include/linux/mfd/stm32-timers.h new file mode 100644 index 0000000..d030004 --- /dev/null +++ b/include/linux/mfd/stm32-timers.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) STMicroelectronics 2016 + * + * Author: Benjamin Gaignard benjamin.gaignard@st.com + * + * License terms: GNU General Public License (GPL), version 2 + */ + +#ifndef _LINUX_STM32_GPTIMER_H_ +#define _LINUX_STM32_GPTIMER_H_ + +#include <linux/clk.h> +#include <linux/regmap.h> + +#define TIM_CR1 0x00 /* Control Register 1 */ +#define TIM_CR2 0x04 /* Control Register 2 */ +#define TIM_SMCR 0x08 /* Slave mode control reg */ +#define TIM_DIER 0x0C /* DMA/interrupt register */ +#define TIM_SR 0x10 /* Status register */ +#define TIM_EGR 0x14 /* Event Generation Reg */ +#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */ +#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */ +#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */ +#define TIM_PSC 0x28 /* Prescaler */ +#define TIM_ARR 0x2c /* Auto-Reload Register */ +#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */ +#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */ +#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */ +#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */ +#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */ + +#define TIM_CR1_CEN BIT(0) /* Counter Enable */ +#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */ +#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */ +#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */ +#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */ +#define TIM_DIER_UIE BIT(0) /* Update interrupt */ +#define TIM_SR_UIF BIT(0) /* Update interrupt flag */ +#define TIM_EGR_UG BIT(0) /* Update Generation */ +#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */ +#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */ +#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */ +#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */ +#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */ +#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */ +#define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */ +#define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */ +#define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */ +#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12)) +#define TIM_BDTR_BKE BIT(12) /* Break input enable */ +#define TIM_BDTR_BKP BIT(13) /* Break input polarity */ +#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */ +#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */ +#define TIM_BDTR_BKF (BIT(16) | BIT(17) | BIT(18) | BIT(19)) +#define TIM_BDTR_BK2F (BIT(20) | BIT(21) | BIT(22) | BIT(23)) +#define TIM_BDTR_BK2E BIT(24) /* Break 2 input enable */ +#define TIM_BDTR_BK2P BIT(25) /* Break 2 input polarity */ + +#define MAX_TIM_PSC 0xFFFF +#define TIM_CR2_MMS_SHIFT 4 +#define TIM_SMCR_TS_SHIFT 4 +#define TIM_BDTR_BKF_MASK 0xF +#define TIM_BDTR_BKF_SHIFT 16 +#define TIM_BDTR_BK2F_SHIFT 20 + +struct stm32_timers { + struct clk *clk; + struct regmap *regmap; + u32 max_arr; +}; +#endif
Define bindings for pwm-stm32
version 9: - change commit message header
version 8: - reword st,breakinput description.
version 6: - change st,breakinput parameter format to make it usuable on stm32f7 too.
version 2: - use parameters instead of compatible of handle the hardware configuration
Signed-off-by: Benjamin Gaignard benjamin.gaignard@st.com Acked-by: Rob Herring robh@kernel.org Acked-by: Thierry Reding thierry.reding@gmail.com --- .../devicetree/bindings/pwm/pwm-stm32.txt | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt
diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt new file mode 100644 index 0000000..6dd0403 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt @@ -0,0 +1,35 @@ +STMicroelectronics STM32 Timers PWM bindings + +Must be a sub-node of an STM32 Timers device tree node. +See ../mfd/stm32-timers.txt for details about the parent node. + +Required parameters: +- compatible: Must be "st,stm32-pwm". +- pinctrl-names: Set to "default". +- pinctrl-0: List of phandles pointing to pin configuration nodes for PWM module. + For Pinctrl properties see ../pinctrl/pinctrl-bindings.txt + +Optional parameters: +- st,breakinput: One or two <index level filter> to describe break input configurations. + "index" indicates on which break input (0 or 1) the configuration + should be applied. + "level" gives the active level (0=low or 1=high) of the input signal + for this configuration. + "filter" gives the filtering value to be applied. + +Example: + timers@40010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40010000 0x400>; + clocks = <&rcc 0 160>; + clock-names = "clk_int"; + + pwm { + compatible = "st,stm32-pwm"; + pinctrl-0 = <&pwm1_pins>; + pinctrl-names = "default"; + st,breakinput = <0 1 5>; + }; + };
This driver adds support for PWM driver on STM32 platform. The SoC have multiple instances of the hardware IP and each of them could have small differences: number of channels, complementary output, auto reload register size...
version 9: - fix commit message header - remove one space MODULE_ALIAS
version 8: - fix comments done by Thierry on version 7
version 6: - change st,breakinput parameter to make it usuable for stm32f7 too.
version 4: - detect at probe time hardware capabilities - fix comments done on v2 and v3 - use PWM atomic ops
version 2: - only keep one comptatible - use DT parameters to discover hardware block configuration
Signed-off-by: Benjamin Gaignard benjamin.gaignard@st.com Acked-by: Thierry Reding treding@nvidia.com --- drivers/pwm/Kconfig | 9 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-stm32.c | 398 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 408 insertions(+) create mode 100644 drivers/pwm/pwm-stm32.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index f92dd41..2d0cfaa 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -397,6 +397,15 @@ config PWM_STI To compile this driver as a module, choose M here: the module will be called pwm-sti.
+config PWM_STM32 + tristate "STMicroelectronics STM32 PWM" + depends on MFD_STM32_TIMERS || COMPILE_TEST + help + Generic PWM framework driver for STM32 SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-stm32. + config PWM_STMPE bool "STMPE expander PWM export" depends on MFD_STMPE diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index a48bdb5..346a83b 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o obj-$(CONFIG_PWM_STI) += pwm-sti.o +obj-$(CONFIG_PWM_STM32) += pwm-stm32.o obj-$(CONFIG_PWM_STMPE) += pwm-stmpe.o obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c new file mode 100644 index 0000000..ce6232e --- /dev/null +++ b/drivers/pwm/pwm-stm32.c @@ -0,0 +1,398 @@ +/* + * Copyright (C) STMicroelectronics 2016 + * + * Author: Gerald Baeza gerald.baeza@st.com + * + * License terms: GNU General Public License (GPL), version 2 + * + * Inspired by timer-stm32.c from Maxime Coquelin + * pwm-atmel.c from Bo Shen + */ + +#include <linux/mfd/stm32-timers.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pwm.h> + +#define CCMR_CHANNEL_SHIFT 8 +#define CCMR_CHANNEL_MASK 0xFF +#define MAX_BREAKINPUT 2 + +struct stm32_pwm { + struct pwm_chip chip; + struct device *dev; + struct clk *clk; + struct regmap *regmap; + u32 max_arr; + bool have_complementary_output; +}; + +struct stm32_breakinput { + u32 index; + u32 level; + u32 filter; +}; + +static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip) +{ + return container_of(chip, struct stm32_pwm, chip); +} + +static u32 active_channels(struct stm32_pwm *dev) +{ + u32 ccer; + + regmap_read(dev->regmap, TIM_CCER, &ccer); + + return ccer & TIM_CCER_CCXE; +} + +static int write_ccrx(struct stm32_pwm *dev, int ch, u32 value) +{ + switch (ch) { + case 0: + return regmap_write(dev->regmap, TIM_CCR1, value); + case 1: + return regmap_write(dev->regmap, TIM_CCR2, value); + case 2: + return regmap_write(dev->regmap, TIM_CCR3, value); + case 3: + return regmap_write(dev->regmap, TIM_CCR4, value); + } + return -EINVAL; +} + +static int stm32_pwm_config(struct stm32_pwm *priv, int ch, + int duty_ns, int period_ns) +{ + unsigned long long prd, div, dty; + unsigned int prescaler = 0; + u32 ccmr, mask, shift; + + /* Period and prescaler values depends on clock rate */ + div = (unsigned long long)clk_get_rate(priv->clk) * period_ns; + + do_div(div, NSEC_PER_SEC); + prd = div; + + while (div > priv->max_arr) { + prescaler++; + div = prd; + do_div(div, prescaler + 1); + } + + prd = div; + + if (prescaler > MAX_TIM_PSC) + return -EINVAL; + + /* + * All channels share the same prescaler and counter so when two + * channels are active at the same time we can't change them + */ + if (active_channels(priv) & ~(1 << ch * 4)) { + u32 psc, arr; + + regmap_read(priv->regmap, TIM_PSC, &psc); + regmap_read(priv->regmap, TIM_ARR, &arr); + + if ((psc != prescaler) || (arr != prd - 1)) + return -EBUSY; + } + + regmap_write(priv->regmap, TIM_PSC, prescaler); + regmap_write(priv->regmap, TIM_ARR, prd - 1); + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE); + + /* Calculate the duty cycles */ + dty = prd * duty_ns; + do_div(dty, period_ns); + + write_ccrx(priv, ch, dty); + + /* Configure output mode */ + shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT; + ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift; + mask = CCMR_CHANNEL_MASK << shift; + + if (ch < 2) + regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr); + else + regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr); + + regmap_update_bits(priv->regmap, TIM_BDTR, + TIM_BDTR_MOE | TIM_BDTR_AOE, + TIM_BDTR_MOE | TIM_BDTR_AOE); + + return 0; +} + +static int stm32_pwm_set_polarity(struct stm32_pwm *priv, int ch, + enum pwm_polarity polarity) +{ + u32 mask; + + mask = TIM_CCER_CC1P << (ch * 4); + if (priv->have_complementary_output) + mask |= TIM_CCER_CC1NP << (ch * 4); + + regmap_update_bits(priv->regmap, TIM_CCER, mask, + polarity == PWM_POLARITY_NORMAL ? 0 : mask); + + return 0; +} + +static int stm32_pwm_enable(struct stm32_pwm *priv, int ch) +{ + u32 mask; + int ret; + + ret = clk_enable(priv->clk); + if (ret) + return ret; + + /* Enable channel */ + mask = TIM_CCER_CC1E << (ch * 4); + if (priv->have_complementary_output) + mask |= TIM_CCER_CC1NE << (ch * 4); + + regmap_update_bits(priv->regmap, TIM_CCER, mask, mask); + + /* Make sure that registers are updated */ + regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); + + /* Enable controller */ + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN); + + return 0; +} + +static void stm32_pwm_disable(struct stm32_pwm *priv, int ch) +{ + u32 mask; + + /* Disable channel */ + mask = TIM_CCER_CC1E << (ch * 4); + if (priv->have_complementary_output) + mask |= TIM_CCER_CC1NE << (ch * 4); + + regmap_update_bits(priv->regmap, TIM_CCER, mask, 0); + + /* When all channels are disabled, we can disable the controller */ + if (!active_channels(priv)) + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); + + clk_disable(priv->clk); +} + +static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct pwm_state curstate; + bool enabled; + struct stm32_pwm *priv = to_stm32_pwm_dev(chip); + int ret; + + enabled = pwm->state.enabled; + + if (enabled && !state->enabled) { + stm32_pwm_disable(priv, pwm->hwpwm); + return 0; + } + + if (state->polarity != curstate.polarity) + stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity); + + ret = stm32_pwm_config(priv, pwm->hwpwm, + state->duty_cycle, state->period); + if (ret) + return ret; + + if (!enabled && state->enabled) + ret = stm32_pwm_enable(priv, pwm->hwpwm); + + return ret; +} + +static const struct pwm_ops stm32pwm_ops = { + .owner = THIS_MODULE, + .apply = stm32_pwm_apply, +}; + +static int stm32_pwm_set_breakinput(struct stm32_pwm *priv, + int index, int level, int filter) +{ + u32 bke = (index == 0) ? TIM_BDTR_BKE : TIM_BDTR_BK2E; + int shift = (index == 0) ? TIM_BDTR_BKF_SHIFT : TIM_BDTR_BK2F_SHIFT; + u32 mask = (index == 0) ? TIM_BDTR_BKE | TIM_BDTR_BKP | TIM_BDTR_BKF + : TIM_BDTR_BK2E | TIM_BDTR_BK2P | TIM_BDTR_BK2F; + u32 bdtr = bke; + + /* + * The both bits could be set since only one will be wrote + * due to mask value. + */ + if (level) + bdtr |= TIM_BDTR_BKP | TIM_BDTR_BK2P; + + bdtr |= (filter & TIM_BDTR_BKF_MASK) << shift; + + regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr); + + regmap_read(priv->regmap, TIM_BDTR, &bdtr); + + return (bdtr & bke) ? 0 : -EINVAL; +} + +static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv, + struct device_node *np) +{ + struct stm32_breakinput breakinput[MAX_BREAKINPUT]; + int nb, ret, i, array_size; + + nb = of_property_count_elems_of_size(np, "st,breakinput", + sizeof(struct stm32_breakinput)); + + /* + * Because "st,breakinput" parameter is optional do not make probe + * failed if it doesn't exist. + */ + if (nb <= 0) + return 0; + + if (nb > MAX_BREAKINPUT) + return -EINVAL; + + array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32); + ret = of_property_read_u32_array(np, "st,breakinput", + (u32 *)breakinput, array_size); + if (ret) + return ret; + + for (i = 0; i < nb && !ret; i++) { + ret = stm32_pwm_set_breakinput(priv, + breakinput[i].index, + breakinput[i].level, + breakinput[i].filter); + } + + return ret; +} + +static void stm32_pwm_detect_complementary(struct stm32_pwm *priv) +{ + u32 ccer; + + /* + * If complementary bit doesn't exist writing 1 will have no + * effect so we can detect it. + */ + regmap_update_bits(priv->regmap, + TIM_CCER, TIM_CCER_CC1NE, TIM_CCER_CC1NE); + regmap_read(priv->regmap, TIM_CCER, &ccer); + regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE, 0); + + priv->have_complementary_output = (ccer != 0); +} + +static int stm32_pwm_detect_channels(struct stm32_pwm *priv) +{ + u32 ccer; + int npwm = 0; + + /* + * If channels enable bits don't exist writing 1 will have no + * effect so we can detect and count them. + */ + regmap_update_bits(priv->regmap, + TIM_CCER, TIM_CCER_CCXE, TIM_CCER_CCXE); + regmap_read(priv->regmap, TIM_CCER, &ccer); + regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE, 0); + + if (ccer & TIM_CCER_CC1E) + npwm++; + + if (ccer & TIM_CCER_CC2E) + npwm++; + + if (ccer & TIM_CCER_CC3E) + npwm++; + + if (ccer & TIM_CCER_CC4E) + npwm++; + + return npwm; +} + +static int stm32_pwm_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); + struct stm32_pwm *priv; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->regmap = ddata->regmap; + priv->clk = ddata->clk; + priv->max_arr = ddata->max_arr; + + if (!priv->regmap || !priv->clk) + return -EINVAL; + + ret = stm32_pwm_apply_breakinputs(priv, np); + if (ret) + return ret; + + stm32_pwm_detect_complementary(priv); + + priv->chip.base = -1; + priv->chip.dev = dev; + priv->chip.ops = &stm32pwm_ops; + priv->chip.npwm = stm32_pwm_detect_channels(priv); + + ret = pwmchip_add(&priv->chip); + if (ret < 0) + return ret; + + platform_set_drvdata(pdev, priv); + + return 0; +} + +static int stm32_pwm_remove(struct platform_device *pdev) +{ + struct stm32_pwm *priv = platform_get_drvdata(pdev); + unsigned int i; + + for (i = 0; i < priv->chip.npwm; i++) + pwm_disable(&priv->chip.pwms[i]); + + pwmchip_remove(&priv->chip); + + return 0; +} + +static const struct of_device_id stm32_pwm_of_match[] = { + { .compatible = "st,stm32-pwm", }, + { /* end node */ }, +}; +MODULE_DEVICE_TABLE(of, stm32_pwm_of_match); + +static struct platform_driver stm32_pwm_driver = { + .probe = stm32_pwm_probe, + .remove = stm32_pwm_remove, + .driver = { + .name = "stm32-pwm", + .of_match_table = stm32_pwm_of_match, + }, +}; +module_platform_driver(stm32_pwm_driver); + +MODULE_ALIAS("platform:stm32-pwm"); +MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver"); +MODULE_LICENSE("GPL v2");
Define bindings for STM32 timer trigger
version 8: - reword "reg" parameter description
version 4: - remove triggers enumeration from DT - add reg parameter
version 3: - change file name - add cross reference with mfd bindings
version 2: - only keep one compatible - add DT parameters to set lists of the triggers: one list describe the triggers created by the device another one give the triggers accepted by the device
Signed-off-by: Benjamin Gaignard benjamin.gaignard@st.com Acked-by: Jonathan Cameron jic23@kernel.org Acked-by: Rob Herring robh@kernel.org --- .../bindings/iio/timer/stm32-timer-trigger.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
diff --git a/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt b/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt new file mode 100644 index 0000000..55a653d --- /dev/null +++ b/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt @@ -0,0 +1,23 @@ +STMicroelectronics STM32 Timers IIO timer bindings + +Must be a sub-node of an STM32 Timers device tree node. +See ../mfd/stm32-timers.txt for details about the parent node. + +Required parameters: +- compatible: Must be "st,stm32-timer-trigger". +- reg: Identify trigger hardware block. + +Example: + timers@40010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40010000 0x400>; + clocks = <&rcc 0 160>; + clock-names = "clk_int"; + + timer@0 { + compatible = "st,stm32-timer-trigger"; + reg = <0>; + }; + };
Timers IPs can be used to generate triggers for other IPs like DAC or ADC. Each trigger may result of timer internals signals like counter enable, reset or edge, this configuration could be done through "master_mode" device attribute.
Since triggers could be used by DAC or ADC their names are defined in include/ nux/iio/timer/stm32-timer-trigger.h and is_stm32_iio_timer_trigger function could be used to check if the trigger is valid or not.
"trgo" trigger have a "sampling_frequency" attribute which allow to configure timer sampling frequency.
version 8: - change kernel version from 4.10 to 4.11 in ABI documentation
version 7: - remove all iio_device related code - move driver into trigger directory
version 5: - simplify tables of triggers - only create an IIO device when needed
version 4: - get triggers configuration from "reg" in DT - add tables of triggers - sampling frequency is enable/disable when writing in trigger sampling_frequency attribute - no more use of interruptions
version 3: - change compatible to "st,stm32-timer-trigger" - fix attributes access right - use string instead of int for master_mode and slave_mode - document device attributes in sysfs-bus-iio-timer-stm32
version 2: - keep only one compatible - use st,input-triggers-names and st,output-triggers-names to know which triggers are accepted and/or create by the device
Signed-off-by: Benjamin Gaignard benjamin.gaignard@st.com Acked-by: Jonathan Cameron jic23@kernel.org --- .../ABI/testing/sysfs-bus-iio-timer-stm32 | 29 ++ drivers/iio/trigger/Kconfig | 9 + drivers/iio/trigger/Makefile | 1 + drivers/iio/trigger/stm32-timer-trigger.c | 342 +++++++++++++++++++++ include/linux/iio/timer/stm32-timer-trigger.h | 62 ++++ 5 files changed, 443 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 create mode 100644 drivers/iio/trigger/stm32-timer-trigger.c create mode 100644 include/linux/iio/timer/stm32-timer-trigger.h
diff --git a/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 b/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 new file mode 100644 index 0000000..6534a60 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 @@ -0,0 +1,29 @@ +What: /sys/bus/iio/devices/triggerX/master_mode_available +KernelVersion: 4.11 +Contact: benjamin.gaignard@st.com +Description: + Reading returns the list possible master modes which are: + - "reset" : The UG bit from the TIMx_EGR register is used as trigger output (TRGO). + - "enable" : The Counter Enable signal CNT_EN is used as trigger output. + - "update" : The update event is selected as trigger output. + For instance a master timer can then be used as a prescaler for a slave timer. + - "compare_pulse" : The trigger output send a positive pulse when the CC1IF flag is to be set. + - "OC1REF" : OC1REF signal is used as trigger output. + - "OC2REF" : OC2REF signal is used as trigger output. + - "OC3REF" : OC3REF signal is used as trigger output. + - "OC4REF" : OC4REF signal is used as trigger output. + +What: /sys/bus/iio/devices/triggerX/master_mode +KernelVersion: 4.11 +Contact: benjamin.gaignard@st.com +Description: + Reading returns the current master modes. + Writing set the master mode + +What: /sys/bus/iio/devices/triggerX/sampling_frequency +KernelVersion: 4.11 +Contact: benjamin.gaignard@st.com +Description: + Reading returns the current sampling frequency. + Writing an value different of 0 set and start sampling. + Writing 0 stop sampling. diff --git a/drivers/iio/trigger/Kconfig b/drivers/iio/trigger/Kconfig index 809b2e7..e4d4e63 100644 --- a/drivers/iio/trigger/Kconfig +++ b/drivers/iio/trigger/Kconfig @@ -24,6 +24,15 @@ config IIO_INTERRUPT_TRIGGER To compile this driver as a module, choose M here: the module will be called iio-trig-interrupt.
+config IIO_STM32_TIMER_TRIGGER + tristate "STM32 Timer Trigger" + depends on (ARCH_STM32 && OF && MFD_STM32_TIMERS) || COMPILE_TEST + help + Select this option to enable STM32 Timer Trigger + + To compile this driver as a module, choose M here: the + module will be called stm32-timer-trigger. + config IIO_TIGHTLOOP_TRIGGER tristate "A kthread based hammering loop trigger" depends on IIO_SW_TRIGGER diff --git a/drivers/iio/trigger/Makefile b/drivers/iio/trigger/Makefile index aab4dc2..5c4ecd3 100644 --- a/drivers/iio/trigger/Makefile +++ b/drivers/iio/trigger/Makefile @@ -6,5 +6,6 @@
obj-$(CONFIG_IIO_HRTIMER_TRIGGER) += iio-trig-hrtimer.o obj-$(CONFIG_IIO_INTERRUPT_TRIGGER) += iio-trig-interrupt.o +obj-$(CONFIG_IIO_STM32_TIMER_TRIGGER) += stm32-timer-trigger.o obj-$(CONFIG_IIO_SYSFS_TRIGGER) += iio-trig-sysfs.o obj-$(CONFIG_IIO_TIGHTLOOP_TRIGGER) += iio-trig-loop.o diff --git a/drivers/iio/trigger/stm32-timer-trigger.c b/drivers/iio/trigger/stm32-timer-trigger.c new file mode 100644 index 0000000..994b96d --- /dev/null +++ b/drivers/iio/trigger/stm32-timer-trigger.c @@ -0,0 +1,342 @@ +/* + * Copyright (C) STMicroelectronics 2016 + * + * Author: Benjamin Gaignard benjamin.gaignard@st.com + * + * License terms: GNU General Public License (GPL), version 2 + */ + +#include <linux/iio/iio.h> +#include <linux/iio/sysfs.h> +#include <linux/iio/timer/stm32-timer-trigger.h> +#include <linux/iio/trigger.h> +#include <linux/mfd/stm32-timers.h> +#include <linux/module.h> +#include <linux/platform_device.h> + +#define MAX_TRIGGERS 6 + +/* List the triggers created by each timer */ +static const void *triggers_table[][MAX_TRIGGERS] = { + { TIM1_TRGO, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,}, + { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,}, + { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,}, + { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,}, + { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,}, + { TIM6_TRGO,}, + { TIM7_TRGO,}, + { TIM8_TRGO, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,}, + { TIM9_TRGO, TIM9_CH1, TIM9_CH2,}, + { }, /* timer 10 */ + { }, /* timer 11 */ + { TIM12_TRGO, TIM12_CH1, TIM12_CH2,}, +}; + +struct stm32_timer_trigger { + struct device *dev; + struct regmap *regmap; + struct clk *clk; + u32 max_arr; + const void *triggers; +}; + +static int stm32_timer_start(struct stm32_timer_trigger *priv, + unsigned int frequency) +{ + unsigned long long prd, div; + int prescaler = 0; + u32 ccer, cr1; + + /* Period and prescaler values depends of clock rate */ + div = (unsigned long long)clk_get_rate(priv->clk); + + do_div(div, frequency); + + prd = div; + + /* + * Increase prescaler value until we get a result that fit + * with auto reload register maximum value. + */ + while (div > priv->max_arr) { + prescaler++; + div = prd; + do_div(div, (prescaler + 1)); + } + prd = div; + + if (prescaler > MAX_TIM_PSC) { + dev_err(priv->dev, "prescaler exceeds the maximum value\n"); + return -EINVAL; + } + + /* Check if nobody else use the timer */ + regmap_read(priv->regmap, TIM_CCER, &ccer); + if (ccer & TIM_CCER_CCXE) + return -EBUSY; + + regmap_read(priv->regmap, TIM_CR1, &cr1); + if (!(cr1 & TIM_CR1_CEN)) + clk_enable(priv->clk); + + regmap_write(priv->regmap, TIM_PSC, prescaler); + regmap_write(priv->regmap, TIM_ARR, prd - 1); + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE); + + /* Force master mode to update mode */ + regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0x20); + + /* Make sure that registers are updated */ + regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); + + /* Enable controller */ + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN); + + return 0; +} + +static void stm32_timer_stop(struct stm32_timer_trigger *priv) +{ + u32 ccer, cr1; + + regmap_read(priv->regmap, TIM_CCER, &ccer); + if (ccer & TIM_CCER_CCXE) + return; + + regmap_read(priv->regmap, TIM_CR1, &cr1); + if (cr1 & TIM_CR1_CEN) + clk_disable(priv->clk); + + /* Stop timer */ + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); + regmap_write(priv->regmap, TIM_PSC, 0); + regmap_write(priv->regmap, TIM_ARR, 0); + + /* Make sure that registers are updated */ + regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); +} + +static ssize_t stm32_tt_store_frequency(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct iio_trigger *trig = to_iio_trigger(dev); + struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig); + unsigned int freq; + int ret; + + ret = kstrtouint(buf, 10, &freq); + if (ret) + return ret; + + if (freq == 0) { + stm32_timer_stop(priv); + } else { + ret = stm32_timer_start(priv, freq); + if (ret) + return ret; + } + + return len; +} + +static ssize_t stm32_tt_read_frequency(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct iio_trigger *trig = to_iio_trigger(dev); + struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig); + u32 psc, arr, cr1; + unsigned long long freq = 0; + + regmap_read(priv->regmap, TIM_CR1, &cr1); + regmap_read(priv->regmap, TIM_PSC, &psc); + regmap_read(priv->regmap, TIM_ARR, &arr); + + if (psc && arr && (cr1 & TIM_CR1_CEN)) { + freq = (unsigned long long)clk_get_rate(priv->clk); + do_div(freq, psc); + do_div(freq, arr); + } + + return sprintf(buf, "%d\n", (unsigned int)freq); +} + +static IIO_DEV_ATTR_SAMP_FREQ(0660, + stm32_tt_read_frequency, + stm32_tt_store_frequency); + +static char *master_mode_table[] = { + "reset", + "enable", + "update", + "compare_pulse", + "OC1REF", + "OC2REF", + "OC3REF", + "OC4REF" +}; + +static ssize_t stm32_tt_show_master_mode(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); + struct stm32_timer_trigger *priv = iio_priv(indio_dev); + u32 cr2; + + regmap_read(priv->regmap, TIM_CR2, &cr2); + cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT; + + return snprintf(buf, PAGE_SIZE, "%s\n", master_mode_table[cr2]); +} + +static ssize_t stm32_tt_store_master_mode(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); + struct stm32_timer_trigger *priv = iio_priv(indio_dev); + int i; + + for (i = 0; i < ARRAY_SIZE(master_mode_table); i++) { + if (!strncmp(master_mode_table[i], buf, + strlen(master_mode_table[i]))) { + regmap_update_bits(priv->regmap, TIM_CR2, + TIM_CR2_MMS, i << TIM_CR2_MMS_SHIFT); + /* Make sure that registers are updated */ + regmap_update_bits(priv->regmap, TIM_EGR, + TIM_EGR_UG, TIM_EGR_UG); + return len; + } + } + + return -EINVAL; +} + +static IIO_CONST_ATTR(master_mode_available, + "reset enable update compare_pulse OC1REF OC2REF OC3REF OC4REF"); + +static IIO_DEVICE_ATTR(master_mode, 0660, + stm32_tt_show_master_mode, + stm32_tt_store_master_mode, + 0); + +static struct attribute *stm32_trigger_attrs[] = { + &iio_dev_attr_sampling_frequency.dev_attr.attr, + &iio_dev_attr_master_mode.dev_attr.attr, + &iio_const_attr_master_mode_available.dev_attr.attr, + NULL, +}; + +static const struct attribute_group stm32_trigger_attr_group = { + .attrs = stm32_trigger_attrs, +}; + +static const struct attribute_group *stm32_trigger_attr_groups[] = { + &stm32_trigger_attr_group, + NULL, +}; + +static const struct iio_trigger_ops timer_trigger_ops = { + .owner = THIS_MODULE, +}; + +static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv) +{ + int ret; + const char * const *cur = priv->triggers; + + while (cur && *cur) { + struct iio_trigger *trig; + + trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur); + if (!trig) + return -ENOMEM; + + trig->dev.parent = priv->dev->parent; + trig->ops = &timer_trigger_ops; + + /* + * sampling frequency and master mode attributes + * should only be available on trgo trigger which + * is always the first in the list. + */ + if (cur == priv->triggers) + trig->dev.groups = stm32_trigger_attr_groups; + + iio_trigger_set_drvdata(trig, priv); + + ret = devm_iio_trigger_register(priv->dev, trig); + if (ret) + return ret; + cur++; + } + + return 0; +} + +/** + * is_stm32_timer_trigger + * @trig: trigger to be checked + * + * return true if the trigger is a valid stm32 iio timer trigger + * either return false + */ +bool is_stm32_timer_trigger(struct iio_trigger *trig) +{ + return (trig->ops == &timer_trigger_ops); +} +EXPORT_SYMBOL(is_stm32_timer_trigger); + +static int stm32_timer_trigger_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct stm32_timer_trigger *priv; + struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); + unsigned int index; + int ret; + + if (of_property_read_u32(dev->of_node, "reg", &index)) + return -EINVAL; + + if (index >= ARRAY_SIZE(triggers_table)) + return -EINVAL; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + + if (!priv) + return -ENOMEM; + + priv->dev = dev; + priv->regmap = ddata->regmap; + priv->clk = ddata->clk; + priv->max_arr = ddata->max_arr; + priv->triggers = triggers_table[index]; + + ret = stm32_setup_iio_triggers(priv); + if (ret) + return ret; + + platform_set_drvdata(pdev, priv); + + return 0; +} + +static const struct of_device_id stm32_trig_of_match[] = { + { .compatible = "st,stm32-timer-trigger", }, + { /* end node */ }, +}; +MODULE_DEVICE_TABLE(of, stm32_trig_of_match); + +static struct platform_driver stm32_timer_trigger_driver = { + .probe = stm32_timer_trigger_probe, + .driver = { + .name = "stm32-timer-trigger", + .of_match_table = stm32_trig_of_match, + }, +}; +module_platform_driver(stm32_timer_trigger_driver); + +MODULE_ALIAS("platform: stm32-timer-trigger"); +MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/iio/timer/stm32-timer-trigger.h b/include/linux/iio/timer/stm32-timer-trigger.h new file mode 100644 index 0000000..55535ae --- /dev/null +++ b/include/linux/iio/timer/stm32-timer-trigger.h @@ -0,0 +1,62 @@ +/* + * Copyright (C) STMicroelectronics 2016 + * + * Author: Benjamin Gaignard benjamin.gaignard@st.com + * + * License terms: GNU General Public License (GPL), version 2 + */ + +#ifndef _STM32_TIMER_TRIGGER_H_ +#define _STM32_TIMER_TRIGGER_H_ + +#define TIM1_TRGO "tim1_trgo" +#define TIM1_CH1 "tim1_ch1" +#define TIM1_CH2 "tim1_ch2" +#define TIM1_CH3 "tim1_ch3" +#define TIM1_CH4 "tim1_ch4" + +#define TIM2_TRGO "tim2_trgo" +#define TIM2_CH1 "tim2_ch1" +#define TIM2_CH2 "tim2_ch2" +#define TIM2_CH3 "tim2_ch3" +#define TIM2_CH4 "tim2_ch4" + +#define TIM3_TRGO "tim3_trgo" +#define TIM3_CH1 "tim3_ch1" +#define TIM3_CH2 "tim3_ch2" +#define TIM3_CH3 "tim3_ch3" +#define TIM3_CH4 "tim3_ch4" + +#define TIM4_TRGO "tim4_trgo" +#define TIM4_CH1 "tim4_ch1" +#define TIM4_CH2 "tim4_ch2" +#define TIM4_CH3 "tim4_ch3" +#define TIM4_CH4 "tim4_ch4" + +#define TIM5_TRGO "tim5_trgo" +#define TIM5_CH1 "tim5_ch1" +#define TIM5_CH2 "tim5_ch2" +#define TIM5_CH3 "tim5_ch3" +#define TIM5_CH4 "tim5_ch4" + +#define TIM6_TRGO "tim6_trgo" + +#define TIM7_TRGO "tim7_trgo" + +#define TIM8_TRGO "tim8_trgo" +#define TIM8_CH1 "tim8_ch1" +#define TIM8_CH2 "tim8_ch2" +#define TIM8_CH3 "tim8_ch3" +#define TIM8_CH4 "tim8_ch4" + +#define TIM9_TRGO "tim9_trgo" +#define TIM9_CH1 "tim9_ch1" +#define TIM9_CH2 "tim9_ch2" + +#define TIM12_TRGO "tim12_trgo" +#define TIM12_CH1 "tim12_ch1" +#define TIM12_CH2 "tim12_ch2" + +bool is_stm32_timer_trigger(struct iio_trigger *trig); + +#endif
Add Timers and it sub-nodes into DT for stm32f429 family.
version 9: - re-order timers node per addresses
version 6: - split patch in two: one for SoC family and one for stm32f469 discovery board.
version 5: - rename gptimer node to timers - re-order timers node per addresses
version 4: - remove unwanted indexing in pwm@ and timer@ node name - use "reg" instead of additional parameters to set timer configuration
version 3: - use "st,stm32-timer-trigger" in DT
version 2: - use parameters to describe hardware capabilities - do not use references for pwm and iio timer subnodes
Signed-off-by: Benjamin Gaignard benjamin.gaignard@st.com --- arch/arm/boot/dts/stm32f429.dtsi | 275 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 275 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index e4dae0e..b608935 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -79,6 +79,27 @@ status = "disabled"; };
+ timers2: timers@40000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000000 0x400>; + clocks = <&rcc 0 128>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@1 { + compatible = "st,stm32-timer-trigger"; + reg = <1>; + status = "disabled"; + }; + }; + timer3: timer@40000400 { compatible = "st,stm32-timer"; reg = <0x40000400 0x400>; @@ -87,6 +108,27 @@ status = "disabled"; };
+ timers3: timers@40000400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000400 0x400>; + clocks = <&rcc 0 129>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@2 { + compatible = "st,stm32-timer-trigger"; + reg = <2>; + status = "disabled"; + }; + }; + timer4: timer@40000800 { compatible = "st,stm32-timer"; reg = <0x40000800 0x400>; @@ -95,6 +137,27 @@ status = "disabled"; };
+ timers4: timers@40000800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000800 0x400>; + clocks = <&rcc 0 130>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@3 { + compatible = "st,stm32-timer-trigger"; + reg = <3>; + status = "disabled"; + }; + }; + timer5: timer@40000c00 { compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; @@ -102,6 +165,27 @@ clocks = <&rcc 0 131>; };
+ timers5: timers@40000c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000C00 0x400>; + clocks = <&rcc 0 131>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@4 { + compatible = "st,stm32-timer-trigger"; + reg = <4>; + status = "disabled"; + }; + }; + timer6: timer@40001000 { compatible = "st,stm32-timer"; reg = <0x40001000 0x400>; @@ -110,6 +194,22 @@ status = "disabled"; };
+ timers6: timers@40001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001000 0x400>; + clocks = <&rcc 0 132>; + clock-names = "int"; + status = "disabled"; + + timer@5 { + compatible = "st,stm32-timer-trigger"; + reg = <5>; + status = "disabled"; + }; + }; + timer7: timer@40001400 { compatible = "st,stm32-timer"; reg = <0x40001400 0x400>; @@ -118,6 +218,73 @@ status = "disabled"; };
+ timers7: timers@40001400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001400 0x400>; + clocks = <&rcc 0 133>; + clock-names = "int"; + status = "disabled"; + + timer@6 { + compatible = "st,stm32-timer-trigger"; + reg = <6>; + status = "disabled"; + }; + }; + + timers12: timers@40001800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001800 0x400>; + clocks = <&rcc 0 134>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@11 { + compatible = "st,stm32-timer-trigger"; + reg = <11>; + status = "disabled"; + }; + }; + + timers13: timers@40001c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001C00 0x400>; + clocks = <&rcc 0 135>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + }; + + timers14: timers@40002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40002000 0x400>; + clocks = <&rcc 0 136>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + }; + usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; @@ -169,6 +336,48 @@ status = "disabled"; };
+ timers1: timers@40010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40010000 0x400>; + clocks = <&rcc 0 160>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@0 { + compatible = "st,stm32-timer-trigger"; + reg = <0>; + status = "disabled"; + }; + }; + + timers8: timers@40010400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40010400 0x400>; + clocks = <&rcc 0 161>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@7 { + compatible = "st,stm32-timer-trigger"; + reg = <7>; + status = "disabled"; + }; + }; + usart1: serial@40011000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011000 0x400>; @@ -201,6 +410,57 @@ interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; };
+ timers9: timers@40014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40014000 0x400>; + clocks = <&rcc 0 176>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@8 { + compatible = "st,stm32-timer-trigger"; + reg = <8>; + status = "disabled"; + }; + }; + + timers10: timers@40014400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40014400 0x400>; + clocks = <&rcc 0 177>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + }; + + timers11: timers@40014800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40014800 0x400>; + clocks = <&rcc 0 178>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + }; + pwrcfg: power-config@40007000 { compatible = "syscon"; reg = <0x40007000 0x400>; @@ -355,6 +615,21 @@ slew-rate = <2>; }; }; + + pwm1_pins: pwm@1 { + pins { + pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>, + <STM32F429_PB13_FUNC_TIM1_CH1N>, + <STM32F429_PB12_FUNC_TIM1_BKIN>; + }; + }; + + pwm3_pins: pwm@3 { + pins { + pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>, + <STM32F429_PB5_FUNC_TIM3_CH2>; + }; + }; };
rcc: rcc@40023810 {
Hi Benjamin,
On 01/20/2017 10:15 AM, Benjamin Gaignard wrote:
Add Timers and it sub-nodes into DT for stm32f429 family.
version 9:
- re-order timers node per addresses
version 6:
- split patch in two: one for SoC family and one for stm32f469 discovery board.
version 5:
- rename gptimer node to timers
- re-order timers node per addresses
version 4:
- remove unwanted indexing in pwm@ and timer@ node name
- use "reg" instead of additional parameters to set timer configuration
version 3:
- use "st,stm32-timer-trigger" in DT
version 2:
- use parameters to describe hardware capabilities
- do not use references for pwm and iio timer subnodes
Signed-off-by: Benjamin Gaignard benjamin.gaignard@st.com
arch/arm/boot/dts/stm32f429.dtsi | 275 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 275 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index e4dae0e..b608935 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -79,6 +79,27 @@ status = "disabled"; };
timers2: timers@40000000 {#address-cells = <1>;#size-cells = <0>;compatible = "st,stm32-timers";reg = <0x40000000 0x400>;clocks = <&rcc 0 128>;clock-names = "int";status = "disabled";pwm {compatible = "st,stm32-pwm";status = "disabled";};timer@1 {compatible = "st,stm32-timer-trigger";reg = <1>;status = "disabled";};};- timer3: timer@40000400 { compatible = "st,stm32-timer"; reg = <0x40000400 0x400>;
@@ -87,6 +108,27 @@ status = "disabled"; };
timers3: timers@40000400 {#address-cells = <1>;#size-cells = <0>;compatible = "st,stm32-timers";reg = <0x40000400 0x400>;clocks = <&rcc 0 129>;clock-names = "int";status = "disabled";pwm {compatible = "st,stm32-pwm";status = "disabled";};timer@2 {compatible = "st,stm32-timer-trigger";reg = <2>;status = "disabled";};};- timer4: timer@40000800 { compatible = "st,stm32-timer"; reg = <0x40000800 0x400>;
@@ -95,6 +137,27 @@ status = "disabled"; };
timers4: timers@40000800 {#address-cells = <1>;#size-cells = <0>;compatible = "st,stm32-timers";reg = <0x40000800 0x400>;clocks = <&rcc 0 130>;clock-names = "int";status = "disabled";pwm {compatible = "st,stm32-pwm";status = "disabled";};timer@3 {compatible = "st,stm32-timer-trigger";reg = <3>;status = "disabled";};};- timer5: timer@40000c00 { compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>;
@@ -102,6 +165,27 @@ clocks = <&rcc 0 131>; };
timers5: timers@40000c00 {#address-cells = <1>;#size-cells = <0>;compatible = "st,stm32-timers";reg = <0x40000C00 0x400>;clocks = <&rcc 0 131>;clock-names = "int";status = "disabled";pwm {compatible = "st,stm32-pwm";status = "disabled";};timer@4 {compatible = "st,stm32-timer-trigger";reg = <4>;status = "disabled";};};- timer6: timer@40001000 { compatible = "st,stm32-timer"; reg = <0x40001000 0x400>;
@@ -110,6 +194,22 @@ status = "disabled"; };
timers6: timers@40001000 {#address-cells = <1>;#size-cells = <0>;compatible = "st,stm32-timers";reg = <0x40001000 0x400>;clocks = <&rcc 0 132>;clock-names = "int";status = "disabled";timer@5 {compatible = "st,stm32-timer-trigger";reg = <5>;status = "disabled";};};- timer7: timer@40001400 { compatible = "st,stm32-timer"; reg = <0x40001400 0x400>;
@@ -118,6 +218,73 @@ status = "disabled"; };
timers7: timers@40001400 {#address-cells = <1>;#size-cells = <0>;compatible = "st,stm32-timers";reg = <0x40001400 0x400>;clocks = <&rcc 0 133>;clock-names = "int";status = "disabled";timer@6 {compatible = "st,stm32-timer-trigger";reg = <6>;status = "disabled";};};timers12: timers@40001800 {#address-cells = <1>;#size-cells = <0>;compatible = "st,stm32-timers";reg = <0x40001800 0x400>;clocks = <&rcc 0 134>;clock-names = "int";status = "disabled";pwm {compatible = "st,stm32-pwm";status = "disabled";};timer@11 {compatible = "st,stm32-timer-trigger";reg = <11>;status = "disabled";};};timers13: timers@40001c00 {#address-cells = <1>;#size-cells = <0>;compatible = "st,stm32-timers";reg = <0x40001C00 0x400>;clocks = <&rcc 0 135>;clock-names = "int";status = "disabled";pwm {compatible = "st,stm32-pwm";status = "disabled";};};timers14: timers@40002000 {#address-cells = <1>;#size-cells = <0>;compatible = "st,stm32-timers";reg = <0x40002000 0x400>;clocks = <&rcc 0 136>;clock-names = "int";status = "disabled";pwm {compatible = "st,stm32-pwm";status = "disabled";};};- usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>;
@@ -169,6 +336,48 @@ status = "disabled"; };
timers1: timers@40010000 {#address-cells = <1>;#size-cells = <0>;compatible = "st,stm32-timers";reg = <0x40010000 0x400>;clocks = <&rcc 0 160>;clock-names = "int";status = "disabled";pwm {compatible = "st,stm32-pwm";status = "disabled";};timer@0 {compatible = "st,stm32-timer-trigger";reg = <0>;status = "disabled";};};timers8: timers@40010400 {#address-cells = <1>;#size-cells = <0>;compatible = "st,stm32-timers";reg = <0x40010400 0x400>;clocks = <&rcc 0 161>;clock-names = "int";status = "disabled";pwm {compatible = "st,stm32-pwm";status = "disabled";};timer@7 {compatible = "st,stm32-timer-trigger";reg = <7>;status = "disabled";};};- usart1: serial@40011000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011000 0x400>;
@@ -201,6 +410,57 @@ interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; };
timers9: timers@40014000 {#address-cells = <1>;#size-cells = <0>;compatible = "st,stm32-timers";reg = <0x40014000 0x400>;clocks = <&rcc 0 176>;clock-names = "int";status = "disabled";pwm {compatible = "st,stm32-pwm";status = "disabled";};timer@8 {compatible = "st,stm32-timer-trigger";reg = <8>;status = "disabled";};};timers10: timers@40014400 {#address-cells = <1>;#size-cells = <0>;compatible = "st,stm32-timers";reg = <0x40014400 0x400>;clocks = <&rcc 0 177>;clock-names = "int";status = "disabled";pwm {compatible = "st,stm32-pwm";status = "disabled";};};timers11: timers@40014800 {#address-cells = <1>;#size-cells = <0>;compatible = "st,stm32-timers";reg = <0x40014800 0x400>;clocks = <&rcc 0 178>;clock-names = "int";status = "disabled";pwm {compatible = "st,stm32-pwm";status = "disabled";};};- pwrcfg: power-config@40007000 { compatible = "syscon"; reg = <0x40007000 0x400>;
@@ -355,6 +615,21 @@ slew-rate = <2>; }; };
pwm1_pins: pwm@1 {pins {pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>,<STM32F429_PB13_FUNC_TIM1_CH1N>,<STM32F429_PB12_FUNC_TIM1_BKIN>;};};pwm3_pins: pwm@3 {pins {pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>,<STM32F429_PB5_FUNC_TIM3_CH2>;};};};
rcc: rcc@40023810 {
Acked-by: Alexandre TORGUE alexandre.torgue@st.com
Thanks! Alex
Define and enable pwm1 and pwm3 for stm32f469 discovery board
Signed-off-by: Benjamin Gaignard benjamin.gaignard@st.com --- arch/arm/boot/dts/stm32f469-disco.dts | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts index 8a163d7..92552d3 100644 --- a/arch/arm/boot/dts/stm32f469-disco.dts +++ b/arch/arm/boot/dts/stm32f469-disco.dts @@ -81,3 +81,31 @@ &usart3 { status = "okay"; }; + +&timers1 { + status = "okay"; + + pwm { + pinctrl-0 = <&pwm1_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + timer@0 { + status = "okay"; + }; +}; + +&timers3 { + status = "okay"; + + pwm { + pinctrl-0 = <&pwm3_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + timer@2 { + status = "okay"; + }; +};
Hi Benjamin,
On 01/20/2017 10:15 AM, Benjamin Gaignard wrote:
Define and enable pwm1 and pwm3 for stm32f469 discovery board
Signed-off-by: Benjamin Gaignard benjamin.gaignard@st.com
arch/arm/boot/dts/stm32f469-disco.dts | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts index 8a163d7..92552d3 100644 --- a/arch/arm/boot/dts/stm32f469-disco.dts +++ b/arch/arm/boot/dts/stm32f469-disco.dts @@ -81,3 +81,31 @@ &usart3 { status = "okay"; };
+&timers1 {
- status = "okay";
- pwm {
pinctrl-0 = <&pwm1_pins>;pinctrl-names = "default";status = "okay";- };
- timer@0 {
status = "okay";- };
+};
+&timers3 {
- status = "okay";
- pwm {
pinctrl-0 = <&pwm3_pins>;pinctrl-names = "default";status = "okay";- };
- timer@2 {
status = "okay";- };
+};
Acked-by: Alexandre TORGUE alexandre.torgue@st.com
Thanks Alex
Arm, IIO and PWM Maintainers,
Enjoy!
The following changes since commit 7ce7d89f48834cefece7804d38fc5d85382edf77:
Linux 4.10-rc1 (2016-12-25 16:13:08 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git ib-mfd-arm-iio-pwm-v4.10
for you to fetch changes up to 94df449273475980a39f1bf47f1e3d2b07ce6577:
ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco (2017-01-23 12:06:28 +0000)
---------------------------------------------------------------- Immutable branch between MFD, ARM, IIO and PWM due for the v4.10 merge window
---------------------------------------------------------------- Benjamin Gaignard (8): dt-bindings: mfd: Add bindings for STM32 Timers driver mfd: Add STM32 Timers driver dt-bindings: pwm: Add STM32 bindings pwm: Add driver for STM32 plaftorm iio: Add bindings for STM32 timer trigger driver iio: Add STM32 timer trigger driver ARM: dts: stm32: add Timers driver for stm32f429 MCU ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco
.../ABI/testing/sysfs-bus-iio-timer-stm32 | 29 ++ .../bindings/iio/timer/stm32-timer-trigger.txt | 23 ++ .../devicetree/bindings/mfd/stm32-timers.txt | 46 +++ .../devicetree/bindings/pwm/pwm-stm32.txt | 35 ++ arch/arm/boot/dts/stm32f429.dtsi | 275 ++++++++++++++ arch/arm/boot/dts/stm32f469-disco.dts | 28 ++ drivers/iio/trigger/Kconfig | 9 + drivers/iio/trigger/Makefile | 1 + drivers/iio/trigger/stm32-timer-trigger.c | 342 ++++++++++++++++++ drivers/mfd/Kconfig | 11 + drivers/mfd/Makefile | 2 + drivers/mfd/stm32-timers.c | 80 +++++ drivers/pwm/Kconfig | 9 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-stm32.c | 398 +++++++++++++++++++++ include/linux/iio/timer/stm32-timer-trigger.h | 62 ++++ include/linux/mfd/stm32-timers.h | 71 ++++ 17 files changed, 1422 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timers.txt create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt create mode 100644 drivers/iio/trigger/stm32-timer-trigger.c create mode 100644 drivers/mfd/stm32-timers.c create mode 100644 drivers/pwm/pwm-stm32.c create mode 100644 include/linux/iio/timer/stm32-timer-trigger.h create mode 100644 include/linux/mfd/stm32-timers.h
Hi Lee,
On Mon, Jan 23, 2017 at 4:12 AM, Lee Jones lee.jones@linaro.org wrote:
Arm, IIO and PWM Maintainers,
Enjoy!
The following changes since commit 7ce7d89f48834cefece7804d38fc5d85382edf77:
Linux 4.10-rc1 (2016-12-25 16:13:08 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git ib-mfd-arm-iio-pwm-v4.10
for you to fetch changes up to 94df449273475980a39f1bf47f1e3d2b07ce6577:
ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco (2017-01-23 12:06:28 +0000)
Immutable branch between MFD, ARM, IIO and PWM due for the v4.10 merge window
Benjamin Gaignard (8): dt-bindings: mfd: Add bindings for STM32 Timers driver mfd: Add STM32 Timers driver dt-bindings: pwm: Add STM32 bindings pwm: Add driver for STM32 plaftorm iio: Add bindings for STM32 timer trigger driver iio: Add STM32 timer trigger driver ARM: dts: stm32: add Timers driver for stm32f429 MCU ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco
.../ABI/testing/sysfs-bus-iio-timer-stm32 | 29 ++ .../bindings/iio/timer/stm32-timer-trigger.txt | 23 ++ .../devicetree/bindings/mfd/stm32-timers.txt | 46 +++ .../devicetree/bindings/pwm/pwm-stm32.txt | 35 ++ arch/arm/boot/dts/stm32f429.dtsi | 275 ++++++++++++++ arch/arm/boot/dts/stm32f469-disco.dts | 28 ++ drivers/iio/trigger/Kconfig | 9 + drivers/iio/trigger/Makefile | 1 + drivers/iio/trigger/stm32-timer-trigger.c | 342 ++++++++++++++++++ drivers/mfd/Kconfig | 11 + drivers/mfd/Makefile | 2 + drivers/mfd/stm32-timers.c | 80 +++++ drivers/pwm/Kconfig | 9 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-stm32.c | 398 +++++++++++++++++++++ include/linux/iio/timer/stm32-timer-trigger.h | 62 ++++ include/linux/mfd/stm32-timers.h | 71 ++++ 17 files changed, 1422 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timers.txt create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt create mode 100644 drivers/iio/trigger/stm32-timer-trigger.c create mode 100644 drivers/mfd/stm32-timers.c create mode 100644 drivers/pwm/pwm-stm32.c create mode 100644 include/linux/iio/timer/stm32-timer-trigger.h create mode 100644 include/linux/mfd/stm32-timers.h
May I ask why you're creating an immutable branch of all this contents?
We should get the dts/dtsi contents like usual from any maintainer; just the DT updates in a branch.
Sometimes (but less and less due to us discouraging the use) we need an immutable branch that includes dt-include updates. But I don't see any of those in this contents.
I.e. I guess I can see the need between mfd and downstream trees (iio/pwm), but not the DTS contents at this time. Or am I missing something here?
-Olof
On Mon, 23 Jan 2017, Olof Johansson wrote:
On Mon, Jan 23, 2017 at 4:12 AM, Lee Jones lee.jones@linaro.org wrote:
Arm, IIO and PWM Maintainers,
Enjoy!
The following changes since commit 7ce7d89f48834cefece7804d38fc5d85382edf77:
Linux 4.10-rc1 (2016-12-25 16:13:08 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git ib-mfd-arm-iio-pwm-v4.10
for you to fetch changes up to 94df449273475980a39f1bf47f1e3d2b07ce6577:
ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco (2017-01-23 12:06:28 +0000)
Immutable branch between MFD, ARM, IIO and PWM due for the v4.10 merge window
Benjamin Gaignard (8): dt-bindings: mfd: Add bindings for STM32 Timers driver mfd: Add STM32 Timers driver dt-bindings: pwm: Add STM32 bindings pwm: Add driver for STM32 plaftorm iio: Add bindings for STM32 timer trigger driver iio: Add STM32 timer trigger driver ARM: dts: stm32: add Timers driver for stm32f429 MCU ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco
.../ABI/testing/sysfs-bus-iio-timer-stm32 | 29 ++ .../bindings/iio/timer/stm32-timer-trigger.txt | 23 ++ .../devicetree/bindings/mfd/stm32-timers.txt | 46 +++ .../devicetree/bindings/pwm/pwm-stm32.txt | 35 ++ arch/arm/boot/dts/stm32f429.dtsi | 275 ++++++++++++++ arch/arm/boot/dts/stm32f469-disco.dts | 28 ++ drivers/iio/trigger/Kconfig | 9 + drivers/iio/trigger/Makefile | 1 + drivers/iio/trigger/stm32-timer-trigger.c | 342 ++++++++++++++++++ drivers/mfd/Kconfig | 11 + drivers/mfd/Makefile | 2 + drivers/mfd/stm32-timers.c | 80 +++++ drivers/pwm/Kconfig | 9 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-stm32.c | 398 +++++++++++++++++++++ include/linux/iio/timer/stm32-timer-trigger.h | 62 ++++ include/linux/mfd/stm32-timers.h | 71 ++++ 17 files changed, 1422 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timers.txt create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt create mode 100644 drivers/iio/trigger/stm32-timer-trigger.c create mode 100644 drivers/mfd/stm32-timers.c create mode 100644 drivers/pwm/pwm-stm32.c create mode 100644 include/linux/iio/timer/stm32-timer-trigger.h create mode 100644 include/linux/mfd/stm32-timers.h
May I ask why you're creating an immutable branch of all this contents?
We should get the dts/dtsi contents like usual from any maintainer; just the DT updates in a branch.
Sometimes (but less and less due to us discouraging the use) we need an immutable branch that includes dt-include updates. But I don't see any of those in this contents.
I.e. I guess I can see the need between mfd and downstream trees (iio/pwm), but not the DTS contents at this time. Or am I missing something here?
I agree with you. However, since one of the STM32 Maintainers Acked the DTS patches, and the other one hasn't been heard from for months, I took that to mean he wanted me to apply and take them through the MFD tree.
A misunderstanding or misaction perhaps, but this is the normal assumption.
On Tue, Jan 24, 2017 at 12:12 AM, Lee Jones lee.jones@linaro.org wrote:
On Mon, 23 Jan 2017, Olof Johansson wrote:
On Mon, Jan 23, 2017 at 4:12 AM, Lee Jones lee.jones@linaro.org wrote:
Arm, IIO and PWM Maintainers,
Enjoy!
The following changes since commit 7ce7d89f48834cefece7804d38fc5d85382edf77:
Linux 4.10-rc1 (2016-12-25 16:13:08 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git ib-mfd-arm-iio-pwm-v4.10
for you to fetch changes up to 94df449273475980a39f1bf47f1e3d2b07ce6577:
ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco (2017-01-23 12:06:28 +0000)
Immutable branch between MFD, ARM, IIO and PWM due for the v4.10 merge window
Benjamin Gaignard (8): dt-bindings: mfd: Add bindings for STM32 Timers driver mfd: Add STM32 Timers driver dt-bindings: pwm: Add STM32 bindings pwm: Add driver for STM32 plaftorm iio: Add bindings for STM32 timer trigger driver iio: Add STM32 timer trigger driver ARM: dts: stm32: add Timers driver for stm32f429 MCU ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco
.../ABI/testing/sysfs-bus-iio-timer-stm32 | 29 ++ .../bindings/iio/timer/stm32-timer-trigger.txt | 23 ++ .../devicetree/bindings/mfd/stm32-timers.txt | 46 +++ .../devicetree/bindings/pwm/pwm-stm32.txt | 35 ++ arch/arm/boot/dts/stm32f429.dtsi | 275 ++++++++++++++ arch/arm/boot/dts/stm32f469-disco.dts | 28 ++ drivers/iio/trigger/Kconfig | 9 + drivers/iio/trigger/Makefile | 1 + drivers/iio/trigger/stm32-timer-trigger.c | 342 ++++++++++++++++++ drivers/mfd/Kconfig | 11 + drivers/mfd/Makefile | 2 + drivers/mfd/stm32-timers.c | 80 +++++ drivers/pwm/Kconfig | 9 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-stm32.c | 398 +++++++++++++++++++++ include/linux/iio/timer/stm32-timer-trigger.h | 62 ++++ include/linux/mfd/stm32-timers.h | 71 ++++ 17 files changed, 1422 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timers.txt create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt create mode 100644 drivers/iio/trigger/stm32-timer-trigger.c create mode 100644 drivers/mfd/stm32-timers.c create mode 100644 drivers/pwm/pwm-stm32.c create mode 100644 include/linux/iio/timer/stm32-timer-trigger.h create mode 100644 include/linux/mfd/stm32-timers.h
May I ask why you're creating an immutable branch of all this contents?
We should get the dts/dtsi contents like usual from any maintainer; just the DT updates in a branch.
Sometimes (but less and less due to us discouraging the use) we need an immutable branch that includes dt-include updates. But I don't see any of those in this contents.
I.e. I guess I can see the need between mfd and downstream trees (iio/pwm), but not the DTS contents at this time. Or am I missing something here?
I agree with you. However, since one of the STM32 Maintainers Acked the DTS patches, and the other one hasn't been heard from for months, I took that to mean he wanted me to apply and take them through the MFD tree.
A misunderstanding or misaction perhaps, but this is the normal assumption.
It seems to be a misunderstanding in this case, since there are other additions in the stm32 tree this release cycle so we should only pick up DTS changes through our tree.
By now, I think it should be pretty well known that we nearly never want DTS contents merged through any other tree. Ever.
So, please revoke your branch and take those out. We'll take them through the normal flow. Thanks!
-Olof
Jonathan, Thierry,
On Tue, 24 Jan 2017, Olof Johansson wrote:
On Tue, Jan 24, 2017 at 12:12 AM, Lee Jones lee.jones@linaro.org wrote:
On Mon, 23 Jan 2017, Olof Johansson wrote:
On Mon, Jan 23, 2017 at 4:12 AM, Lee Jones lee.jones@linaro.org wrote:
Arm, IIO and PWM Maintainers,
Enjoy!
The following changes since commit 7ce7d89f48834cefece7804d38fc5d85382edf77:
Linux 4.10-rc1 (2016-12-25 16:13:08 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git ib-mfd-arm-iio-pwm-v4.10
for you to fetch changes up to 94df449273475980a39f1bf47f1e3d2b07ce6577:
ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco (2017-01-23 12:06:28 +0000)
Immutable branch between MFD, ARM, IIO and PWM due for the v4.10 merge window
Benjamin Gaignard (8): dt-bindings: mfd: Add bindings for STM32 Timers driver mfd: Add STM32 Timers driver dt-bindings: pwm: Add STM32 bindings pwm: Add driver for STM32 plaftorm iio: Add bindings for STM32 timer trigger driver iio: Add STM32 timer trigger driver ARM: dts: stm32: add Timers driver for stm32f429 MCU ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco
.../ABI/testing/sysfs-bus-iio-timer-stm32 | 29 ++ .../bindings/iio/timer/stm32-timer-trigger.txt | 23 ++ .../devicetree/bindings/mfd/stm32-timers.txt | 46 +++ .../devicetree/bindings/pwm/pwm-stm32.txt | 35 ++ arch/arm/boot/dts/stm32f429.dtsi | 275 ++++++++++++++ arch/arm/boot/dts/stm32f469-disco.dts | 28 ++ drivers/iio/trigger/Kconfig | 9 + drivers/iio/trigger/Makefile | 1 + drivers/iio/trigger/stm32-timer-trigger.c | 342 ++++++++++++++++++ drivers/mfd/Kconfig | 11 + drivers/mfd/Makefile | 2 + drivers/mfd/stm32-timers.c | 80 +++++ drivers/pwm/Kconfig | 9 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-stm32.c | 398 +++++++++++++++++++++ include/linux/iio/timer/stm32-timer-trigger.h | 62 ++++ include/linux/mfd/stm32-timers.h | 71 ++++ 17 files changed, 1422 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timers.txt create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt create mode 100644 drivers/iio/trigger/stm32-timer-trigger.c create mode 100644 drivers/mfd/stm32-timers.c create mode 100644 drivers/pwm/pwm-stm32.c create mode 100644 include/linux/iio/timer/stm32-timer-trigger.h create mode 100644 include/linux/mfd/stm32-timers.h
May I ask why you're creating an immutable branch of all this contents?
We should get the dts/dtsi contents like usual from any maintainer; just the DT updates in a branch.
Sometimes (but less and less due to us discouraging the use) we need an immutable branch that includes dt-include updates. But I don't see any of those in this contents.
I.e. I guess I can see the need between mfd and downstream trees (iio/pwm), but not the DTS contents at this time. Or am I missing something here?
I agree with you. However, since one of the STM32 Maintainers Acked the DTS patches, and the other one hasn't been heard from for months, I took that to mean he wanted me to apply and take them through the MFD tree.
A misunderstanding or misaction perhaps, but this is the normal assumption.
It seems to be a misunderstanding in this case, since there are other additions in the stm32 tree this release cycle so we should only pick up DTS changes through our tree.
By now, I think it should be pretty well known that we nearly never want DTS contents merged through any other tree. Ever.
So, please revoke your branch and take those out. We'll take them through the normal flow. Thanks!
That okay with you?
On Wed, Jan 25, 2017 at 10:08:58AM +0000, Lee Jones wrote:
Jonathan, Thierry,
On Tue, 24 Jan 2017, Olof Johansson wrote:
On Tue, Jan 24, 2017 at 12:12 AM, Lee Jones lee.jones@linaro.org wrote:
On Mon, 23 Jan 2017, Olof Johansson wrote:
On Mon, Jan 23, 2017 at 4:12 AM, Lee Jones lee.jones@linaro.org wrote:
Arm, IIO and PWM Maintainers,
Enjoy!
The following changes since commit 7ce7d89f48834cefece7804d38fc5d85382edf77:
Linux 4.10-rc1 (2016-12-25 16:13:08 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git ib-mfd-arm-iio-pwm-v4.10
for you to fetch changes up to 94df449273475980a39f1bf47f1e3d2b07ce6577:
ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco (2017-01-23 12:06:28 +0000)
Immutable branch between MFD, ARM, IIO and PWM due for the v4.10 merge window
Benjamin Gaignard (8): dt-bindings: mfd: Add bindings for STM32 Timers driver mfd: Add STM32 Timers driver dt-bindings: pwm: Add STM32 bindings pwm: Add driver for STM32 plaftorm iio: Add bindings for STM32 timer trigger driver iio: Add STM32 timer trigger driver ARM: dts: stm32: add Timers driver for stm32f429 MCU ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco
.../ABI/testing/sysfs-bus-iio-timer-stm32 | 29 ++ .../bindings/iio/timer/stm32-timer-trigger.txt | 23 ++ .../devicetree/bindings/mfd/stm32-timers.txt | 46 +++ .../devicetree/bindings/pwm/pwm-stm32.txt | 35 ++ arch/arm/boot/dts/stm32f429.dtsi | 275 ++++++++++++++ arch/arm/boot/dts/stm32f469-disco.dts | 28 ++ drivers/iio/trigger/Kconfig | 9 + drivers/iio/trigger/Makefile | 1 + drivers/iio/trigger/stm32-timer-trigger.c | 342 ++++++++++++++++++ drivers/mfd/Kconfig | 11 + drivers/mfd/Makefile | 2 + drivers/mfd/stm32-timers.c | 80 +++++ drivers/pwm/Kconfig | 9 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-stm32.c | 398 +++++++++++++++++++++ include/linux/iio/timer/stm32-timer-trigger.h | 62 ++++ include/linux/mfd/stm32-timers.h | 71 ++++ 17 files changed, 1422 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timers.txt create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt create mode 100644 drivers/iio/trigger/stm32-timer-trigger.c create mode 100644 drivers/mfd/stm32-timers.c create mode 100644 drivers/pwm/pwm-stm32.c create mode 100644 include/linux/iio/timer/stm32-timer-trigger.h create mode 100644 include/linux/mfd/stm32-timers.h
May I ask why you're creating an immutable branch of all this contents?
We should get the dts/dtsi contents like usual from any maintainer; just the DT updates in a branch.
Sometimes (but less and less due to us discouraging the use) we need an immutable branch that includes dt-include updates. But I don't see any of those in this contents.
I.e. I guess I can see the need between mfd and downstream trees (iio/pwm), but not the DTS contents at this time. Or am I missing something here?
I agree with you. However, since one of the STM32 Maintainers Acked the DTS patches, and the other one hasn't been heard from for months, I took that to mean he wanted me to apply and take them through the MFD tree.
A misunderstanding or misaction perhaps, but this is the normal assumption.
It seems to be a misunderstanding in this case, since there are other additions in the stm32 tree this release cycle so we should only pick up DTS changes through our tree.
By now, I think it should be pretty well known that we nearly never want DTS contents merged through any other tree. Ever.
So, please revoke your branch and take those out. We'll take them through the normal flow. Thanks!
That okay with you?
Do you still want to carry the PWM patches in your tree? Or should they all just be picked up into the respective subsystem trees, then?
Either way is fine with me.
Thierry
On Wed, 25 Jan 2017, Thierry Reding wrote:
On Wed, Jan 25, 2017 at 10:08:58AM +0000, Lee Jones wrote:
Jonathan, Thierry,
On Tue, 24 Jan 2017, Olof Johansson wrote:
On Tue, Jan 24, 2017 at 12:12 AM, Lee Jones lee.jones@linaro.org wrote:
On Mon, 23 Jan 2017, Olof Johansson wrote:
On Mon, Jan 23, 2017 at 4:12 AM, Lee Jones lee.jones@linaro.org wrote:
Arm, IIO and PWM Maintainers,
Enjoy!
The following changes since commit 7ce7d89f48834cefece7804d38fc5d85382edf77:
Linux 4.10-rc1 (2016-12-25 16:13:08 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git ib-mfd-arm-iio-pwm-v4.10
for you to fetch changes up to 94df449273475980a39f1bf47f1e3d2b07ce6577:
ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco (2017-01-23 12:06:28 +0000)
Immutable branch between MFD, ARM, IIO and PWM due for the v4.10 merge window
Benjamin Gaignard (8): dt-bindings: mfd: Add bindings for STM32 Timers driver mfd: Add STM32 Timers driver dt-bindings: pwm: Add STM32 bindings pwm: Add driver for STM32 plaftorm iio: Add bindings for STM32 timer trigger driver iio: Add STM32 timer trigger driver ARM: dts: stm32: add Timers driver for stm32f429 MCU ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco
.../ABI/testing/sysfs-bus-iio-timer-stm32 | 29 ++ .../bindings/iio/timer/stm32-timer-trigger.txt | 23 ++ .../devicetree/bindings/mfd/stm32-timers.txt | 46 +++ .../devicetree/bindings/pwm/pwm-stm32.txt | 35 ++ arch/arm/boot/dts/stm32f429.dtsi | 275 ++++++++++++++ arch/arm/boot/dts/stm32f469-disco.dts | 28 ++ drivers/iio/trigger/Kconfig | 9 + drivers/iio/trigger/Makefile | 1 + drivers/iio/trigger/stm32-timer-trigger.c | 342 ++++++++++++++++++ drivers/mfd/Kconfig | 11 + drivers/mfd/Makefile | 2 + drivers/mfd/stm32-timers.c | 80 +++++ drivers/pwm/Kconfig | 9 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-stm32.c | 398 +++++++++++++++++++++ include/linux/iio/timer/stm32-timer-trigger.h | 62 ++++ include/linux/mfd/stm32-timers.h | 71 ++++ 17 files changed, 1422 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timers.txt create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt create mode 100644 drivers/iio/trigger/stm32-timer-trigger.c create mode 100644 drivers/mfd/stm32-timers.c create mode 100644 drivers/pwm/pwm-stm32.c create mode 100644 include/linux/iio/timer/stm32-timer-trigger.h create mode 100644 include/linux/mfd/stm32-timers.h
May I ask why you're creating an immutable branch of all this contents?
We should get the dts/dtsi contents like usual from any maintainer; just the DT updates in a branch.
Sometimes (but less and less due to us discouraging the use) we need an immutable branch that includes dt-include updates. But I don't see any of those in this contents.
I.e. I guess I can see the need between mfd and downstream trees (iio/pwm), but not the DTS contents at this time. Or am I missing something here?
I agree with you. However, since one of the STM32 Maintainers Acked the DTS patches, and the other one hasn't been heard from for months, I took that to mean he wanted me to apply and take them through the MFD tree.
A misunderstanding or misaction perhaps, but this is the normal assumption.
It seems to be a misunderstanding in this case, since there are other additions in the stm32 tree this release cycle so we should only pick up DTS changes through our tree.
By now, I think it should be pretty well known that we nearly never want DTS contents merged through any other tree. Ever.
So, please revoke your branch and take those out. We'll take them through the normal flow. Thanks!
That okay with you?
Do you still want to carry the PWM patches in your tree? Or should they all just be picked up into the respective subsystem trees, then?
Either way is fine with me.
I'm also happy either way. For ease, I guess we'll keep things as they are. I'll just drop the Arm patches and re-send the pull-request. This also gives us the opportunity to roll in Ben's recent fix.
On 25 January 2017 10:08:58 GMT+00:00, Lee Jones lee.jones@linaro.org wrote:
Jonathan, Thierry,
On Tue, 24 Jan 2017, Olof Johansson wrote:
On Tue, Jan 24, 2017 at 12:12 AM, Lee Jones lee.jones@linaro.org
wrote:
On Mon, 23 Jan 2017, Olof Johansson wrote:
On Mon, Jan 23, 2017 at 4:12 AM, Lee Jones lee.jones@linaro.org
wrote:
Arm, IIO and PWM Maintainers,
Enjoy!
The following changes since commit
7ce7d89f48834cefece7804d38fc5d85382edf77:
Linux 4.10-rc1 (2016-12-25 16:13:08 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git
ib-mfd-arm-iio-pwm-v4.10
for you to fetch changes up to
94df449273475980a39f1bf47f1e3d2b07ce6577:
ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco
(2017-01-23 12:06:28 +0000)
Immutable branch between MFD, ARM, IIO and PWM due for the v4.10
merge window
Benjamin Gaignard (8): dt-bindings: mfd: Add bindings for STM32 Timers driver mfd: Add STM32 Timers driver dt-bindings: pwm: Add STM32 bindings pwm: Add driver for STM32 plaftorm iio: Add bindings for STM32 timer trigger driver iio: Add STM32 timer trigger driver ARM: dts: stm32: add Timers driver for stm32f429 MCU ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco
.../ABI/testing/sysfs-bus-iio-timer-stm32 | 29 ++ .../bindings/iio/timer/stm32-timer-trigger.txt | 23 ++ .../devicetree/bindings/mfd/stm32-timers.txt | 46 +++ .../devicetree/bindings/pwm/pwm-stm32.txt | 35 ++ arch/arm/boot/dts/stm32f429.dtsi | 275
++++++++++++++
arch/arm/boot/dts/stm32f469-disco.dts | 28 ++ drivers/iio/trigger/Kconfig | 9 + drivers/iio/trigger/Makefile | 1 + drivers/iio/trigger/stm32-timer-trigger.c | 342
++++++++++++++++++
drivers/mfd/Kconfig | 11 + drivers/mfd/Makefile | 2 + drivers/mfd/stm32-timers.c | 80 +++++ drivers/pwm/Kconfig | 9 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-stm32.c | 398
+++++++++++++++++++++
include/linux/iio/timer/stm32-timer-trigger.h | 62 ++++ include/linux/mfd/stm32-timers.h | 71 ++++ 17 files changed, 1422 insertions(+) create mode 100644
Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
create mode 100644
Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
create mode 100644
Documentation/devicetree/bindings/mfd/stm32-timers.txt
create mode 100644
Documentation/devicetree/bindings/pwm/pwm-stm32.txt
create mode 100644 drivers/iio/trigger/stm32-timer-trigger.c create mode 100644 drivers/mfd/stm32-timers.c create mode 100644 drivers/pwm/pwm-stm32.c create mode 100644
include/linux/iio/timer/stm32-timer-trigger.h
create mode 100644 include/linux/mfd/stm32-timers.h
May I ask why you're creating an immutable branch of all this
contents?
We should get the dts/dtsi contents like usual from any
maintainer;
just the DT updates in a branch.
Sometimes (but less and less due to us discouraging the use) we
need
an immutable branch that includes dt-include updates. But I don't
see
any of those in this contents.
I.e. I guess I can see the need between mfd and downstream trees (iio/pwm), but not the DTS contents at this time. Or am I missing something here?
I agree with you. However, since one of the STM32 Maintainers
Acked
the DTS patches, and the other one hasn't been heard from for
months,
I took that to mean he wanted me to apply and take them through the MFD tree.
A misunderstanding or misaction perhaps, but this is the normal assumption.
It seems to be a misunderstanding in this case, since there are other additions in the stm32 tree this release cycle so we should only pick up DTS changes through our tree.
By now, I think it should be pretty well known that we nearly never want DTS contents merged through any other tree. Ever.
So, please revoke your branch and take those out. We'll take them through the normal flow. Thanks!
That okay with you?
Bit late from me but fine. I tend to only pull in these branches when stuff to go on top turns up. Not happened with this set yet!
J
As promised.
The following changes since commit 7ce7d89f48834cefece7804d38fc5d85382edf77:
Linux 4.10-rc1 (2016-12-25 16:13:08 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git ib-mfd-iio-pwm-4.11
for you to fetch changes up to 93fbe91b552194af970256ce72934745d01df435:
iio: Add STM32 timer trigger driver (2017-01-25 16:11:56 +0000)
---------------------------------------------------------------- Immutable branch between MFD, IIO and PWM due for the v4.11 merge window
---------------------------------------------------------------- Benjamin Gaignard (6): dt-bindings: mfd: Add bindings for STM32 Timers driver mfd: Add STM32 Timers driver dt-bindings: pwm: Add STM32 bindings pwm: Add driver for STM32 plaftorm iio: Add bindings for STM32 timer trigger driver iio: Add STM32 timer trigger driver
.../ABI/testing/sysfs-bus-iio-timer-stm32 | 29 ++ .../bindings/iio/timer/stm32-timer-trigger.txt | 23 ++ .../devicetree/bindings/mfd/stm32-timers.txt | 46 +++ .../devicetree/bindings/pwm/pwm-stm32.txt | 35 ++ drivers/iio/trigger/Kconfig | 9 + drivers/iio/trigger/Makefile | 1 + drivers/iio/trigger/stm32-timer-trigger.c | 342 ++++++++++++++++++ drivers/mfd/Kconfig | 11 + drivers/mfd/Makefile | 2 + drivers/mfd/stm32-timers.c | 80 +++++ drivers/pwm/Kconfig | 9 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-stm32.c | 397 +++++++++++++++++++++ include/linux/iio/timer/stm32-timer-trigger.h | 62 ++++ include/linux/mfd/stm32-timers.h | 71 ++++ 15 files changed, 1118 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timers.txt create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt create mode 100644 drivers/iio/trigger/stm32-timer-trigger.c create mode 100644 drivers/mfd/stm32-timers.c create mode 100644 drivers/pwm/pwm-stm32.c create mode 100644 include/linux/iio/timer/stm32-timer-trigger.h create mode 100644 include/linux/mfd/stm32-timers.h
linaro-kernel@lists.linaro.org
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Alexandre Torgue -
Benjamin Gaignard -
Jonathan Cameron -
Lee Jones -
Olof Johansson -
Thierry Reding