On Fri, Sep 06, 2013 at 02:59:08PM +0100, Peter Maydell wrote:

On 23 August 2013 21:10, Christoffer Dall christoffer.dall@linaro.org wrote:

...

For some reason only edge-triggered or enabled level-triggered interrupts would set the pending state of a raised IRQ. This is not in compliance with the specs, which indicate that the pending state is separate from the enabled state, which only controls if a pending interrupt is actually forwarded to the CPU interface.

Therefore, simply always set the pending state on a rising edge, but only clear the pending state of falling edge if the interrupt is level triggered.

Signed-off-by: Christoffer Dall christoffer.dall@linaro.org

hw/intc/arm_gic.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index d431b7a..bff3f9e 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -128,11 +128,12 @@ static void gic_set_irq(void *opaque, int irq, int level)

 if (level) {
     GIC_SET_LEVEL(irq, cm);

•    if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) {
  

•        DPRINTF("Set %d pending mask %x\n", irq, target);
  

•        GIC_SET_PENDING(irq, target);
  

•    }
  

•    DPRINTF("Set %d pending mask %x\n", irq, target);
  

•    GIC_SET_PENDING(irq, target);
  

  } else {

•    if (!GIC_TEST_TRIGGER(irq)) {
  

•        gic_clear_pending(s, irq, target, 0);
  

•    }
     GIC_CLEAR_LEVEL(irq, cm);
  

  } gic_update(s);

This doesn't compile:

hw/intc/arm_gic.c: In function ‘gic_set_irq’: hw/intc/arm_gic.c:135:13: error: implicit declaration of function ‘gic_clear_pending’ [-Werror=implicit-function-declaration] hw/intc/arm_gic.c:135:13: error: nested extern declaration of ‘gic_clear_pending’ [-Werror=nested-externs]

(you don't provide that function until patch 3).

whoops, should be GIC_CLEAR_PENDING at this stage. Thanks for testing the bisectability.

-Christoffer

On 23.08.2013, at 21:10, Christoffer Dall wrote:

To make the code slightly cleaner to look at and make the save/restore code easier to understand, introduce this macro to set the priority of interrupts.

Signed-off-by: Christoffer Dall christoffer.dall@linaro.org

hw/intc/arm_gic.c | 6 +----- hw/intc/gic_internal.h | 6 ++++++ 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index bff3f9e..a7bb528 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -444,11 +444,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, irq = (offset - 0x400) + GIC_BASE_IRQ; if (irq >= s->num_irq) goto bad_reg;

•    if (irq < GIC_INTERNAL) {
  

•        s->priority1[irq][cpu] = value;
  

•    } else {
  

•        s->priority2[irq - GIC_INTERNAL] = value;
  

•    }
  

•    GIC_SET_PRIORITY(irq, cpu, value);
  

  } else if (offset < 0xc00) { /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the * annoying exception of the 11MPCore's GIC.

diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 1426437..d835aa1 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -57,6 +57,12 @@ #define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \ s->priority1[irq][cpu] : \ s->priority2[(irq) - GIC_INTERNAL]) +#define GIC_SET_PRIORITY(irq, cpu, val) do { \

• uint8_t *__x = ((irq) < GIC_INTERNAL) ? \

•                &s->priority1[irq][cpu] : \
  

•                &s->priority2[(irq) - GIC_INTERNAL]; \
  

• *__x = val; \

+} while (0)

Why not make this a function?

Alex

#define GIC_TARGET(irq) s->irq_target[irq]

typedef struct gic_irq_state {

1.7.10.4

---

kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/cucslists/listinfo/kvmarm

On Fri, Sep 06, 2013 at 03:08:16PM +0100, Peter Maydell wrote:

On 23 August 2013 21:10, Christoffer Dall christoffer.dall@linaro.org wrote:

...

Right now the arm gic emulation doesn't keep track of the source of an SGI (which apparently Linux guests don't use, or they're fine with assuming CPU 0 always).

Add the necessary matrix on the GICState structure and maintain the data when setting and clearing the pending state of an IRQ.

Note that we always choose to present the source as the lowest-numbered CPU in case multiple cores have signalled the same SGI number to a core on the system.

...

@@ -525,6 +538,11 @@ static void gic_dist_writel(void *opaque, hwaddr offset, break; } GIC_SET_PENDING(irq, mask);

•    target_cpu = (unsigned)ffs(mask) - 1;
  

•    while (target_cpu < NCPU) {
  

•        s->sgi_source[irq][target_cpu] |= (1 << cpu);
  

•        target_cpu = (unsigned)ffs(mask) - 1;
  

•    }
  

This is an infinite loop, because you don't do anything with mask inside the loop, so target_cpu is always the same each time round. gcc with optimization is smart enough to notice this:

=> 0x00005555556c1625 <+229>: jmp 0x5555556c1625 <gic_dist_writel+229>

:-)

Unsurprisingly, my test vexpress-a9 image hangs on startup.

that's unfortunate, I think I meant to use find_next_bit and pass target_cpu, but ended up deciding to just clear the bit in the mask, but forgot to actually clear the bit. Whoops.

-Christoffer

...

--- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -71,6 +71,7 @@ static const VMStateDescription vmstate_gic = { VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, NCPU), VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL), VMSTATE_UINT16_2DARRAY(last_active, GICState, GIC_MAXIRQ, NCPU),

•    VMSTATE_UINT8_2DARRAY(sgi_source, GICState, GIC_NR_SGIS, NCPU),
     VMSTATE_UINT16_ARRAY(priority_mask, GICState, NCPU),
     VMSTATE_UINT16_ARRAY(running_irq, GICState, NCPU),
     VMSTATE_UINT16_ARRAY(running_priority, GICState, NCPU),
  

You need to bump the version_id and minimum_version_id if you add a new field here.

"arm_gic:" is sufficient, "hw/arm_gic:" if you see the need.

Am 23.08.2013 22:10, schrieb Christoffer Dall:

Add a binary_point field to the gic emulation structure and support setting/getting this register now when we have it. We don't actually support interrupt grouping yet, oh well.

Signed-off-by: Christoffer Dall christoffer.dall@linaro.org

hw/intc/arm_gic.c | 5 ++--- hw/intc/arm_gic_common.c | 1 + hw/intc/gic_internal.h | 3 +++ 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 4da534f..cb2004d 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -568,8 +568,7 @@ static uint32_t gic_cpu_read(GICState *s, int cpu, int offset) case 0x04: /* Priority mask */ return s->priority_mask[cpu]; case 0x08: /* Binary Point */

•    /* ??? Not implemented.  */
  

•    return 0;
  

•    return s->binary_point[0][cpu];
  

  case 0x0c: /* Acknowledge */ value = gic_acknowledge_irq(s, cpu); value |= (GIC_SGI_SRC(value, cpu) & 0x7) << 10;

@@ -596,7 +595,7 @@ static void gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value) s->priority_mask[cpu] = (value & 0xff); break; case 0x08: /* Binary Point */

•    /* ??? Not implemented.  */
  

•    s->binary_point[0][cpu] = (value & 0x7);
     break;
  

  case 0x10: /* End Of Interrupt */ return gic_complete_irq(s, cpu, value & 0x3ff);

diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index 7a1c9e5..a50ded2 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -76,6 +76,7 @@ static const VMStateDescription vmstate_gic = { VMSTATE_UINT16_ARRAY(running_irq, GICState, NCPU), VMSTATE_UINT16_ARRAY(running_priority, GICState, NCPU), VMSTATE_UINT16_ARRAY(current_pending, GICState, NCPU),

•    VMSTATE_UINT8_2DARRAY(binary_point, GICState, 2, NCPU),
     VMSTATE_END_OF_LIST()
  

  }

};

You can't just add VMState fields without bumping the version_id and marking the field as starting in that version. That breaks loadvm/migration format compatibility.

diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 6f04885..424a41f 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -98,6 +98,9 @@ typedef struct GICState { uint16_t running_priority[NCPU]; uint16_t current_pending[NCPU];

• /* these registers are mainly used for save/restore of KVM state */
• uint8_t binary_point[2][NCPU]; /* [0]: group 0, [1]: group 1 */

binary_point[1] is never used, but changing the VMState field from length 1 to length 2 is probably more difficult than having a few extra bytes here.

Regards, Andreas

• uint32_t num_cpu;

MemoryRegion iomem; /* Distributor */

On Fri, Sep 06, 2013 at 03:41:04PM +0100, Peter Maydell wrote:

On 23 August 2013 21:10, Christoffer Dall christoffer.dall@linaro.org wrote:

...

Add a binary_point field to the gic emulation structure and support setting/getting this register now when we have it. We don't actually support interrupt grouping yet, oh well.

Signed-off-by: Christoffer Dall christoffer.dall@linaro.org

hw/intc/arm_gic.c | 5 ++--- hw/intc/arm_gic_common.c | 1 + hw/intc/gic_internal.h | 3 +++ 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 4da534f..cb2004d 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -568,8 +568,7 @@ static uint32_t gic_cpu_read(GICState *s, int cpu, int offset) case 0x04: /* Priority mask */ return s->priority_mask[cpu]; case 0x08: /* Binary Point */

•    /* ??? Not implemented.  */
  

•    return 0;
  

•    return s->binary_point[0][cpu];
  

  case 0x0c: /* Acknowledge */ value = gic_acknowledge_irq(s, cpu); value |= (GIC_SGI_SRC(value, cpu) & 0x7) << 10;

@@ -596,7 +595,7 @@ static void gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value) s->priority_mask[cpu] = (value & 0xff); break; case 0x08: /* Binary Point */

•    /* ??? Not implemented.  */
  

•    s->binary_point[0][cpu] = (value & 0x7);
     break;
  

  case 0x10: /* End Of Interrupt */ return gic_complete_irq(s, cpu, value & 0x3ff);

diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index 7a1c9e5..a50ded2 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -76,6 +76,7 @@ static const VMStateDescription vmstate_gic = { VMSTATE_UINT16_ARRAY(running_irq, GICState, NCPU), VMSTATE_UINT16_ARRAY(running_priority, GICState, NCPU), VMSTATE_UINT16_ARRAY(current_pending, GICState, NCPU),

•    VMSTATE_UINT8_2DARRAY(binary_point, GICState, 2, NCPU),
     VMSTATE_END_OF_LIST()
  

  }

}; diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 6f04885..424a41f 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -98,6 +98,9 @@ typedef struct GICState { uint16_t running_priority[NCPU]; uint16_t current_pending[NCPU];

• /* these registers are mainly used for save/restore of KVM state */
• uint8_t binary_point[2][NCPU]; /* [0]: group 0, [1]: group 1 */

This looks a bit fishy. I think fundamentally we need to be clear about what kind of GIC we (and KVM) are exposing to the guest. I think that that is supposed to be "a v2 GIC without the Security Extensions", yes?

yes, at least that's what we export through the GICD_TYPER.

The other possible answer would be "a v2 GIC with the security extensions, but you're stuck in the NS world". The distinction is important, because it affects what state the guest can see. For v2-GIC-no-TZ, there are two registers' worth of state per CPU, accessible as GICC_BPR and GICC_ABPR. For v2-GIC-TZ, a guest stuck in the NS world only gets to see one register worth of state, ie the NS banked version of GICC_BPR (and GICC_ABPR is an alias of it). There is another register worth of state in the S banked GICC_BPR, but it's totally inaccessible to the guest.

I'm a little uneasy about what the GICV_ABPR actually lets the guest see, but as far as I can tell it is consistent with the v2-GIC-no-TZ because group 1 interrupts can be configured to inject virtual FIQs to the guest (not that we implement distributor support for that yet) so the GICC_ABPR accesses from the non-secure (and only) state will control group 1 interrupts if the GICC_CTLR.CBPR==0 and will just be ignored if GICC_CTLR.CBPR==1.

(Reading this part of the spec is not a particularly pleasent experience, especially the wording of the GICC_ABPR is funky, and it actually says that reading the GICC_ABPR reads the NS copy of GICC_IAR, which I think is a typo?)

The TCG QEMU GIC model is currently adopting the "GIC without Security Extensions" model, which implies that we should be implementing GIC_ABPR too. What model does KVM's in-kernel vGIC use? (ie what state does it put into binary_point[0] and [1] on save/load)?

We put whatever the guest writes into the GICV_BPR and GICV_ABPR, but the in-kernel distributor does not care about priorities at all and considers all interrupts to be group 0 interrupts, which just happens to work for Linux.

So yes, we should implement the GIC_ABPR, but there's no need for it yet. But, if I don't add these fields the guest will (by reading the GICC_[A]BPR registers) be able to tell it was migrated, but it will not influence anything on the distributor level. Therefore, by adding these fields we support the kernel's limited model fully without adding a bunch of code that we can't really test in real life anyhow, and it doesn't prevent us from adding full grouping support later on.

-Christoffer

Il 25/08/2013 17:47, Alexander Graf ha scritto:

On 23.08.2013, at 21:10, Christoffer Dall wrote:

...

Save and restore the ARM KVM VGIC state from the kernel. We rely on QEMU to marshal the GICState data structure and therefore simply synchronize the kernel state with the QEMU emulated state in both directions.

We take some care on the restore path to check the VGIC has been configured with enough IRQs and CPU interfaces that we can properly restore the state, and for separate set/clear registers we first fully clear the registers and then set the required bits.

Signed-off-by: Christoffer Dall christoffer.dall@linaro.org

hw/intc/arm_gic_common.c | 2 + hw/intc/arm_gic_kvm.c | 418 ++++++++++++++++++++++++++++++++++++++++++- hw/intc/gic_internal.h | 1 + include/migration/vmstate.h | 6 + 4 files changed, 425 insertions(+), 2 deletions(-)

diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index a50ded2..f39bdc1 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -77,6 +77,8 @@ static const VMStateDescription vmstate_gic = { VMSTATE_UINT16_ARRAY(running_priority, GICState, NCPU), VMSTATE_UINT16_ARRAY(current_pending, GICState, NCPU), VMSTATE_UINT8_2DARRAY(binary_point, GICState, 2, NCPU),

•    VMSTATE_UINT32_2DARRAY(active_prio, GICState, 4, NCPU),
  

•    VMSTATE_UINT32(num_irq, GICState),
    VMSTATE_END_OF_LIST()
  

  }

}; diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index 9f0a852..9785281 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -23,6 +23,15 @@ #include "kvm_arm.h" #include "gic_internal.h"

+//#define DEBUG_GIC_KVM

+#ifdef DEBUG_GIC_KVM +#define DPRINTF(fmt, ...) \ +do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0) +#else +#define DPRINTF(fmt, ...) do {} while(0)

You really want to make DPRINTF still be format checked by the compiler. Check out hw/intc/openpic.c for an example how to get there.

...

+#endif

#define TYPE_KVM_ARM_GIC "kvm-arm-gic" #define KVM_ARM_GIC(obj) \ OBJECT_CHECK(GICState, (obj), TYPE_KVM_ARM_GIC) @@ -73,14 +82,419 @@ static void kvm_arm_gic_set_irq(void *opaque, int irq, int level) kvm_set_irq(kvm_state, kvm_irq, !!level); }

+static bool kvm_arm_gic_can_save_restore(GICState *s) +{

• KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
• return kgc->dev_fd >= 0;

+}

+static void kvm_arm_gic_reg_access(GICState *s, int group, int offset,

•                               int cpu, uint32_t *val, bool write)
  

+{

• KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
• struct kvm_device_attr attr;
• int type;
• cpu = cpu & 0xff;
• attr.flags = 0;
• attr.group = group;
• attr.attr = (((uint64_t)cpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) &

•             KVM_DEV_ARM_VGIC_CPUID_MASK) |
  

•            (((uint64_t)offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) &
  

•             KVM_DEV_ARM_VGIC_OFFSET_MASK);
  

• attr.addr = (uint64_t)(long)val;

uintptr_t?

...

• if (write) {

•    type = KVM_SET_DEVICE_ATTR;
  

• } else {

•    type = KVM_GET_DEVICE_ATTR;
  

• }
• if (kvm_device_ioctl(kgc->dev_fd, type, &attr) < 0) {

•        fprintf(stderr, "KVM_{SET/GET}_DEVICE_ATTR failed: %s\n",
  

•                strerror(errno));
  

•        abort();
  

• }

+}

+static void kvm_arm_gic_dist_reg_access(GICState *s, int offset, int cpu,

•                                    uint32_t *val, bool write)
  

+{

• kvm_arm_gic_reg_access(s, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,

•                       offset, cpu, val, write);
  

+}

+static void kvm_arm_gic_cpu_reg_access(GICState *s, int offset, int cpu,

•                                   uint32_t *val, bool write)
  

+{

• kvm_arm_gic_reg_access(s, KVM_DEV_ARM_VGIC_GRP_CPU_REGS,

•                       offset, cpu, val, write);
  

+}

+#define for_each_irq_reg(_ctr, _max_irq, _field_width) \

• for (_ctr = 0; _ctr < ((_max_irq) / (32 / (_field_width))); _ctr++)

+/*

• • Translate from the in-kernel field for an IRQ value to/from the qemu
• • representation.
• */

+typedef void (*vgic_translate_fn)(GICState *s, int irq, int cpu,

•                              uint32_t *field, bool to_kernel);
  

+/* synthetic translate function used for clear/set registers to completely

• • clear a setting using a clear-register before setting the remaing bits
• • using a set-register */

+static void translate_clear(GICState *s, int irq, int cpu,

•                        uint32_t *field, bool to_kernel)
  

+{

• if (to_kernel) {

•    *field = ~0;
  

• } else {

•    /* does not make sense: qemu model doesn't use set/clear regs */
  

•    abort();
  

• }

I don't understand the to_kernel bits. I thought we're in a device file that only works with KVM?

The opposite of "to_kernel" is "from_kernel".

IIUC this is for GIC registers that are modelled as a pair of MMIO registers, one with write-1-sets and one with write-1-clears semantics. The patch is first writing all ones to the w1c register, and then writing the actual value to the w1s register.

The way we solved this for x86 is that the set-registers, when called from userspace, also clear the zero bits. See the "host_initiated" parts in arch/x86/kvm/x86.c. However, this would be an ABI change for ARM, so Christoffer's solution is also fine.

One comment on the function names:

kvm_arm_gic_dist_readr kvm_arm_gic_dist_writer

Why not get_reg/set_reg (I was quite surprised to see readr instead of reader :) and it took me a while to understand the convention)? Or if the name is too long, s/readr/get/ and s/writer/set/ would be enough to match the ioctls.

Paolo

...

+}

+static void translate_enabled(GICState *s, int irq, int cpu,

•                          uint32_t *field, bool to_kernel)
  

+{

• int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
• if (to_kernel) {

•    *field = GIC_TEST_ENABLED(irq, cm);
  

• } else {

•    if (*field & 1) {
  

•        GIC_SET_ENABLED(irq, cm);
  

•    }
  

• }

+}

+static void translate_pending(GICState *s, int irq, int cpu,

•                          uint32_t *field, bool to_kernel)
  

+{

• int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
• if (to_kernel) {

•    *field = GIC_TEST_PENDING(irq, cm);
  

• } else {

•    if (*field & 1) {
  

•        GIC_SET_PENDING(irq, cm);
  

•        /* TODO: Capture is level-line is held high in the kernel */
  

•    }
  

• }

+}

+static void translate_active(GICState *s, int irq, int cpu,

•                         uint32_t *field, bool to_kernel)
  

+{

• int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
• if (to_kernel) {

•    *field = GIC_TEST_ACTIVE(irq, cm);
  

• } else {

•    if (*field & 1) {
  

•        GIC_SET_ACTIVE(irq, cm);
  

•    }
  

• }

+}

+static void translate_trigger(GICState *s, int irq, int cpu,

•                        uint32_t *field, bool to_kernel)
  

+{

• if (to_kernel) {

•    *field = (GIC_TEST_TRIGGER(irq)) ? 0x2 : 0x0;
  

• } else {

•    if (*field & 0x2) {
  

•        GIC_SET_TRIGGER(irq);
  

•    }
  

• }

+}

+static void translate_priority(GICState *s, int irq, int cpu,

•                           uint32_t *field, bool to_kernel)
  

+{

• if (to_kernel) {

•    *field = GIC_GET_PRIORITY(irq, cpu) & 0xff;
  

• } else {

•    GIC_SET_PRIORITY(irq, cpu, *field & 0xff);
  

• }

+}

+static void translate_targets(GICState *s, int irq, int cpu,

•                          uint32_t *field, bool to_kernel)
  

+{

• if (to_kernel) {

•    *field = s->irq_target[irq] & 0xff;
  

• } else {

•    s->irq_target[irq] = *field & 0xff;
  

• }

+}

+static void translate_sgisource(GICState *s, int irq, int cpu,

•                            uint32_t *field, bool to_kernel)
  

+{

• if (to_kernel) {

•    *field = s->sgi_source[irq][cpu] & 0xff;
  

• } else {

•    s->sgi_source[irq][cpu] = *field & 0xff;
  

• }

+}

+/* Read a register group from the kernel VGIC */ +static void kvm_arm_gic_dist_readr(GICState *s, uint32_t offset, int width,

•                               int maxirq, vgic_translate_fn translate_fn)
  

+{

• uint32_t reg;
• int i;
• int j;
• int irq;
• int cpu;
• int regsz = 32 / width; /* irqs per kernel register */
• uint32_t field;
• for_each_irq_reg(i, maxirq, width) {

•    irq = i * regsz;
  

•    cpu = 0;
  

•    while ((cpu < s->num_cpu && irq < GIC_INTERNAL) || cpu == 0) {
  

•        kvm_arm_gic_dist_reg_access(s, offset, cpu, &reg, false);
  

•        for (j = 0; j < regsz; j++) {
  

•            field = reg >> (j * width) & ((1 << width) - 1);
  

•            translate_fn(s, irq + j, cpu, &field, false);
  

•        }
  

•        cpu++;
  

•    }
  

•    offset += 4;
  

• }

+}

+/* Write a register group to the kernel VGIC */ +static void kvm_arm_gic_dist_writer(GICState *s, uint32_t offset, int width,

•                                int maxirq, vgic_translate_fn translate_fn)
  

+{

• uint32_t reg;
• int i;
• int j;
• int irq;
• int cpu;
• int regsz = 32 / width; /* irqs per kernel register */
• uint32_t field;
• for_each_irq_reg(i, maxirq, width) {

•    irq = i * regsz;
  

•    cpu = 0;
  

•    while ((cpu < s->num_cpu && irq < GIC_INTERNAL) || cpu == 0) {
  

•        reg = 0;
  

•        for (j = 0; j < regsz; j++) {
  

•            translate_fn(s, irq + j, cpu, &field, true);
  

•            reg |= (field & ((1 << width) - 1)) << (j * width);
  

•        }
  

•        kvm_arm_gic_dist_reg_access(s, offset, cpu, &reg, true);
  

•        cpu++;
  

•    }
  

•    offset += 4;
  

• }

+}

static void kvm_arm_gic_put(GICState *s) {

• /* TODO: there isn't currently a kernel interface to set the GIC state */

• uint32_t reg;
• int i;
• int cpu;
• int num_cpu;
• int num_irq;
• if (!kvm_arm_gic_can_save_restore(s)) {

•        DPRINTF("Cannot put kernel gic state, no kernel interface");
  

•        return;
  

• }
• /* Note: We do the restore in a slightly different order than the save

• * (where the order doesn't matter and is simply ordered according to the
  

• * register offset values */
  

• /*****************************************************************

• * Distributor State
  

• */
  

• /* s->enabled -> GICD_CTLR */
• reg = s->enabled;
• kvm_arm_gic_dist_reg_access(s, 0x0, 0, &reg, true);
• /* Sanity checking on GICD_TYPER and s->num_irq, s->num_cpu */
• kvm_arm_gic_dist_reg_access(s, 0x4, 0, &reg, false);
• num_irq = ((reg & 0x1f) + 1) * 32;
• num_cpu = ((reg & 0xe0) >> 5) + 1;
• if (num_irq < s->num_irq) {

•        fprintf(stderr, "Restoring %u IRQs, but kernel supports max %d\n",
  

•                s->num_irq, num_irq);
  

•        abort();
  

• } else if (num_cpu != s->num_cpu ) {

•        fprintf(stderr, "Restoring %u CPU interfaces, kernel only has %d\n",
  

•                s->num_cpu, num_cpu);
  

•        /* Did we not create the VCPUs in the kernel yet? */
  

•        abort();
  

• }
• /* TODO: Consider checking compatibility with the IIDR ? */
• /* irq_state[n].enabled -> GICD_ISENABLERn */
• kvm_arm_gic_dist_writer(s, 0x180, 1, s->num_irq, translate_clear);
• kvm_arm_gic_dist_writer(s, 0x100, 1, s->num_irq, translate_enabled);

Don't these magic numbers have #define'd equivalents in their GIC implementation header file? Then you don't need the comments above each of these.

I also find the function names quite long, but I guess as long as everything still fits that doesn't really matter.

Alex

On Sun, Aug 25, 2013 at 04:47:59PM +0100, Alexander Graf wrote:

On 23.08.2013, at 21:10, Christoffer Dall wrote:

...

Save and restore the ARM KVM VGIC state from the kernel. We rely on QEMU to marshal the GICState data structure and therefore simply synchronize the kernel state with the QEMU emulated state in both directions.

We take some care on the restore path to check the VGIC has been configured with enough IRQs and CPU interfaces that we can properly restore the state, and for separate set/clear registers we first fully clear the registers and then set the required bits.

Signed-off-by: Christoffer Dall christoffer.dall@linaro.org

hw/intc/arm_gic_common.c | 2 + hw/intc/arm_gic_kvm.c | 418 ++++++++++++++++++++++++++++++++++++++++++- hw/intc/gic_internal.h | 1 + include/migration/vmstate.h | 6 + 4 files changed, 425 insertions(+), 2 deletions(-)

diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index a50ded2..f39bdc1 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -77,6 +77,8 @@ static const VMStateDescription vmstate_gic = { VMSTATE_UINT16_ARRAY(running_priority, GICState, NCPU), VMSTATE_UINT16_ARRAY(current_pending, GICState, NCPU), VMSTATE_UINT8_2DARRAY(binary_point, GICState, 2, NCPU),

•    VMSTATE_UINT32_2DARRAY(active_prio, GICState, 4, NCPU),
  

•    VMSTATE_UINT32(num_irq, GICState),
    VMSTATE_END_OF_LIST()
  

  }

}; diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index 9f0a852..9785281 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -23,6 +23,15 @@ #include "kvm_arm.h" #include "gic_internal.h"

+//#define DEBUG_GIC_KVM

+#ifdef DEBUG_GIC_KVM +#define DPRINTF(fmt, ...) \ +do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0) +#else +#define DPRINTF(fmt, ...) do {} while(0)

You really want to make DPRINTF still be format checked by the compiler. Check out hw/intc/openpic.c for an example how to get there.

good point, thanks for the pointer.

...

+#endif

#define TYPE_KVM_ARM_GIC "kvm-arm-gic" #define KVM_ARM_GIC(obj) \ OBJECT_CHECK(GICState, (obj), TYPE_KVM_ARM_GIC) @@ -73,14 +82,419 @@ static void kvm_arm_gic_set_irq(void *opaque, int irq, int level) kvm_set_irq(kvm_state, kvm_irq, !!level); }

+static bool kvm_arm_gic_can_save_restore(GICState *s) +{

• KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
• return kgc->dev_fd >= 0;

+}

+static void kvm_arm_gic_reg_access(GICState *s, int group, int offset,

•                               int cpu, uint32_t *val, bool write)
  

+{

• KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
• struct kvm_device_attr attr;
• int type;
• cpu = cpu & 0xff;
• attr.flags = 0;
• attr.group = group;
• attr.attr = (((uint64_t)cpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) &

•             KVM_DEV_ARM_VGIC_CPUID_MASK) |
  

•            (((uint64_t)offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) &
  

•             KVM_DEV_ARM_VGIC_OFFSET_MASK);
  

• attr.addr = (uint64_t)(long)val;

uintptr_t?

yup

...

• if (write) {

•    type = KVM_SET_DEVICE_ATTR;
  

• } else {

•    type = KVM_GET_DEVICE_ATTR;
  

• }
• if (kvm_device_ioctl(kgc->dev_fd, type, &attr) < 0) {

•        fprintf(stderr, "KVM_{SET/GET}_DEVICE_ATTR failed: %s\n",
  

•                strerror(errno));
  

•        abort();
  

• }

+}

+static void kvm_arm_gic_dist_reg_access(GICState *s, int offset, int cpu,

•                                    uint32_t *val, bool write)
  

+{

• kvm_arm_gic_reg_access(s, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,

•                       offset, cpu, val, write);
  

+}

+static void kvm_arm_gic_cpu_reg_access(GICState *s, int offset, int cpu,

•                                   uint32_t *val, bool write)
  

+{

• kvm_arm_gic_reg_access(s, KVM_DEV_ARM_VGIC_GRP_CPU_REGS,

•                       offset, cpu, val, write);
  

+}

+#define for_each_irq_reg(_ctr, _max_irq, _field_width) \

• for (_ctr = 0; _ctr < ((_max_irq) / (32 / (_field_width))); _ctr++)

+/*

• • Translate from the in-kernel field for an IRQ value to/from the qemu
• • representation.
• */

+typedef void (*vgic_translate_fn)(GICState *s, int irq, int cpu,

•                              uint32_t *field, bool to_kernel);
  

+/* synthetic translate function used for clear/set registers to completely

• • clear a setting using a clear-register before setting the remaing bits
• • using a set-register */

+static void translate_clear(GICState *s, int irq, int cpu,

•                        uint32_t *field, bool to_kernel)
  

+{

• if (to_kernel) {

•    *field = ~0;
  

• } else {

•    /* does not make sense: qemu model doesn't use set/clear regs */
  

•    abort();
  

• }

I don't understand the to_kernel bits. I thought we're in a device file that only works with KVM?

yeah, but you need to retrieve the state from the kernel on a suspend "from_kernel" and you need to save the state "to_kernel" on a resume operation. These small functions translate between a qemu-representation and a KVM representation, which allows us to do saving of the in-kernel state by reusing the qemu model of the gic.

This specific little function is used for MMIO registers that have a separate register for clearing bits than setting bits, like Paolo describes. The performance of these operations are going to be vastly dominated by saving/restoring your memory and I therefore prefer keeping the interface coherent with the hardware spec, instead of rewriting things to save a few writes to the kernel. Does that answer your question?

...

+}

+static void translate_enabled(GICState *s, int irq, int cpu,

•                          uint32_t *field, bool to_kernel)
  

+{

• int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
• if (to_kernel) {

•    *field = GIC_TEST_ENABLED(irq, cm);
  

• } else {

•    if (*field & 1) {
  

•        GIC_SET_ENABLED(irq, cm);
  

•    }
  

• }

+}

+static void translate_pending(GICState *s, int irq, int cpu,

•                          uint32_t *field, bool to_kernel)
  

+{

• int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
• if (to_kernel) {

•    *field = GIC_TEST_PENDING(irq, cm);
  

• } else {

•    if (*field & 1) {
  

•        GIC_SET_PENDING(irq, cm);
  

•        /* TODO: Capture is level-line is held high in the kernel */
  

•    }
  

• }

+}

+static void translate_active(GICState *s, int irq, int cpu,

•                         uint32_t *field, bool to_kernel)
  

+{

• int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
• if (to_kernel) {

•    *field = GIC_TEST_ACTIVE(irq, cm);
  

• } else {

•    if (*field & 1) {
  

•        GIC_SET_ACTIVE(irq, cm);
  

•    }
  

• }

+}

+static void translate_trigger(GICState *s, int irq, int cpu,

•                        uint32_t *field, bool to_kernel)
  

+{

• if (to_kernel) {

•    *field = (GIC_TEST_TRIGGER(irq)) ? 0x2 : 0x0;
  

• } else {

•    if (*field & 0x2) {
  

•        GIC_SET_TRIGGER(irq);
  

•    }
  

• }

+}

+static void translate_priority(GICState *s, int irq, int cpu,

•                           uint32_t *field, bool to_kernel)
  

+{

• if (to_kernel) {

•    *field = GIC_GET_PRIORITY(irq, cpu) & 0xff;
  

• } else {

•    GIC_SET_PRIORITY(irq, cpu, *field & 0xff);
  

• }

+}

+static void translate_targets(GICState *s, int irq, int cpu,

•                          uint32_t *field, bool to_kernel)
  

+{

• if (to_kernel) {

•    *field = s->irq_target[irq] & 0xff;
  

• } else {

•    s->irq_target[irq] = *field & 0xff;
  

• }

+}

+static void translate_sgisource(GICState *s, int irq, int cpu,

•                            uint32_t *field, bool to_kernel)
  

+{

• if (to_kernel) {

•    *field = s->sgi_source[irq][cpu] & 0xff;
  

• } else {

•    s->sgi_source[irq][cpu] = *field & 0xff;
  

• }

+}

+/* Read a register group from the kernel VGIC */ +static void kvm_arm_gic_dist_readr(GICState *s, uint32_t offset, int width,

•                               int maxirq, vgic_translate_fn translate_fn)
  

+{

• uint32_t reg;
• int i;
• int j;
• int irq;
• int cpu;
• int regsz = 32 / width; /* irqs per kernel register */
• uint32_t field;
• for_each_irq_reg(i, maxirq, width) {

•    irq = i * regsz;
  

•    cpu = 0;
  

•    while ((cpu < s->num_cpu && irq < GIC_INTERNAL) || cpu == 0) {
  

•        kvm_arm_gic_dist_reg_access(s, offset, cpu, &reg, false);
  

•        for (j = 0; j < regsz; j++) {
  

•            field = reg >> (j * width) & ((1 << width) - 1);
  

•            translate_fn(s, irq + j, cpu, &field, false);
  

•        }
  

•        cpu++;
  

•    }
  

•    offset += 4;
  

• }

+}

+/* Write a register group to the kernel VGIC */ +static void kvm_arm_gic_dist_writer(GICState *s, uint32_t offset, int width,

•                                int maxirq, vgic_translate_fn translate_fn)
  

+{

• uint32_t reg;
• int i;
• int j;
• int irq;
• int cpu;
• int regsz = 32 / width; /* irqs per kernel register */
• uint32_t field;
• for_each_irq_reg(i, maxirq, width) {

•    irq = i * regsz;
  

•    cpu = 0;
  

•    while ((cpu < s->num_cpu && irq < GIC_INTERNAL) || cpu == 0) {
  

•        reg = 0;
  

•        for (j = 0; j < regsz; j++) {
  

•            translate_fn(s, irq + j, cpu, &field, true);
  

•            reg |= (field & ((1 << width) - 1)) << (j * width);
  

•        }
  

•        kvm_arm_gic_dist_reg_access(s, offset, cpu, &reg, true);
  

•        cpu++;
  

•    }
  

•    offset += 4;
  

• }

+}

static void kvm_arm_gic_put(GICState *s) {

• /* TODO: there isn't currently a kernel interface to set the GIC state */

• uint32_t reg;
• int i;
• int cpu;
• int num_cpu;
• int num_irq;
• if (!kvm_arm_gic_can_save_restore(s)) {

•        DPRINTF("Cannot put kernel gic state, no kernel interface");
  

•        return;
  

• }
• /* Note: We do the restore in a slightly different order than the save

• * (where the order doesn't matter and is simply ordered according to the
  

• * register offset values */
  

• /*****************************************************************

• * Distributor State
  

• */
  

• /* s->enabled -> GICD_CTLR */
• reg = s->enabled;
• kvm_arm_gic_dist_reg_access(s, 0x0, 0, &reg, true);
• /* Sanity checking on GICD_TYPER and s->num_irq, s->num_cpu */
• kvm_arm_gic_dist_reg_access(s, 0x4, 0, &reg, false);
• num_irq = ((reg & 0x1f) + 1) * 32;
• num_cpu = ((reg & 0xe0) >> 5) + 1;
• if (num_irq < s->num_irq) {

•        fprintf(stderr, "Restoring %u IRQs, but kernel supports max %d\n",
  

•                s->num_irq, num_irq);
  

•        abort();
  

• } else if (num_cpu != s->num_cpu ) {

•        fprintf(stderr, "Restoring %u CPU interfaces, kernel only has %d\n",
  

•                s->num_cpu, num_cpu);
  

•        /* Did we not create the VCPUs in the kernel yet? */
  

•        abort();
  

• }
• /* TODO: Consider checking compatibility with the IIDR ? */
• /* irq_state[n].enabled -> GICD_ISENABLERn */
• kvm_arm_gic_dist_writer(s, 0x180, 1, s->num_irq, translate_clear);
• kvm_arm_gic_dist_writer(s, 0x100, 1, s->num_irq, translate_enabled);

Don't these magic numbers have #define'd equivalents in their GIC implementation header file? Then you don't need the comments above each of these.

in the kernel yes, in qemu no. Unless I'm mistaken, in which case please point me in the right direction. I don't want to taint the git history with a rewrite of every mmio function in the tcg version or have defines for one file and not use them in the other file, which is also a bit weird. If people feel this is necessary, I can have a rewrite of the whole thing, but I prefer not to. Surprisingly.

I also find the function names quite long, but I guess as long as everything still fits that doesn't really matter.

I think the names are as descriptive as they should be, but we can drop some of the kvm_arm_gic prefixes if that's what you have in mind. So far, most calls and definitions fit on 80 chars width so I'm not too worried...

-Christoffer

On Fri, Sep 06, 2013 at 04:13:32PM +0100, Peter Maydell wrote:

On 23 August 2013 21:10, Christoffer Dall christoffer.dall@linaro.org wrote:

...

Save and restore the ARM KVM VGIC state from the kernel. We rely on QEMU to marshal the GICState data structure and therefore simply synchronize the kernel state with the QEMU emulated state in both directions.

We take some care on the restore path to check the VGIC has been configured with enough IRQs and CPU interfaces that we can properly restore the state, and for separate set/clear registers we first fully clear the registers and then set the required bits.

Signed-off-by: Christoffer Dall christoffer.dall@linaro.org

hw/intc/arm_gic_common.c | 2 + hw/intc/arm_gic_kvm.c | 418 ++++++++++++++++++++++++++++++++++++++++++- hw/intc/gic_internal.h | 1 + include/migration/vmstate.h | 6 + 4 files changed, 425 insertions(+), 2 deletions(-)

diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index a50ded2..f39bdc1 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -77,6 +77,8 @@ static const VMStateDescription vmstate_gic = { VMSTATE_UINT16_ARRAY(running_priority, GICState, NCPU), VMSTATE_UINT16_ARRAY(current_pending, GICState, NCPU), VMSTATE_UINT8_2DARRAY(binary_point, GICState, 2, NCPU),

•    VMSTATE_UINT32_2DARRAY(active_prio, GICState, 4, NCPU),
  

•    VMSTATE_UINT32(num_irq, GICState),
  

You don't need to save and restore num_irq, it is constant for the lifetime of the device (set by a property on the device which is fixed by the board model). Migration only works between two identical command lines; if the command lines are identical at each end then num_irq should be too.

ok

...

     VMSTATE_END_OF_LIST()
 }

}; diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index 9f0a852..9785281 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -23,6 +23,15 @@ #include "kvm_arm.h" #include "gic_internal.h"

+//#define DEBUG_GIC_KVM

+#ifdef DEBUG_GIC_KVM +#define DPRINTF(fmt, ...) \ +do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0) +#else +#define DPRINTF(fmt, ...) do {} while(0) +#endif

#define TYPE_KVM_ARM_GIC "kvm-arm-gic" #define KVM_ARM_GIC(obj) \ OBJECT_CHECK(GICState, (obj), TYPE_KVM_ARM_GIC) @@ -73,14 +82,419 @@ static void kvm_arm_gic_set_irq(void *opaque, int irq, int level) kvm_set_irq(kvm_state, kvm_irq, !!level); }

+static bool kvm_arm_gic_can_save_restore(GICState *s) +{

• KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
• return kgc->dev_fd >= 0;

+}

+static void kvm_arm_gic_reg_access(GICState *s, int group, int offset,

•                               int cpu, uint32_t *val, bool write)
  

+{

• KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
• struct kvm_device_attr attr;
• int type;
• cpu = cpu & 0xff;
• attr.flags = 0;
• attr.group = group;
• attr.attr = (((uint64_t)cpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) &

•             KVM_DEV_ARM_VGIC_CPUID_MASK) |
  

•            (((uint64_t)offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) &
  

•             KVM_DEV_ARM_VGIC_OFFSET_MASK);
  

• attr.addr = (uint64_t)(long)val;

(uintptr_t) should suffice.

yes

...

• if (write) {

•    type = KVM_SET_DEVICE_ATTR;
  

• } else {

•    type = KVM_GET_DEVICE_ATTR;
  

• }
• if (kvm_device_ioctl(kgc->dev_fd, type, &attr) < 0) {

•        fprintf(stderr, "KVM_{SET/GET}_DEVICE_ATTR failed: %s\n",
  

•                strerror(errno));
  

Your kvm_device_ioctl returns -errno rather than setting errno, doesn't it?

yes, it does

...

•        abort();
  

• }

+}

...

+/* Read a register group from the kernel VGIC */ +static void kvm_arm_gic_dist_readr(GICState *s, uint32_t offset, int width,

•                               int maxirq, vgic_translate_fn translate_fn)
  

+{

• uint32_t reg;
• int i;
• int j;
• int irq;
• int cpu;
• int regsz = 32 / width; /* irqs per kernel register */
• uint32_t field;
• for_each_irq_reg(i, maxirq, width) {

•    irq = i * regsz;
  

•    cpu = 0;
  

•    while ((cpu < s->num_cpu && irq < GIC_INTERNAL) || cpu == 0) {
  

•        kvm_arm_gic_dist_reg_access(s, offset, cpu, &reg, false);
  

•        for (j = 0; j < regsz; j++) {
  

•            field = reg >> (j * width) & ((1 << width) - 1);
  

field = extract32(reg, j * width, width);

ok

...

•            translate_fn(s, irq + j, cpu, &field, false);
  

•        }
  

•        cpu++;
  

•    }
  

•    offset += 4;
  

• }

+}

+/* Write a register group to the kernel VGIC */ +static void kvm_arm_gic_dist_writer(GICState *s, uint32_t offset, int width,

•                                int maxirq, vgic_translate_fn translate_fn)
  

+{

• uint32_t reg;
• int i;
• int j;
• int irq;
• int cpu;
• int regsz = 32 / width; /* irqs per kernel register */
• uint32_t field;
• for_each_irq_reg(i, maxirq, width) {

•    irq = i * regsz;
  

•    cpu = 0;
  

•    while ((cpu < s->num_cpu && irq < GIC_INTERNAL) || cpu == 0) {
  

•        reg = 0;
  

•        for (j = 0; j < regsz; j++) {
  

•            translate_fn(s, irq + j, cpu, &field, true);
  

•            reg |= (field & ((1 << width) - 1)) << (j * width);
  

reg = deposit32(reg, j * width, width, field);

ok

...

•        }
  

•        kvm_arm_gic_dist_reg_access(s, offset, cpu, &reg, true);
  

•        cpu++;
  

•    }
  

•    offset += 4;
  

• }

+}

...

static void kvm_arm_gic_reset(DeviceState *dev) diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 424a41f..9771163 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -100,6 +100,7 @@ typedef struct GICState {

 /* these registers are mainly used for save/restore of KVM state */
 uint8_t  binary_point[2][NCPU]; /* [0]: group 0, [1]: group 1 */

• uint32_t active_prio[4][NCPU]; /* implementation defined layout */

You can't make this impdef in QEMU's state, that would mean we couldn't do migration between implementations which use different layouts. We need to pick a standard ("whatever the ARM v2 GIC implementation is" seems the obvious choice) and make the kernel convert if it's on an implementation which doesn't follow that version.

Implementation defined as in implementation defined in the architecture. I didn't think it would make sense to choose a format for an a15 implementation, for example, and then translate to that format for other cores using the ARM gic. Wouldn't migration only be support for same qemu model to same qemu model, in which case the format of this register would always be the same, and the kernel must return a format corresponding to the target cpu. Am I missing something here?

...

 uint32_t num_cpu;

diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h index 1c31b5d..e5538c7 100644 --- a/include/migration/vmstate.h +++ b/include/migration/vmstate.h @@ -633,9 +633,15 @@ extern const VMStateInfo vmstate_info_bitmap; #define VMSTATE_UINT32_ARRAY_V(_f, _s, _n, _v) \ VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_uint32, uint32_t)

+#define VMSTATE_UINT32_2DARRAY_V(_f, _s, _n1, _n2, _v) \

• VMSTATE_2DARRAY(_f, _s, _n1, _n2, _v, vmstate_info_uint32, uint32_t)

#define VMSTATE_UINT32_ARRAY(_f, _s, _n) \ VMSTATE_UINT32_ARRAY_V(_f, _s, _n, 0)

+#define VMSTATE_UINT32_2DARRAY(_f, _s, _n1, _n2) \

• VMSTATE_UINT32_2DARRAY_V(_f, _s, _n1, _n2, 0)

#define VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v) \ VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_uint64, uint64_t)

Can you put the vmstate improvements in their own patch, please?

yes,

-Christoffer