Hi Leif/Linaro Team,

Thanks for your response.

Will they both be needing ACPI? Cortex-A5 is an ARMv7 processor.

Yes I need to implement ACPI 5.0 for both( armv7 and armv8 architecture ) processors.

As I see it, C0 and C1 are straightforward enough: C0 is "running" and C1 is corresponding to simply executing WFI/WFE without any further use of power management hardware support. To reach C2 and C3, interaction with a power controller will be necessary. The same is true for >S1-S5.

Does Arm have a power controller which can fulfill such requirements.

ARM has started to work on interfaces to enable the use of generic software in power management solutions. One example of this of the Power State Coordination Interface document: http://infocenter.arm.com/help/topic/com.arm.doc.den0022a/index.html

As the document has discussed Operating System and Power Management(OSPM) and its interfaces, does ARM have any codebase which implements the features described in the document.

Some work on ACPI for ARM is being planned by the Linaro Enterprise Group.

I would interested to know further the implementation of ACPI for ARM. Which ACPI model(Reduced/Fixed/Generic as described by Hardware specifications of ACPI5.0) does the Linaro group plan to implement on the SOC. Do they intend to target both armv7 and armv8 architecture? Besides adding ACPI registers and an ACPI compliant BIOS(UEFI containing ACPI tables), are there any changes from the hardware perspective( of armv7 and armv8 ). I would greatly appreciate if you could provide me some more details on this.

Regards, Ayan Kumar Halder

-----Original Message----- From: Leif Lindholm [mailto:leif.lindholm@linaro.org] Sent: Monday, December 03, 2012 11:49 PM To: Ayan Halder Cc: linaro-kernel@lists.linaro.org Subject: Re: ACPI 5.0 implementation for armv7 and armv8 archoitecture

Hi,

I am planning to implement ACPI5.0 on an SOC having Cortex A5 and Atlas cpu( based on armv8 architecture) running linux on top of them.

Will they both be needing ACPI? Cortex-A5 is an ARMv7 processor.

As per the ACPI 5.0 hardware specification(Fixed Hardware/ Generic Hardware model) of ACPI5.0, the processor needs to support various low power modes(C0, C1, C2, C3) and sleep states(S1, S2, S3, S4, S5) via register interfaces as well as OEM provided AML(ACPI Machine Language).

OK.

Therefore, which instructions in armv7 and armv8 put the processor into the afore-mentioned low power modes and sleep states? ( The arm instruction manual specifies "wfe" and "wfi" to put the processor in a sleep state, but I am not sure if this confirms to the ACPI 5.0 requirements )

As I see it, C0 and C1 are straightforward enough: C0 is "running" and C1 is corresponding to simply executing WFI/WFE without any further use of power management hardware support. To reach C2 and C3, interaction with a power controller will be necessary. The same is true for S1-S5.

ARM has started to work on interfaces to enable the use of generic software in power management solutions. One example of this of the Power State Coordination Interface document: http://infocenter.arm.com/help/topic/com.arm.doc.den0022a/index.html (free registration required). It does not however contain ACPI-specific information.

Besides, does arm provide any AML(ACPI Machine Language) code to put the processor to low power modes? If not, then how do we create an ACPI machine language code for armv7 and armv8 architecture and do we have an AML interpreter for armv7 and armv8 architecture?

Not as far as I'm aware.

Some work on ACPI for ARM is being planned by the Linaro Enterprise Group.

/ Leif