Dear All:
we use arm64 dma_alloc_coherent to get a expected non-cacheable buffer. but when we use the buffer as a dma memory for device, after cpu write datas to the buffer, It is not coherent in ddr so that device cann't get proper datas. so we find the LSK current version's dma alloc is malfunctional.
we have to flushcacheall after cpu write datas and It is ok. It shows that dma_alloc_coherent doesn't work properly.
thanks
Peter
________________________________________ 发件人: Alex Shi [alex.shi@linaro.org] 发送时间: 2014年5月7日 12:06 收件人: Panshilin (Peter); Mark Brown; Guodong Xu; Haojian Zhuang 主题: Re: 答复: 答复: Is this patch included in LSK April release
CC to guodong.
Peter,
I am not MM experts. So could you like to give bit more detailed info of your concern? I did find not any abuse of flush_cache_all in arm64 code.
And AFAIK, If you have no a *hardware* cache coherency unit for DMA access, do you? kernel need to flush(inv) cache lines which involved. but don't need to flush all. Flush range of involved address is fine. Did you try this?
On 05/06/2014 05:10 PM, Panshilin (Peter) wrote:
we verified the patch based on linaro lsk April release and it didn't work .now we have to call flush cache all before start dma transfer. obviously it is not ok for dma coherent function in LSK. Please solve this issue as soon as you can. urgency, thanks . ________________________________________ 发件人: Alex Shi [alex.shi@linaro.org] 发送时间: 2014年5月6日 10:08 收件人: Panshilin (Peter); Mark Brown 主题: Re: 答复: Is this patch included in LSK April release
On 05/05/2014 03:18 PM, Panshilin (Peter) wrote:
de2db74 arm64: Make DMA coherent and strongly ordered mappings not
Peter, did you try the patch in your hardware? Does it work?
-- Thanks Alex
-- Thanks Alex
On Wednesday 07 May 2014 09:38:57 Panshilin wrote:
we use arm64 dma_alloc_coherent to get a expected non-cacheable buffer. but when we use the buffer as a dma memory for device, after cpu write datas to the buffer, It is not coherent in ddr so that device cann't get proper datas. so we find the LSK current version's dma alloc is malfunctional.
we have to flushcacheall after cpu write datas and It is ok. It shows that dma_alloc_coherent doesn't work properly.
In the beginning, we only supported arm64 machines that are fully cache coherent. This has only changed very recently, in v3.15-rc4 with commit c7a4a7658d689f "arm64: Make default dma_ops to be noncoherent" after someone else also tried running on a noncoherent machine.
Can you retry with the latest kernel?
Arnd
On Wed, May 07, 2014 at 09:38:57AM +0000, Panshilin (Peter) wrote:
we use arm64 dma_alloc_coherent to get a expected non-cacheable buffer. but when we use the buffer as a dma memory for device, after cpu write datas to the buffer, It is not coherent in ddr so that device cann't get proper datas. so we find the LSK current version's dma alloc is malfunctional.
we have to flushcacheall after cpu write datas and It is ok. It shows that dma_alloc_coherent doesn't work properly.
Yes, this is the case. The code in mainline didn't work at the time the last release was made and as only models were available for testing this code could not be verified in LSK at that time. This should be resolved in the 14.05 release.
linaro-kernel@lists.linaro.org
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Arnd Bergmann -
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Panshilin (Peter)