Tegra had always been switching to intermediate frequency (pll_p_clk) since ever. CPUFreq core has better support for handling notifications for these frequencies and so we can adapt Tegra's driver to it.

Signed-off-by: Viresh Kumar viresh.kumar@linaro.org --- drivers/cpufreq/tegra-cpufreq.c | 81 +++++++++++++++++++---------------------- 1 file changed, 38 insertions(+), 43 deletions(-)

diff --git a/drivers/cpufreq/tegra-cpufreq.c b/drivers/cpufreq/tegra-cpufreq.c index 6e774c6..10b29ec 100644 --- a/drivers/cpufreq/tegra-cpufreq.c +++ b/drivers/cpufreq/tegra-cpufreq.c @@ -46,9 +46,33 @@ static struct clk *pll_x_clk; static struct clk *pll_p_clk; static struct clk *emc_clk;

-static int tegra_cpu_clk_set_rate(unsigned long rate) +static unsigned int +tegra_get_intermediate(struct cpufreq_policy *policy, unsigned int index) { - int ret; + return clk_get_rate(pll_p_clk); +} + +static int +tegra_target_intermediate(struct cpufreq_policy *policy, unsigned int frequency) +{ + return clk_set_parent(cpu_clk, pll_p_clk); +} + +static int tegra_target(struct cpufreq_policy *policy, unsigned int index) +{ + unsigned long rate = freq_table[index].frequency; + int ret = 0; + + /* + * Vote on memory bus frequency based on cpu frequency + * This sets the minimum frequency, display or avp may request higher + */ + if (rate >= 816000) + clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */ + else if (rate >= 456000) + clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */ + else + clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */

/* * Take an extra reference to the main pll so it doesn't turn @@ -56,12 +80,6 @@ static int tegra_cpu_clk_set_rate(unsigned long rate) */ clk_prepare_enable(pll_x_clk);

- ret = clk_set_parent(cpu_clk, pll_p_clk); - if (ret) { - pr_err("Failed to switch cpu to clock pll_p\n"); - goto out; - } - if (rate == clk_get_rate(pll_p_clk)) goto out;

@@ -72,36 +90,11 @@ static int tegra_cpu_clk_set_rate(unsigned long rate) }

ret = clk_set_parent(cpu_clk, pll_x_clk); - if (ret) { + if (ret) pr_err("Failed to switch cpu to clock pll_x\n"); - goto out; - }

out: clk_disable_unprepare(pll_x_clk); - return ret; -} - -static int tegra_target(struct cpufreq_policy *policy, unsigned int index) -{ - unsigned long rate = freq_table[index].frequency; - int ret = 0; - - /* - * Vote on memory bus frequency based on cpu frequency - * This sets the minimum frequency, display or avp may request higher - */ - if (rate >= 816000) - clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */ - else if (rate >= 456000) - clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */ - else - clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */ - - ret = tegra_cpu_clk_set_rate(rate * 1000); - if (ret) - pr_err("cpu-tegra: Failed to set cpu frequency to %lu kHz\n", - rate);

return ret; } @@ -137,16 +130,18 @@ static int tegra_cpu_exit(struct cpufreq_policy *policy) }

static struct cpufreq_driver tegra_cpufreq_driver = { - .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, - .verify = cpufreq_generic_frequency_table_verify, - .target_index = tegra_target, - .get = cpufreq_generic_get, - .init = tegra_cpu_init, - .exit = tegra_cpu_exit, - .name = "tegra", - .attr = cpufreq_generic_attr, + .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, + .verify = cpufreq_generic_frequency_table_verify, + .get_intermediate = tegra_get_intermediate, + .target_intermediate = tegra_target_intermediate, + .target_index = tegra_target, + .get = cpufreq_generic_get, + .init = tegra_cpu_init, + .exit = tegra_cpu_exit, + .name = "tegra", + .attr = cpufreq_generic_attr, #ifdef CONFIG_PM - .suspend = cpufreq_generic_suspend, + .suspend = cpufreq_generic_suspend, #endif };

On 05/16/2014 03:07 AM, Viresh Kumar wrote:

Tegra had always been switching to intermediate frequency (pll_p_clk) since ever. CPUFreq core has better support for handling notifications for these frequencies and so we can adapt Tegra's driver to it.

You need to squash in the patch below in order for this series to work. Once that's done,

Tested-by: Stephen Warren swarren@nvidia.com

Signed-off-by: Stephen Warren <swarren@nvidia.com>

diff --git a/drivers/cpufreq/tegra-cpufreq.c b/drivers/cpufreq/tegra-cpufreq.c index 10b29ec99bdc..c04fec02ac6a 100644 --- a/drivers/cpufreq/tegra-cpufreq.c +++ b/drivers/cpufreq/tegra-cpufreq.c @@ -49,13 +49,22 @@ static struct clk *emc_clk; static unsigned int tegra_get_intermediate(struct cpufreq_policy *policy, unsigned int index) {

•   return clk_get_rate(pll_p_clk);
  

•   return clk_get_rate(pll_p_clk) / 1000; /* kHz */
  

} static int tegra_target_intermediate(struct cpufreq_policy *policy, unsigned int frequency) {

•   WARN_ON(frequency != clk_get_rate(pll_p_clk) / 1000);
  

•   /*
  

•    * Take an extra reference to the main pll so it doesn't turn
  

•    * off when we move the cpu off of it
  

•    */
  

•   clk_prepare_enable(pll_x_clk);
  

•   return clk_set_parent(cpu_clk, pll_p_clk);
  

•   /* FIXME: if error, remove pll_x reference */
  

} static int tegra_target(struct cpufreq_policy *policy, unsigned int index) @@ -74,16 +83,10 @@ static int tegra_target(struct cpufreq_policy *policy, unsigned int index) else clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */

•   /*
  

•    * Take an extra reference to the main pll so it doesn't turn
  

•    * off when we move the cpu off of it
  

•    */
  

•   clk_prepare_enable(pll_x_clk);
  

•   if (rate == clk_get_rate(pll_p_clk))
            goto out;
  

•   ret = clk_set_rate(pll_x_clk, rate);
  

•   ret = clk_set_rate(pll_x_clk, rate * 1000);
    if (ret) {
            pr_err("Failed to change pll_x to %lu\n", rate);
            goto out;
  

On 05/16/2014 03:07 AM, Viresh Kumar wrote:

Douglas Anderson, recently pointed out an interesting problem due to which udelay() was expiring earlier than it should.

While transitioning between frequencies few platforms may temporarily switch to a stable frequency, waiting for the main PLL to stabilize.

For example: When we transition between very low frequencies on exynos, like between 200MHz and 300MHz, we may temporarily switch to a PLL running at 800MHz. No CPUFREQ notification is sent for that. That means there's a period of time when we're running at 800MHz but loops_per_jiffy is calibrated at between 200MHz and 300MHz. And so udelay behaves badly.

To get this fixed in a generic way, lets introduce another set of callbacks get_intermediate() and target_intermediate(), only for drivers with target_index() and CPUFREQ_ASYNC_NOTIFICATION unset.

get_intermediate should return a stable intermediate frequency platform wants to switch to, and target_intermediate() should set CPU to to that frequency, before jumping to the frequency corresponding to 'index'. Core will take care of sending notifications and driver doesn't have to handle them in target_intermediate() or target_index().

NOTE: Once set to intermediate frequency, driver isn't expected to fail for the following ->target_index() call, if it fails core will issue a WARN().

diff --git a/Documentation/cpu-freq/cpu-drivers.txt b/Documentation/cpu-freq/cpu-drivers.txt

+cpufreq_driver.get_intermediate +and target_intermediate Uset to switch to stable frequency while

• 		changing CPU frequency.
  

s/Uset/Used.

diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h

@@ -226,6 +226,21 @@ struct cpufreq_driver {

• unsigned int (*get_intermediate)(struct cpufreq_policy *policy,

• 			 unsigned int index);
  

Should get_intermediate be passed a struct cpufreq_freqs freqs rather than just the target index? That way, if the intermediate frequency varies depending on old/new frequencies, then the driver won't have to go look up the current frequency in order to implement that logic.