The ASMedia ASM1062 SATA controller causes an External Abort on
controllers which support Max Payload Size >= 512. It happens with
Aardvark PCIe controller (tested on Turris MOX) and also with DesignWare
controller (armada8k, tested on CN9130-CRB):
ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
ata1.00: ATA-9: WDC WD40EFRX-68WT0N0, 80.00A80, max UDMA/133
ata1.00: 7814037168 sectors, multi 0: LBA48 NCQ (depth 32), AA
ERROR: Unhandled External Abort received on 0x80000000 at EL3!
ERROR: exception reason=1 syndrome=0x92000210
PANIC at PC : 0x00000000040273bc
Limiting Max Payload Size to 256 bytes solves this problem.
On Turris MOX this problem first appeared when the pci-aardvark
controller started using the pci-emul-bridge API, in commit 8a3ebd8de328
("PCI: aardvark: Implement emulated root PCI bridge config space").
On armada8k this was always a problem because it has HW root bridge.
Signed-off-by: Marek Behún <kabel(a)kernel.org>
Reported-by: Rötti <espressobinboardarmbiantempmailaddress(a)posteo.de>
Cc: Pali Rohár <pali(a)kernel.org>
Cc: stable(a)vger.kernel.org
---
drivers/pci/quirks.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 653660e3ba9e..a561136efb08 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -3251,6 +3251,11 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
+/*
+ * For some reason DECLARE_PCI_FIXUP_HEADER does not work with pci-aardvark
+ * controller. We have to use DECLARE_PCI_FIXUP_EARLY.
+ */
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256);
/*
* Intel 5000 and 5100 Memory controllers have an erratum with read completion
--
2.26.2
This is a note to let you know that I've just added the patch titled
staging: mt7621-pci: fix hang when nothing is connected to pcie ports
to my staging git tree which can be found at
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git
in the staging-testing branch.
The patch will show up in the next release of the linux-next tree
(usually sometime within the next 24 hours during the week.)
The patch will be merged to the staging-next branch sometime soon,
after it passes testing, and the merge window is open.
If you have any questions about this process, please let me know.
>From 7d761b084b3c785e1fbbe707fbdf7baba905c6ad Mon Sep 17 00:00:00 2001
From: Sergio Paracuellos <sergio.paracuellos(a)gmail.com>
Date: Mon, 23 Aug 2021 19:08:03 +0200
Subject: staging: mt7621-pci: fix hang when nothing is connected to pcie ports
When nothing is connected to pcie ports, each port is set to reset state.
When this occurs, next access result in a hang on boot as follows:
mt7621-pci 1e140000.pcie: pcie0 no card, disable it (RST & CLK)
mt7621-pci 1e140000.pcie: pcie1 no card, disable it (RST & CLK)
mt7621-pci 1e140000.pcie: pcie2 no card, disable it (RST & CLK)
[ HANGS HERE ]
Fix this just detecting 'nothing is connected state' to avoid next accesses
to pcie port related configuration registers.
Fixes: b99cc3a2b6b6 ("staging: mt7621-pci: avoid custom 'map_irq' function")
Cc: stable <stable(a)vger.kernel.org>
Reported-by: DENG Qingfang <dqfext(a)gmail.com>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos(a)gmail.com>
Link: https://lore.kernel.org/r/20210823170803.2108-1-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org>
---
drivers/staging/mt7621-pci/pci-mt7621.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index f9bdf4e33134..6acfc94a16e7 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -56,6 +56,7 @@
#define PCIE_BAR_ENABLE BIT(0)
#define PCIE_PORT_INT_EN(x) BIT(20 + (x))
#define PCIE_PORT_LINKUP BIT(0)
+#define PCIE_PORT_CNT 3
#define PERST_DELAY_MS 100
@@ -388,10 +389,11 @@ static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie)
msleep(PERST_DELAY_MS);
}
-static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
+static int mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
{
struct device *dev = pcie->dev;
struct mt7621_pcie_port *port, *tmp;
+ u8 num_disabled = 0;
int err;
mt7621_pcie_reset_assert(pcie);
@@ -423,6 +425,7 @@ static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
slot);
mt7621_control_assert(port);
port->enabled = false;
+ num_disabled++;
if (slot == 0) {
tmp = port;
@@ -433,6 +436,8 @@ static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
phy_power_off(tmp->phy);
}
}
+
+ return (num_disabled != PCIE_PORT_CNT) ? 0 : -ENODEV;
}
static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
@@ -540,7 +545,11 @@ static int mt7621_pci_probe(struct platform_device *pdev)
return err;
}
- mt7621_pcie_init_ports(pcie);
+ err = mt7621_pcie_init_ports(pcie);
+ if (err) {
+ dev_err(dev, "Nothing connected in virtual bridges\n");
+ return 0;
+ }
err = mt7621_pcie_enable_ports(bridge);
if (err) {
--
2.32.0