August 2024 - Linux-stable-mirror

FAILED: patch "[PATCH] drm/amd/display: Add HW cursor visual confirm" failed to apply to 6.1-stable tree

by gregkh＠linuxfoundation.org

The patch below does not apply to the 6.1-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <stable(a)vger.kernel.org>. To reproduce the conflict and resubmit, you may use the following commands: git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.1.y git checkout FETCH_HEAD git cherry-pick -x 0b8de7a04f7c14abd28bd8b9f3e1e5737a3702e2 # <resolve conflicts, build, test, etc.> git commit -s git send-email --to '<stable(a)vger.kernel.org>' --in-reply-to '2024081226-overplay-swell-db4b@gregkh' --subject-prefix 'PATCH 6.1.y' HEAD^.. Possible dependencies: 0b8de7a04f7c ("drm/amd/display: Add HW cursor visual confirm") f63f86b5affc ("drm/amd/display: Separate setting and programming of cursor") 00c391102abc ("drm/amd/display: Add misc DC changes for DCN401") da87132f641e ("drm/amd/display: Add some DCN401 reg name to macro definitions") ef319dff5475 ("drm/amd/display: add support for chroma offset") a41aa6a7d0a6 ("drm/amd/display: Add comments to improve the code readability") 5324e2b205a2 ("drm/amd/display: Add driver support for future FAMS versions") f3736c0d979a ("drm/amd/display: Add code comments clock and encode code") 8b2cb32cf0c6 ("drm/amd/display: FEC overhead should be checked once for mst slot nums") 4df96ba66760 ("drm/amd/display: Add timing pixel encoding for mst mode validation") 2dbe9c2b2685 ("drm/amd/display: add DCN 351 version for microcode load") 1c5c36530a57 ("drm/amd/display: Set DCN351 BB and IP the same as DCN35") 5034b935f62a ("drm/amd/display: Modify DHCUB waterwark structures and functions") 9d43241953f7 ("drm/amd/display: Refactor DML2 interfaces") 8cffa89bd5e2 ("drm/amd/display: Expand DML2 callbacks") 2d5bb791e24f ("drm/amd/display: Implement update_planes_and_stream_v3 sequence") 88867807564e ("drm/amd/display: Refactor DPP into a component directory") 27f03bc680ef ("drm/amd/display: Guard cursor idle reallow by DC debug option") eed4edda910f ("drm/amd/display: Support long vblank feature") caef6c453cf2 ("drm/amd/display: Add DML2 folder to include path") thanks, greg k-h ------------------ original commit in Linus's tree ------------------ From 0b8de7a04f7c14abd28bd8b9f3e1e5737a3702e2 Mon Sep 17 00:00:00 2001 From: Ryan Seto <ryanseto(a)amd.com> Date: Fri, 14 Jun 2024 14:23:41 -0400 Subject: [PATCH] drm/amd/display: Add HW cursor visual confirm [WHY] Added HW cursor visual confirm [HOW] Added visual confirm logic when programming cursor positions. HW is programmed on cursor updates since cursor can change without flips. Reviewed-by: Alvin Lee <alvin.lee2(a)amd.com> Cc: Mario Limonciello <mario.limonciello(a)amd.com> Cc: Alex Deucher <alexander.deucher(a)amd.com> Cc: stable(a)vger.kernel.org Signed-off-by: Alex Hung <alex.hung(a)amd.com> Signed-off-by: Ryan Seto <ryanseto(a)amd.com> Tested-by: Daniel Wheeler <daniel.wheeler(a)amd.com> Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 9b24f448ce50..de0633f98158 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -416,6 +416,35 @@ bool dc_stream_program_cursor_position( if (reset_idle_optimizations && !dc->debug.disable_dmub_reallow_idle) dc_allow_idle_optimizations(dc, true); + /* apply/update visual confirm */ + if (dc->debug.visual_confirm == VISUAL_CONFIRM_HW_CURSOR) { + /* update software state */ + uint32_t color_value = MAX_TG_COLOR_VALUE; + int i; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + + /* adjust visual confirm color for all pipes with current stream */ + if (stream == pipe_ctx->stream) { + if (stream->cursor_position.enable) { + pipe_ctx->visual_confirm_color.color_r_cr = color_value; + pipe_ctx->visual_confirm_color.color_g_y = 0; + pipe_ctx->visual_confirm_color.color_b_cb = 0; + } else { + pipe_ctx->visual_confirm_color.color_r_cr = 0; + pipe_ctx->visual_confirm_color.color_g_y = 0; + pipe_ctx->visual_confirm_color.color_b_cb = color_value; + } + + /* programming hardware */ + if (pipe_ctx->plane_state) + dc->hwss.update_visual_confirm_color(dc, pipe_ctx, + pipe_ctx->plane_res.hubp->mpcc_id); + } + } + } + return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e0334b573f2d..64241de70f15 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -476,6 +476,7 @@ enum visual_confirm { VISUAL_CONFIRM_SUBVP = 14, VISUAL_CONFIRM_MCLK_SWITCH = 16, VISUAL_CONFIRM_FAMS2 = 19, + VISUAL_CONFIRM_HW_CURSOR = 20, }; enum dc_psr_power_opts {

1 year, 4 months

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FAILED: patch "[PATCH] drm/amd/display: Add HW cursor visual confirm" failed to apply to 6.10-stable tree

by gregkh＠linuxfoundation.org

The patch below does not apply to the 6.10-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <stable(a)vger.kernel.org>. To reproduce the conflict and resubmit, you may use the following commands: git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.10.y git checkout FETCH_HEAD git cherry-pick -x 0b8de7a04f7c14abd28bd8b9f3e1e5737a3702e2 # <resolve conflicts, build, test, etc.> git commit -s git send-email --to '<stable(a)vger.kernel.org>' --in-reply-to '2024081225-customize-semantic-0c0b@gregkh' --subject-prefix 'PATCH 6.10.y' HEAD^.. Possible dependencies: 0b8de7a04f7c ("drm/amd/display: Add HW cursor visual confirm") f63f86b5affc ("drm/amd/display: Separate setting and programming of cursor") 00c391102abc ("drm/amd/display: Add misc DC changes for DCN401") da87132f641e ("drm/amd/display: Add some DCN401 reg name to macro definitions") thanks, greg k-h ------------------ original commit in Linus's tree ------------------ From 0b8de7a04f7c14abd28bd8b9f3e1e5737a3702e2 Mon Sep 17 00:00:00 2001 From: Ryan Seto <ryanseto(a)amd.com> Date: Fri, 14 Jun 2024 14:23:41 -0400 Subject: [PATCH] drm/amd/display: Add HW cursor visual confirm [WHY] Added HW cursor visual confirm [HOW] Added visual confirm logic when programming cursor positions. HW is programmed on cursor updates since cursor can change without flips. Reviewed-by: Alvin Lee <alvin.lee2(a)amd.com> Cc: Mario Limonciello <mario.limonciello(a)amd.com> Cc: Alex Deucher <alexander.deucher(a)amd.com> Cc: stable(a)vger.kernel.org Signed-off-by: Alex Hung <alex.hung(a)amd.com> Signed-off-by: Ryan Seto <ryanseto(a)amd.com> Tested-by: Daniel Wheeler <daniel.wheeler(a)amd.com> Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 9b24f448ce50..de0633f98158 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -416,6 +416,35 @@ bool dc_stream_program_cursor_position( if (reset_idle_optimizations && !dc->debug.disable_dmub_reallow_idle) dc_allow_idle_optimizations(dc, true); + /* apply/update visual confirm */ + if (dc->debug.visual_confirm == VISUAL_CONFIRM_HW_CURSOR) { + /* update software state */ + uint32_t color_value = MAX_TG_COLOR_VALUE; + int i; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + + /* adjust visual confirm color for all pipes with current stream */ + if (stream == pipe_ctx->stream) { + if (stream->cursor_position.enable) { + pipe_ctx->visual_confirm_color.color_r_cr = color_value; + pipe_ctx->visual_confirm_color.color_g_y = 0; + pipe_ctx->visual_confirm_color.color_b_cb = 0; + } else { + pipe_ctx->visual_confirm_color.color_r_cr = 0; + pipe_ctx->visual_confirm_color.color_g_y = 0; + pipe_ctx->visual_confirm_color.color_b_cb = color_value; + } + + /* programming hardware */ + if (pipe_ctx->plane_state) + dc->hwss.update_visual_confirm_color(dc, pipe_ctx, + pipe_ctx->plane_res.hubp->mpcc_id); + } + } + } + return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e0334b573f2d..64241de70f15 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -476,6 +476,7 @@ enum visual_confirm { VISUAL_CONFIRM_SUBVP = 14, VISUAL_CONFIRM_MCLK_SWITCH = 16, VISUAL_CONFIRM_FAMS2 = 19, + VISUAL_CONFIRM_HW_CURSOR = 20, }; enum dc_psr_power_opts {

1 year, 4 months

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FAILED: patch "[PATCH] drm/amd/display: Add HW cursor visual confirm" failed to apply to 6.6-stable tree

by gregkh＠linuxfoundation.org

The patch below does not apply to the 6.6-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <stable(a)vger.kernel.org>. To reproduce the conflict and resubmit, you may use the following commands: git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.6.y git checkout FETCH_HEAD git cherry-pick -x 0b8de7a04f7c14abd28bd8b9f3e1e5737a3702e2 # <resolve conflicts, build, test, etc.> git commit -s git send-email --to '<stable(a)vger.kernel.org>' --in-reply-to '2024081225-albatross-dastardly-d4a3@gregkh' --subject-prefix 'PATCH 6.6.y' HEAD^.. Possible dependencies: 0b8de7a04f7c ("drm/amd/display: Add HW cursor visual confirm") f63f86b5affc ("drm/amd/display: Separate setting and programming of cursor") 00c391102abc ("drm/amd/display: Add misc DC changes for DCN401") da87132f641e ("drm/amd/display: Add some DCN401 reg name to macro definitions") ef319dff5475 ("drm/amd/display: add support for chroma offset") a41aa6a7d0a6 ("drm/amd/display: Add comments to improve the code readability") 5324e2b205a2 ("drm/amd/display: Add driver support for future FAMS versions") f3736c0d979a ("drm/amd/display: Add code comments clock and encode code") 8b2cb32cf0c6 ("drm/amd/display: FEC overhead should be checked once for mst slot nums") 4df96ba66760 ("drm/amd/display: Add timing pixel encoding for mst mode validation") 2dbe9c2b2685 ("drm/amd/display: add DCN 351 version for microcode load") 1c5c36530a57 ("drm/amd/display: Set DCN351 BB and IP the same as DCN35") 5034b935f62a ("drm/amd/display: Modify DHCUB waterwark structures and functions") 9d43241953f7 ("drm/amd/display: Refactor DML2 interfaces") 8cffa89bd5e2 ("drm/amd/display: Expand DML2 callbacks") 2d5bb791e24f ("drm/amd/display: Implement update_planes_and_stream_v3 sequence") 88867807564e ("drm/amd/display: Refactor DPP into a component directory") 27f03bc680ef ("drm/amd/display: Guard cursor idle reallow by DC debug option") eed4edda910f ("drm/amd/display: Support long vblank feature") caef6c453cf2 ("drm/amd/display: Add DML2 folder to include path") thanks, greg k-h ------------------ original commit in Linus's tree ------------------ From 0b8de7a04f7c14abd28bd8b9f3e1e5737a3702e2 Mon Sep 17 00:00:00 2001 From: Ryan Seto <ryanseto(a)amd.com> Date: Fri, 14 Jun 2024 14:23:41 -0400 Subject: [PATCH] drm/amd/display: Add HW cursor visual confirm [WHY] Added HW cursor visual confirm [HOW] Added visual confirm logic when programming cursor positions. HW is programmed on cursor updates since cursor can change without flips. Reviewed-by: Alvin Lee <alvin.lee2(a)amd.com> Cc: Mario Limonciello <mario.limonciello(a)amd.com> Cc: Alex Deucher <alexander.deucher(a)amd.com> Cc: stable(a)vger.kernel.org Signed-off-by: Alex Hung <alex.hung(a)amd.com> Signed-off-by: Ryan Seto <ryanseto(a)amd.com> Tested-by: Daniel Wheeler <daniel.wheeler(a)amd.com> Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 9b24f448ce50..de0633f98158 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -416,6 +416,35 @@ bool dc_stream_program_cursor_position( if (reset_idle_optimizations && !dc->debug.disable_dmub_reallow_idle) dc_allow_idle_optimizations(dc, true); + /* apply/update visual confirm */ + if (dc->debug.visual_confirm == VISUAL_CONFIRM_HW_CURSOR) { + /* update software state */ + uint32_t color_value = MAX_TG_COLOR_VALUE; + int i; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + + /* adjust visual confirm color for all pipes with current stream */ + if (stream == pipe_ctx->stream) { + if (stream->cursor_position.enable) { + pipe_ctx->visual_confirm_color.color_r_cr = color_value; + pipe_ctx->visual_confirm_color.color_g_y = 0; + pipe_ctx->visual_confirm_color.color_b_cb = 0; + } else { + pipe_ctx->visual_confirm_color.color_r_cr = 0; + pipe_ctx->visual_confirm_color.color_g_y = 0; + pipe_ctx->visual_confirm_color.color_b_cb = color_value; + } + + /* programming hardware */ + if (pipe_ctx->plane_state) + dc->hwss.update_visual_confirm_color(dc, pipe_ctx, + pipe_ctx->plane_res.hubp->mpcc_id); + } + } + } + return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e0334b573f2d..64241de70f15 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -476,6 +476,7 @@ enum visual_confirm { VISUAL_CONFIRM_SUBVP = 14, VISUAL_CONFIRM_MCLK_SWITCH = 16, VISUAL_CONFIRM_FAMS2 = 19, + VISUAL_CONFIRM_HW_CURSOR = 20, }; enum dc_psr_power_opts {

1 year, 4 months

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FAILED: patch "[PATCH] drm/amd/display: Adjust reg field for DSC wait for disconnect" failed to apply to 4.19-stable tree

by gregkh＠linuxfoundation.org

The patch below does not apply to the 4.19-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <stable(a)vger.kernel.org>. To reproduce the conflict and resubmit, you may use the following commands: git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-4.19.y git checkout FETCH_HEAD git cherry-pick -x 569d7db70e5dcf13fbf072f10e9096577ac1e565 # <resolve conflicts, build, test, etc.> git commit -s git send-email --to '<stable(a)vger.kernel.org>' --in-reply-to '2024081219-sermon-snorkel-dd21@gregkh' --subject-prefix 'PATCH 4.19.y' HEAD^.. Possible dependencies: 569d7db70e5d ("drm/amd/display: Adjust reg field for DSC wait for disconnect") 176278d8bff2 ("drm/amd/display: reset DSC clock in post unlock update") 0127f0445f7c ("drm/amd/display: Refactor input mode programming for DIG FIFO") e6a901a00822 ("drm/amd/display: use even ODM slice width for two pixels per container") 532a0d2ad292 ("drm/amd/display: Revert "dc: Keep VBios pixel rate div setting util next mode set"") 47745acc5e8d ("drm/amd/display: Add trigger FIFO resync path for DCN35") 4d4d3ff16db2 ("drm/amd/display: Keep VBios pixel rate div setting util next mode set") 70839da63605 ("drm/amd/display: Add new DCN401 sources") 9712b64d6f3f ("drm/amd/display: Remove MPC rate control logic from DCN30 and above") eed4edda910f ("drm/amd/display: Support long vblank feature") 2d7f3d1a5866 ("drm/amd/display: Implement wait_for_odm_update_pending_complete") c7b33856139d ("drm/amd/display: Drop some unnecessary guards") 6a068e64fb25 ("drm/amd/display: Update phantom pipe enable / disable sequence") db8391479f44 ("drm/amd/display: correct static screen event mask") 4ba9ca63e696 ("drm/amd/display: Fix dcn35 8k30 Underflow/Corruption Issue") 9af68235ad3d ("drm/amd/display: Fix static screen event mask definition change") f6154d8babbb ("drm/amd/display: Refactor INIT into component folder") a71e1310a43f ("drm/amd/display: Add more mechanisms for tests") 85fce153995e ("drm/amd/display: change static screen wait frame_count for ips") 09a4ec5da92c ("drm/amd/display: Refactor dc_state interface") thanks, greg k-h ------------------ original commit in Linus's tree ------------------ From 569d7db70e5dcf13fbf072f10e9096577ac1e565 Mon Sep 17 00:00:00 2001 From: Ryan Seto <ryanseto(a)amd.com> Date: Fri, 14 Jun 2024 14:56:15 -0400 Subject: [PATCH] drm/amd/display: Adjust reg field for DSC wait for disconnect [WHY] DSC was waiting for the wrong field to disconnect cleanly. [HOW] Changed field the DSC disconnect was waiting on. Reviewed-by: Wenjing Liu <wenjing.liu(a)amd.com> Cc: Mario Limonciello <mario.limonciello(a)amd.com> Cc: Alex Deucher <alexander.deucher(a)amd.com> Cc: stable(a)vger.kernel.org Signed-off-by: Alex Hung <alex.hung(a)amd.com> Signed-off-by: Ryan Seto <ryanseto(a)amd.com> Tested-by: Daniel Wheeler <daniel.wheeler(a)amd.com> Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h index a23308a785bc..1fb90b52b814 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h @@ -454,7 +454,9 @@ type DSCCIF_UPDATE_TAKEN_ACK; \ type DSCRM_DSC_FORWARD_EN; \ type DSCRM_DSC_OPP_PIPE_SOURCE; \ - type DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING + type DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING; \ + type DSCRM_DSC_FORWARD_EN_STATUS + struct dcn20_dsc_registers { uint32_t DSC_TOP_CONTROL; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c index 52f23bb554af..6acb6699f146 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c @@ -208,7 +208,7 @@ static void dsc401_wait_disconnect_pending_clear(struct display_stream_compresso { struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); - REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING, 0, 2, 50000); + REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, 0, 2, 50000); } static void dsc401_disconnect(struct display_stream_compressor *dsc) diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h index 2143e81ca22a..3c9fa8988974 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h @@ -196,7 +196,8 @@ DSC2_SF(DSCCIF0, DSCCIF_CONFIG0__BITS_PER_COMPONENT, mask_sh), \ DSC_SF(DSCCIF0_DSCCIF_CONFIG0, DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \ DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, mask_sh), \ - DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh) + DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh), \ + DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, mask_sh) struct dcn401_dsc_registers { uint32_t DSC_TOP_CONTROL;

1 year, 4 months

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FAILED: patch "[PATCH] drm/amd/display: Adjust reg field for DSC wait for disconnect" failed to apply to 5.4-stable tree

by gregkh＠linuxfoundation.org

The patch below does not apply to the 5.4-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <stable(a)vger.kernel.org>. To reproduce the conflict and resubmit, you may use the following commands: git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-5.4.y git checkout FETCH_HEAD git cherry-pick -x 569d7db70e5dcf13fbf072f10e9096577ac1e565 # <resolve conflicts, build, test, etc.> git commit -s git send-email --to '<stable(a)vger.kernel.org>' --in-reply-to '2024081213-guileless-sludge-4dcb@gregkh' --subject-prefix 'PATCH 5.4.y' HEAD^.. Possible dependencies: 569d7db70e5d ("drm/amd/display: Adjust reg field for DSC wait for disconnect") 176278d8bff2 ("drm/amd/display: reset DSC clock in post unlock update") 0127f0445f7c ("drm/amd/display: Refactor input mode programming for DIG FIFO") e6a901a00822 ("drm/amd/display: use even ODM slice width for two pixels per container") 532a0d2ad292 ("drm/amd/display: Revert "dc: Keep VBios pixel rate div setting util next mode set"") 47745acc5e8d ("drm/amd/display: Add trigger FIFO resync path for DCN35") 4d4d3ff16db2 ("drm/amd/display: Keep VBios pixel rate div setting util next mode set") 70839da63605 ("drm/amd/display: Add new DCN401 sources") 9712b64d6f3f ("drm/amd/display: Remove MPC rate control logic from DCN30 and above") eed4edda910f ("drm/amd/display: Support long vblank feature") 2d7f3d1a5866 ("drm/amd/display: Implement wait_for_odm_update_pending_complete") c7b33856139d ("drm/amd/display: Drop some unnecessary guards") 6a068e64fb25 ("drm/amd/display: Update phantom pipe enable / disable sequence") db8391479f44 ("drm/amd/display: correct static screen event mask") 4ba9ca63e696 ("drm/amd/display: Fix dcn35 8k30 Underflow/Corruption Issue") 9af68235ad3d ("drm/amd/display: Fix static screen event mask definition change") f6154d8babbb ("drm/amd/display: Refactor INIT into component folder") a71e1310a43f ("drm/amd/display: Add more mechanisms for tests") 85fce153995e ("drm/amd/display: change static screen wait frame_count for ips") 09a4ec5da92c ("drm/amd/display: Refactor dc_state interface") thanks, greg k-h ------------------ original commit in Linus's tree ------------------ From 569d7db70e5dcf13fbf072f10e9096577ac1e565 Mon Sep 17 00:00:00 2001 From: Ryan Seto <ryanseto(a)amd.com> Date: Fri, 14 Jun 2024 14:56:15 -0400 Subject: [PATCH] drm/amd/display: Adjust reg field for DSC wait for disconnect [WHY] DSC was waiting for the wrong field to disconnect cleanly. [HOW] Changed field the DSC disconnect was waiting on. Reviewed-by: Wenjing Liu <wenjing.liu(a)amd.com> Cc: Mario Limonciello <mario.limonciello(a)amd.com> Cc: Alex Deucher <alexander.deucher(a)amd.com> Cc: stable(a)vger.kernel.org Signed-off-by: Alex Hung <alex.hung(a)amd.com> Signed-off-by: Ryan Seto <ryanseto(a)amd.com> Tested-by: Daniel Wheeler <daniel.wheeler(a)amd.com> Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h index a23308a785bc..1fb90b52b814 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h @@ -454,7 +454,9 @@ type DSCCIF_UPDATE_TAKEN_ACK; \ type DSCRM_DSC_FORWARD_EN; \ type DSCRM_DSC_OPP_PIPE_SOURCE; \ - type DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING + type DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING; \ + type DSCRM_DSC_FORWARD_EN_STATUS + struct dcn20_dsc_registers { uint32_t DSC_TOP_CONTROL; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c index 52f23bb554af..6acb6699f146 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c @@ -208,7 +208,7 @@ static void dsc401_wait_disconnect_pending_clear(struct display_stream_compresso { struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); - REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING, 0, 2, 50000); + REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, 0, 2, 50000); } static void dsc401_disconnect(struct display_stream_compressor *dsc) diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h index 2143e81ca22a..3c9fa8988974 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h @@ -196,7 +196,8 @@ DSC2_SF(DSCCIF0, DSCCIF_CONFIG0__BITS_PER_COMPONENT, mask_sh), \ DSC_SF(DSCCIF0_DSCCIF_CONFIG0, DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \ DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, mask_sh), \ - DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh) + DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh), \ + DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, mask_sh) struct dcn401_dsc_registers { uint32_t DSC_TOP_CONTROL;

1 year, 4 months

1
0
0 0

FAILED: patch "[PATCH] drm/amd/display: Adjust reg field for DSC wait for disconnect" failed to apply to 5.15-stable tree

by gregkh＠linuxfoundation.org

The patch below does not apply to the 5.15-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <stable(a)vger.kernel.org>. To reproduce the conflict and resubmit, you may use the following commands: git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-5.15.y git checkout FETCH_HEAD git cherry-pick -x 569d7db70e5dcf13fbf072f10e9096577ac1e565 # <resolve conflicts, build, test, etc.> git commit -s git send-email --to '<stable(a)vger.kernel.org>' --in-reply-to '2024081211-whacking-visa-8ff1@gregkh' --subject-prefix 'PATCH 5.15.y' HEAD^.. Possible dependencies: 569d7db70e5d ("drm/amd/display: Adjust reg field for DSC wait for disconnect") 176278d8bff2 ("drm/amd/display: reset DSC clock in post unlock update") 0127f0445f7c ("drm/amd/display: Refactor input mode programming for DIG FIFO") e6a901a00822 ("drm/amd/display: use even ODM slice width for two pixels per container") 532a0d2ad292 ("drm/amd/display: Revert "dc: Keep VBios pixel rate div setting util next mode set"") 47745acc5e8d ("drm/amd/display: Add trigger FIFO resync path for DCN35") 4d4d3ff16db2 ("drm/amd/display: Keep VBios pixel rate div setting util next mode set") 70839da63605 ("drm/amd/display: Add new DCN401 sources") 9712b64d6f3f ("drm/amd/display: Remove MPC rate control logic from DCN30 and above") eed4edda910f ("drm/amd/display: Support long vblank feature") 2d7f3d1a5866 ("drm/amd/display: Implement wait_for_odm_update_pending_complete") c7b33856139d ("drm/amd/display: Drop some unnecessary guards") 6a068e64fb25 ("drm/amd/display: Update phantom pipe enable / disable sequence") db8391479f44 ("drm/amd/display: correct static screen event mask") 4ba9ca63e696 ("drm/amd/display: Fix dcn35 8k30 Underflow/Corruption Issue") 9af68235ad3d ("drm/amd/display: Fix static screen event mask definition change") f6154d8babbb ("drm/amd/display: Refactor INIT into component folder") a71e1310a43f ("drm/amd/display: Add more mechanisms for tests") 85fce153995e ("drm/amd/display: change static screen wait frame_count for ips") 09a4ec5da92c ("drm/amd/display: Refactor dc_state interface") thanks, greg k-h ------------------ original commit in Linus's tree ------------------ From 569d7db70e5dcf13fbf072f10e9096577ac1e565 Mon Sep 17 00:00:00 2001 From: Ryan Seto <ryanseto(a)amd.com> Date: Fri, 14 Jun 2024 14:56:15 -0400 Subject: [PATCH] drm/amd/display: Adjust reg field for DSC wait for disconnect [WHY] DSC was waiting for the wrong field to disconnect cleanly. [HOW] Changed field the DSC disconnect was waiting on. Reviewed-by: Wenjing Liu <wenjing.liu(a)amd.com> Cc: Mario Limonciello <mario.limonciello(a)amd.com> Cc: Alex Deucher <alexander.deucher(a)amd.com> Cc: stable(a)vger.kernel.org Signed-off-by: Alex Hung <alex.hung(a)amd.com> Signed-off-by: Ryan Seto <ryanseto(a)amd.com> Tested-by: Daniel Wheeler <daniel.wheeler(a)amd.com> Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h index a23308a785bc..1fb90b52b814 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h @@ -454,7 +454,9 @@ type DSCCIF_UPDATE_TAKEN_ACK; \ type DSCRM_DSC_FORWARD_EN; \ type DSCRM_DSC_OPP_PIPE_SOURCE; \ - type DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING + type DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING; \ + type DSCRM_DSC_FORWARD_EN_STATUS + struct dcn20_dsc_registers { uint32_t DSC_TOP_CONTROL; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c index 52f23bb554af..6acb6699f146 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c @@ -208,7 +208,7 @@ static void dsc401_wait_disconnect_pending_clear(struct display_stream_compresso { struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); - REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING, 0, 2, 50000); + REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, 0, 2, 50000); } static void dsc401_disconnect(struct display_stream_compressor *dsc) diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h index 2143e81ca22a..3c9fa8988974 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h @@ -196,7 +196,8 @@ DSC2_SF(DSCCIF0, DSCCIF_CONFIG0__BITS_PER_COMPONENT, mask_sh), \ DSC_SF(DSCCIF0_DSCCIF_CONFIG0, DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \ DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, mask_sh), \ - DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh) + DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh), \ + DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, mask_sh) struct dcn401_dsc_registers { uint32_t DSC_TOP_CONTROL;

1 year, 4 months

1
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FAILED: patch "[PATCH] drm/amd/display: Adjust reg field for DSC wait for disconnect" failed to apply to 5.10-stable tree

by gregkh＠linuxfoundation.org

The patch below does not apply to the 5.10-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <stable(a)vger.kernel.org>. To reproduce the conflict and resubmit, you may use the following commands: git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-5.10.y git checkout FETCH_HEAD git cherry-pick -x 569d7db70e5dcf13fbf072f10e9096577ac1e565 # <resolve conflicts, build, test, etc.> git commit -s git send-email --to '<stable(a)vger.kernel.org>' --in-reply-to '2024081212-unflawed-neatness-4c03@gregkh' --subject-prefix 'PATCH 5.10.y' HEAD^.. Possible dependencies: 569d7db70e5d ("drm/amd/display: Adjust reg field for DSC wait for disconnect") 176278d8bff2 ("drm/amd/display: reset DSC clock in post unlock update") 0127f0445f7c ("drm/amd/display: Refactor input mode programming for DIG FIFO") e6a901a00822 ("drm/amd/display: use even ODM slice width for two pixels per container") 532a0d2ad292 ("drm/amd/display: Revert "dc: Keep VBios pixel rate div setting util next mode set"") 47745acc5e8d ("drm/amd/display: Add trigger FIFO resync path for DCN35") 4d4d3ff16db2 ("drm/amd/display: Keep VBios pixel rate div setting util next mode set") 70839da63605 ("drm/amd/display: Add new DCN401 sources") 9712b64d6f3f ("drm/amd/display: Remove MPC rate control logic from DCN30 and above") eed4edda910f ("drm/amd/display: Support long vblank feature") 2d7f3d1a5866 ("drm/amd/display: Implement wait_for_odm_update_pending_complete") c7b33856139d ("drm/amd/display: Drop some unnecessary guards") 6a068e64fb25 ("drm/amd/display: Update phantom pipe enable / disable sequence") db8391479f44 ("drm/amd/display: correct static screen event mask") 4ba9ca63e696 ("drm/amd/display: Fix dcn35 8k30 Underflow/Corruption Issue") 9af68235ad3d ("drm/amd/display: Fix static screen event mask definition change") f6154d8babbb ("drm/amd/display: Refactor INIT into component folder") a71e1310a43f ("drm/amd/display: Add more mechanisms for tests") 85fce153995e ("drm/amd/display: change static screen wait frame_count for ips") 09a4ec5da92c ("drm/amd/display: Refactor dc_state interface") thanks, greg k-h ------------------ original commit in Linus's tree ------------------ From 569d7db70e5dcf13fbf072f10e9096577ac1e565 Mon Sep 17 00:00:00 2001 From: Ryan Seto <ryanseto(a)amd.com> Date: Fri, 14 Jun 2024 14:56:15 -0400 Subject: [PATCH] drm/amd/display: Adjust reg field for DSC wait for disconnect [WHY] DSC was waiting for the wrong field to disconnect cleanly. [HOW] Changed field the DSC disconnect was waiting on. Reviewed-by: Wenjing Liu <wenjing.liu(a)amd.com> Cc: Mario Limonciello <mario.limonciello(a)amd.com> Cc: Alex Deucher <alexander.deucher(a)amd.com> Cc: stable(a)vger.kernel.org Signed-off-by: Alex Hung <alex.hung(a)amd.com> Signed-off-by: Ryan Seto <ryanseto(a)amd.com> Tested-by: Daniel Wheeler <daniel.wheeler(a)amd.com> Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h index a23308a785bc..1fb90b52b814 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h @@ -454,7 +454,9 @@ type DSCCIF_UPDATE_TAKEN_ACK; \ type DSCRM_DSC_FORWARD_EN; \ type DSCRM_DSC_OPP_PIPE_SOURCE; \ - type DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING + type DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING; \ + type DSCRM_DSC_FORWARD_EN_STATUS + struct dcn20_dsc_registers { uint32_t DSC_TOP_CONTROL; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c index 52f23bb554af..6acb6699f146 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c @@ -208,7 +208,7 @@ static void dsc401_wait_disconnect_pending_clear(struct display_stream_compresso { struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); - REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING, 0, 2, 50000); + REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, 0, 2, 50000); } static void dsc401_disconnect(struct display_stream_compressor *dsc) diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h index 2143e81ca22a..3c9fa8988974 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h @@ -196,7 +196,8 @@ DSC2_SF(DSCCIF0, DSCCIF_CONFIG0__BITS_PER_COMPONENT, mask_sh), \ DSC_SF(DSCCIF0_DSCCIF_CONFIG0, DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \ DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, mask_sh), \ - DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh) + DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh), \ + DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, mask_sh) struct dcn401_dsc_registers { uint32_t DSC_TOP_CONTROL;

1 year, 4 months

1
0
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FAILED: patch "[PATCH] drm/amd/display: Adjust reg field for DSC wait for disconnect" failed to apply to 6.1-stable tree

by gregkh＠linuxfoundation.org

The patch below does not apply to the 6.1-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <stable(a)vger.kernel.org>. To reproduce the conflict and resubmit, you may use the following commands: git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.1.y git checkout FETCH_HEAD git cherry-pick -x 569d7db70e5dcf13fbf072f10e9096577ac1e565 # <resolve conflicts, build, test, etc.> git commit -s git send-email --to '<stable(a)vger.kernel.org>' --in-reply-to '2024081211-foothold-crayfish-6d6d@gregkh' --subject-prefix 'PATCH 6.1.y' HEAD^.. Possible dependencies: 569d7db70e5d ("drm/amd/display: Adjust reg field for DSC wait for disconnect") 176278d8bff2 ("drm/amd/display: reset DSC clock in post unlock update") 0127f0445f7c ("drm/amd/display: Refactor input mode programming for DIG FIFO") e6a901a00822 ("drm/amd/display: use even ODM slice width for two pixels per container") 532a0d2ad292 ("drm/amd/display: Revert "dc: Keep VBios pixel rate div setting util next mode set"") 47745acc5e8d ("drm/amd/display: Add trigger FIFO resync path for DCN35") 4d4d3ff16db2 ("drm/amd/display: Keep VBios pixel rate div setting util next mode set") 70839da63605 ("drm/amd/display: Add new DCN401 sources") 9712b64d6f3f ("drm/amd/display: Remove MPC rate control logic from DCN30 and above") eed4edda910f ("drm/amd/display: Support long vblank feature") 2d7f3d1a5866 ("drm/amd/display: Implement wait_for_odm_update_pending_complete") c7b33856139d ("drm/amd/display: Drop some unnecessary guards") 6a068e64fb25 ("drm/amd/display: Update phantom pipe enable / disable sequence") db8391479f44 ("drm/amd/display: correct static screen event mask") 4ba9ca63e696 ("drm/amd/display: Fix dcn35 8k30 Underflow/Corruption Issue") 9af68235ad3d ("drm/amd/display: Fix static screen event mask definition change") f6154d8babbb ("drm/amd/display: Refactor INIT into component folder") a71e1310a43f ("drm/amd/display: Add more mechanisms for tests") 85fce153995e ("drm/amd/display: change static screen wait frame_count for ips") 09a4ec5da92c ("drm/amd/display: Refactor dc_state interface") thanks, greg k-h ------------------ original commit in Linus's tree ------------------ From 569d7db70e5dcf13fbf072f10e9096577ac1e565 Mon Sep 17 00:00:00 2001 From: Ryan Seto <ryanseto(a)amd.com> Date: Fri, 14 Jun 2024 14:56:15 -0400 Subject: [PATCH] drm/amd/display: Adjust reg field for DSC wait for disconnect [WHY] DSC was waiting for the wrong field to disconnect cleanly. [HOW] Changed field the DSC disconnect was waiting on. Reviewed-by: Wenjing Liu <wenjing.liu(a)amd.com> Cc: Mario Limonciello <mario.limonciello(a)amd.com> Cc: Alex Deucher <alexander.deucher(a)amd.com> Cc: stable(a)vger.kernel.org Signed-off-by: Alex Hung <alex.hung(a)amd.com> Signed-off-by: Ryan Seto <ryanseto(a)amd.com> Tested-by: Daniel Wheeler <daniel.wheeler(a)amd.com> Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h index a23308a785bc..1fb90b52b814 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h @@ -454,7 +454,9 @@ type DSCCIF_UPDATE_TAKEN_ACK; \ type DSCRM_DSC_FORWARD_EN; \ type DSCRM_DSC_OPP_PIPE_SOURCE; \ - type DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING + type DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING; \ + type DSCRM_DSC_FORWARD_EN_STATUS + struct dcn20_dsc_registers { uint32_t DSC_TOP_CONTROL; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c index 52f23bb554af..6acb6699f146 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c @@ -208,7 +208,7 @@ static void dsc401_wait_disconnect_pending_clear(struct display_stream_compresso { struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); - REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING, 0, 2, 50000); + REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, 0, 2, 50000); } static void dsc401_disconnect(struct display_stream_compressor *dsc) diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h index 2143e81ca22a..3c9fa8988974 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h @@ -196,7 +196,8 @@ DSC2_SF(DSCCIF0, DSCCIF_CONFIG0__BITS_PER_COMPONENT, mask_sh), \ DSC_SF(DSCCIF0_DSCCIF_CONFIG0, DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \ DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, mask_sh), \ - DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh) + DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh), \ + DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, mask_sh) struct dcn401_dsc_registers { uint32_t DSC_TOP_CONTROL;

1 year, 4 months

1
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FAILED: patch "[PATCH] drm/amd/display: Adjust reg field for DSC wait for disconnect" failed to apply to 6.6-stable tree

by gregkh＠linuxfoundation.org

The patch below does not apply to the 6.6-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <stable(a)vger.kernel.org>. To reproduce the conflict and resubmit, you may use the following commands: git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.6.y git checkout FETCH_HEAD git cherry-pick -x 569d7db70e5dcf13fbf072f10e9096577ac1e565 # <resolve conflicts, build, test, etc.> git commit -s git send-email --to '<stable(a)vger.kernel.org>' --in-reply-to '2024081210-ascertain-reverend-8249@gregkh' --subject-prefix 'PATCH 6.6.y' HEAD^.. Possible dependencies: 569d7db70e5d ("drm/amd/display: Adjust reg field for DSC wait for disconnect") 176278d8bff2 ("drm/amd/display: reset DSC clock in post unlock update") 0127f0445f7c ("drm/amd/display: Refactor input mode programming for DIG FIFO") e6a901a00822 ("drm/amd/display: use even ODM slice width for two pixels per container") 532a0d2ad292 ("drm/amd/display: Revert "dc: Keep VBios pixel rate div setting util next mode set"") 47745acc5e8d ("drm/amd/display: Add trigger FIFO resync path for DCN35") 4d4d3ff16db2 ("drm/amd/display: Keep VBios pixel rate div setting util next mode set") 70839da63605 ("drm/amd/display: Add new DCN401 sources") 9712b64d6f3f ("drm/amd/display: Remove MPC rate control logic from DCN30 and above") eed4edda910f ("drm/amd/display: Support long vblank feature") 2d7f3d1a5866 ("drm/amd/display: Implement wait_for_odm_update_pending_complete") c7b33856139d ("drm/amd/display: Drop some unnecessary guards") 6a068e64fb25 ("drm/amd/display: Update phantom pipe enable / disable sequence") db8391479f44 ("drm/amd/display: correct static screen event mask") 4ba9ca63e696 ("drm/amd/display: Fix dcn35 8k30 Underflow/Corruption Issue") 9af68235ad3d ("drm/amd/display: Fix static screen event mask definition change") f6154d8babbb ("drm/amd/display: Refactor INIT into component folder") a71e1310a43f ("drm/amd/display: Add more mechanisms for tests") 85fce153995e ("drm/amd/display: change static screen wait frame_count for ips") 09a4ec5da92c ("drm/amd/display: Refactor dc_state interface") thanks, greg k-h ------------------ original commit in Linus's tree ------------------ From 569d7db70e5dcf13fbf072f10e9096577ac1e565 Mon Sep 17 00:00:00 2001 From: Ryan Seto <ryanseto(a)amd.com> Date: Fri, 14 Jun 2024 14:56:15 -0400 Subject: [PATCH] drm/amd/display: Adjust reg field for DSC wait for disconnect [WHY] DSC was waiting for the wrong field to disconnect cleanly. [HOW] Changed field the DSC disconnect was waiting on. Reviewed-by: Wenjing Liu <wenjing.liu(a)amd.com> Cc: Mario Limonciello <mario.limonciello(a)amd.com> Cc: Alex Deucher <alexander.deucher(a)amd.com> Cc: stable(a)vger.kernel.org Signed-off-by: Alex Hung <alex.hung(a)amd.com> Signed-off-by: Ryan Seto <ryanseto(a)amd.com> Tested-by: Daniel Wheeler <daniel.wheeler(a)amd.com> Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h index a23308a785bc..1fb90b52b814 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h @@ -454,7 +454,9 @@ type DSCCIF_UPDATE_TAKEN_ACK; \ type DSCRM_DSC_FORWARD_EN; \ type DSCRM_DSC_OPP_PIPE_SOURCE; \ - type DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING + type DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING; \ + type DSCRM_DSC_FORWARD_EN_STATUS + struct dcn20_dsc_registers { uint32_t DSC_TOP_CONTROL; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c index 52f23bb554af..6acb6699f146 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c @@ -208,7 +208,7 @@ static void dsc401_wait_disconnect_pending_clear(struct display_stream_compresso { struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); - REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING, 0, 2, 50000); + REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, 0, 2, 50000); } static void dsc401_disconnect(struct display_stream_compressor *dsc) diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h index 2143e81ca22a..3c9fa8988974 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h @@ -196,7 +196,8 @@ DSC2_SF(DSCCIF0, DSCCIF_CONFIG0__BITS_PER_COMPONENT, mask_sh), \ DSC_SF(DSCCIF0_DSCCIF_CONFIG0, DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \ DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, mask_sh), \ - DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh) + DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh), \ + DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, mask_sh) struct dcn401_dsc_registers { uint32_t DSC_TOP_CONTROL;

1 year, 4 months

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FAILED: patch "[PATCH] drm/amd/display: Adjust reg field for DSC wait for disconnect" failed to apply to 6.10-stable tree

by gregkh＠linuxfoundation.org

The patch below does not apply to the 6.10-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <stable(a)vger.kernel.org>. To reproduce the conflict and resubmit, you may use the following commands: git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.10.y git checkout FETCH_HEAD git cherry-pick -x 569d7db70e5dcf13fbf072f10e9096577ac1e565 # <resolve conflicts, build, test, etc.> git commit -s git send-email --to '<stable(a)vger.kernel.org>' --in-reply-to '2024081209-condiment-kick-c449@gregkh' --subject-prefix 'PATCH 6.10.y' HEAD^.. Possible dependencies: 569d7db70e5d ("drm/amd/display: Adjust reg field for DSC wait for disconnect") 176278d8bff2 ("drm/amd/display: reset DSC clock in post unlock update") 0127f0445f7c ("drm/amd/display: Refactor input mode programming for DIG FIFO") e6a901a00822 ("drm/amd/display: use even ODM slice width for two pixels per container") 532a0d2ad292 ("drm/amd/display: Revert "dc: Keep VBios pixel rate div setting util next mode set"") 47745acc5e8d ("drm/amd/display: Add trigger FIFO resync path for DCN35") 4d4d3ff16db2 ("drm/amd/display: Keep VBios pixel rate div setting util next mode set") 70839da63605 ("drm/amd/display: Add new DCN401 sources") thanks, greg k-h ------------------ original commit in Linus's tree ------------------ From 569d7db70e5dcf13fbf072f10e9096577ac1e565 Mon Sep 17 00:00:00 2001 From: Ryan Seto <ryanseto(a)amd.com> Date: Fri, 14 Jun 2024 14:56:15 -0400 Subject: [PATCH] drm/amd/display: Adjust reg field for DSC wait for disconnect [WHY] DSC was waiting for the wrong field to disconnect cleanly. [HOW] Changed field the DSC disconnect was waiting on. Reviewed-by: Wenjing Liu <wenjing.liu(a)amd.com> Cc: Mario Limonciello <mario.limonciello(a)amd.com> Cc: Alex Deucher <alexander.deucher(a)amd.com> Cc: stable(a)vger.kernel.org Signed-off-by: Alex Hung <alex.hung(a)amd.com> Signed-off-by: Ryan Seto <ryanseto(a)amd.com> Tested-by: Daniel Wheeler <daniel.wheeler(a)amd.com> Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h index a23308a785bc..1fb90b52b814 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h @@ -454,7 +454,9 @@ type DSCCIF_UPDATE_TAKEN_ACK; \ type DSCRM_DSC_FORWARD_EN; \ type DSCRM_DSC_OPP_PIPE_SOURCE; \ - type DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING + type DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING; \ + type DSCRM_DSC_FORWARD_EN_STATUS + struct dcn20_dsc_registers { uint32_t DSC_TOP_CONTROL; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c index 52f23bb554af..6acb6699f146 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c @@ -208,7 +208,7 @@ static void dsc401_wait_disconnect_pending_clear(struct display_stream_compresso { struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); - REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING, 0, 2, 50000); + REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, 0, 2, 50000); } static void dsc401_disconnect(struct display_stream_compressor *dsc) diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h index 2143e81ca22a..3c9fa8988974 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h @@ -196,7 +196,8 @@ DSC2_SF(DSCCIF0, DSCCIF_CONFIG0__BITS_PER_COMPONENT, mask_sh), \ DSC_SF(DSCCIF0_DSCCIF_CONFIG0, DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \ DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, mask_sh), \ - DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh) + DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh), \ + DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, mask_sh) struct dcn401_dsc_registers { uint32_t DSC_TOP_CONTROL;

1 year, 4 months

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