On Tue, 7 Jun 2022 14:15:36 -0700, Brian Norris wrote:
Before commit 9998943f6dfc ("media: rkvdec: Stop overclocking the decoder"), the rkvdec driver was forcing the VDU clock rate. After that commit, we rely on the default clock rate. That rate works OK on many boards, with the default PLL settings (CPLL is 800MHz, VDU dividers leave it at 400MHz); but some boards change PLL settings.
Assign the expected default clock rate explicitly, so that the rate is consistent, regardless of PLL configuration.
[...]
Applied, thanks!
[1/1] arm64: dts: rockchip: Assign RK3399 VDU clock rate commit: 2d56af33d4df94d2b76446ffc3e3654c42232f4b
as fix for 5.19
Best regards,