The dt-bindings for the display, specifically ti,am65x-dss, need to include a clock property for data edge synchronization. The current implementation does not correctly apply the data edge sampling property.
To address this, synchronization of writes to two different registers is required: one in the TIDSS IP (which is already described in the tidss node) and one is in the Memory Mapped Control Register Modules (added by the previous commit).
As the Memory Mapped Control Register Modules is located in a different IP, we need to use a phandle to write values in its registers.
Fixes: 32a1795f57ee ("drm/tidss: New driver for TI Keystone platform Display SubSystem") Signed-off-by: Louis Chauvet louis.chauvet@bootlin.com
---
Cc: stable@vger.kernel.org --- Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index 361e9cae6896c1f4d7fa1ec47a6e3a73bca2b102..b9a373b569170332f671416eb7bbc0c83f7b5ea6 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -133,6 +133,12 @@ properties: and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI interface to work.
+ ti,clk-ctrl: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to syscon device node mapping CFG0_CLK_CTRL registers. + This property is needed for proper data sampling edge. + max-memory-bandwidth: $ref: /schemas/types.yaml#/definitions/uint32 description: