On Fri, Jul 15, 2022 at 07:22:09AM -0700, Guenter Roeck wrote:
On Tue, Jun 14, 2022 at 10:31:38AM +0200, Sascha Hauer wrote:
The DEVICE_BUSY_TIMEOUT value is described in the Reference Manual as:
| Timeout waiting for NAND Ready/Busy or ATA IRQ. Used in WAIT_FOR_READY | mode. This value is the number of GPMI_CLK cycles multiplied by 4096.
So instead of multiplying the value in cycles with 4096, we have to divide it by that value. Use DIV_ROUND_UP to make sure we are on the safe side, especially when the calculated value in cycles is smaller than 4096 as typically the case.
This bug likely never triggered because any timeout != 0 usually will do. In my case the busy timeout in cycles was originally calculated as 2408, which multiplied with 4096 is 0x968000. The lower 16 bits were taken for the 16 bit wide register field, so the register value was 0x8000. With 2970bf5a32f0 ("mtd: rawnand: gpmi: fix controller timings setting") however the value in cycles became 2384, which multiplied with 4096 is 0x950000. The lower 16 bit are 0x0 now resulting in an intermediate timeout when reading from NAND.
Fixes: b1206122069aa ("mtd: rawnand: gpmi: use core timings instead of an empirical derivation") Cc: stable@vger.kernel.org Signed-off-by: Sascha Hauer s.hauer@pengutronix.de
I see this patch was reverted in a set of rush stable releases, but I still see it in the mainline kernel. Is it going to be reverted there as well ?
A fix has been sent, it was said to be picked up hopefully next week: https://lore.kernel.org/all/20220701110341.3094023-1-s.hauer@pengutronix.de/
thanks,
greg k-h