The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: b8c3a2502a205321fe66c356f4b70cabd8e1a5fc Gitweb: https://git.kernel.org/tip/b8c3a2502a205321fe66c356f4b70cabd8e1a5fc Author: Kan Liang kan.liang@linux.intel.com AuthorDate: Mon, 16 Dec 2024 12:45:02 -08:00 Committer: Peter Zijlstra peterz@infradead.org CommitterDate: Tue, 17 Dec 2024 17:47:23 +01:00
perf/x86/intel/ds: Add PEBS format 6
The only difference between 5 and 6 is the new counters snapshotting group, without the following counters snapshotting enabling patches, it's impossible to utilize the feature in a PEBS record. It's safe to share the same code path with format 5.
Add format 6, so the end user can at least utilize the legacy PEBS features.
Fixes: a932aa0e868f ("perf/x86: Add Lunar Lake and Arrow Lake support") Signed-off-by: Kan Liang kan.liang@linux.intel.com Signed-off-by: Peter Zijlstra (Intel) peterz@infradead.org Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20241216204505.748363-1-kan.liang@linux.intel.com --- arch/x86/events/intel/ds.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 1a4b326..6ba6549 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -2517,6 +2517,7 @@ void __init intel_ds_init(void) x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME; break;
+ case 6: case 5: x86_pmu.pebs_ept = 1; fallthrough;