4.16-stable review patch. If anyone has any objections, please let me know.
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From: Maxime Chevallier maxime.chevallier@bootlin.com
[ Upstream commit da42bb271305d68df6cbf99eed90542f1f1ee1c9 ]
PPv2 TX/RX descriptors uses 40bits DMA addresses, but 41 bits masks were used (GENMASK_ULL(40, 0)).
This commit fixes that by using the correct mask.
Fixes: e7c5359f2eed ("net: mvpp2: introduce PPv2.2 HW descriptors and adapt accessors") Signed-off-by: Maxime Chevallier maxime.chevallier@bootlin.com Signed-off-by: David S. Miller davem@davemloft.net Signed-off-by: Greg Kroah-Hartman gregkh@linuxfoundation.org --- drivers/net/ethernet/marvell/mvpp2.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-)
--- a/drivers/net/ethernet/marvell/mvpp2.c +++ b/drivers/net/ethernet/marvell/mvpp2.c @@ -838,6 +838,8 @@ enum mvpp2_bm_type {
#define MVPP2_MIB_COUNTERS_STATS_DELAY (1 * HZ)
+#define MVPP2_DESC_DMA_MASK DMA_BIT_MASK(40) + /* Definitions */
/* Shared Packet Processor resources */ @@ -1336,7 +1338,7 @@ static dma_addr_t mvpp2_txdesc_dma_addr_ if (port->priv->hw_version == MVPP21) return tx_desc->pp21.buf_dma_addr; else - return tx_desc->pp22.buf_dma_addr_ptp & GENMASK_ULL(40, 0); + return tx_desc->pp22.buf_dma_addr_ptp & MVPP2_DESC_DMA_MASK; }
static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, @@ -1354,7 +1356,7 @@ static void mvpp2_txdesc_dma_addr_set(st } else { u64 val = (u64)addr;
- tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0); + tx_desc->pp22.buf_dma_addr_ptp &= ~MVPP2_DESC_DMA_MASK; tx_desc->pp22.buf_dma_addr_ptp |= val; tx_desc->pp22.packet_offset = offset; } @@ -1414,7 +1416,7 @@ static dma_addr_t mvpp2_rxdesc_dma_addr_ if (port->priv->hw_version == MVPP21) return rx_desc->pp21.buf_dma_addr; else - return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0); + return rx_desc->pp22.buf_dma_addr_key_hash & MVPP2_DESC_DMA_MASK; }
static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, @@ -1423,7 +1425,7 @@ static unsigned long mvpp2_rxdesc_cookie if (port->priv->hw_version == MVPP21) return rx_desc->pp21.buf_cookie; else - return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0); + return rx_desc->pp22.buf_cookie_misc & MVPP2_DESC_DMA_MASK; }
static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, @@ -8347,7 +8349,7 @@ static int mvpp2_probe(struct platform_d }
if (priv->hw_version == MVPP22) { - err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(40)); + err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK); if (err) goto err_mg_clk; /* Sadly, the BM pools all share the same register to