Hi,
On Thu, Sep 04 2025, Santhosh Kumar K wrote:
From: Pratyush Yadav pratyush@kernel.org
cqspi_indirect_read_execute() and cqspi_indirect_write_execute() first set the enable bit on APB region and then start reading/writing to the AHB region. On TI K3 SoCs these regions lie on different endpoints. This means that the order of the two operations is not guaranteed, and they might be reordered at the interconnect level.
It is possible for the AHB write to be executed before the APB write to enable the indirect controller, causing the transaction to be invalid and the write erroring out. Read back the APB region write before accessing the AHB region to make sure the write got flushed and the race condition is eliminated.
Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller") CC: stable@vger.kernel.org Signed-off-by: Pratyush Yadav pratyush@kernel.org Signed-off-by: Santhosh Kumar K s-k6@ti.com
IIRC I wrote this patch a few years ago when I was still at TI. Nice to see it being upstreamed! It feels strange to review my own patch, but FWIW,
Reviewed-by: Pratyush Yadav pratyush@kernel.org
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