On Wed, Apr 9, 2025 at 10:55 PM Anshuman Khandual anshuman.khandual@arm.com wrote:
From: "Rob Herring (Arm)" robh@kernel.org
Armv8.9/9.4 PMUv3.9 adds per counter EL0 access controls. Per counter access is enabled with the UEN bit in PMUSERENR_EL1 register. Individual counters are enabled/disabled in the PMUACR_EL1 register. When UEN is set, the CR/ER bits control EL0 write access and must be set to disable write access.
With the access controls, the clearing of unused counters can be skipped.
KVM also configures PMUSERENR_EL1 in order to trap to EL2. UEN does not need to be set for it since only PMUv3.5 is exposed to guests.
Signed-off-by: Rob Herring (Arm) robh@kernel.org Link: https://lore.kernel.org/r/20241002184326.1105499-1-robh@kernel.org Signed-off-by: Will Deacon will@kernel.org [cherry picked from commit 0bbff9ed81654d5f06bfca484681756ee407f924] Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com
This one doesn't belong in 6.12. It's a feature that landed in 6.13. It's only the fixed instruction counter support that landed in 6.12.
Rob