On 7/30/24 10:39, Krzysztof Kozlowski wrote:
On 30/07/2024 10:23, Krzysztof Kozlowski wrote:
On 29/07/2024 16:25, Pierre-Louis Bossart wrote:
On 7/29/24 16:01, Krzysztof Kozlowski wrote:
Two bitmasks in 'struct sdw_slave_prop' - 'source_ports' and 'sink_ports' - define which ports to program in sdw_program_slave_port_params(). The masks are used to get the appropriate data port properties ('struct sdw_get_slave_dpn_prop') from an array.
Bitmasks can be non-continuous or can start from index different than 0, thus when looking for matching port property for given port, we must iterate over mask bits, not from 0 up to number of ports.
This fixes allocation and programming slave ports, when a source or sink masks start from further index.
Fixes: f8101c74aa54 ("soundwire: Add Master and Slave port programming") Cc: stable@vger.kernel.org Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
This is a valid change to optimize how the port are accessed.
But the commit message is not completely clear, the allocation in mipi_disco.c is not modified and I don't think there's anything that would crash. If there are non-contiguous ports, we will still allocate space that will not be initialized/used.
/* Allocate memory for set bits in port lists */ nval = hweight32(prop->source_ports); prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, sizeof(*prop->src_dpn_prop), GFP_KERNEL); if (!prop->src_dpn_prop) return -ENOMEM;
/* Read dpn properties for source port(s) */ sdw_slave_read_dpn(slave, prop->src_dpn_prop, nval, prop->source_ports, "source");
IOW, this is a valid change, but it's an optimization, not a fix in the usual sense of 'kernel oops otherwise'.
Am I missing something?
BTW, the notion of DPn is that n > 0. DP0 is a special case with different properties, BIT(0) cannot be set for either of the sink/source port bitmask.
I think we speak about two different things. port num > 1, that's correct. But index for src_dpn_prop array is something different. Look at mipi-disco sdw_slave_read_dpn():
173 u32 bit, i = 0; ... 178 addr = ports; 179 /* valid ports are 1 to 14 so apply mask */ 180 addr &= GENMASK(14, 1); 181 182 for_each_set_bit(bit, &addr, 32) { ... 186 dpn[i].num = bit;
so dpn[0..i] = 1..n where i is also the bit in the mask.
yes, agreed on the indexing.
But are we in agreement that the case of non-contiguous ports would not create any issues? the existing code is not efficient but it wouldn't crash, would it?
There are multiple cases of non-contiguous ports, I am not aware of any issues...
rt700-sdw.c: prop->source_ports = 0x14; /* BITMAP: 00010100 */ rt711-sdca-sdw.c: prop->source_ports = 0x14; /* BITMAP: 00010100 rt712-sdca-sdw.c: prop->source_ports = BIT(8) | BIT(4); rt715-sdca-sdw.c: prop->source_ports = 0x50;/* BITMAP: 01010000 */ rt722-sdca-sdw.c: prop->source_ports = BIT(6) | BIT(2); /* BITMAP: 01000100 */
same for sinks:
rt712-sdca-sdw.c: prop->sink_ports = BIT(3) | BIT(1); /* BITMAP: 00001010 */ rt722-sdca-sdw.c: prop->sink_ports = BIT(3) | BIT(1); /* BITMAP: 00001010 */
Similar implementation was done in Qualcomm wsa and wcd codecs like: array indexed from 0: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/soun...
genmask from 0, with a mistake: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/soun...
The mistake I corrected here: https://lore.kernel.org/all/20240726-asoc-wcd-wsa-swr-ports-genmask-v1-0-d4d...
To summarize, the mask does not denote port numbers (1...14) but indices of the dpn array which are from 0..whatever (usually -1 from port number).
Let me also complete this with a real life example of my work in progress. I want to use same dpn_prop array for sink and source ports and use different masks. The code in progress is:
https://git.codelinaro.org/krzysztof.kozlowski/linux/-/commit/ef709a0e8ab249...
Without this patch, I get -EINVAL from sdw_get_slave_dpn_prop(): soundwire sdw-master-1-0: Program transport params failed: -2
Not following, sorry. The sink and source masks are separate on purpose, to allow for bi-directional ports. The SoundWire spec allows a port to be configured at run-time either as source or sink. In practice I've never seen this happen, all existing hardware relies on ports where the direction is hard-coded/fixed, but still we want to follow the spec.
So if ports can be either source or sink, I am not sure how the properties could be shared with a single array?
Those two lines aren't clear to me at all:
pdev->prop.sink_dpn_prop = wsa884x_sink_dpn_prop; pdev->prop.src_dpn_prop = wsa884x_sink_dpn_prop;