From: Jerome Brunet jbrunet@baylibre.com
[ Upstream commit 2c130695ad5265ce2eb38f55ee0cce26238f7891 ]
Enable SCPI on the axg platform, with cpu clock and hwmon (core temperature) support
Signed-off-by: Jerome Brunet jbrunet@baylibre.com Reviewed-by: Neil Armstrong narmstrong@baylibre.com Signed-off-by: Kevin Hilman khilman@baylibre.com Stable-dep-of: 5b7069d72f03 ("arm64: dts: amlogic: meson-axg: fix SCPI clock dvfs node name") Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 90e9cbcc891f2..8355818153775 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -47,6 +47,7 @@ cpu0: cpu@0 { reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; };
cpu1: cpu@1 { @@ -55,6 +56,7 @@ cpu1: cpu@1 { reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; };
cpu2: cpu@2 { @@ -63,6 +65,7 @@ cpu2: cpu@2 { reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; };
cpu3: cpu@3 { @@ -71,6 +74,7 @@ cpu3: cpu@3 { reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; };
l2: l2-cache0 { @@ -151,6 +155,28 @@ ao_alt_xtal: ao_alt_xtal-clk { #clock-cells = <0>; };
+ scpi { + compatible = "arm,scpi-pre-1.0"; + mboxes = <&mailbox 1 &mailbox 2>; + shmem = <&cpu_scp_lpri &cpu_scp_hpri>; + + scpi_clocks: clocks { + compatible = "arm,scpi-clocks"; + + scpi_dvfs: clock-controller { + compatible = "arm,scpi-dvfs-clocks"; + #clock-cells = <1>; + clock-indices = <0>; + clock-output-names = "vcpu"; + }; + }; + + scpi_sensors: sensors { + compatible = "amlogic,meson-gxbb-scpi-sensors"; + #thermal-sensor-cells = <1>; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <2>;