Hi,
On 11/05/2025 19:39, Da Xue wrote:
HHI_SPICC_CLK_CNTL bits 25:23 controls spicc clk_sel.
This sentence can be removed, this patch doesn't change anything in this= regard.
It is missing fclk_div 2 and gp0_pll which causes the spicc module to output the incorrect clocks for spicc sclk at 2.5x the expected rate.
The sentence is not correct, the spicc sclk will be at the freq computed but CCF, it simply can't achieve the requested rate without the missing parents.
But I'm against adding the GP0 PLL since this PLL is required to drive DSI panels.
And GP0 isn't needed since on G12, the SPICC has the "enhance_clk_div" which should be able to to reach much more rates with the fclk_divX clocks.
Neil
Add the missing clocks resolves this.
Fixes: a18c8e0b7697 ("clk: meson: g12a: add support for the SPICC SCLK Source clocks") Cc: stable@vger.kernel.org # 6.1 Signed-off-by: Da Xue da@libre.computer
Changelog:
v1 -> v2: add Fixes as an older version of the patch was incorrectly sent as v1
drivers/clk/meson/g12a.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 4f92b83965d5a..892862bf39996 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -4099,8 +4099,10 @@ static const struct clk_parent_data spicc_sclk_parent_data[] = { { .hw = &g12a_clk81.hw }, { .hw = &g12a_fclk_div4.hw }, { .hw = &g12a_fclk_div3.hw },
- { .hw = &g12a_fclk_div2.hw }, { .hw = &g12a_fclk_div5.hw }, { .hw = &g12a_fclk_div7.hw },
- { .hw = &g12a_gp0_pll.hw, }, };
static struct clk_regmap g12a_spicc0_sclk_sel = {