Hi!
[ Upstream commit c7861adbe37f576931650ad8ef805e0c47564b9a ]
Each eTSEC MAC has its own TBI (SGMII) PCS and private MDIO bus. But due to a DTS oversight, both SGMII-compatible MACs of the LS1021 SoC are pointing towards the same internal PCS. Therefore nobody is controlling the internal PCS of eTSEC0.
Upon initial ndo_open, the SGMII link is ok by virtue of U-boot initialization. But upon an ifdown/ifup sequence, the code path from ndo_open -> init_phy -> gfar_configure_serdes does not get executed for the PCS of eTSEC0 (and is executed twice for MAC eTSEC1). So the SGMII link remains down for eTSEC0. On the LS1021A-TWR board, to signal this failure condition, the PHY driver keeps printing '803x_aneg_done: SGMII link is not ok'.
Also, it changes compatible of mdio0 to "fsl,etsec2-mdio" to match mdio1 device.
It actually changes compatible of both devices.
+++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -584,7 +584,7 @@ }; mdio0: mdio@2d24000 {
compatible = "gianfar";
compatible = "fsl,etsec2-mdio"; device_type = "mdio"; #address-cells = <1>; #size-cells = <0>;@@ -592,6 +592,15 @@ <0x0 0x2d10030 0x0 0x4>; };
mdio1: mdio@2d64000 {compatible = "fsl,etsec2-mdio";
And they trigger different code in the driver:
.type = "mdio", .compatible = "gianfar", .data = &(struct fsl_pq_mdio_data) { ... .get_tbipa = get_gfar_tbipa_from_mdio, },
.compatible = "fsl,etsec2-mdio", .data = &(struct fsl_pq_mdio_data) { ... .get_tbipa = get_etsec_tbipa, },
Are you sure that is good idea for both mainline and stable?
Best regards, Pavel